Index: dwc_eqos.c =================================================================== RCS file: /cvsroot/src/sys/dev/ic/dwc_eqos.c,v retrieving revision 1.34 diff -p -u -r1.34 dwc_eqos.c --- dwc_eqos.c 13 Nov 2023 15:07:19 -0000 1.34 +++ dwc_eqos.c 14 Dec 2023 08:26:51 -0000 @@ -146,15 +146,13 @@ eqos_mii_readreg(device_t dev, int phy, GMAC_MAC_MDIO_ADDRESS_GOC_READ | GMAC_MAC_MDIO_ADDRESS_GB; WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); - delay(10000); - for (retry = MII_BUSY_RETRY; retry > 0; retry--) { + delay(10); addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); if ((addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { *val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF; break; } - delay(10); } if (retry == 0) { device_printf(dev, "phy read timeout, phy=%d reg=%d\n", @@ -180,14 +178,12 @@ eqos_mii_writereg(device_t dev, int phy, GMAC_MAC_MDIO_ADDRESS_GOC_WRITE | GMAC_MAC_MDIO_ADDRESS_GB; WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); - delay(10000); - for (retry = MII_BUSY_RETRY; retry > 0; retry--) { + delay(10); addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); if ((addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { break; } - delay(10); } if (retry == 0) { device_printf(dev, "phy write timeout, phy=%d reg=%d\n", @@ -503,33 +499,58 @@ eqos_setup_rxfilter(struct eqos_softc *s EQOS_ASSERT_LOCKED(sc); pfil = RD4(sc, GMAC_MAC_PACKET_FILTER); + + /* turn off promiscous mode */ + /* turn off the receive-all mode */ + /* turn off the non-UDP/TCP filter */ + /* turn off broadcast filter */ + /* turn off pass all multicast mode */ + /* turn on hash or perfect mode */ + /* turn off source address filter */ + /* turn off inverse source address filter */ + /* turn off inverse destination address filter */ + /* turn off multicast hash table matching */ + /* turn off unicast hash table matching */ + /* XXX keep IP Layer3+4 filter */ + /* XXX keep VLAN tag filter */ + /* don't pass control packets */ pfil &= ~(GMAC_MAC_PACKET_FILTER_PR | + GMAC_MAC_PACKET_FILTER_RA | + GMAC_MAC_PACKET_FILTER_DNTU | + GMAC_MAC_PACKET_FILTER_DBF | GMAC_MAC_PACKET_FILTER_PM | + GMAC_MAC_PACKET_FILTER_SAF | + GMAC_MAC_PACKET_FILTER_SAIF | + GMAC_MAC_PACKET_FILTER_DAIF | GMAC_MAC_PACKET_FILTER_HMC | - GMAC_MAC_PACKET_FILTER_PCF_MASK); - hash[0] = hash[1] = ~0U; + GMAC_MAC_PACKET_FILTER_HUC | + GMAC_MAC_PACKET_FILTER_PCF_MASK); + pfil |= GMAC_MAC_PACKET_FILTER_HPF; ETHER_LOCK(ec); - if (sc->sc_promisc) { + if (ifp->if_flags & IFF_PROMISC) { ec->ec_flags |= ETHER_F_ALLMULTI; - pfil |= GMAC_MAC_PACKET_FILTER_PR | - GMAC_MAC_PACKET_FILTER_PCF_ALL; + /* enable promiscous mode */ + pfil |= GMAC_MAC_PACKET_FILTER_PR; + /* also receive control packets */ + pfil |= GMAC_MAC_PACKET_FILTER_PCF_ALL; + /* ignored */ + hash[0] = hash[1] = ~0U; } else { - pfil |= GMAC_MAC_PACKET_FILTER_HMC; - hash[0] = hash[1] = 0; + hash[0] = hash[1] = 0U; ec->ec_flags &= ~ETHER_F_ALLMULTI; + /* enable multicast hash table matching */ + pfil |= GMAC_MAC_PACKET_FILTER_HMC; ETHER_FIRST_MULTI(step, ec, enm); while (enm != NULL) { if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { - ec->ec_flags |= ETHER_F_ALLMULTI; + /* disable multicast hash table matching */ pfil &= ~GMAC_MAC_PACKET_FILTER_HMC; + /* pass all multicast instead */ pfil |= GMAC_MAC_PACKET_FILTER_PM; - /* - * Shouldn't matter if we clear HMC but - * let's avoid using different values. - */ - hash[0] = hash[1] = 0xffffffff; + /* ignored */ + hash[0] = hash[1] = ~0U; break; } crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); @@ -545,13 +566,16 @@ eqos_setup_rxfilter(struct eqos_softc *s /* Write our unicast address */ eaddr = CLLADDR(ifp->if_sadl); - val = eaddr[4] | (eaddr[5] << 8) | GMAC_MAC_ADDRESS0_HIGH_AE; + val = eaddr[4] | (eaddr[5] << 8); + val = __SHIFTIN(val, GMAC_MAC_ADDRESS_HIGH_ADDR) + | GMAC_MAC_ADDRESS_HIGH_AE; WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val); val = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | (eaddr[3] << 24); WR4(sc, GMAC_MAC_ADDRESS0_LOW, val); /* Multicast hash filters */ + /* XXX assumes 64 bit hashtable size */ WR4(sc, GMAC_MAC_HASH_TABLE_REG0, hash[0]); WR4(sc, GMAC_MAC_HASH_TABLE_REG1, hash[1]); @@ -622,14 +646,16 @@ eqos_init_locked(struct eqos_softc *sc) EQOS_ASSERT_LOCKED(sc); EQOS_ASSERT_TXLOCKED(sc); - if ((ifp->if_flags & IFF_RUNNING) != 0) + if ((ifp->if_flags & IFF_RUNNING) != 0) { + /* Only Setup RX filter */ + eqos_setup_rxfilter(sc); return 0; + } /* Setup TX/RX rings */ eqos_init_rings(sc, 0); /* Setup RX filter */ - sc->sc_promisc = ifp->if_flags & IFF_PROMISC; eqos_setup_rxfilter(sc); WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->sc_csr_clock / 1000000) - 1); @@ -825,6 +851,9 @@ eqos_rxintr(struct eqos_softc *sc, int q m0 = sc->sc_rx_receiving_m; mprev = sc->sc_rx_receiving_m_last; + DPRINTF(EDEB_INTR, "qid: %u, discarding %u, m0 %p\n", + qid, discarding, m0); + for (index = sc->sc_rx.cur; ; index = RX_NEXT(index)) { eqos_dma_sync(sc, sc->sc_rx.desc_map, index, index + 1, RX_DESC_COUNT, @@ -1278,17 +1307,16 @@ eqos_get_eaddr(struct eqos_softc *sc, ui } maclo = RD4(sc, GMAC_MAC_ADDRESS0_LOW); - machi = RD4(sc, GMAC_MAC_ADDRESS0_HIGH) & 0xFFFF; - if ((maclo & 0x00000001) != 0) { - aprint_error_dev(sc->sc_dev, - "Wrong MAC address. Clear the multicast bit.\n"); - maclo &= ~0x00000001; - } - + machi = __SHIFTOUT(RD4(sc, GMAC_MAC_ADDRESS0_HIGH), + GMAC_MAC_ADDRESS_HIGH_ADDR); if (maclo == 0xFFFFFFFF && machi == 0xFFFF) { /* Create one */ - maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); + maclo = 0x00f2 | (cprng_strong32() << 16); machi = cprng_strong32() & 0xffff; + } else { + aprint_error_dev(sc->sc_dev, + "Wrong MAC address. Clear the multicast bit.\n"); + maclo &= ~0x00000001; } eaddr[0] = maclo & 0xff; Index: dwc_eqos_reg.h =================================================================== RCS file: /cvsroot/src/sys/dev/ic/dwc_eqos_reg.h,v retrieving revision 1.10 diff -p -u -r1.10 dwc_eqos_reg.h --- dwc_eqos_reg.h 13 Nov 2023 15:08:06 -0000 1.10 +++ dwc_eqos_reg.h 14 Dec 2023 08:26:51 -0000 @@ -47,11 +47,21 @@ #define GMAC_MAC_CONFIGURATION_RE (1U << 0) #define GMAC_MAC_EXT_CONFIGURATION 0x0004 #define GMAC_MAC_PACKET_FILTER 0x0008 +#define GMAC_MAC_PACKET_FILTER_RA (1U << 31) +#define GMAC_MAC_PACKET_FILTER_DNTU (1U << 21) +#define GMAC_MAC_PACKET_FILTER_IPFE (1U << 20) +#define GMAC_MAC_PACKET_FILTER_VTFE (1U << 16) #define GMAC_MAC_PACKET_FILTER_HPF (1U << 10) +#define GMAC_MAC_PACKET_FILTER_SAF (1U << 9) +#define GMAC_MAC_PACKET_FILTER_SAIF (1U << 8) #define GMAC_MAC_PACKET_FILTER_PCF_MASK (3U << 6) +#define GMAC_MAC_PACKET_FILTER_PCF_NOCTL (0U << 6) +#define GMAC_MAC_PACKET_FILTER_PCF_CTL (1U << 6) #define GMAC_MAC_PACKET_FILTER_PCF_ALL (2U << 6) +#define GMAC_MAC_PACKET_FILTER_PCF_MATCH (3U << 6) #define GMAC_MAC_PACKET_FILTER_DBF (1U << 5) #define GMAC_MAC_PACKET_FILTER_PM (1U << 4) +#define GMAC_MAC_PACKET_FILTER_DAIF (1U << 3) #define GMAC_MAC_PACKET_FILTER_HMC (1U << 2) #define GMAC_MAC_PACKET_FILTER_HUC (1U << 1) #define GMAC_MAC_PACKET_FILTER_PR (1U << 0) @@ -93,6 +103,11 @@ #define GMAC_MAC_VERSION_SNPSVER_MASK 0xFFU #define GMAC_MAC_DEBUG 0x0114 #define GMAC_MAC_HW_FEATURE(n) (0x011C + 0x4 * (n)) +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ __BITS(25,24) +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_0 0 +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_64 1 +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_128 2 +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_256 3 #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE __BITS(10,6) #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE __BITS(4,0) #define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT 14 @@ -122,6 +137,17 @@ #define GMAC_MAC_ADDRESS0_HIGH 0x0300 #define GMAC_MAC_ADDRESS0_HIGH_AE (1U << 31) #define GMAC_MAC_ADDRESS0_LOW 0x0304 +#define GMAC_MAC_ADDRESS1_HIGH 0x0308 +#define GMAC_MAC_ADDRESS1_LOW 0x030c +#define GMAC_MAC_ADDRESS2_HIGH 0x0310 +#define GMAC_MAC_ADDRESS2_LOW 0x0314 +#define GMAC_MAC_ADDRESS3_HIGH 0x0314 +#define GMAC_MAC_ADDRESS3_LOW 0x031c +#define GMAC_MAC_ADDRESS_HIGH_AE __BIT(31) +#define GMAC_MAC_ADDRESS_HIGH_SE __BIT(30) +#define GMAC_MAC_ADDRESS_HIGH_MB __BITS(29,24) +#define GMAC_MAC_ADDRESS_HIGH_DCS __BIT(16) +#define GMAC_MAC_ADDRESS_HIGH_ADDR __BITS(15,0) #define GMAC_MMC_CONTROL 0x0700 #define GMAC_MMC_CONTROL_UCDBC (1U << 8) #define GMAC_MMC_CONTROL_CNTPRSTLVL (1U << 5) Index: dwc_eqos_var.h =================================================================== RCS file: /cvsroot/src/sys/dev/ic/dwc_eqos_var.h,v retrieving revision 1.9 diff -p -u -r1.9 dwc_eqos_var.h --- dwc_eqos_var.h 2 Nov 2023 13:50:02 -0000 1.9 +++ dwc_eqos_var.h 14 Dec 2023 08:26:51 -0000 @@ -1,4 +1,4 @@ -/* $NetBSD: dwc_eqos_var.h,v 1.9 2023/11/02 13:50:02 riastradh Exp $ */ +/* $NetBSD: dwc_eqos_var.h,v 1.4.4.2 2023/11/03 10:04:55 martin Exp $ */ /*- * Copyright (c) 2022 Jared McNeill @@ -72,8 +72,6 @@ struct eqos_softc { kmutex_t sc_txlock; bool sc_running; bool sc_txrunning; - bool sc_promisc; - bool sc_allmulti; struct eqos_ring sc_tx; struct eqos_ring sc_rx;