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Title:          Ver
Version:        1.3.36-12
Entered-date:   07JUL03
Description:    Structural Verilog compiler for UN*X operating systems.
		Some synthesizable behavioral constructs are now supported.
                An event simulator (vsim) is included for testing of
                logic designs.  A cycle simulation compiler (cyco/csim) is
                included which can compile netlists into fast levelized C
                code.  Cyco can also generate ABEL netlists that may be used
		for FPGA generation.  GTKWave is a fully-featured wave viewer
		which requires GTK+-1.2.0 or greater.  An experimental BDD
		package is in the process of being integrated for model
		checking purposes.  A new PCCTS parser (Vertex) is in
		experimental status but should be useful soon.
Keywords:       Verilog, structural, HDL, ABEL, digital, logic, simulator, 
                testing, cycle simulation, wave viewer, VCD, LXT, scope, BDD,
		model checking
Author:         bybell@linux-workshop.com (Tony Bybell)
Maintained-by:  bybell@linux-workshop.com (Tony Bybell)
Primary-site:   metalab.unc.edu /pub/Linux/apps/circuits
                1384584 ver-1.3.36-12.tgz
Copying-policy: GPL
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