Copyright (c) 2004-2005 Advanced Micro Devices, Inc. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. Neither the name of the Advanced Micro Devices, Inc. nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. --- xc/config/cf/xorg.cf 2005-12-14 12:12:08.471825920 -0700 +++ xc.new/config/cf/xorg.cf 2005-09-30 15:38:05.000000000 -0600 @@ -160,12 +160,8 @@ * a full build. */ #ifndef BuildXFree86ConfigTools -#ifdef BuildServersOnly -#define BuildXFree86ConfigTools !BuildServersOnly -#else #define BuildXFree86ConfigTools YES #endif -#endif #ifndef BuildLibrariesForConfigTools #define BuildLibrariesForConfigTools BuildXFree86ConfigTools @@ -399,9 +395,9 @@ /* Pure PCI drivers should go first */ # ifndef XF86CardDrivers -# /* Don't build the nsc driver on IA64 */ +# /* Don't build the amd geode driver on IA64 */ # ifndef ia64Architecture -# define i386Drivers nsc i810 +# define i386Drivers amd i810 # else # define i386Drivers /**/ # endif @@ -446,8 +442,8 @@ # ifndef XF86CardDrivers # define XF86CardDrivers mga glint nv tga s3 s3virge sis rendition \ neomagic tdfx savage cirrus tseng trident \ - chips apm i128 ati ark cyrix siliconmotion \ - vga dummy vesa \ + chips apm i128 ati i810 ark cyrix \ + siliconmotion vga dummy vesa \ XF86OSCardDrivers XF86ExtraCardDrivers # endif --- xc/config/cf/xfree86.cf 2005-12-14 12:12:08.472825768 -0700 +++ xc.new/config/cf/xfree86.cf 2005-09-30 15:31:40.000000000 -0600 @@ -365,16 +365,16 @@ /* Pure PCI drivers should go first */ # ifndef XF86CardDrivers -# /* Don't build the nsc driver on IA64 */ +# /* Don't build the amd geode driver on IA64 */ # ifndef ia64Architecture -# define NscDriver nsc +# define geodeDriver amd # else -# define NscDriver /**/ +# define geodeDriver /**/ # endif # define XF86CardDrivers mga glint nv tga s3 s3virge sis rendition \ neomagic i740 tdfx savage \ cirrus vmware tseng trident chips apm \ - GlideDriver i128 NscDriver \ + GlideDriver i128 geodeDriver \ ati i810 AgpGartDrivers DevelDrivers ark \ cyrix siliconmotion via \ fbdev vesa vga \ --- xc/programs/x11perf/x11perf.c 2005-12-14 12:12:08.473825616 -0700 +++ xc.new/programs/x11perf/x11perf.c 2005-09-30 15:02:28.000000000 -0600 @@ -24,6 +24,8 @@ /* $XFree86: xc/programs/x11perf/x11perf.c,v 3.6 2001/11/03 21:59:20 dawes Exp $ */ #include +#include +#include #include #include @@ -44,8 +46,14 @@ static Bool drawToFakeServer = False; static Pixmap tileToQuery = None; static char *displayName; +static int window_x, window_y; + int abortTest; +char *crcfn; +unsigned long ckcrc; +FILE *crcfp; + typedef struct _RopNames { char *name; int rop; } RopNameRec, *RopNamePtr; RopNameRec ropNames[] = { @@ -182,6 +190,247 @@ static struct timeval start; +static void +DumpProc(XParms xp, Parms p, + void(*init)(int w,int h), + void(*putb)(int ch)) +{ + int i, n, x, y, w, h; + Window rw; + XImage *image; + Visual *visual; + XWindowAttributes xwa; + Colormap colormap; + unsigned char *data; + + if( !XGetWindowAttributes(xp->d, xp->w, &xwa) ) + return; + w = xwa.width; + h = xwa.height; + +#if 0 + x = y = 0; + image = XGetImage(xp->d, xp->w, x,y, w,h, AllPlanes, ZPixmap); +#else + rw = DefaultRootWindow(xp->d); +#ifdef NO_WINDOW_DRESSING + x = xwa.x + xwa.border_width; + y = xwa.y + xwa.border_width; + image = XGetImage(xp->d, rw, x,y, w,h, AllPlanes, ZPixmap); +#else + x = xwa.x; w += 2*xwa.border_width; + y = xwa.y; h += 2*xwa.border_width; + image = XGetImage(xp->d, rw, x,y, w,h, AllPlanes, ZPixmap); +#endif +#endif + visual = xwa.visual; + + if( init != NULL ) init(w,h); + + switch( visual->class ) { + case TrueColor: { + int b0; /* Byte 0 index */ + int bi; /* Byte index increment */ + + /* develop pixel format */ + + int rmask = image->red_mask; double fr = 255.0 / rmask; + int gmask = image->green_mask; double fg = 255.0 / gmask; + int bmask = image->blue_mask; double fb = 255.0 / bmask; + + int nbyte = (image->bits_per_pixel+7)/8; /* bytes per pixel */ + + /* A/R/G/B or A/B/G/R byte ordering */ + + if( image->byte_order == MSBFirst ) { + b0 = 0; + bi = 1; + } + else { + b0 = nbyte-1; + bi = -1; + } + + data = (unsigned char *)image->data; + + /* scan output rows */ + + for( y=0; ybytes_per_line]; + + /* scan output columns */ + + for( x=0; x0; n|=*cp ) { + cp += bi; + n <<= 8; + } + + /* decompose pixel to R/G/B */ + + putb((int)((double)(n&rmask)*fr + 0.5)); + putb((int)((double)(n&gmask)*fg + 0.5)); + putb((int)((double)(n&bmask)*fb + 0.5)); + } + } + break; + } + + + case PseudoColor: { + XColor xcolors[256]; + unsigned char rgbColors[256][3]; + + /* access color map */ + + for( i = 0; i < 256; i++ ) + xcolors[i].pixel = i; + + colormap = xwa.colormap; + XQueryColors(xp->d, colormap, xcolors, 256 ); + for( i = 0; i<256; i++ ) { + rgbColors[i][0] = xcolors[i].red * 255 / 65535; + rgbColors[i][1] = xcolors[i].green * 255 / 65535; + rgbColors[i][2] = xcolors[i].blue * 255 / 65535; + } + + /* scan output rows */ + + data = (unsigned char *)image->data; + for( y=0; ybytes_per_line]; + + /* scan output columns */ + + for( x=0; xclass); + break; + } + + XDestroyImage(image); +} + +static FILE *DumpFp = NULL; +static char *dump = NULL; + +void DumpInit(int w,int h) +{ + fprintf(DumpFp,"%d %d\n",w,h); + fprintf(DumpFp,"255\n"); +} + +void DumpPutc(int ch) +{ + putc(ch,DumpFp); +} + +void +DumpTest(XParms xp, Parms p, char *opt, int func, unsigned long pm) +{ + int cycle = 0; + char filename[1024]; + sprintf(&filename[0],"%s/%s_%02d.pgm",dump,&opt[1],func); + for(;;){ + if( access(&filename[0],F_OK) < 0 && errno == ENOENT ) break; + sprintf(&filename[0],"%s/%s.%d_%02d.pgm",dump,&opt[1],++cycle,func); + } + DumpFp = fopen(&filename[0],"w"); + if( DumpFp == NULL ) { + perror("DumpPixmap fopen"); + return; + } + sprintf(&filename[0],"%s_%02d.pgm",&opt[1],func); + fprintf(DumpFp,"P6\n"); + fprintf(DumpFp,"# %s\n",&filename[0]); + DumpProc(xp,p,DumpInit,DumpPutc); + fclose(DumpFp); + DumpFp = NULL; +} + +static char *swfn = NULL; +static long sw_crc; +static unsigned long sw_pix; +static int sw_byt; + +#define sw_crc_reset(p) sw_crc=1,sw_byt=3 +#define sw_crc_pixel(p) (sw_crc=(sw_crc<<1)^(sw_crc<0?0x04C11DB7:0)^(p)) +#define sw_crc_byte(ch) (sw_pix=(sw_pix<<8)|(ch)) + +void SwCrcb(int ch) +{ + sw_crc_byte(ch); + if( --sw_byt > 0 ) return; + sw_byt = 3; + sw_crc_pixel(sw_pix&0xffffff); +} + +unsigned long +swcrcTest(XParms xp, Parms p,char *opt, int func, unsigned long pm) +{ + sw_crc_reset(); + DumpProc(xp,p,NULL,SwCrcb); + return (unsigned long)sw_crc; +} + +void +SwcrcTest(XParms xp, Parms p,char *opt, int func, unsigned long pm) +{ + FILE *fp; + ckcrc = swcrcTest(xp,p,opt,func,pm); + if( swfn == NULL ) return; + if( (fp=fopen(swfn,"a")) != NULL ) { + fprintf(fp,"%s_%02d %08lx\n",&opt[1],func,ckcrc); + fclose(fp); + } + else + perror("SwcrcTest fopen"); +} + +void CheckTest(XParms xp, Test *test, int func, unsigned long pm) +{ + int do_dump; + char tstnm[64]; + unsigned long crc; + if (swfn != NULL) + SwcrcTest(xp, &test->parms, test->option, func, pm); + if (crcfp != NULL) { + if( swfn == NULL ) + ckcrc = swcrcTest(xp,&test->parms,test->option,func,pm); + do_dump = 0; + if( fscanf(crcfp,"%63s %lx\n",&tstnm[0],&crc) == 2 ) { + if( ckcrc != crc ) { + do_dump = 1; + fprintf(stderr,"crcck %s %08lx!=%08lx\n",&tstnm[0],crc,ckcrc); + } + } + } + else + do_dump = 1; + if( dump != NULL && do_dump != 0 ) { + DumpTest(xp, &test->parms, test->option, func, pm); + XSetWindowBorder(xp->d, xp->w, xp->background); + XFlush(xp->d); + XSetWindowBorder(xp->d, xp->w, xp->foreground); + XFlush(xp->d); + } +} + static void PrintTime(void) { @@ -452,6 +701,11 @@ " -v1.3 perform only v1.3 tests using old semantics", " -su request save unders on windows", " -bs WhenMapped or Always (default = NotUseful)", +" -dump dump each pixmap to /_.pgm", +" -swcrc dump each pixmap swcrc to ", +" -crcck read and cmpr crcs, dump only errs", +" -wx x-coord of test window", +" -wy y-coord of test window", NULL}; fflush(stdout); @@ -583,7 +837,7 @@ static double -DoTest(XParms xp, Test *test, int reps) +DoTest(XParms xp, Test *test, int reps, int func, unsigned long pm) { double time; unsigned int ret_width, ret_height; @@ -601,6 +855,7 @@ if (drawToFakeServer) XQueryBestSize(xp->d, TileShape, tileToQuery, 32, 32, &ret_width, &ret_height); + CheckTest(xp, test, func, pm); (*test->passCleanup) (xp, &test->parms); return time; } @@ -711,7 +966,7 @@ gcvbg.background = gcvfg.background = bg; /* Double Dash GCs (This doesn't make a huge amount of sense) */ gcvddbg.foreground = gcvddfg.foreground = bg ^ fg; - gcvddbg.background = gcvddfg.foreground = bg ^ ddbg; + gcvddbg.background = gcvddfg.background = bg ^ ddbg; } else { gcvfg.foreground = fg; gcvfg.background = bg; @@ -816,7 +1071,7 @@ totalTime = 0.0; for (j = 0; j != repeat; j++) { DisplayStatus(xp->d, "Testing", label, j+1); - time = DoTest(xp, test, reps); + time = DoTest(xp, test, reps, func, pm); if (abortTest) AbortTest (); totalTime += time; @@ -854,7 +1109,6 @@ XGCValues tgcv; int screen; int rop, pm; - int window_y, window_x; XVisualInfo *vinfolist, vinfotempl; unsigned long vmask; @@ -963,6 +1217,31 @@ } else if (strcmp(argv[i], "-rop") == 0) { skip = GetRops (i+1, argc, argv, rops, &numRops); i += skip; + } else if (strcmp(argv[i], "-dump") == 0) { + i++; + if (argc <= i) usage (); + dump = argv[i]; + } else if (strcmp(argv[i], "-swcrc") == 0) { + i++; + if (argc <= i) usage (); + swfn = argv[i]; + } else if (strcmp(argv[i], "-crcck") == 0) { + i++; + if (argc <= i) usage (); + crcfn = argv[i]; + crcfp = fopen(crcfn,"r"); + if( crcfp == NULL ) { + fprintf(stderr, "unable to open crc check file - %s\n",crcfn); + exit(1); + } + } else if (strcmp(argv[i], "-wx") == 0) { + i++; + if (argc <= i) usage (); + window_x = atoi(argv[i]); + } else if (strcmp(argv[i], "-wy") == 0) { + i++; + if (argc <= i) usage (); + window_y = atoi(argv[i]); } else if (strcmp(argv[i], "-pm") == 0) { skip = GetNumbers (i+1, argc, argv, planemasks, &numPlanemasks); i += skip; @@ -1109,6 +1388,7 @@ if (!foundOne) usage (); + xparms.d = Open_Display (displayName); screen = DefaultScreen(xparms.d); @@ -1212,10 +1492,8 @@ AllocateColor(xparms.d, background, WhitePixel(xparms.d, screen)); xparms.ddbackground = AllocateColor(xparms.d, ddbackground, WhitePixel(xparms.d, screen)); - window_x = 2; if (DisplayWidth(xparms.d, screen) < WIDTH + window_x + 1) window_x = -1; - window_y = 2; if (DisplayHeight(xparms.d, screen) < HEIGHT + window_y + 1) window_y = -1; xparms.w = CreatePerfWindow(&xparms, window_x, window_y, WIDTH, HEIGHT); @@ -1225,7 +1503,7 @@ HSy = HEIGHT-1; if (window_y + 1 + HEIGHT > DisplayHeight(xparms.d, screen)) HSy = DisplayHeight(xparms.d, screen) - (1 + window_y + 1); - status = CreatePerfWindow(&xparms, window_x, HEIGHT+5, WIDTH, 20); + status = CreatePerfWindow(&xparms, window_x, window_y+HEIGHT+3, WIDTH, 20); tgcv.foreground = AllocateColor(xparms.d, "black", BlackPixel(xparms.d, screen)); tgcv.background = --- xc/programs/x11perf/x11perf.h 2005-12-14 12:12:08.476825160 -0700 +++ xc.new/programs/x11perf/x11perf.h 2005-09-30 14:57:01.000000000 -0600 @@ -299,6 +299,11 @@ extern void DoPopUps ( XParms xp, Parms p, int reps ); extern void EndPopups ( XParms xp, Parms p ); +/* do_paint.c */ +extern int InitPaint ( XParms xp, Parms p, int reps ); +extern void DoPaint ( XParms xp, Parms p, int reps ); +extern void EndPaint ( XParms xp, Parms p ); + /***************************************************************************** --- xc/programs/x11perf/Imakefile 2005-12-14 12:12:08.914758584 -0700 +++ xc.new/programs/x11perf/Imakefile 2005-09-30 14:48:00.000000000 -0600 @@ -33,13 +33,13 @@ do_lines.c do_segs.c \ do_dots.c do_windows.c do_movewin.c do_text.c \ do_blt.c do_arcs.c \ - do_tris.c do_complex.c do_traps.c + do_tris.c do_complex.c do_traps.c do_paint.c OBJS = x11perf.o bitmaps.o do_tests.o \ do_simple.o do_rects.o do_valgc.o \ do_lines.o do_segs.o \ do_dots.o do_windows.o do_movewin.o do_text.o \ do_blt.o do_arcs.o \ - do_tris.o do_complex.o do_traps.o + do_tris.o do_complex.o do_traps.o do_paint.o LOCAL_LIBRARIES = $(XFTLIBS) $(XRENDERLIBS) $(XMUULIB) $(XLIB) DEPLIBS = $(XFTDEPS) $(XRENDERDEPS) $(DEPXMUULIB) $(DEPXLIB) SYS_LIBRARIES = MathLibrary --- xc/programs/x11perf/do_tests.c 2005-12-14 12:12:09.615652032 -0700 +++ xc.new/programs/x11perf/do_tests.c 2005-09-30 14:56:21.000000000 -0600 @@ -1005,6 +1005,18 @@ {30, False, "-adobe-times-medium-r-normal--24-240-75-75-p-124-iso8859-1", NULL}}, + {"-paint8", "Paint window 8x8 color pixmap", NULL, + InitPaint, DoPaint, NullProc, EndPaint, + V1_5FEATURE, NONROP, 0, + {1, 8, NULL, NULL }}, + {"-paint33", "Paint window 33x33 color pixmap", NULL, + InitPaint, DoPaint, NullProc, EndPaint, + V1_5FEATURE, NONROP, 0, + {1, 33, NULL, NULL }}, + {"-paint65", "Paint window 65x65 color pixmap", NULL, + InitPaint, DoPaint, NullProc, EndPaint, + V1_5FEATURE, NONROP, 0, + {1, 65, NULL, NULL }}, #ifdef XFT {"-aa10text", "Char in 80-char aa line (Charter 10)", NULL, InitAAText, DoAAText, ClearTextWin, EndAAText, --- xc/programs/x11perf/do_paint.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/x11perf/do_paint.c 2005-07-13 13:16:48.000000000 -0600 @@ -0,0 +1,211 @@ +/* $Xorg: do_dots.c,v 1.3 2000/08/17 19:54:09 cpqbld Exp $ */ +/***************************************************************************** +Copyright 1988, 1989 by Digital Equipment Corporation, Maynard, Massachusetts. + + All Rights Reserved + +Permission to use, copy, modify, and distribute this software and its +documentation for any purpose and without fee is hereby granted, +provided that the above copyright notice appear in all copies and that +both that copyright notice and this permission notice appear in +supporting documentation, and that the name of Digital not be +used in advertising or publicity pertaining to distribution of the +software without specific, written prior permission. + +DIGITAL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING +ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL +DIGITAL BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR +ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, +WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS +SOFTWARE. + +******************************************************************************/ +/* $XFree86: xc/programs/x11perf/do_dots.c,v 1.4 2000/11/29 08:58:19 keithp Exp $ */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + +#include "x11perf.h" + +static GC pgc; +static int pwidth; +static int pheight; +static int ipix; + +static Pixmap bg_pixmap[2]; +static XImage *image; +static unsigned char rgbColors[256][4]; + +static unsigned long XlateColor(unsigned long pixel) +{ + unsigned char r, g, b, *cp; + int i, se, te, re, ge, be; + + b = pixel; pixel >>= 8; + g = pixel; pixel >>= 8; + r = pixel; pixel = 0; + + cp = &rgbColors[0][0]; + re = cp[0] - r; + ge = cp[1] - g; + be = cp[2] - b; + se = re*re + ge*ge + be*be; + + for( i=1; i<256; ++i ) { + cp += 4; + re = cp[0] - r; + ge = cp[1] - g; + be = cp[2] - b; + te = re*re + ge*ge + be*be; + if( te < se ) { + se = te; + pixel = i; + } + } + + return pixel; +} + +#undef iabs +#define iabs(n) ((n)<0?-(n):(n)) + +int +InitPaint(XParms xp, Parms p, int reps) +{ + int n, x, y, w1, h1, wh1; + int depth, depthfactor; + int trueColor, psize; + XColor xcolors[256]; + XWindowAttributes xwa; + Colormap colormap; + unsigned long pixel, rpix, gpix, bpix; + unsigned long rmask, gmask, bmask; + Visual *visual; + char *pixels; + + pgc = xp->fggc; + pwidth = pheight = p->special; + depth = xp->vinfo.depth; + depthfactor = (depth+7)/8; + if( depthfactor == 3 ) depthfactor = 4; + visual = xp->vinfo.visual; + psize = pheight*pwidth*depthfactor; + pixels = (char *) malloc(psize); + psize = pwidth*depthfactor; + image = XCreateImage(xp->d, visual, depth, ZPixmap, 0, + pixels, pwidth, pheight, 8, psize); + + if( visual->class != TrueColor ) { + XGetWindowAttributes(xp->d, xp->w, &xwa); + colormap = xwa.colormap; + trueColor = 0; + for( n=0; n<256; n++ ) + xcolors[n].pixel = n; + XQueryColors(xp->d,colormap,xcolors,256); + for( n = 0; n<256; n++ ) { + rgbColors[n][0] = xcolors[n].red * 255 / 65535; + rgbColors[n][1] = xcolors[n].green * 255 / 65535; + rgbColors[n][2] = xcolors[n].blue * 255 / 65535; + } + rmask = 0xff0000; + gmask = 0x00ff00; + bmask = 0x0000ff; + } + else { + trueColor = 1; + rmask = visual->red_mask; + gmask = visual->green_mask; + bmask = visual->blue_mask; + } + + w1 = pwidth - 1; + h1 = pheight - 1; + wh1 = w1 + h1; + for( x=0; xd, xp->w, pwidth,pheight, depth); + XPutImage(xp->d,bg_pixmap[0],pgc,image, 0,0, 0,0, pwidth, pheight); + + w1 = pwidth - 1; + h1 = pheight - 1; + wh1 = w1; + if( h1 > wh1 ) wh1 = h1; + for( x=0; xd, xp->w, pwidth,pheight, depth); + XPutImage(xp->d,bg_pixmap[1],pgc,image, 0,0, 0,0, pwidth, pheight); + + XDestroyImage(image); + ipix = 0; + return reps; +} + +void +DoPaint(XParms xp, Parms p, int reps) +{ + int i; + + for (i = 0; i != reps; i++) { + XSetWindowBackgroundPixmap(xp->d, xp->w, bg_pixmap[ipix]); + ipix = 1-ipix; + XClearWindow(xp->d, xp->w); + } +} + +void +EndPaint(XParms xp, Parms p) +{ + XSetWindowBackground(xp->d, xp->w, xp->background); + XClearWindow(xp->d, xp->w); + XFreePixmap(xp->d, bg_pixmap[0]); + XFreePixmap(xp->d, bg_pixmap[1]); +} + --- xc/programs/Xserver/hw/xfree86/drivers/amd/durango.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/durango.c 2005-08-03 13:15:14.000000000 -0600 @@ -0,0 +1,630 @@ +/* + * $Workfile: durango.c $ + * $Revision: #2 $ + * $Author: raymondd $ + * + * This is the main file used to add Durango graphics support to a software + * project. The main reason to have a single file include the other files + * is that it centralizes the location of the compiler options. This file + * should be tuned for a specific implementation, and then modified as needed + * for new Durango releases. The releases.txt file indicates any updates to + * this main file, such as a new definition for a new hardware platform. + * + * In other words, this file should be copied from the Durango source files + * once when a software project starts, and then maintained as necessary. + * It should not be recopied with new versions of Durango unless the + * developer is willing to tune the file again for the specific project. + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +/* COMPILER OPTIONS + * These compiler options specify how the Durango routines are compiled + * for the different hardware platforms. For best performance, a driver + * would build for a specific platform. The "dynamic" switches are set + * by diagnostic applications such as Darwin that will run on a variety + * of platforms and use the appropriate code at runtime. Each component + * may be separately dynamic, so that a driver has the option of being + * tuned for a specific 2D accelerator, but will still run with a variety + * of chipsets. + */ + +#define GFX_DISPLAY_DYNAMIC 0 /* runtime selection */ +#define GFX_DISPLAY_GU1 0 /* 1st generation display controller */ +#define GFX_DISPLAY_GU2 1 /* 2nd generation display controller */ +#define GFX_DISPLAY_GU3 0 /* 3nd generation display controller */ + +#define GFX_INIT_DYNAMIC 0 /* runtime selection */ +#define GFX_INIT_GU1 0 /* Geode family */ +#define GFX_INIT_GU2 1 /* Redcloud */ +#define GFX_INIT_GU3 0 /* Castle */ + +#define GFX_MSR_DYNAMIC 1 /* runtime selection */ +#define GFX_MSR_REDCLOUD 1 /* Redcloud */ + +#define GFX_2DACCEL_DYNAMIC 0 /* runtime selection */ +#define GFX_2DACCEL_GU1 0 /* 1st generation 2D accelerator */ +#define GFX_2DACCEL_GU2 1 /* 2nd generation 2D accelerator */ + +#define GFX_VIDEO_DYNAMIC 0 /* runtime selection */ +#define GFX_VIDEO_CS5530 0 /* support for CS5530 */ +#define GFX_VIDEO_SC1200 0 /* support for SC1200 */ +#define GFX_VIDEO_REDCLOUD 1 /* support for Redcloud */ +#define GFX_VIDEO_CASTLE 0 /* support for Castle */ + +#define GFX_VIP_DYNAMIC 0 /* runtime selection */ +#define GFX_VIP_SC1200 0 /* support for SC1200 */ + +#define GFX_DECODER_DYNAMIC 0 /* runtime selection */ +#define GFX_DECODER_SAA7114 0 /* Philips SAA7114 decoder */ + +#define GFX_TV_DYNAMIC 0 /* runtime selection */ +#define GFX_TV_FS451 0 /* Focus Enhancements FS450 */ +#define GFX_TV_SC1200 0 /* SC1200 integrated TV encoder */ + +#define GFX_I2C_DYNAMIC 0 /* runtime selection */ +#define GFX_I2C_ACCESS 0 /* support for ACCESS.BUS */ +#define GFX_I2C_GPIO 0 /* support for CS5530 GPIOs */ + +#define GFX_VGA_DYNAMIC 0 /* runtime selection */ +#define GFX_VGA_GU1 0 /* 1st generation graphics unit */ + +#define FB4MB 1 /* Set to use 4Mb video ram for Pyramid */ + +#define GFX_NO_IO_IN_WAIT_MACROS 1 /* Set to remove I/O accesses in GP bit testing */ + +/* ROUTINES TO READ VALUES + * These are routines used by Darwin or other diagnostics to read the + * current state of the hardware. Display drivers or embedded applications can + * reduce the size of the Durango code by not including these routines. + */ +#define GFX_READ_ROUTINES 1 /* add routines to read values */ + +/* HEADER FILE FOR DURANGO ROUTINE DEFINITIONS + * Needed since some of the Durango routines call other Durango routines. + * Also defines the size of chipset array (GFX_CSPTR_SIZE). + */ +#include "gfx_rtns.h" /* routine definitions */ +#include "gfx_priv.h" +/* VARIABLES USED FOR RUNTIME SELECTION + * If part of the graphics subsystem is declared as dynamic, then the + * following variables are used to specify which platform has been detected. + * The variables are set in the "gfx_detect_cpu" routine. The values should + * be bit flags to allow masks to be used to check for multiple platforms. + */ + +#if GFX_DISPLAY_DYNAMIC +int gfx_display_type = 0; +#endif + +#if GFX_INIT_DYNAMIC +int gfx_init_type = 0; +#endif + +#if GFX_MSR_DYNAMIC +int gfx_msr_type = 0; +#endif + +#if GFX_2DACCEL_DYNAMIC +int gfx_2daccel_type = 0; +#endif + +#if GFX_VIDEO_DYNAMIC +int gfx_video_type = 0; +#endif + +#if GFX_VIP_DYNAMIC +int gfx_vip_type = 0; +#endif + +#if GFX_DECODER_DYNAMIC +int gfx_decoder_type = 0; +#endif + +#if GFX_TV_DYNAMIC +int gfx_tv_type = 0; +#endif + +#if GFX_I2C_DYNAMIC +int gfx_i2c_type = 0; +#endif + +#if GFX_VGA_DYNAMIC +int gfx_vga_type = 0; +#endif + +/* DEFINE POINTERS TO MEMORY MAPPED REGIONS + * These pointers are used by the Durango routines to access the hardware. + * The variables must be set by the project's initialization code after + * mapping the regions in the appropriate manner. + */ + +/* DEFINE VIRTUAL ADDRESSES */ +/* Note: These addresses define the starting base expected by all */ +/* Durango offsets. Under an OS that requires these pointers */ +/* to be mapped to linear addresses (i.e Windows), it may not */ +/* be possible to keep these base offsets. In these cases, */ +/* the addresses are modified to point to the beginning of the */ +/* relevant memory region and the access macros are adjusted */ +/* to subtract the offset from the default base. For example, */ +/* the register pointer could be moved to be 0x40008000, while */ +/* the WRITE_REG* macros are modified to subtract 0x8000 from */ +/* the offset. */ + +unsigned char *gfx_virt_regptr = (unsigned char *)0x40000000; +unsigned char *gfx_virt_fbptr = (unsigned char *)0x40800000; +unsigned char *gfx_virt_vidptr = (unsigned char *)0x40010000; +unsigned char *gfx_virt_vipptr = (unsigned char *)0x40015000; +unsigned char *gfx_virt_spptr = (unsigned char *)0x40000000; +unsigned char *gfx_virt_gpptr = (unsigned char *)0x40000000; + +/* DEFINE PHYSICAL ADDRESSES */ + +unsigned char *gfx_phys_regptr = (unsigned char *)0x40000000; +unsigned char *gfx_phys_fbptr = (unsigned char *)0x40800000; +unsigned char *gfx_phys_vidptr = (unsigned char *)0x40010000; +unsigned char *gfx_phys_vipptr = (unsigned char *)0x40015000; + +/* HEADER FILE FOR GRAPHICS REGISTER DEFINITIONS + * This contains only constant definitions, so it should be able to be + * included in any software project as is. + */ +#include "gfx_regs.h" /* graphics register definitions */ + +/* HEADER FILE FOR REGISTER ACCESS MACROS + * This file contains the definitions of the WRITE_REG32 and similar macros + * used by the Durango routines to access the hardware. The file assumes + * that the environment can handle 32-bit pointer access. If this is not + * the case, or if there are special requirements, then this header file + * should not be included and the project must define the macros itself. + * (A project may define WRITE_REG32 to call a routine, for example). + */ +#include "gfx_defs.h" /* register access macros */ + +/* IO MACROS AND ROUTINES + * These macros must be defined before the initialization or I2C + * routines will work properly. + */ + +#if defined(OS_WIN32) /* For Windows */ + +/* VSA II CALL */ + +void +gfx_msr_asm_read(unsigned short msrReg, unsigned long msrAddr, + unsigned long *ptrHigh, unsigned long *ptrLow) +{ + unsigned long temp1, temp2; + + _asm { + mov dx, 0x0AC1C + mov eax, 0x0FC530007 + out dx, eax + add dl, 2 + mov ecx, msrAddr + mov cx, msrReg + in ax, dx; + ;EDX:EAX will contain MSR contents. + mov temp1, edx + mov temp2, eax + } + + *ptrHigh = temp1; + *ptrLow = temp2; +} + +void +gfx_msr_asm_write(unsigned short msrReg, unsigned long msrAddr, + unsigned long *ptrHigh, unsigned long *ptrLow) +{ + unsigned long temp1 = *ptrHigh; + unsigned long temp2 = *ptrLow; + + _asm { + mov dx, 0x0AC1C + mov eax, 0x0FC530007 + out dx, eax i + add dl, 2 + ;ECX contains msrAddr | msrReg + mov ecx, msrAddr + mov cx, msrReg + ; + mov ebx, temp1 + + ; + mov eax, temp2 + ; + mov esi, 0 + ; + mov edi, 0 + ;MSR is written at this point + out dx, ax + } +} + +unsigned char +gfx_inb(unsigned short port) +{ + unsigned char data; + + _asm { + pushf + mov dx, port + in al, dx + mov data, al + popf + } + return (data); +} + +unsigned short +gfx_inw(unsigned short port) +{ + unsigned short data; + + _asm { + pushf + mov dx, port + in ax, dx + mov data, ax + popf + } + return (data); +} + +unsigned long +gfx_ind(unsigned short port) +{ + unsigned long data; + + _asm { + pushf + mov dx, port + in eax, dx + mov data, eax + popf + } + return (data); +} + +void +gfx_outb(unsigned short port, unsigned char data) +{ + _asm { + pushf + mov al, data + mov dx, port + out dx, al + popf + } +} + +void +gfx_outw(unsigned short port, unsigned short data) +{ + _asm { + pushf + mov ax, data + mov dx, port + out dx, ax + popf + } +} + +void +gfx_outd(unsigned short port, unsigned long data) +{ + _asm { + pushf + mov eax, data + mov dx, port + out dx, eax + popf + } +} + +#elif defined(OS_VXWORKS) || defined (OS_LINUX) /* VxWorks and Linux */ + +extern unsigned long amd_asm_msr_vsa_rd(unsigned long, unsigned long *, + unsigned long *); +extern unsigned long amd_asm_msr_vsa_wr(unsigned long, unsigned long, + unsigned long); + +void +gfx_msr_asm_read(unsigned short msrReg, unsigned long msrAddr, + unsigned long *ptrHigh, unsigned long *ptrLow) +{ + unsigned long addr, val1, val2; + + addr = msrAddr | (unsigned long)msrReg; + amd_asm_msr_vsa_rd(addr, &val2, &val1); + *ptrHigh = val2; + *ptrLow = val1; +} + +void +gfx_msr_asm_write(unsigned short msrReg, unsigned long msrAddr, + unsigned long *ptrHigh, unsigned long *ptrLow) +{ + unsigned long addr, val1, val2; + + val2 = *ptrHigh; + val1 = *ptrLow; + addr = (msrAddr & 0xFFFF0000) | (unsigned long)msrReg; + amd_asm_msr_vsa_wr(addr, val2, val1); +} + +unsigned char +gfx_inb(unsigned short port) +{ + unsigned char value; + __asm__ volatile ("inb %1,%0":"=a" (value):"d"(port)); + + return value; +} + +unsigned short +gfx_inw(unsigned short port) +{ + unsigned short value; + __asm__ volatile ("in %1,%0":"=a" (value):"d"(port)); + + return value; +} + +unsigned long +gfx_ind(unsigned short port) +{ + unsigned long value; + __asm__ volatile ("inl %1,%0":"=a" (value):"d"(port)); + + return value; +} + +void +gfx_outb(unsigned short port, unsigned char data) +{ + __asm__ volatile ("outb %0,%1"::"a" (data), "d"(port)); +} + +void +gfx_outw(unsigned short port, unsigned short data) +{ + __asm__ volatile ("out %0,%1"::"a" (data), "d"(port)); +} + +void +gfx_outd(unsigned short port, unsigned long data) +{ + __asm__ volatile ("outl %0,%1"::"a" (data), "d"(port)); +} + +#elif defined(XFree86Server) + +#include +#include +#define INB(port) inb(port) +#define INW(port) inw(port) +#define IND(port) inl(port) +#define OUTB(port,data) outb(port, data) +#define OUTW(port,data) outw(port, data) +#define OUTD(port,data) outl(port, data) + +unsigned char gfx_inb(unsigned short port); +unsigned short gfx_inw(unsigned short port); +unsigned long gfx_ind(unsigned short port); +void gfx_outb(unsigned short port, unsigned char data); +void gfx_outw(unsigned short port, unsigned short data); +void gfx_outd(unsigned short port, unsigned long data); + +unsigned char +gfx_inb(unsigned short port) +{ + return inb(port); +} + +unsigned short +gfx_inw(unsigned short port) +{ + return inw(port); +} + +unsigned long +gfx_ind(unsigned short port) +{ + return inl(port); +} + +void +gfx_outb(unsigned short port, unsigned char data) +{ + outb(port, data); +} + +void +gfx_outw(unsigned short port, unsigned short data) +{ + outw(port, data); +} + +void +gfx_outd(unsigned short port, unsigned long data) +{ + outl(port, data); +} + +/*----------------------------------------------------------------- + * gfx_msr_asm_read + * Read the contents of a 64 bit MSR into address pointers + *-----------------------------------------------------------------*/ + +#define gfx_msr_asm_read(msr,adr,high,low) \ + __asm__ __volatile__( \ + " mov $0x0AC1C, %%edx\n" \ + " mov $0xFC530007, %%eax\n" \ + " out %%eax,%%dx\n" \ + " add $2,%%dl\n" \ + " in %%dx, %%ax" \ + : "=a" (*(low)), "=d" (*(high)) \ + : "c" (msr | adr)) + +/*----------------------------------------------------------------- + * gfx_msr_asm_write + * Write the contents of address pointers to a MSR. + *-----------------------------------------------------------------*/ + +#define gfx_msr_asm_write(msr,adr,high,low) \ + { int d0, d1, d2, d3, d4; \ + __asm__ __volatile__( \ + " mov $0x0AC1C, %%edx\n" \ + " mov $0xFC530007, %%eax\n" \ + " out %%eax,%%dx\n" \ + " add $2,%%dl\n" \ + " mov %6, %1\n" \ + " mov %7, %0\n" \ + " mov %5, %4\n" \ + " xor %3, %3\n" \ + " xor %2, %2\n" \ + " out %%ax, %%dx" \ + : "=a" (d0), "=b" (d1), "=&D" (d2), "=&S" (d3), "=c" (d4) \ + : "2" (msr | adr), "3" (*(high)), "4" (*(low))); \ + } + +#else /* else nothing */ + +unsigned char +gfx_inb(unsigned short port) +{ + /* ADD OS SPECIFIC IMPLEMENTATION */ + return (0); +} + +unsigned short +gfx_inw(unsigned short port) +{ + /* ADD OS SPECIFIC IMPLEMENTATION */ + return (0); +} + +unsigned long +gfx_ind(unsigned short port) +{ + /* ADD OS SPECIFIC IMPLEMENTATION */ + return (0); +} + +void +gfx_outb(unsigned short port, unsigned char data) +{ + /* ADD OS SPECIFIC IMPLEMENTATION */ +} + +void +gfx_outw(unsigned short port, unsigned short data) +{ + /* ADD OS SPECIFIC IMPLEMENTATION */ +} + +void +gfx_outd(unsigned short port, unsigned long data) +{ + /* ADD OS SPECIFIC IMPLEMENTATION */ +} +#endif + +#ifndef XFree86Server +#define INB(port) gfx_inb(port) +#define INW(port) gfx_inw(port) +#define IND(port) gfx_ind(port) +#define OUTB(port, data) gfx_outb(port, data) +#define OUTW(port, data) gfx_outw(port, data) +#define OUTD(port, data) gfx_outd(port, data) +#endif + +/* INITIALIZATION ROUTINES + * These routines are used during the initialization of the driver to + * perform such tasks as detecting the type of CPU and video hardware. + * The routines require the use of IO, so the above IO routines need + * to be implemented before the initialization routines will work + * properly. + */ + +#include "gfx_init.c" + +/* INCLUDE MSR ACCESS ROUTINES */ + +#include "gfx_msr.c" + +/* INCLUDE GRAPHICS ENGINE ROUTINES + * These routines are used to program the 2D graphics accelerator. If + * the project does not use graphics acceleration (direct frame buffer + * access only), then this file does not need to be included. + */ +#include "gfx_rndr.c" /* graphics engine routines */ + +/* INCLUDE DISPLAY CONTROLLER ROUTINES + * These routines are used if the display mode is set directly. If the + * project uses VGA registers to set a display mode, then these files + * do not need to be included. + */ +#include "gfx_mode.h" /* display mode tables */ +#include "gfx_disp.c" /* display controller routines */ + +/* INCLUDE VIDEO OVERLAY ROUTINES + * These routines control the video overlay hardware. + */ +#include "gfx_vid.c" /* video overlay routines */ + +/* VIDEO PORT AND VIDEO DECODER ROUTINES + * These routines rely on the I2C routines. + */ +#include "gfx_vip.c" /* video port routines */ +#include "gfx_dcdr.c" /* video decoder routines */ + +/* I2C BUS ACCESS ROUTINES + * These routines are used by the video decoder and possibly an + * external TV encoer. + */ +#include "gfx_i2c.c" /* I2C bus access routines */ + +/* TV ENCODER ROUTINES + * This file does not need to be included if the system does not + * support TV output. + */ +#include "gfx_tv.c" /* TV encoder routines */ + +/* VGA ROUTINES + * This file is used if setting display modes using VGA registers. + */ +#include "gfx_vga.c" /* VGA routines */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_version.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_version.h 2005-12-14 11:38:18.000000000 -0700 @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron Version information + * */ + +#define CIMARRON_REVISION 30103 \ No newline at end of file --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_defs.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_defs.h 2005-12-14 11:39:42.000000000 -0700 @@ -0,0 +1,734 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron hardware access macros. + * */ + +#ifndef _cim_defs_h +#define _cim_defs_h + +/*-----------------------------------------*/ +/* MEMORY ACCESS MACROS */ +/*-----------------------------------------*/ + +#ifndef CIMARRON_EXCLUDE_REGISTER_ACCESS_MACROS + +#define READ_GP32(offset) \ + (*(volatile unsigned long *)(cim_gp_ptr + (offset))) + +#define READ_REG32(offset) \ + (*(volatile unsigned long *)(cim_vg_ptr + (offset))) + +#define READ_FB32(offset) \ + (*(volatile unsigned long *)(cim_fb_ptr + (offset))) + +#define WRITE_GP32(offset, value) \ + (*(volatile unsigned long *)(cim_gp_ptr + (offset))) = (value) + +#define WRITE_REG32(offset, value) \ + (*(volatile unsigned long *)(cim_vg_ptr + (offset))) = (value) + +#define WRITE_COMMAND32(offset, value) \ + (*(unsigned long *)(cim_cmd_ptr + (offset))) = (value) + +#define WRITE_COMMAND8(offset, value) \ + (*(unsigned char *)(cim_cmd_ptr + (offset))) = (value) + +#define WRITE_FB32(offset, value) \ + (*(unsigned long *)(cim_fb_ptr + (offset))) = (value) + +#define READ_VID32(offset) \ + (*(volatile unsigned long *)(cim_vid_ptr + (offset))) + +#define WRITE_VID32(offset, value) \ + (*(volatile unsigned long *)(cim_vid_ptr + (offset))) = (value) + +#define READ_VIP32(offset) \ + (*(volatile unsigned long *)(cim_vip_ptr + (offset))) + +#define WRITE_VIP32(offset, value) \ + (*(volatile unsigned long *)(cim_vip_ptr + (offset))) = (value) + +#define READ_VOP32(offset) \ + (*(volatile unsigned long *)(cim_vid_ptr + (offset))) + +#define WRITE_VOP32(offset, value) \ + (*(volatile unsigned long *)(cim_vid_ptr + (offset))) = (value) + +#endif + +/*-----------------------------------------*/ +/* GP POLLING MACROS */ +/*-----------------------------------------*/ + +#define GP3_WAIT_WRAP(variable) \ + while(((variable = READ_GP32 (GP3_CMD_READ)) > gp3_cmd_current) || \ + (variable <= (gp3_cmd_top + GP3_BLT_COMMAND_SIZE + GP3_BLT_COMMAND_SIZE + 96))) + +#define GP3_WAIT_PRIMITIVE(variable) \ + while (((variable = READ_GP32 (GP3_CMD_READ)) > gp3_cmd_current) && \ + (variable <= (gp3_cmd_next + 96))) + +#define GP3_WAIT_BUSY \ + while(READ_GP32 (GP3_BLT_STATUS) & GP3_BS_BLT_BUSY) + +#define GP3_WAIT_PENDING \ + while(READ_GP32 (GP3_BLT_STATUS) & GP3_BS_BLT_PENDING) + +/*-----------------------------------------------------------------*/ +/* MSR MACROS */ +/* These macros facilitate interaction with the model specific */ +/* registers in GeodeLX. There are two included methods, direct */ +/* access using the rdmsr and wrmsr opcodes and an indirect method */ +/* using VSAII. */ +/*-----------------------------------------------------------------*/ + +#ifdef CIMARRON_INCLUDE_MSR_MACROS + +#if CIMARRON_MSR_DIRECT_ASM + +/*----------------------------------------------------------------- + * MSR_READ + * Read the contents of a 64 bit MSR into a data structure + *-----------------------------------------------------------------*/ + +#define MSR_READ(msr_reg, device_add, data64_ptr) \ +{ \ + unsigned long msr_add = (unsigned long)(msr_reg) | (unsigned long)(device_add); \ + unsigned long data_high, data_low; \ + _asm { mov ecx, msr_add } \ + _asm { rdmsr } \ + _asm { mov data_high, edx } \ + _asm { mov data_low, eax } \ + \ + ((Q_WORD *)(data64_ptr))->high = data_high; \ + ((Q_WORD *)(data64_ptr))->low = data_low; \ +} + +/*----------------------------------------------------------------- + * MSR_WRITE + * Write the contents of a 64 bit data structure to a MSR. + *-----------------------------------------------------------------*/ + +#define MSR_WRITE(msr_reg, device_add, data64_ptr) \ +{ \ + unsigned long msr_add = (unsigned long)(msr_reg) | (unsigned long)(device_add); \ + unsigned long data_high, data_low; \ + \ + data_high = ((Q_WORD *)(data64_ptr))->high; \ + data_low = ((Q_WORD *)(data64_ptr))->low; \ + \ + _asm { mov ecx, msr_add } \ + _asm { mov edx, data_high } \ + _asm { mov eax, data_low } \ + _asm { wrmsr } \ +} + +#elif CIMARRON_MSR_VSA_IO + +/*----------------------------------------------------------------- + * MSR_READ + * Read the contents of a 64 bit MSR into a data structure + *-----------------------------------------------------------------*/ + +#define MSR_READ(msr_reg, device_add, data64_ptr) \ +{ \ + unsigned long msr_add = (unsigned long)(msr_reg) | (unsigned long)(device_add); \ + unsigned long data_high, data_low; \ + \ + _asm { mov dx, 0x0AC1C } \ + _asm { mov eax, 0x0FC530007 } \ + _asm { out dx, eax } \ + \ + _asm { add dl, 2 } \ + _asm { mov ecx, msr_add } \ + _asm { in ax, dx } \ + _asm { mov data_high, edx } \ + _asm { mov data_low, eax } \ + \ + ((Q_WORD *)(data64_ptr))->high = data_high; \ + ((Q_WORD *)(data64_ptr))->low = data_low; \ +} + +/*----------------------------------------------------------------- + * MSR_WRITE + * Write the contents of a 64 bit data structure to a MSR. + *-----------------------------------------------------------------*/ + +#define MSR_WRITE(msr_reg, device_add, data64_ptr) \ +{ \ + unsigned long msr_add = (unsigned long)(msr_reg) | (unsigned long)(device_add); \ + unsigned long data_high, data_low; \ + \ + data_high = ((Q_WORD *)(data64_ptr))->high; \ + data_low = ((Q_WORD *)(data64_ptr))->low; \ + \ + _asm { mov dx, 0x0AC1C } \ + _asm { mov eax, 0x0FC530007 } \ + _asm { out dx, eax } \ + \ + _asm { add dl, 2 } \ + _asm { mov ecx, msr_add } \ + _asm { mov ebx, data_high } \ + _asm { mov eax, data_low } \ + \ + _asm { mov esi, 0 } \ + _asm { mov edi, 0 } \ + _asm { out dx, ax } \ +} + +#elif CIMARRON_MSR_ABSTRACTED_ASM + +/*----------------------------------------------------------------- + * MSR_READ + * Read the contents of a 64 bit MSR into a data structure + *-----------------------------------------------------------------*/ + +#define MSR_READ(msr,adr,val) \ + __asm__ __volatile__( \ + " mov $0x0AC1C, %%edx\n" \ + " mov $0xFC530007, %%eax\n" \ + " out %%eax,%%dx\n" \ + " add $2,%%dl\n" \ + " in %%dx, %%ax" \ + : "=a" ((val)->low), "=d" ((val)->high) \ + : "c" (msr | adr)) + +/*----------------------------------------------------------------- + * MSR_WRITE + * Write the contents of a 64 bit data structure to a MSR. + *-----------------------------------------------------------------*/ + +#define MSR_WRITE(msr,adr,val) \ + { int d0, d1, d2, d3, d4; \ + __asm__ __volatile__( \ + " mov $0x0AC1C, %%edx\n" \ + " mov $0xFC530007, %%eax\n" \ + " out %%eax,%%dx\n" \ + " add $2,%%dl\n" \ + " mov %5, %4\n" \ + " mov 0(%6), %1\n" \ + " mov 4(%6), %0\n" \ + " xor %3, %3\n" \ + " xor %2, %2\n" \ + " out %%ax, %%dx" \ + : "=a" (d0), "=b" (d1), "=&D" (d2), "=&S" (d3), "=c" (d4) \ + : "2" (msr | adr), "3" (val)); \ + } + +#elif CIMARRON_MSR_KERNEL_ROUTINE + +#include "asm/msr.h" + +/*----------------------------------------------------------------- + * MSR_READ + * Read the contents of a 64 bit MSR into a data structure + *-----------------------------------------------------------------*/ + +#define MSR_READ(msr_reg, device_add, data64_ptr) \ +{ \ + unsigned long addr, val1, val2; \ + \ + addr = device_add | msr_reg; \ + rdmsr (addr, val1, val2); \ + \ + ((Q_WORD *)(data64_ptr))->high = val2; \ + ((Q_WORD *)(data64_ptr))->low = val1; \ +} + +/*----------------------------------------------------------------- + * MSR_WRITE + * Read the contents of a 64 bit data structure to a MSR. + *-----------------------------------------------------------------*/ + +#define MSR_WRITE(msr_reg, device_add, data64_ptr) \ +{ \ + unsigned long addr, val1, val2; \ + \ + val2 = ((Q_WORD *)(data64_ptr))->high; \ + val1 = ((Q_WORD *)(data64_ptr))->low; \ + \ + addr = (device_add & 0xFFFF0000) | (unsigned long)msr_reg; \ + wrmsr(addr, val1, val2); \ +} + +#endif + +#endif /* #ifdef CIMARRON_INCLUDE_MSR_MACROS */ + +/*-----------------------------------------------------------------*/ +/* STRING MACROS */ +/* These macros are included to facilitate the optimization of */ +/* routines that write or copy large amounts of data. Two vesions */ +/* of these macros are included. One is intended for operating */ +/* systems that allow the use of inline assembly, while the other */ +/* is a pure C implementation for stricter operating systems. */ +/*-----------------------------------------------------------------*/ + +#ifdef CIMARRON_INCLUDE_STRING_MACROS + +#if CIMARRON_OPTIMIZE_ASSEMBLY + +/*----------------------------------------------------------------- + * WRITE_COMMAND_STRING32 + * Write a series of DWORDs to the current command buffer offset + *-----------------------------------------------------------------*/ + +#define WRITE_COMMAND_STRING32(offset, dataptr, dataoffset, dword_count) \ +{ \ + _asm { cld } \ + _asm { mov edi, cim_cmd_ptr } \ + _asm { add edi, offset } \ + _asm { mov esi, dataptr } \ + _asm { add esi, dataoffset } \ + _asm { mov ecx, dword_count } \ + _asm { rep movsd } \ +} + +/*----------------------------------------------------------------- + * WRITE_FB_STRING32 + * Write a series of DWORDS to video memory. + *-----------------------------------------------------------------*/ + +#define WRITE_FB_STRING32(offset, dataptr, dword_count) \ +{ \ + unsigned long temp = (unsigned long)(dataptr); \ + _asm { cld } \ + _asm { mov edi, cim_fb_ptr } \ + _asm { add edi, offset } \ + _asm { mov esi, temp } \ + _asm { mov ecx, dword_count } \ + _asm { rep movsd } \ +} + +/*----------------------------------------------------------------- + * WRITE_FB_CONSTANT + * Write a constant DWORD to multiple video memory addresses + *-----------------------------------------------------------------*/ + +#define WRITE_FB_CONSTANT(offset, value, dword_count) \ +{ \ + unsigned long outptr = (unsigned long)cim_fb_ptr + offset; \ + unsigned long dwords = dword_count; \ + _asm { cld } \ + _asm { mov edi, outptr } \ + _asm { mov eax, value } \ + _asm { mov ecx, dwords } \ + _asm { rep stosd } \ +} + +/*----------------------------------------------------------------- + * WRITE_HOST_SOURCE_STRING32 + * Write a series of DWORDs to the GP host source register + *-----------------------------------------------------------------*/ + +#define WRITE_HOST_SOURCE_STRING32(dataptr, dataoffset, dword_count) \ +{ \ + _asm { cld } \ + _asm { mov edi, cim_gp_ptr } \ + _asm { add edi, GP3_HST_SRC_RANGE } \ + _asm { mov esi, dataptr } \ + _asm { add esi, dataoffset } \ + _asm { mov ecx, dword_count } \ + _asm { rep movsd } \ +} + +#elif CIMARRON_OPTIMIZE_FORLOOP + +/*----------------------------------------------------------------- + * WRITE_COMMAND_STRING32 + * Write a series of DWORDs to the current command buffer offset + *-----------------------------------------------------------------*/ + +#define WRITE_COMMAND_STRING32(offset, dataptr, dataoffset, dword_count) \ +{ \ + unsigned long i; \ + unsigned long tempdata = (unsigned long)dataptr + (dataoffset); \ + unsigned long byte_off = 0; \ + for (i = 0; i < dword_count; i++, byte_off += 4) \ + WRITE_COMMAND32 ((offset) + byte_off, *((unsigned long *)(tempdata + byte_off))); \ +} + +/*----------------------------------------------------------------- + * WRITE_FB_STRING32 + * Write a series of DWORDS to video memory. + *-----------------------------------------------------------------*/ + +#define WRITE_FB_STRING32(offset, dataptr, dword_count) \ +{ \ + unsigned long i; \ + unsigned long tempdata = (unsigned long)dataptr; \ + unsigned long byte_off = 0; \ + for (i = 0; i < dword_count; i++, byte_off += 4) \ + WRITE_FB32 ((offset) + byte_off, *((unsigned long *)(tempdata + byte_off))); \ +} + +/*----------------------------------------------------------------- + * WRITE_FB_CONSTANT + * Write a constant DWORD to multiple video memory addresses + *-----------------------------------------------------------------*/ + +#define WRITE_FB_CONSTANT(offset, value, dword_count) \ +{ \ + unsigned long i; \ + unsigned long tempoffset = offset; \ + for (i = 0; i < dword_count; i++, tempoffset += 4) \ + WRITE_FB32 (tempoffset, value); \ +} + +/*----------------------------------------------------------------- + * WRITE_HOST_SOURCE_STRING32 + * Write a series of DWORDs to the GP host source register + *-----------------------------------------------------------------*/ + +#define WRITE_HOST_SOURCE_STRING32(dataptr, dataoffset, dword_count) \ +{ \ + unsigned long i; \ + unsigned long tempdata = (unsigned long)dataptr + (dataoffset); \ + unsigned long byte_off = 0; \ + for (i = 0; i < dword_count; i++, byte_off += 4) \ + WRITE_GP32 (byte_off + GP3_HST_SRC_RANGE, *((unsigned long *)(tempdata + byte_off))); \ +} + +#elif CIMARRON_OPTIMIZE_ABSTRACTED_ASM + +#define move_dw(d,s,n) \ + __asm__ __volatile__( \ + " rep\n" \ + " movsl\n" \ + : "=&c" (d0), "=&S" (d1), "=&D" (d2) \ + : "0" (n), "1" ((const char *)s), "2" ((char *)d) \ + : "memory") + +/*----------------------------------------------------------------- + * WRITE_COMMAND_STRING32 + * Write a series of DWORDs to the current command buffer offset + *-----------------------------------------------------------------*/ + +#define WRITE_COMMAND_STRING32(offset, dataptr, dataoffset, dword_count) \ +{ \ + int d0, d1, d2; \ + move_dw (cim_cmd_ptr+ ((unsigned long)(offset)), \ + ((unsigned long)(dataptr)+(dataoffset)), \ + dword_count); \ +} + +/*----------------------------------------------------------------- + * WRITE_FB_STRING32 + * Write a series of DWORDS to video memory. + *-----------------------------------------------------------------*/ + +#define WRITE_FB_STRING32(offset, dataptr, dword_count) \ +{ \ + unsigned long i; \ + unsigned long tempdata = (unsigned long)dataptr; \ + unsigned long byte_off = 0; \ + for (i = 0; i < dword_count; i++, byte_off += 4) \ + WRITE_FB32 ((offset) + byte_off, *((unsigned long *)(tempdata + byte_off))); \ +} + +/*----------------------------------------------------------------- + * WRITE_FB_CONSTANT + * Write a constant DWORD to multiple video memory addresses + *-----------------------------------------------------------------*/ + +#define WRITE_FB_CONSTANT(offset, value, dword_count) \ +{ \ + unsigned long i; \ + unsigned long tempoffset = offset; \ + for (i = 0; i < dword_count; i++, tempoffset += 4) \ + WRITE_FB32 (tempoffset, value); \ +} + +/*----------------------------------------------------------------- + * WRITE_HOST_SOURCE_STRING32 + * Write a series of DWORDs to the GP host source register + *-----------------------------------------------------------------*/ + +#define WRITE_HOST_SOURCE_STRING32(dataptr, dataoffset, dword_count) \ +{ \ + unsigned long i; \ + unsigned long tempdata = (unsigned long)dataptr + (dataoffset); \ + unsigned long byte_off = 0; \ + for (i = 0; i < dword_count; i++, byte_off += 4) \ + WRITE_GP32 (byte_off + GP3_HST_SRC_RANGE, *((unsigned long *)(tempdata + byte_off))); \ +} + +#endif + +#endif /* #ifdef CIMARRON_INCLUDE_STRING_MACROS */ + +/*----------------------------------------------------------------- + * WRITE_COMMAND_STRING8 + * Write a series of bytes to the current command buffer offset + *-----------------------------------------------------------------*/ + +#define WRITE_COMMAND_STRING8(offset, dataptr, dataoffset, byte_count) \ +{ \ + unsigned long i; \ + unsigned long array = (unsigned long)dataptr + (dataoffset); \ + for (i = 0; i < byte_count; i++) \ + WRITE_COMMAND8 ((offset) + i, *((unsigned char *)(array + i))); \ +} + +/*----------------------------------------------------------------- + * WRITE_HOST_SOURCE_STRING8 + * Write a series of bytes to the host source register + *-----------------------------------------------------------------*/ + +#define WRITE_HOST_SOURCE_STRING8(dataptr, dataoffset, byte_count) \ +{ \ + unsigned long temp1 = (unsigned long)dataptr + (dataoffset); \ + unsigned long temp2 = 0; \ + unsigned long shift = 0; \ + unsigned long counter; \ + if (byte_count) \ + { \ + for (counter = 0; counter < byte_count; counter++) \ + { \ + temp2 |= ((unsigned long)(*((unsigned char *)(temp1 + counter)))) << shift; \ + shift += 8; \ + } \ + WRITE_GP32 (GP3_HST_SRC, temp2); \ + } \ +} + +/*-----------------------------------------*/ +/* CUSTOM STRING MACROS */ +/*-----------------------------------------*/ + +#ifndef CIMARRON_EXCLUDE_CUSTOM_MACROS + +#define WRITE_CUSTOM_COMMAND_STRING32 WRITE_COMMAND_STRING32 +#define WRITE_CUSTOM_COMMAND_STRING8 WRITE_COMMAND_STRING8 + +#endif + +/*-----------------------------------------*/ +/* IO ACCESS MACROS */ +/*-----------------------------------------*/ + +#ifdef CIMARRON_INCLUDE_IO_MACROS + +#if CIMARRON_IO_DIRECT_ACCESS + +/*------------------------------------------- + * OUTD + * Writes one DWORD to a single I/O address. + *-------------------------------------------*/ + +#define OUTD(port, data) cim_outd(port, data) +void cim_outd (unsigned short port, unsigned long data) +{ + _asm { + pushf + mov eax, data + mov dx, port + out dx, eax + popf + } +} + +/*------------------------------------------- + * IND + * Reads one DWORD from a single I/O address. + *-------------------------------------------*/ + +#define IND(port) cim_ind(port) +unsigned long cim_ind (unsigned short port) +{ + unsigned long data; + _asm { + pushf + mov dx, port + in eax, dx + mov data, eax + popf + } + return data; +} + +/*------------------------------------------- + * OUTW + * Writes one WORD to a single I/O address. + *-------------------------------------------*/ + +#define OUTW(port, data) cim_outw(port, data) +void cim_outw (unsigned short port, unsigned short data) +{ + _asm { + pushf + mov ax, data + mov dx, port + out dx, ax + popf + } +} + +/*------------------------------------------- + * INW + * Reads one WORD from a single I/O address. + *-------------------------------------------*/ + +#define INW(port) cim_inw(port) +unsigned short cim_inw (unsigned short port) +{ + unsigned short data; + _asm { + pushf + mov dx, port + in ax, dx + mov data, ax + popf + } + return data; +} + +/*------------------------------------------- + * OUTB + * Writes one BYTE to a single I/O address. + *-------------------------------------------*/ + +#define OUTB(port, data) cim_outb(port, data) +void cim_outb (unsigned short port, unsigned char data) +{ + _asm { + pushf + mov al, data + mov dx, port + out dx, al + popf + } +} + +/*------------------------------------------- + * INB + * Reads one BYTE from a single I/O address. + *-------------------------------------------*/ + +#define INB(port) cim_inb(port) +unsigned char cim_inb (unsigned short port) +{ + unsigned char data; + _asm { + pushf + mov dx, port + in al, dx + mov data, al + popf + } + return data; +} + +#elif CIMARRON_IO_ABSTRACTED_ASM + +/*------------------------------------------- + * OUTD + * Writes one DWORD to a single I/O address. + *-------------------------------------------*/ + +#define OUTD(port, data) cim_outd(port, data) +void cim_outd (unsigned short port, unsigned long data); +void cim_outd (unsigned short port, unsigned long data) +{ + __asm__ __volatile__ ("outl %0,%w1" : : "a" (data), "Nd" (port)); +} + +/*------------------------------------------- + * IND + * Reads one DWORD from a single I/O address. + *-------------------------------------------*/ + +#define IND(port) cim_ind(port) +unsigned long cim_ind (unsigned short port); +unsigned long cim_ind (unsigned short port) +{ + unsigned long value; + __asm__ __volatile__ ("inl %w1,%0" : "=a" (value) : "Nd" (port) ); + + return value; +} + +/*------------------------------------------- + * OUTW + * Writes one WORD to a single I/O address. + *-------------------------------------------*/ + +#define OUTW(port, data) cim_outw(port, data) +void cim_outw (unsigned short port, unsigned short data); +void cim_outw (unsigned short port, unsigned short data) +{ + __asm__ volatile ("out %0,%1" : : "a" (data),"d" (port)); +} + +/*------------------------------------------- + * INW + * Reads one WORD from a single I/O address. + *-------------------------------------------*/ + +#define INW(port) cim_inw(port) +unsigned short cim_inw (unsigned short port); +unsigned short cim_inw (unsigned short port) +{ + unsigned short value; + __asm__ volatile ("in %1,%0" : "=a" (value) : "d" (port)); + return value; +} + +/*------------------------------------------- + * INB + * Reads one BYTE from a single I/O address. + *-------------------------------------------*/ + +#define INB(port) cim_inb(port) +unsigned char cim_inb(unsigned short port); +unsigned char cim_inb(unsigned short port) +{ + unsigned char value; + __asm__ volatile ("inb %1,%0":"=a" (value):"d"(port)); + + return value; +} + +/*------------------------------------------- + * OUTB + * Writes one BYTE to a single I/O address. + *-------------------------------------------*/ + +#define OUTB(port) cim_outb(port) +void cim_outb(unsigned short port, unsigned char data); +void cim_outb(unsigned short port, unsigned char data) +{ + __asm__ volatile ("outb %0,%1"::"a" (data), "d"(port)); +} + +#endif + +#endif /* CIMARRON_INCLUDE_IO_MACROS */ + +#endif --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_init.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_init.c 2005-12-14 11:39:08.000000000 -0700 @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron initialization routines. These routines detect a Geode LX and read + * all hardware base addresses. + * */ + +CIMARRON_STATIC unsigned long init_video_base = 0x80000900; + +/*--------------------------------------------------------------------------- + * init_detect_cpu + * + * This routine verifies that a Geode LX is present and returns the processor revision + * ID. For compatibility, this routine can also detect a Redcloud processor. + * bits[24:16] = minor version + * bits[15:8] = major version + * bits[7:0] = type (1 = Geode GX, 2 = Geode LX) + *---------------------------------------------------------------------------*/ + +int init_detect_cpu (unsigned long *cpu_revision, unsigned long *companion_revision) +{ + unsigned long bus, device, i; + unsigned long cpu_bus = 0, cpu_device = 0; + unsigned long address, data; + unsigned long num_bars, function; + int cpu_found, sb_found; + Q_WORD msr_value; + + /* SEARCH THROUGH PCI BUS */ + /* We search the PCI bus for the Geode LX or Geode GX northbridge. */ + /* We then verify that one of its functions is the graphics */ + /* controller and that all bars are filled in. */ + + cpu_found = sb_found = 0; + for (bus = 0; bus < 256; bus++) + { + for (device = 0; device < 21; device++) + { + address = 0x80000000 | (bus << 16) | (device << 11); + + data = init_read_pci (address); + + if (data == PCI_VENDOR_DEVICE_GEODEGX || data == PCI_VENDOR_DEVICE_GEODELX) + { + cpu_found = 1; + cpu_device = device; + cpu_bus = bus; + if (data == PCI_VENDOR_DEVICE_GEODEGX) + *cpu_revision = CIM_CPU_GEODEGX; + else + *cpu_revision = CIM_CPU_GEODELX; + } + else if (data == PCI_VENDOR_5535 || data == PCI_VENDOR_5536) + { + sb_found = 1; + if (data == PCI_VENDOR_5535) + *companion_revision = CIM_SB_5535; + else + *companion_revision = CIM_SB_5536; + } + + if (cpu_found && sb_found) + break; + } + if (device != 21) + break; + } + + if (bus == 256) + { + *cpu_revision = 0; + return CIM_STATUS_CPUNOTFOUND; + } + + msr_init_table(); + + if (msr_read64 (MSR_DEVICE_GEODELX_GLCP, GLCP_REVID, &msr_value) != CIM_STATUS_OK) + { + *cpu_revision = 0; + return CIM_STATUS_CPUNOTFOUND; + } + + *cpu_revision |= ((msr_value.low & 0xF0) << 4) | + ((msr_value.low & 0x0F) << 16); + + if (msr_read64 (MSR_DEVICE_5535_GLCP, GLCP_REVID, &msr_value) != CIM_STATUS_OK) + { + *cpu_revision = 0; + return CIM_STATUS_CPUNOTFOUND; + } + + *companion_revision |= ((msr_value.low & 0xF0) << 4) | + ((msr_value.low & 0x0F) << 16); + + /* SEARCH ALL FUNCTIONS FOR INTEGRATED GRAPHICS */ + + num_bars = 0; + for (function = 0; function < 7; function++) + { + address = 0x80000000 | (cpu_bus << 16) | (cpu_device << 11) | (function << 8); + data = init_read_pci (address); + + if (data == PCI_VENDOR_DEVICE_GEODEGX_VIDEO) + { + num_bars = 4; + break; + } + else if (data == PCI_VENDOR_DEVICE_GEODELX_VIDEO) + { + num_bars = 5; + break; + } + } + + /* VERIFY THAT ALL BARS ARE PRESENT */ + + if (function == 7) + return CIM_STATUS_DISPLAYUNAVAILABLE; + + for (i = 0; i < num_bars; i++) + { + data = init_read_pci (address + 0x10 + (i << 2)); + + if (data == 0 || data == 0xFFFFFFFF) + break; + } + + if (i != num_bars) + return CIM_STATUS_DISPLAYUNAVAILABLE; + + /* SAVE VIDEO BASE ADDRESS FOR FUTURE CALLS */ + + init_video_base = address; + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * init_read_pci + * + * This routine reads an unsigned long value from a PCI address. + *---------------------------------------------------------------------------*/ + +unsigned long init_read_pci (unsigned long address) +{ + OUTD (0xCF8, address); + return IND (0xCFC); +} + +/*--------------------------------------------------------------------------- + * init_read_base_addresses + * + * This routine reads all base addresses for the peripherals from the PCI BARs. + *---------------------------------------------------------------------------*/ + +int init_read_base_addresses (INIT_BASE_ADDRESSES *base_addresses) +{ + unsigned long value; + + /* READ ALL BASE ADDRESSES */ + + base_addresses->framebuffer_base = init_read_pci (init_video_base + 0x10); + base_addresses->gp_register_base = init_read_pci (init_video_base + 0x14); + base_addresses->vg_register_base = init_read_pci (init_video_base + 0x18); + base_addresses->df_register_base = init_read_pci (init_video_base + 0x1C); + base_addresses->vip_register_base = init_read_pci (init_video_base + 0x20); + + /* READ FRAME BUFFER SIZE */ + /* The frame buffer size is reported by a VSM in VSA II */ + /* Virtual Register Class = 0x02 */ + /* VG_MEM_SIZE (1MB units) = 0x00 */ + + OUTW (0xAC1C, 0xFC53); + OUTW (0xAC1C, 0x0200); + + value = (unsigned long)(INW (0xAC1E)) & 0xFE; + + base_addresses->framebuffer_size = value << 20; + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * init_read_cpu_frequency + * + * This routine returns the current CPU core frequency, in MHz. + *---------------------------------------------------------------------------*/ + +int init_read_cpu_frequency (unsigned long *cpu_frequency) +{ + /* CPU SPEED IS REPORTED BY A VSM IN VSA II */ + /* Virtual Register Class = 0x12 (Sysinfo) */ + /* CPU Speed Register = 0x01 */ + + OUTW (0xAC1C, 0xFC53); + OUTW (0xAC1C, 0x1201); + + *cpu_frequency = (unsigned long)(INW (0xAC1E)); + + return CIM_STATUS_OK; +} --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_msr.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_msr.c 2005-12-14 11:38:53.000000000 -0700 @@ -0,0 +1,396 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron MSR access routines. These routines allow the user to query the + * state of the GeodeLink Bus and read and write model-specfic registers. + * */ + +/*--------------------------------------------------------------*/ +/* MSR GLOBALS */ +/* These variables hold a local copy of the GeodeLink mapping */ +/* as well as a lookup table for easy device addressing. */ +/*--------------------------------------------------------------*/ + +GEODELINK_NODE gliu_nodes[24]; +GEODELINK_NODE msr_dev_lookup[MSR_DEVICE_EMPTY]; + +#define GET_DEVICE_ID(macrohigh, macrolow) ((macrolow >> 12) & 0xFF) + +/*--------------------------------------------------------------------------- + * msr_init_table + * + * This routine intializes the internal MSR table in Cimarron. This table is + * used for any MSR device accesses. + *---------------------------------------------------------------------------*/ + +int msr_init_table (void) +{ + Q_WORD msr_value; + unsigned int i, j; + int return_value = CIM_STATUS_OK; + + /* CHECK FOR VALID GEODELINK CONFIGURATION */ + /* The CPU and the three GLIUs are assumed to be at known static addresses, so */ + /* we will check the device IDs at these addresses as proof of a valid */ + /* GeodeLink configuration */ + + MSR_READ (MSR_GEODELINK_CAP, MSR_ADDRESS_VAIL, &msr_value); + if (GET_DEVICE_ID (msr_value.high, msr_value.low) != MSR_CLASS_CODE_VAIL) + return_value = CIM_STATUS_ERROR; + + MSR_READ (MSR_GEODELINK_CAP, MSR_ADDRESS_GLIU0, &msr_value); + if (GET_DEVICE_ID (msr_value.high, msr_value.low) != MSR_CLASS_CODE_GLIU) + return_value = CIM_STATUS_ERROR; + + MSR_READ (MSR_GEODELINK_CAP, MSR_ADDRESS_GLIU1, &msr_value); + if (GET_DEVICE_ID (msr_value.high, msr_value.low) != MSR_CLASS_CODE_GLIU) + return_value = CIM_STATUS_ERROR; + + MSR_READ (MSR_GEODELINK_CAP, MSR_ADDRESS_GLIU2, &msr_value); + if (GET_DEVICE_ID (msr_value.high, msr_value.low) != MSR_CLASS_CODE_GLIU) + return_value = CIM_STATUS_ERROR; + + if (return_value == CIM_STATUS_OK) + { + /* BUILD LOCAL COPY OF THE GEODELINK BUS */ + + msr_create_geodelink_table (gliu_nodes); + + /* CLEAR TABLE STATUS */ + + for (i = 0; i < MSR_DEVICE_EMPTY; i++) + msr_dev_lookup[i].device_id = MSR_DEVICE_NOTFOUND; + + /* CREATE EASY LOOKUP TABLE FOR FUTURE HARDWARE ACCESS */ + /* Note that MSR_DEVICE_EMPTY is the index after the last */ + /* available device. Also note that we fill in known */ + /* devices before filling in the rest of the table. */ + + msr_dev_lookup[MSR_DEVICE_GEODELX_GLIU0].address_from_cpu = MSR_ADDRESS_GLIU0; + msr_dev_lookup[MSR_DEVICE_GEODELX_GLIU0].device_id = MSR_DEVICE_PRESENT; + msr_dev_lookup[MSR_DEVICE_GEODELX_GLIU1].address_from_cpu = MSR_ADDRESS_GLIU1; + msr_dev_lookup[MSR_DEVICE_GEODELX_GLIU1].device_id = MSR_DEVICE_PRESENT; + msr_dev_lookup[MSR_DEVICE_5535_GLIU].address_from_cpu = MSR_ADDRESS_GLIU2; + msr_dev_lookup[MSR_DEVICE_5535_GLIU].device_id = MSR_DEVICE_PRESENT; + msr_dev_lookup[MSR_DEVICE_GEODELX_VAIL].address_from_cpu = MSR_ADDRESS_VAIL; + msr_dev_lookup[MSR_DEVICE_GEODELX_VAIL].device_id = MSR_DEVICE_PRESENT; + + for (i = 0; i < MSR_DEVICE_EMPTY; i++) + { + if (msr_dev_lookup[i].device_id == MSR_DEVICE_NOTFOUND) + { + for (j = 0; j < 24; j++) + { + if (gliu_nodes[j].device_id == i) + break; + } + + if (j == 24) + msr_dev_lookup[i].device_id = MSR_DEVICE_NOTFOUND; + else + { + msr_dev_lookup[i].device_id = MSR_DEVICE_PRESENT; + msr_dev_lookup[i].address_from_cpu = gliu_nodes[j].address_from_cpu; + } + } + } + } + else + { + /* ERROR OUT THE GEODELINK TABLES */ + + for (i = 0; i < 24; i++) + { + gliu_nodes[i].address_from_cpu = 0xFFFFFFFF; + gliu_nodes[i].device_id = MSR_DEVICE_EMPTY; + } + + for (i = 0; i < MSR_DEVICE_EMPTY; i++) + { + msr_dev_lookup[i].address_from_cpu = 0xFFFFFFFF; + msr_dev_lookup[i].device_id = MSR_DEVICE_NOTFOUND; + } + } + return return_value; +} + +/*--------------------------------------------------------------------------- + * msr_create_geodelink_table + * + * This routine dumps the contents of the GeodeLink bus into an array of + * 24 GEODELINK_NODE structures. Indexes 0-7 represent ports 0-7 of GLIU0, + * indexes 8-15 represent ports 0-7 of GLIU1 and indexes 16-23 represent + * ports 0-7 of GLIU2 (5535). + *---------------------------------------------------------------------------*/ + +int msr_create_geodelink_table (GEODELINK_NODE *gliu_nodes) +{ + unsigned long mbiu_port_count, reflective; + unsigned long port, index; + unsigned long gliu_count = 0; + int glcp_count = 0; + int usb_count = 0; + int mpci_count = 0; + Q_WORD msr_value; + + /* ALL THREE GLIUS ARE IN ONE ARRAY */ + /* Entries 0-7 contain the port information for GLIU0, entries */ + /* 8-15 contain GLIU1 and 15-23 contain GLIU2. We perform the */ + /* enumeration in two passes. The first simply fills in the */ + /* addresses and class codes at each node. The second pass */ + /* translates the class codes into indexes into Cimarron's device */ + /* lookup table. */ + + /* COUNT GLIU0 PORTS */ + + MSR_READ (MSR_GLIU_CAP, MSR_ADDRESS_GLIU0, &msr_value); + mbiu_port_count = (msr_value.high >> NUM_PORTS_SHIFT) & 7; + + /* FIND REFLECTIVE PORT */ + /* Query the GLIU for the port through which we are communicating. */ + /* We will avoid accesses to this port to avoid a self-reference. */ + + MSR_READ (MSR_GLIU_WHOAMI, MSR_ADDRESS_GLIU0, &msr_value); + reflective = msr_value.low & WHOAMI_MASK; + + /* SPECIAL CASE FOR PORT 0 */ + /* GLIU0 port 0 is a special case, as it points back to GLIU0. GLIU0 */ + /* responds at address 0x10000xxx, which does not equal 0 << 29. */ + + gliu_nodes[0].address_from_cpu = MSR_ADDRESS_GLIU0; + gliu_nodes[0].device_id = MSR_CLASS_CODE_GLIU; + + /* ENUMERATE ALL PORTS */ + + for (port = 1; port < 8; port++) + { + /* FILL IN ADDRESS */ + + gliu_nodes[port].address_from_cpu = port << 29; + + if (port == reflective) + gliu_nodes[port].device_id = MSR_CLASS_CODE_REFLECTIVE; + else if (port > mbiu_port_count) + gliu_nodes[port].device_id = MSR_CLASS_CODE_UNPOPULATED; + else + { + MSR_READ (MSR_GEODELINK_CAP, gliu_nodes[port].address_from_cpu, &msr_value); + gliu_nodes[port].device_id = GET_DEVICE_ID (msr_value.high, msr_value.low); + } + } + + /* COUNT GLIU1 PORTS */ + + MSR_READ (MSR_GLIU_CAP, MSR_ADDRESS_GLIU1, &msr_value); + mbiu_port_count = (msr_value.high >> NUM_PORTS_SHIFT) & 7; + + /* FIND REFLECTIVE PORT */ + + MSR_READ (MSR_GLIU_WHOAMI, MSR_ADDRESS_GLIU1, &msr_value); + reflective = msr_value.low & WHOAMI_MASK; + + /* ENUMERATE ALL PORTS */ + + for (port = 0; port < 8; port++) + { + index = port + 8; + + /* FILL IN ADDRESS */ + + gliu_nodes[index].address_from_cpu = (0x02l << 29) + (port << 26); + + if (port == reflective) + gliu_nodes[index].device_id = MSR_CLASS_CODE_REFLECTIVE; + else if (port > mbiu_port_count) + gliu_nodes[index].device_id = MSR_CLASS_CODE_UNPOPULATED; + else + { + MSR_READ (MSR_GEODELINK_CAP, gliu_nodes[index].address_from_cpu, &msr_value); + gliu_nodes[index].device_id = GET_DEVICE_ID (msr_value.high, msr_value.low); + } + } + + /* COUNT GLIU2 PORTS */ + + MSR_READ (MSR_GLIU_CAP, MSR_ADDRESS_GLIU2, &msr_value); + mbiu_port_count = (msr_value.high >> NUM_PORTS_SHIFT) & 7; + + /* FIND REFLECTIVE PORT */ + + MSR_READ (MSR_GLIU_WHOAMI, MSR_ADDRESS_GLIU2, &msr_value); + reflective = msr_value.low & WHOAMI_MASK; + + /* FILL IN PORT 0 AND 1 */ + /* Port 0 on 5535 is MBIU2. Port 1 is MPCI, but it is referenced at */ + /* a special address. */ + + gliu_nodes[16].address_from_cpu = MSR_ADDRESS_GLIU2; + gliu_nodes[16].device_id = MSR_CLASS_CODE_GLIU; + + gliu_nodes[17].address_from_cpu = MSR_ADDRESS_5535MPCI; + gliu_nodes[17].device_id = MSR_CLASS_CODE_MPCI; + + /* ENUMERATE ALL PORTS */ + + for (port = 2; port < 8; port++) + { + index = port + 16; + + /* FILL IN ADDRESS */ + + gliu_nodes[index].address_from_cpu = + (0x02l << 29) + (0x04l << 26) + (0x02l << 23) + (port << 20); + + if (port == reflective) + gliu_nodes[index].device_id = MSR_CLASS_CODE_REFLECTIVE; + else if (port > mbiu_port_count) + gliu_nodes[index].device_id = MSR_CLASS_CODE_UNPOPULATED; + else + { + MSR_READ (MSR_GEODELINK_CAP, gliu_nodes[index].address_from_cpu, &msr_value); + gliu_nodes[index].device_id = GET_DEVICE_ID (msr_value.high, msr_value.low); + } + } + + /* SECOND PASS - TRANSLATION */ + /* Now that the class codes for each device are stored in the */ + /* array, we walk through the array and translate the class */ + /* codes to table indexes. For class codes that have multiple */ + /* instances, the table indexes are sequential. */ + + for (port = 0; port < 24; port++) + { + /* SPECIAL CASE FOR GLIU UNITS */ + /* A GLIU can be both on another port and on its own port. These */ + /* end up as the same address, but are shown as duplicate nodes in */ + /* the GeodeLink table. */ + + if ((port & 7) == 0) + gliu_count = port >> 3; + + switch (gliu_nodes[port].device_id) + { + /* UNPOPULATED OR REFLECTIVE NODES */ + + case MSR_CLASS_CODE_UNPOPULATED: index = MSR_DEVICE_EMPTY; break; + case MSR_CLASS_CODE_REFLECTIVE: index = MSR_DEVICE_REFLECTIVE; break; + + /* KNOWN CLASS CODES */ + + case MSR_CLASS_CODE_GLIU: index = MSR_DEVICE_GEODELX_GLIU0 + gliu_count++; break; + case MSR_CLASS_CODE_GLCP: index = MSR_DEVICE_GEODELX_GLCP + glcp_count++; break; + case MSR_CLASS_CODE_MPCI: index = MSR_DEVICE_GEODELX_MPCI + mpci_count++; break; + case MSR_CLASS_CODE_USB: index = MSR_DEVICE_5535_USB2 + usb_count++; break; + case MSR_CLASS_CODE_USB2: index = MSR_DEVICE_5536_USB_2_0; break; + case MSR_CLASS_CODE_ATAC: index = MSR_DEVICE_5535_ATAC; break; + case MSR_CLASS_CODE_MDD: index = MSR_DEVICE_5535_MDD; break; + case MSR_CLASS_CODE_ACC: index = MSR_DEVICE_5535_ACC; break; + case MSR_CLASS_CODE_MC: index = MSR_DEVICE_GEODELX_MC; break; + case MSR_CLASS_CODE_GP: index = MSR_DEVICE_GEODELX_GP; break; + case MSR_CLASS_CODE_VG: index = MSR_DEVICE_GEODELX_VG; break; + case MSR_CLASS_CODE_DF: index = MSR_DEVICE_GEODELX_DF; break; + case MSR_CLASS_CODE_FG: index = MSR_DEVICE_GEODELX_FG; break; + case MSR_CLASS_CODE_VIP: index = MSR_DEVICE_GEODELX_VIP; break; + case MSR_CLASS_CODE_AES: index = MSR_DEVICE_GEODELX_AES; break; + case MSR_CLASS_CODE_VAIL: index = MSR_DEVICE_GEODELX_VAIL; break; + default: index = MSR_DEVICE_EMPTY; break; + } + + gliu_nodes[port].device_id = index; + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * msr_create_device_list + * + * This routine dumps a list of all known GeodeLX/5535 devices as well as their + * respective status and address. + *---------------------------------------------------------------------------*/ + +int msr_create_device_list (GEODELINK_NODE *gliu_nodes, int max_devices) +{ + int i, count; + + if (max_devices < MSR_DEVICE_EMPTY) count = max_devices; + else count = MSR_DEVICE_EMPTY; + + for (i = 0; i < count; i++) + { + gliu_nodes[i].address_from_cpu = msr_dev_lookup[i].address_from_cpu; + gliu_nodes[i].device_id = msr_dev_lookup[i].device_id; + } + + return CIM_STATUS_OK; +} + +/*-------------------------------------------------------------------- + * msr_read64 + * + * Performs a 64-bit read from 'msr_register' in device 'device'. 'device' is + * an index into Cimarron's table of known GeodeLink devices. + *-------------------------------------------------------------------*/ + +int msr_read64 (unsigned long device, unsigned long msr_register, + Q_WORD *msr_value) +{ + if (device < MSR_DEVICE_EMPTY) + { + if (msr_dev_lookup[device].device_id == MSR_DEVICE_PRESENT) + { + MSR_READ (msr_register, msr_dev_lookup[device].address_from_cpu, msr_value); + return CIM_STATUS_OK; + } + } + + msr_value->low = msr_value->high = 0; + return CIM_STATUS_DEVNOTFOUND; +} + +/*-------------------------------------------------------------------- + * msr_write64 + * + * Performs a 64-bit write to 'msr_register' in device 'device'. 'device' is + * an index into Cimarron's table of known GeodeLink devices. + *-------------------------------------------------------------------*/ + +int msr_write64 (unsigned long device, unsigned long msr_register, + Q_WORD *msr_value) +{ + if (device < MSR_DEVICE_EMPTY) + { + if (msr_dev_lookup[device].device_id == MSR_DEVICE_PRESENT) + { + MSR_WRITE (msr_register, msr_dev_lookup[device].address_from_cpu, msr_value); + return CIM_STATUS_OK; + } + } + return CIM_STATUS_DEVNOTFOUND; +} + --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_vip.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_vip.c 2005-12-14 11:38:01.000000000 -0700 @@ -0,0 +1,1582 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron VIP configuration routines. + * */ + +/*--------------------------------------------------------------------------- + * vip_initialize + * + * This routine initializes the internal module state and prepares the + * module for subsequent VIP orientated activities. + *---------------------------------------------------------------------------*/ + +int vip_initialize(VIPSETMODEBUFFER *buffer) +{ + unsigned long vip_control1, vip_control2, vip_control3; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + vip_control1 = 0; + vip_control2 = 0; + vip_control3 = 0; + + /* CONFIGURE CONTROL WORDS BASED ON MODE STRUCTURE */ + /* Note that some of the input parameters match the register fields */ + /* they represent. */ + + /* STREAM ENABLES */ + + vip_control1 |= buffer->stream_enables; + + /* VIP CAPTURE MODE */ + + vip_control1 |= buffer->operating_mode; + + /* HANDLE PLANAR CAPTURE */ + + if (buffer->flags & VIP_MODEFLAG_PLANARCAPTURE) + { + vip_control1 |= VIP_CONTROL1_PLANAR; + + if (buffer->planar_capture == VIP_420CAPTURE_EVERYLINE) + { + vip_control1 |= VIP_CONTROL1_DISABLE_DECIMATION; + } + else if (buffer->planar_capture == VIP_420CAPTURE_ALTERNATINGFIELDS) + { + if (buffer->flags & VIP_MODEFLAG_PROGRESSIVE) + return CIM_STATUS_INVALIDPARAMS; + + vip_control1 |= VIP_CONTROL1_DISABLE_DECIMATION; + vip_control3 |= VIP_CONTROL3_DECIMATE_EVEN; + } + else if (buffer->planar_capture != VIP_420CAPTURE_ALTERNATINGLINES) + return CIM_STATUS_INVALIDPARAMS; + + /* CONFIGURE THE VIDEO FIFO THRESHOLD BASED ON THE FIFO DEPTH */ + + vip_control2 |= VIP_CONTROL2_DEFAULT_VIDTH_420 << VIP_CONTROL2_VIDTH_SHIFT; + + } + else + { + vip_control2 |= VIP_CONTROL2_DEFAULT_VIDTH_422 << VIP_CONTROL2_VIDTH_SHIFT; + } + + /* CONFIGURE DEFAULT ANCILARRY THRESHOLD AND VIDEO FLUSH VALUES */ + + vip_control2 |= VIP_CONTROL2_DEFAULT_ANCTH << VIP_CONTROL2_ANCTH_SHIFT; + vip_control1 |= VIP_CONTROL1_DEFAULT_ANC_FF << VIP_CONTROL1_ANC_FF_SHIFT; + vip_control1 |= VIP_CONTROL1_DEFAULT_VID_FF << VIP_CONTROL1_VID_FF_SHIFT; + + /* PROGRAM VIP OPTIONS */ + /* The options are sanitized based on the current configuration. */ + + if (buffer->flags & VIP_MODEFLAG_PROGRESSIVE) + vip_control1 |= VIP_CONTROL1_NON_INTERLACED; + else + { + if (buffer->flags & VIP_MODEFLAG_TOGGLEEACHFIELD) + vip_control3 |= VIP_CONTROL3_BASE_UPDATE; + if (buffer->flags & VIP_MODEFLAG_INVERTPOLARITY) + vip_control2 |= VIP_CONTROL2_INVERT_POLARITY; + } + + if ((buffer->operating_mode == VIP_MODE_MSG || + buffer->operating_mode == VIP_MODE_DATA) && + (buffer->flags & VIP_MODEFLAG_FLIPMESSAGEWHENFULL)) + { + vip_control1 |= VIP_CONTROL1_MSG_STRM_CTRL; + } + + else if (buffer->operating_mode == VIP_MODE_VIP2_8BIT || + buffer->operating_mode == VIP_MODE_VIP2_16BIT) + { + if (buffer->flags & VIP_MODEFLAG_ENABLEREPEATFLAG) + vip_control2 |= VIP_CONTROL2_REPEAT_ENABLE; + if (buffer->flags & VIP_MODEFLAG_INVERTTASKPOLARITY) + vip_control3 |= VIP_CONTROL3_TASK_POLARITY; + } + + if (buffer->flags & VIP_MODEFLAG_DISABLEZERODETECT) + vip_control1 |= VIP_CONTROL1_DISABLE_ZERO_DETECT; + if (buffer->flags & VIP_MODEFLAG_10BITANCILLARY) + vip_control2 |= VIP_CONTROL2_ANC10; + + /* WRITE THE CONTROL REGISTERS */ + /* The control registers are kept 'live' to allow separate instances of */ + /* Cimarron to control the VIP hardware. */ + + WRITE_VIP32 (VIP_CONTROL1, vip_control1); + WRITE_VIP32 (VIP_CONTROL2, vip_control2); + WRITE_VIP32 (VIP_CONTROL3, vip_control3); + + /* CONFIGURE 601 PARAMETERS */ + + if (buffer->operating_mode == VIP_MODE_8BIT601 || + buffer->operating_mode == VIP_MODE_16BIT601) + { + vip_update_601_params (&buffer->vip601_settings); + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_update_601_params + * + * This routine configures all aspects of 601 VIP data capture, including + * start and stop timings and input polarities. + *---------------------------------------------------------------------------*/ + +int vip_update_601_params (VIP_601PARAMS *buffer) +{ + unsigned long vip_control3, vip_control1; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + vip_control1 = READ_VIP32 (VIP_CONTROL3); + vip_control3 = READ_VIP32 (VIP_CONTROL3); + + if (buffer->flags & VIP_MODEFLAG_VSYNCACTIVEHIGH) vip_control3 |= VIP_CONTROL3_VSYNC_POLARITY; + else vip_control3 &= ~VIP_CONTROL3_VSYNC_POLARITY; + if (buffer->flags & VIP_MODEFLAG_HSYNCACTIVEHIGH) vip_control3 |= VIP_CONTROL3_HSYNC_POLARITY; + else vip_control3 &= ~VIP_CONTROL3_HSYNC_POLARITY; + + WRITE_VIP32 (VIP_CONTROL3, vip_control3); + WRITE_VIP32 (VIP_601_HORZ_START, buffer->horz_start); + WRITE_VIP32 (VIP_601_VBI_START, buffer->vbi_start); + WRITE_VIP32 (VIP_601_VBI_END, buffer->vbi_start + buffer->vbi_height - 1); + WRITE_VIP32 (VIP_601_EVEN_START_STOP, + buffer->vert_start_even | ((buffer->vert_start_even + buffer->even_height - 1) << 16)); + WRITE_VIP32 (VIP_601_ODD_START_STOP, + buffer->vert_start_odd | ((buffer->vert_start_odd + buffer->odd_height - 1) << 16)); + WRITE_VIP32 (VIP_ODD_FIELD_DETECT, + buffer->odd_detect_start | (buffer->odd_detect_end << 16)); + + /* SPECIAL CASE FOR HORIZONTAL DATA */ + /* 601 horizontal parameters are based on the number of clocks and not the */ + /* number of pixels. */ + + if ((vip_control1 & VIP_CONTROL1_MODE_MASK) == VIP_MODE_16BIT601) + WRITE_VIP32 (VIP_601_HORZ_END, buffer->horz_start + (buffer->width << 1) + 3); + else + WRITE_VIP32 (VIP_601_HORZ_END, buffer->horz_start + buffer->width + 3); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_configure_capture_buffers + * + * This routine configures the base offsets for video, ancillary or message + * mode capture. The input structure can also contain multiple offsets, such + * that the calling application can avoid updating the structure for each flip. + * + * The new buffer addresses are written to the hardware registers although + * they may not be latched immediately. Calling vip_is_buffer_update_latched + * allows the determination of whether the update has occured. + * + * Review the Cimarron VIP API documentation to determine which buffer addresses are + * latched immediately. + *---------------------------------------------------------------------------*/ + +int vip_configure_capture_buffers (int buffer_type, VIPINPUTBUFFER *buffer) +{ + VIPINPUTBUFFER_ADDR *offsets; + unsigned long cur_buffer = buffer->current_buffer; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + if (buffer_type == VIP_BUFFER_A || buffer_type == VIP_BUFFER_601) + { + offsets = &buffer->offsets[VIP_BUFFER_TASK_A]; + + /* SET VIDEO PITCH */ + + WRITE_VIP32 (VIP_TASKA_VID_PITCH, offsets->y_pitch | (offsets->uv_pitch << 16)); + + /* SET BASE OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY) + { + WRITE_VIP32 (VIP_TASKA_VID_ODD_BASE, offsets->even_base[cur_buffer]); + WRITE_VIP32 (VIP_TASKA_VID_EVEN_BASE, offsets->odd_base[cur_buffer]); + if (buffer->flags & VIP_INPUTFLAG_VBI) + { + WRITE_VIP32 (VIP_TASKA_VBI_ODD_BASE, offsets->vbi_even_base); + WRITE_VIP32 (VIP_TASKA_VBI_EVEN_BASE, offsets->vbi_odd_base); + } + } + else + { + WRITE_VIP32 (VIP_TASKA_VID_ODD_BASE, offsets->odd_base[cur_buffer]); + WRITE_VIP32 (VIP_TASKA_VID_EVEN_BASE, offsets->even_base[cur_buffer]); + if (buffer->flags & VIP_INPUTFLAG_VBI) + { + WRITE_VIP32 (VIP_TASKA_VBI_ODD_BASE, offsets->vbi_odd_base); + WRITE_VIP32 (VIP_TASKA_VBI_EVEN_BASE, offsets->vbi_even_base); + } + } + + /* SET 4:2:0 OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_PLANAR) + { + WRITE_VIP32 (VIP_TASKA_U_OFFSET, offsets->odd_uoffset); + WRITE_VIP32 (VIP_TASKA_V_OFFSET, offsets->odd_voffset); + WRITE_VIP32 (VIP_TASKA_U_EVEN_OFFSET, offsets->even_uoffset); + WRITE_VIP32 (VIP_TASKA_V_EVEN_OFFSET, offsets->even_voffset); + } + } + else if (buffer_type == VIP_BUFFER_B) + { + offsets = &buffer->offsets[VIP_BUFFER_TASK_B]; + + /* SET VIDEO PITCH */ + + WRITE_VIP32 (VIP_TASKB_VID_PITCH, offsets->y_pitch | (offsets->uv_pitch << 16)); + + /* SET BASE OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY) + { + WRITE_VIP32 (VIP_TASKB_VID_ODD_BASE, offsets->even_base[cur_buffer]); + WRITE_VIP32 (VIP_TASKB_VID_EVEN_BASE, offsets->odd_base[cur_buffer]); + if (buffer->flags & VIP_INPUTFLAG_VBI) + { + WRITE_VIP32 (VIP_TASKB_VBI_ODD_BASE, offsets->vbi_even_base); + WRITE_VIP32 (VIP_TASKB_VBI_EVEN_BASE, offsets->vbi_odd_base); + } + } + else + { + WRITE_VIP32 (VIP_TASKB_VID_ODD_BASE, offsets->odd_base[cur_buffer]); + WRITE_VIP32 (VIP_TASKB_VID_EVEN_BASE, offsets->even_base[cur_buffer]); + if (buffer->flags & VIP_INPUTFLAG_VBI) + { + WRITE_VIP32 (VIP_TASKB_VBI_ODD_BASE, offsets->vbi_odd_base); + WRITE_VIP32 (VIP_TASKB_VBI_EVEN_BASE, offsets->vbi_even_base); + } + } + + /* SET 4:2:0 OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_PLANAR) + { + WRITE_VIP32 (VIP_TASKB_U_OFFSET, offsets->odd_uoffset); + WRITE_VIP32 (VIP_TASKB_V_OFFSET, offsets->odd_voffset); + } + } + else if (buffer_type == VIP_BUFFER_ANC || buffer_type == VIP_BUFFER_MSG) + { + WRITE_VIP32(VIP_ANC_MSG1_BASE, buffer->ancillaryData.msg1_base); + WRITE_VIP32(VIP_ANC_MSG2_BASE, buffer->ancillaryData.msg2_base); + WRITE_VIP32(VIP_ANC_MSG_SIZE, buffer->ancillaryData.msg_size); + } + else + { + return CIM_STATUS_INVALIDPARAMS; + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_toggle_vip_video_offsets + * + * This routine updates the offsets for video capture. It is a simplified + * version of vip_configure_capture_buffers that is designed to be called from + * interrupt service routines or other buffer flipping applications that + * require low latency. + *---------------------------------------------------------------------------*/ + +int vip_toggle_video_offsets (int buffer_type, VIPINPUTBUFFER *buffer) +{ + unsigned long cur_buffer = buffer->current_buffer; + VIPINPUTBUFFER_ADDR *offsets; + + if (buffer_type == VIP_BUFFER_A) + { + offsets = &buffer->offsets[VIP_BUFFER_TASK_A]; + + /* SET BASE OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY) + { + WRITE_VIP32 (VIP_TASKA_VID_ODD_BASE, offsets->even_base[cur_buffer]); + WRITE_VIP32 (VIP_TASKA_VID_EVEN_BASE, offsets->odd_base[cur_buffer]); + } + else + { + WRITE_VIP32 (VIP_TASKA_VID_ODD_BASE, offsets->odd_base[cur_buffer]); + WRITE_VIP32 (VIP_TASKA_VID_EVEN_BASE, offsets->even_base[cur_buffer]); + } + } + else if (buffer_type == VIP_BUFFER_B) + { + offsets = &buffer->offsets[VIP_BUFFER_TASK_B]; + + /* SET BASE OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY) + { + WRITE_VIP32 (VIP_TASKB_VID_ODD_BASE, offsets->even_base[cur_buffer]); + WRITE_VIP32 (VIP_TASKB_VID_EVEN_BASE, offsets->odd_base[cur_buffer]); + } + else + { + WRITE_VIP32 (VIP_TASKB_VID_ODD_BASE, offsets->odd_base[cur_buffer]); + WRITE_VIP32 (VIP_TASKB_VID_EVEN_BASE, offsets->even_base[cur_buffer]); + } + } + else if (buffer_type == VIP_BUFFER_A_ODD) + { + offsets = &buffer->offsets[VIP_BUFFER_TASK_A]; + + /* SET BASE OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY) + WRITE_VIP32 (VIP_TASKA_VID_ODD_BASE, offsets->even_base[cur_buffer]); + else + WRITE_VIP32 (VIP_TASKA_VID_ODD_BASE, offsets->odd_base[cur_buffer]); + } + else if (buffer_type == VIP_BUFFER_A_EVEN) + { + offsets = &buffer->offsets[VIP_BUFFER_TASK_A]; + + /* SET BASE OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY) + WRITE_VIP32 (VIP_TASKA_VID_EVEN_BASE, offsets->odd_base[cur_buffer]); + else + WRITE_VIP32 (VIP_TASKA_VID_EVEN_BASE, offsets->even_base[cur_buffer]); + } + else if (buffer_type == VIP_BUFFER_B_ODD) + { + offsets = &buffer->offsets[VIP_BUFFER_TASK_B]; + + /* SET BASE OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY) + WRITE_VIP32 (VIP_TASKB_VID_ODD_BASE, offsets->even_base[cur_buffer]); + else + WRITE_VIP32 (VIP_TASKB_VID_ODD_BASE, offsets->odd_base[cur_buffer]); + } + else if (buffer_type == VIP_BUFFER_B_EVEN) + { + offsets = &buffer->offsets[VIP_BUFFER_TASK_B]; + + /* SET BASE OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY) + WRITE_VIP32 (VIP_TASKB_VID_EVEN_BASE, offsets->odd_base[cur_buffer]); + else + WRITE_VIP32 (VIP_TASKB_VID_EVEN_BASE, offsets->even_base[cur_buffer]); + } + else + return CIM_STATUS_INVALIDPARAMS; + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_set_capture_state + * + * This routine takes the current control word definition ( stored in locals ) + * adds in the specified state, and writes the control word. + *---------------------------------------------------------------------------*/ + +int vip_set_capture_state (unsigned long state) +{ + unsigned long vip_control1, vip_control3; + + /* UPDATE THE CURRENT CAPTURE MODE */ + + vip_control1 = READ_VIP32 (VIP_CONTROL1); + vip_control3 = READ_VIP32 (VIP_CONTROL3); + vip_control1 &= ~VIP_CONTROL1_RUNMODE_MASK; + vip_control1 |= (state << VIP_CONTROL1_RUNMODE_SHIFT); + + WRITE_VIP32 (VIP_CONTROL1, vip_control1); + + if (state >= VIP_STARTCAPTUREATNEXTLINE) + { + /* WHACK VIP RESET */ + /* The VIP can get confused when switching between capture settings, such as */ + /* between linear and planar. We will thus whack VIP reset when enabling */ + /* capture to ensure a pristine VIP state. */ + + WRITE_VIP32 (VIP_CONTROL1, vip_control1 | VIP_CONTROL1_RESET); + WRITE_VIP32 (VIP_CONTROL1, vip_control1 & ~VIP_CONTROL1_RESET); + WRITE_VIP32 (VIP_CONTROL3, vip_control3 | VIP_CONTROL3_FIFO_RESET); + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_terminate + * + * This routine stops VIP capture and resets the VIP internal state. + *---------------------------------------------------------------------------*/ + +int vip_terminate (void) +{ + unsigned long timeout = 50000; + + /* DISABLE AND CLEAR ALL VIP INTERRUPTS */ + + WRITE_VIP32 (VIP_INTERRUPT, VIP_ALL_INTERRUPTS | (VIP_ALL_INTERRUPTS >> 16)); + + /* DISABLE VIP CAPTURE */ + /* We will try to let the VIP FIFO flush before shutting it down. */ + + WRITE_VIP32 (VIP_CONTROL1, 0); + while (timeout) + { + timeout--; + if (READ_VIP32 (VIP_STATUS) & VIP_STATUS_WRITES_COMPLETE) + break; + } + + /* RESET THE HARDWARE REGISTERS */ + /* Note that we enable VIP reset to allow clock gating to lower VIP */ + /* power consumption. */ + + WRITE_VIP32 (VIP_CONTROL1, VIP_CONTROL1_RESET); + WRITE_VIP32 (VIP_CONTROL3, VIP_CONTROL3_FIFO_RESET); + WRITE_VIP32 (VIP_CONTROL2, 0); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_configure_fifo + * + * This routine sets the desired threshold or flush for the specified fifo. + *---------------------------------------------------------------------------*/ + +int vip_configure_fifo (unsigned long fifo_type, unsigned long fifo_size) +{ + unsigned long vip_control1, vip_control2; + + vip_control1 = READ_VIP32 (VIP_CONTROL1); + vip_control2 = READ_VIP32 (VIP_CONTROL2); + + switch (fifo_type) + { + case VIP_VIDEOTHRESHOLD: + vip_control2 &= ~VIP_CONTROL2_VIDTH_MASK; + vip_control2 |= (fifo_size << VIP_CONTROL2_VIDTH_SHIFT) & VIP_CONTROL2_VIDTH_MASK; + break; + + case VIP_ANCILLARYTHRESHOLD: + vip_control2 &= ~VIP_CONTROL2_ANCTH_MASK; + vip_control2 |= (fifo_size << VIP_CONTROL2_ANCTH_SHIFT) & VIP_CONTROL2_ANCTH_MASK; + break; + + case VIP_VIDEOFLUSH: + vip_control1 &= ~VIP_CONTROL1_VID_FF_MASK; + vip_control1 |= ((fifo_size >> 2) << VIP_CONTROL1_VID_FF_SHIFT) & VIP_CONTROL1_VID_FF_MASK; + break; + + case VIP_ANCILLARYFLUSH: + vip_control1 &= ~VIP_CONTROL1_ANC_FF_MASK; + vip_control1 |= ((fifo_size >> 2) << VIP_CONTROL1_ANC_FF_SHIFT) & VIP_CONTROL1_ANC_FF_MASK; + break; + + default: + return CIM_STATUS_INVALIDPARAMS; + } + + WRITE_VIP32 (VIP_CONTROL1, vip_control1); + WRITE_VIP32 (VIP_CONTROL2, vip_control2); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_set_interrupt_enable + * + * This routine accepts a mask of interrupts to be enabled/disabled and + * an enable flag. + * + * For each mask match, the interrupt will be enabled or disabled based on + * enable + *---------------------------------------------------------------------------*/ + +int vip_set_interrupt_enable (unsigned long mask, int enable) +{ + /* CHECK IF ANY VALID INTERRUPTS ARE BEING CHANGED */ + + if (mask & VIP_ALL_INTERRUPTS) + { + unsigned long int_enable = READ_VIP32(VIP_INTERRUPT) & 0xFFFF; + + /* SET OR CLEAR THE MASK BITS */ + /* Note that the upper 16-bits of the register are 0 after this */ + /* operation. This prevents us from indadvertently clearing a */ + /* pending interrupt by enabling/disabling another one. */ + + if (enable) int_enable &= ~(mask >> 16); + else int_enable |= (mask >> 16); + + WRITE_VIP32 (VIP_INTERRUPT, int_enable); + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_set_vsync_error + * + * This routine defines a region that is used to determine if the vsync is + * within an acceptable range. This definition is accomplished using + * a count and a vertical window. The count specifies the exact number + * of clocks expected for one field. The window parameters specify the number + * of clocks variation allowed before and after the expected vsync. For + * example, if vertical_count is 1000, window_before is 5 and window_after + * is 12, VSync will be considered valid if it occurs between 995 and 1012 + * clocks after the last VSync. The total window size (window_before + window_after) + * cannot exceed 255. + *---------------------------------------------------------------------------*/ + +int vip_set_vsync_error (unsigned long vertical_count, unsigned long window_before, + unsigned long window_after, int enable) +{ + unsigned long vip_control2 = READ_VIP32 (VIP_CONTROL2); + unsigned long temp; + + if (enable) + { + /* CREATE THE VERTICAL WINDOW */ + /* The VIP uses two counters. The first counter defines the minimum clock count */ + /* before a valid VSync can occur. The second counter starts after the first */ + /* completes and defines the acceptable region of variation. */ + + temp = ((window_before + window_after) << VIP_VSYNC_ERR_WINDOW_SHIFT) & VIP_VSYNC_ERR_WINDOW_MASK; + temp |= (vertical_count - window_before) & VIP_VSYNC_ERR_COUNT_MASK; + + vip_control2 |= VIP_CONTROL2_VERTERROR_ENABLE; + + WRITE_VIP32(VIP_VSYNC_ERR_COUNT, temp); + } + else + { + vip_control2 &= ~VIP_CONTROL2_VERTERROR_ENABLE; + } + WRITE_VIP32 (VIP_CONTROL2, vip_control2); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_max_address_enable + * + * This routine specifies the maximum address to which the the hardware should + * write during data storage. If this value is exceeded an error is generated, + * (this may be monitored using the appropriate interrupt flags - see + * vip_set_interrupt_enable) + *---------------------------------------------------------------------------*/ + +int vip_max_address_enable (unsigned long max_address, int enable) +{ + unsigned long vip_control2 = READ_VIP32 (VIP_CONTROL2); + + if (enable) + { + /* ENABLE THE CONTROL BIT */ + + vip_control2 |= VIP_CONTROL2_ADD_ERROR_ENABLE; + + WRITE_VIP32(VIP_MAX_ADDRESS, max_address & VIP_MAXADDR_MASK); + } + else + { + /* DISABLE DETECTION */ + + vip_control2 &= ~VIP_CONTROL2_ADD_ERROR_ENABLE; + } + WRITE_VIP32 (VIP_CONTROL2, vip_control2); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_set_loopback_enable + * + * This routine enables/disables internal loopback functionality. When + * loopback is enabled, the VOP outputs are rerouted to the VIP inputs + * internal to the chip. No loopback connector is required. + *---------------------------------------------------------------------------*/ + +int vip_set_loopback_enable(int enable) +{ + unsigned long vip_control2 = READ_VIP32 (VIP_CONTROL2); + + if (enable) vip_control2 |= VIP_CONTROL2_LOOPBACK_ENABLE; + else vip_control2 &= ~VIP_CONTROL2_LOOPBACK_ENABLE; + + WRITE_VIP32 (VIP_CONTROL2, vip_control2); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_configure_genlock + * + * This routine configures genlock functionality. + *---------------------------------------------------------------------------*/ + +int vip_configure_genlock (VIPGENLOCKBUFFER *buffer) +{ + unsigned long vip_control1, vip_control2; + unsigned long unlock, genlk_ctl; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + unlock = READ_REG32 (DC3_UNLOCK); + genlk_ctl = READ_REG32 (DC3_GENLK_CTL); + vip_control1 = READ_VIP32 (VIP_CONTROL1); + vip_control2 = READ_VIP32 (VIP_CONTROL2); + + /* UPDATE VIDEO DETECTION */ + /* These flags are used to indicate the ways in which the VIP signal can */ + /* be considered 'lost'. */ + + vip_control1 &= ~VIP_CONTROL1_VDE_FF_MASK; + vip_control2 &= ~(VIP_CONTROL2_FIELD2VG_MASK | VIP_CONTROL2_SYNC2VG_MASK); + vip_control1 |= buffer->vip_signal_loss; + + /* UPDATE FIELD AND VSYNC INFORMATION */ + /* These flags control how and when the even/odd field and Vsync */ + /* information is communicated to the VG. */ + + vip_control2 |= buffer->field_to_vg; + vip_control2 |= buffer->vsync_to_vg; + + /* ENABLE OR DISABLE GENLOCK TIMEOUT */ + /* Enabling genlock timeout allows the VG to revert to its own sync */ + /* timings when the VIP input is lost. Note that the VIP will not */ + /* know the signal is lost unless the appropriate error detection */ + /* flags have been enabled inside vip_initialize. */ + + if (buffer->enable_timeout) genlk_ctl |= DC3_GC_GENLOCK_TO_ENABLE; + else genlk_ctl &= ~DC3_GC_GENLOCK_TO_ENABLE; + + genlk_ctl &= ~DC3_GC_GENLOCK_SKEW_MASK; + genlk_ctl |= buffer->genlock_skew & DC3_GC_GENLOCK_SKEW_MASK; + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_GENLK_CTL, genlk_ctl); + WRITE_VIP32 (VIP_CONTROL1, vip_control1); + WRITE_VIP32 (VIP_CONTROL2, vip_control2); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_set_genlock_enable + * + * This routine enables/disables genlock inside the VG. + *---------------------------------------------------------------------------*/ + +int vip_set_genlock_enable (int enable) +{ + unsigned long unlock, temp; + + unlock = READ_REG32 (DC3_UNLOCK); + temp = READ_REG32 (DC3_GENLK_CTL); + + if (enable) temp |= DC3_GC_GENLOCK_ENABLE; + else temp &= ~DC3_GC_GENLOCK_ENABLE; + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_GENLK_CTL, temp); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_set_power_characteristics + * + * This routine takes a VIPPOWERBUFFER structure, and selectively sets the + * GeodeLink power and/or Vip clock power states. + *---------------------------------------------------------------------------*/ + +int vip_set_power_characteristics (VIPPOWERBUFFER *buffer) +{ + Q_WORD q_word; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + q_word.low = q_word.high = 0; + + /* ENABLE GEODELINK CLOCK GATING */ + + if (buffer->glink_clock_mode) + q_word.low |= VIP_MSR_POWER_GLINK; + + /* ENABLE VIP CLOCK GATING */ + + if (buffer->vip_clock_mode) + q_word.low |= VIP_MSR_POWER_CLOCK; + + /* WRITE THE NEW VALUE */ + + msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_PM, &q_word); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_set_priority_characteristics + * + * This routine programs the VIP GeodeLink priority characteristics + *---------------------------------------------------------------------------*/ + +int vip_set_priority_characteristics (VIPPRIORITYBUFFER *buffer) +{ + Q_WORD q_word; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + q_word.low = q_word.high = 0; + + q_word.low |= (buffer->secondary << VIP_MSR_MCR_SECOND_PRIORITY_SHIFT) & VIP_MSR_MCR_SECOND_PRIORITY_MASK; + q_word.low |= (buffer->primary << VIP_MSR_MCR_PRIMARY_PRIORITY_SHIFT) & VIP_MSR_MCR_PRIMARY_PRIORITY_MASK; + q_word.low |= (buffer->pid << VIP_MSR_MCR_PID_SHIFT) & VIP_MSR_MCR_PID_MASK; + + msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_CONFIG, &q_word); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_set_debug_characteristics + * + * This routine configures the debug data that is exposed over the diag bus. + *---------------------------------------------------------------------------*/ + +int vip_set_debug_characteristics (VIPDEBUGBUFFER *buffer) +{ + Q_WORD q_word; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + q_word.low = q_word.high = 0; + + q_word.high |= (buffer->bist << VIP_MSR_DIAG_BIST_SHIFT) & VIP_MSR_DIAG_BIST_WMASK; + q_word.low |= (buffer->enable_upper ? VIP_MSR_DIAG_MSB_ENABLE : 0x00000000); + q_word.low |= (buffer->select_upper << VIP_MSR_DIAG_SEL_UPPER_SHIFT) & VIP_MSR_DIAG_SEL_UPPER_MASK; + q_word.low |= (buffer->enable_lower ? VIP_MSR_DIAG_LSB_ENABLE : 0x00000000 ); + q_word.low |= (buffer->select_lower << VIP_MSR_DIAG_SEL_LOWER_SHIFT) & VIP_MSR_DIAG_SEL_LOWER_MASK; + + msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_DIAG, &q_word); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_configure_pages + * + * This routine sets the number of pages, and their offset from each other. + *---------------------------------------------------------------------------*/ + +int vip_configure_pages (int page_count, unsigned long page_offset) +{ + unsigned long vip_control2 = READ_VIP32 (VIP_CONTROL2); + + /* SET THE NEW PAGE COUNT */ + + vip_control2 &= ~VIP_CONTROL2_PAGECNT_MASK; + vip_control2 |= (page_count << VIP_CONTROL2_PAGECNT_SHIFT) & VIP_CONTROL2_PAGECNT_MASK; + + /* WRITE THE PAGE OFFSET */ + + WRITE_VIP32 (VIP_CONTROL2, vip_control2); + WRITE_VIP32 (VIP_PAGE_OFFSET, page_offset); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_set_interrupt_line + * + * This routine sets the line at which a line interrupt should be generated. + *---------------------------------------------------------------------------*/ + +int vip_set_interrupt_line (int line) +{ + WRITE_VIP32 (VIP_CURRENT_TARGET, (line << VIP_CTARGET_TLINE_SHIFT) & VIP_CTARGET_TLINE_MASK); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_reset + * + * This routine does a one-shot enable of the VIP hardware. It is useful + * for handling unrecoverable VIP errors. + *---------------------------------------------------------------------------*/ + +int vip_reset (void) +{ + unsigned long vip_control1, vip_control3; + + /* INVERT THE PAUSE BIT */ + + vip_control1 = READ_VIP32 (VIP_CONTROL1); + vip_control3 = READ_VIP32 (VIP_CONTROL3); + + WRITE_VIP32 (VIP_CONTROL1, vip_control1 | VIP_CONTROL1_RESET); + WRITE_VIP32 (VIP_CONTROL1, vip_control1 & ~VIP_CONTROL1_RESET); + WRITE_VIP32 (VIP_CONTROL3, vip_control3 | VIP_CONTROL3_FIFO_RESET); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_set_subwindow_enable + * + * This routine turns on SubWindow capture, that is a portion of the incoming + * signal is captured rather than the entire frame. The window always has + * the same width as the frame, only the vertical component can be + * modified. + *---------------------------------------------------------------------------*/ + +int vip_set_subwindow_enable (VIPSUBWINDOWBUFFER *buffer) +{ + unsigned long vip_control2; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + vip_control2 = READ_VIP32 (VIP_CONTROL2); + if (buffer->enable) + { + /* WRITE THE WINDOW VALUE */ + + WRITE_VIP32(VIP_VERTICAL_START_STOP, + ((buffer->stop << VIP_VSTART_VERTEND_SHIFT) & VIP_VSTART_VERTEND_MASK) | + ((buffer->start << VIP_VSTART_VERTSTART_SHIFT) & VIP_VSTART_VERTSTART_MASK)); + + /* ENABLE IN THE CONTROL REGISTER */ + + vip_control2 |= VIP_CONTROL2_SWC_ENABLE; + } + else + { + /* DISABLE SUBWINDOW CAPTURE IN THE CONTROL REGISTER */ + + vip_control2 &= ~VIP_CONTROL2_SWC_ENABLE; + } + WRITE_VIP32 (VIP_CONTROL2, vip_control2); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_reset_interrupt_state + * + * This routine resets the state of one or more interrupts. + *---------------------------------------------------------------------------*/ + +int vip_reset_interrupt_state(unsigned long interrupt_mask) +{ + unsigned long temp; + + temp = READ_VIP32(VIP_INTERRUPT); + WRITE_VIP32 (VIP_INTERRUPT, temp | (interrupt_mask & VIP_ALL_INTERRUPTS)); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_save_state + * + * This routine saves the necessary register contents in order to restore + * at a later point to the same state. + * + * NOTE: Capture state is forced to OFF in this routine + *---------------------------------------------------------------------------*/ + +int vip_save_state(VIPSTATEBUFFER *save_buffer) +{ + if (!save_buffer) + return CIM_STATUS_INVALIDPARAMS; + + /* FORCE CAPTURE TO BE DISABLED */ + + vip_set_capture_state (VIP_STOPCAPTURE); + + /* READ AND SAVE THE REGISTER CONTENTS */ + + save_buffer->control1 = READ_VIP32(VIP_CONTROL1); + save_buffer->control2 = READ_VIP32(VIP_CONTROL2); + save_buffer->vip_int = READ_VIP32(VIP_INTERRUPT); + save_buffer->current_target = READ_VIP32(VIP_CURRENT_TARGET); + save_buffer->max_address = READ_VIP32(VIP_MAX_ADDRESS); + save_buffer->taska_evenbase = READ_VIP32(VIP_TASKA_VID_EVEN_BASE); + save_buffer->taska_oddbase = READ_VIP32(VIP_TASKA_VID_ODD_BASE); + save_buffer->taska_vbi_evenbase = READ_VIP32(VIP_TASKA_VBI_EVEN_BASE); + save_buffer->taska_vbi_oddbase = READ_VIP32(VIP_TASKA_VBI_ODD_BASE); + save_buffer->taska_data_pitch = READ_VIP32(VIP_TASKA_VID_PITCH); + save_buffer->control3 = READ_VIP32(VIP_CONTROL3); + save_buffer->taska_v_oddoffset = READ_VIP32(VIP_TASKA_U_OFFSET); + save_buffer->taska_u_oddoffset = READ_VIP32(VIP_TASKA_V_OFFSET); + save_buffer->taskb_evenbase = READ_VIP32(VIP_TASKB_VID_EVEN_BASE); + save_buffer->taskb_oddbase = READ_VIP32(VIP_TASKB_VID_ODD_BASE); + save_buffer->taskb_vbi_evenbase = READ_VIP32(VIP_TASKB_VBI_EVEN_BASE); + save_buffer->taskb_vbi_oddbase = READ_VIP32(VIP_TASKB_VBI_ODD_BASE); + save_buffer->taskb_pitch = READ_VIP32(VIP_TASKB_VID_PITCH); + save_buffer->taskb_voffset = READ_VIP32(VIP_TASKB_U_OFFSET); + save_buffer->taskb_uoffset = READ_VIP32(VIP_TASKB_V_OFFSET); + save_buffer->msg1_base = READ_VIP32(VIP_ANC_MSG1_BASE); + save_buffer->msg2_base = READ_VIP32(VIP_ANC_MSG2_BASE); + save_buffer->msg_size = READ_VIP32(VIP_ANC_MSG_SIZE); + save_buffer->page_offset = READ_VIP32(VIP_PAGE_OFFSET); + save_buffer->vert_start_stop = READ_VIP32(VIP_VERTICAL_START_STOP); + save_buffer->vsync_err_count = READ_VIP32(VIP_VSYNC_ERR_COUNT); + save_buffer->taska_u_evenoffset = READ_VIP32(VIP_TASKA_U_EVEN_OFFSET); + save_buffer->taska_v_evenoffset = READ_VIP32(VIP_TASKA_V_EVEN_OFFSET); + + /* READ ALL VIP MSRS */ + + msr_read64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_CONFIG, &(save_buffer->msr_config)); + msr_read64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_SMI, &(save_buffer->msr_smi)); + msr_read64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_PM, &(save_buffer->msr_pm)); + msr_read64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_DIAG, &(save_buffer->msr_diag)); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_restore_state + * + * This routine restores the state of the vip registers - which were + * previously saved using vip_save_state. + *---------------------------------------------------------------------------*/ + +int vip_restore_state (VIPSTATEBUFFER *restore_buffer) +{ + if (!restore_buffer) + return CIM_STATUS_OK; + + /* RESTORE THE REGISTERS */ + + WRITE_VIP32(VIP_CURRENT_TARGET, restore_buffer->current_target); + WRITE_VIP32(VIP_MAX_ADDRESS, restore_buffer->max_address); + WRITE_VIP32(VIP_TASKA_VID_EVEN_BASE, restore_buffer->taska_evenbase); + WRITE_VIP32(VIP_TASKA_VID_ODD_BASE, restore_buffer->taska_oddbase); + WRITE_VIP32(VIP_TASKA_VBI_EVEN_BASE, restore_buffer->taska_vbi_evenbase); + WRITE_VIP32(VIP_TASKA_VBI_ODD_BASE, restore_buffer->taska_vbi_oddbase); + WRITE_VIP32(VIP_TASKA_VID_PITCH, restore_buffer->taska_data_pitch); + WRITE_VIP32(VIP_CONTROL3, restore_buffer->control3); + WRITE_VIP32(VIP_TASKA_U_OFFSET, restore_buffer->taska_v_oddoffset); + WRITE_VIP32(VIP_TASKA_V_OFFSET, restore_buffer->taska_u_oddoffset); + WRITE_VIP32(VIP_TASKB_VID_EVEN_BASE, restore_buffer->taskb_evenbase); + WRITE_VIP32(VIP_TASKB_VID_ODD_BASE, restore_buffer->taskb_oddbase); + WRITE_VIP32(VIP_TASKB_VBI_EVEN_BASE, restore_buffer->taskb_vbi_evenbase); + WRITE_VIP32(VIP_TASKB_VBI_ODD_BASE, restore_buffer->taskb_vbi_oddbase); + WRITE_VIP32(VIP_TASKB_VID_PITCH, restore_buffer->taskb_pitch); + WRITE_VIP32(VIP_TASKB_U_OFFSET, restore_buffer->taskb_voffset); + WRITE_VIP32(VIP_TASKB_V_OFFSET, restore_buffer->taskb_uoffset); + WRITE_VIP32(VIP_ANC_MSG1_BASE, restore_buffer->msg1_base); + WRITE_VIP32(VIP_ANC_MSG2_BASE, restore_buffer->msg2_base); + WRITE_VIP32(VIP_ANC_MSG_SIZE, restore_buffer->msg_size); + WRITE_VIP32(VIP_PAGE_OFFSET, restore_buffer->page_offset); + WRITE_VIP32(VIP_VERTICAL_START_STOP, restore_buffer->vert_start_stop); + WRITE_VIP32(VIP_VSYNC_ERR_COUNT, restore_buffer->vsync_err_count); + WRITE_VIP32(VIP_TASKA_U_EVEN_OFFSET, restore_buffer->taska_u_evenoffset); + WRITE_VIP32(VIP_TASKA_V_EVEN_OFFSET, restore_buffer->taska_v_evenoffset); + + /* RESTORE THE VIP MSRS */ + + msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_CONFIG, &(restore_buffer->msr_config)); + msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_SMI, &(restore_buffer->msr_smi)); + msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_PM, &(restore_buffer->msr_pm)); + msr_write64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_DIAG, &(restore_buffer->msr_diag)); + + /* RESTORE THE CONTROL WORDS LAST */ + + WRITE_VIP32(VIP_CONTROL1, restore_buffer->control1); + WRITE_VIP32(VIP_CONTROL2, restore_buffer->control2); + WRITE_VIP32(VIP_CONTROL3, restore_buffer->control3); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_get_interrupt_state + * + * This routine returns the current interrupt state of the system. The + * rv can be tested with the following flags to determine if the appropriate + * event has occured. + *---------------------------------------------------------------------------*/ + +unsigned long vip_get_interrupt_state(void) +{ + unsigned long interrupt_mask = READ_VIP32(VIP_INTERRUPT); + + return (~(interrupt_mask << 16) & interrupt_mask & VIP_ALL_INTERRUPTS); +} + +/*--------------------------------------------------------------------------- + * vip_test_genlock_active + * + * This routine reads the live status of the genlock connection between the VIP + * and VG blocks. + *---------------------------------------------------------------------------*/ + +int vip_test_genlock_active (void) +{ + if (READ_REG32 (DC3_GENLK_CTL) & DC3_GC_GENLK_ACTIVE) + return 1; + + return 0; +} + +/*--------------------------------------------------------------------------- + * vip_test_signal_status + * + * This routine reads the live signal status coming into the VIP block. + *---------------------------------------------------------------------------*/ + +int vip_test_signal_status (void) +{ + if (READ_REG32 (DC3_GENLK_CTL) & DC3_GC_VIP_VID_OK) + return 1; + + return 0; +} + +/*--------------------------------------------------------------------------- + * vip_get_current_field + * + * This routine returns the current field being received. + *---------------------------------------------------------------------------*/ + +unsigned long vip_get_current_field (void) +{ + if (READ_VIP32(VIP_STATUS) & VIP_STATUS_FIELD) + return VIP_EVEN_FIELD; + + return VIP_ODD_FIELD; +} + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * CIMARRON VIP READ ROUTINES + * These routines are included for use in diagnostics or when debugging. They + * can be optionally excluded from a project. + *+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ + +#if CIMARRON_INCLUDE_VIP_READ_ROUTINES + +/*--------------------------------------------------------------------------- + * vip_get_current_mode + * + * This routine reads the current VIP operating mode. + *---------------------------------------------------------------------------*/ + +int vip_get_current_mode (VIPSETMODEBUFFER *buffer) +{ + unsigned long vip_control1, vip_control2, vip_control3; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + vip_control1 = READ_VIP32 (VIP_CONTROL1); + vip_control2 = READ_VIP32 (VIP_CONTROL2); + vip_control3 = READ_VIP32 (VIP_CONTROL3); + + /* READ CURRENT OPERATING MODE AND ENABLES */ + + buffer->stream_enables = vip_control1 & VIP_ENABLE_ALL; + buffer->operating_mode = vip_control1 & VIP_CONTROL1_MODE_MASK; + + /* READ CURRENT PLANAR CAPTURE SETTINGS */ + + buffer->flags = 0; + buffer->planar_capture = 0; + if (vip_control1 & VIP_CONTROL1_PLANAR) + { + buffer->flags |= VIP_MODEFLAG_PLANARCAPTURE; + if (vip_control1 & VIP_CONTROL1_DISABLE_DECIMATION) + { + if (vip_control3 & VIP_CONTROL3_DECIMATE_EVEN) + buffer->planar_capture = VIP_420CAPTURE_ALTERNATINGFIELDS; + else + buffer->planar_capture = VIP_420CAPTURE_EVERYLINE; + } + else + buffer->planar_capture = VIP_420CAPTURE_ALTERNATINGLINES; + } + + /* READ MISCELLANEOUS FLAGS */ + + if (vip_control1 & VIP_CONTROL1_NON_INTERLACED) + buffer->flags |= VIP_MODEFLAG_PROGRESSIVE; + if (vip_control3 & VIP_CONTROL3_BASE_UPDATE) + buffer->flags |= VIP_MODEFLAG_TOGGLEEACHFIELD; + if (vip_control2 & VIP_CONTROL2_INVERT_POLARITY) + buffer->flags |= VIP_MODEFLAG_INVERTPOLARITY; + if (vip_control1 & VIP_CONTROL1_MSG_STRM_CTRL) + buffer->flags |= VIP_MODEFLAG_FLIPMESSAGEWHENFULL; + if (vip_control2 & VIP_CONTROL2_REPEAT_ENABLE) + buffer->flags |= VIP_MODEFLAG_ENABLEREPEATFLAG; + if (vip_control3 & VIP_CONTROL3_TASK_POLARITY) + buffer->flags |= VIP_MODEFLAG_INVERTTASKPOLARITY; + if (vip_control1 & VIP_CONTROL1_DISABLE_ZERO_DETECT) + buffer->flags |= VIP_MODEFLAG_DISABLEZERODETECT; + if (vip_control2 & VIP_CONTROL2_ANC10) + buffer->flags |= VIP_MODEFLAG_10BITANCILLARY; + + /* READ THE CURRENT VIP 601 SETTINGS */ + + vip_get_601_configuration (&buffer->vip601_settings); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_get_601_configuration + * + * This routine returns the current 601 configuration information. + *---------------------------------------------------------------------------*/ + +int vip_get_601_configuration (VIP_601PARAMS *buffer) +{ + unsigned long vip_control3, vip_control1; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + vip_control1 = READ_VIP32 (VIP_CONTROL3); + vip_control3 = READ_VIP32 (VIP_CONTROL3); + + buffer->flags = 0; + if (vip_control3 & VIP_CONTROL3_VSYNC_POLARITY) buffer->flags |= VIP_MODEFLAG_VSYNCACTIVEHIGH; + if (vip_control3 & VIP_CONTROL3_HSYNC_POLARITY) buffer->flags |= VIP_MODEFLAG_HSYNCACTIVEHIGH; + + buffer->horz_start = READ_VIP32 (VIP_601_HORZ_START); + buffer->vbi_start = READ_VIP32 (VIP_601_VBI_START); + buffer->vbi_height = READ_VIP32 (VIP_601_VBI_END) - buffer->vbi_start + 1; + buffer->vert_start_even = READ_VIP32 (VIP_601_EVEN_START_STOP) & 0xFFFF; + buffer->even_height = (READ_VIP32 (VIP_601_EVEN_START_STOP) >> 16) - buffer->vert_start_even + 1; + buffer->vert_start_odd = READ_VIP32 (VIP_601_ODD_START_STOP) & 0xFFFF; + buffer->odd_height = (READ_VIP32 (VIP_601_ODD_START_STOP) >> 16) - buffer->vert_start_odd + 1; + buffer->odd_detect_start = READ_VIP32 (VIP_ODD_FIELD_DETECT) & 0xFFFF; + buffer->odd_detect_end = READ_VIP32 (VIP_ODD_FIELD_DETECT) >> 16; + + /* SPECIAL CASE FOR HORIZONTAL DATA */ + /* 601 horizontal parameters are based on the number of clocks and not the */ + /* number of pixels. */ + + if ((vip_control1 & VIP_CONTROL1_MODE_MASK) == VIP_MODE_16BIT601) + buffer->width = (READ_VIP32 (VIP_601_HORZ_END) - buffer->horz_start - 3) >> 1; + else + buffer->width = (READ_VIP32 (VIP_601_HORZ_END) - buffer->horz_start - 3); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_get_buffer_configuration + * + * This routine reads the current buffer configuration for Task A, Task B, + * ancillary or message data. The current_buffer member indicates which + * array index should hold the new values for Task A or Task B data. + *---------------------------------------------------------------------------*/ + +int vip_get_buffer_configuration (int buffer_type, VIPINPUTBUFFER *buffer) +{ + unsigned long cur_buffer = buffer->current_buffer; + VIPINPUTBUFFER_ADDR *offsets; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + if (buffer_type == VIP_BUFFER_A) + { + offsets = &buffer->offsets[VIP_BUFFER_TASK_A]; + + /* READ VIDEO PITCH */ + + offsets->y_pitch = READ_VIP32 (VIP_TASKA_VID_PITCH) & 0xFFFF; + offsets->uv_pitch = READ_VIP32 (VIP_TASKA_VID_PITCH) >> 16; + + /* READ BASE OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY) + { + offsets->even_base[cur_buffer] = READ_VIP32 (VIP_TASKA_VID_ODD_BASE); + offsets->odd_base[cur_buffer] = READ_VIP32 (VIP_TASKA_VID_EVEN_BASE); + + if (buffer->flags & VIP_INPUTFLAG_VBI) + { + offsets->vbi_even_base = READ_VIP32 (VIP_TASKA_VBI_ODD_BASE); + offsets->vbi_odd_base = READ_VIP32 (VIP_TASKA_VBI_EVEN_BASE); + } + } + else + { + offsets->even_base[cur_buffer] = READ_VIP32 (VIP_TASKA_VID_EVEN_BASE); + offsets->odd_base[cur_buffer] = READ_VIP32 (VIP_TASKA_VID_ODD_BASE); + + if (buffer->flags & VIP_INPUTFLAG_VBI) + { + offsets->vbi_even_base = READ_VIP32 (VIP_TASKA_VBI_EVEN_BASE); + offsets->vbi_odd_base = READ_VIP32 (VIP_TASKA_VBI_ODD_BASE); + } + } + + /* READ 4:2:0 OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_PLANAR) + { + offsets->odd_uoffset = READ_VIP32 (VIP_TASKA_U_OFFSET); + offsets->odd_voffset = READ_VIP32 (VIP_TASKA_V_OFFSET); + offsets->even_uoffset = READ_VIP32 (VIP_TASKA_U_EVEN_OFFSET); + offsets->even_voffset = READ_VIP32 (VIP_TASKA_V_EVEN_OFFSET); + } + } + else if (buffer_type == VIP_BUFFER_B) + { + offsets = &buffer->offsets[VIP_BUFFER_TASK_B]; + + /* READ VIDEO PITCH */ + + offsets->y_pitch = READ_VIP32 (VIP_TASKB_VID_PITCH) & 0xFFFF; + offsets->uv_pitch = READ_VIP32 (VIP_TASKB_VID_PITCH) >> 16; + + /* READ BASE OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_INVERTPOLARITY) + { + offsets->even_base[cur_buffer] = READ_VIP32 (VIP_TASKB_VID_ODD_BASE); + offsets->odd_base[cur_buffer] = READ_VIP32 (VIP_TASKB_VID_EVEN_BASE); + + if (buffer->flags & VIP_INPUTFLAG_VBI) + { + offsets->vbi_even_base = READ_VIP32 (VIP_TASKB_VBI_ODD_BASE); + offsets->vbi_odd_base = READ_VIP32 (VIP_TASKB_VBI_EVEN_BASE); + } + } + else + { + offsets->even_base[cur_buffer] = READ_VIP32 (VIP_TASKB_VID_EVEN_BASE); + offsets->odd_base[cur_buffer] = READ_VIP32 (VIP_TASKB_VID_ODD_BASE); + + if (buffer->flags & VIP_INPUTFLAG_VBI) + { + offsets->vbi_even_base = READ_VIP32 (VIP_TASKB_VBI_EVEN_BASE); + offsets->vbi_odd_base = READ_VIP32 (VIP_TASKB_VBI_ODD_BASE); + } + } + + /* READ 4:2:0 OFFSETS */ + + if (buffer->flags & VIP_INPUTFLAG_PLANAR) + { + offsets->odd_uoffset = READ_VIP32 (VIP_TASKB_U_OFFSET); + offsets->odd_voffset = READ_VIP32 (VIP_TASKB_V_OFFSET); + } + } + else if (buffer_type == VIP_BUFFER_ANC || buffer_type == VIP_BUFFER_MSG) + { + buffer->ancillaryData.msg1_base = READ_VIP32(VIP_ANC_MSG1_BASE); + buffer->ancillaryData.msg2_base = READ_VIP32(VIP_ANC_MSG2_BASE); + buffer->ancillaryData.msg_size = READ_VIP32(VIP_ANC_MSG_SIZE); + } + else + { + return CIM_STATUS_INVALIDPARAMS; + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_get_genlock_configuration + * + * This routine reads the current genlock configuration. + *---------------------------------------------------------------------------*/ + +int vip_get_genlock_configuration (VIPGENLOCKBUFFER *buffer) +{ + unsigned long vip_control1, vip_control2; + unsigned long genlk_ctl; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + genlk_ctl = READ_REG32 (DC3_GENLK_CTL); + vip_control1 = READ_VIP32 (VIP_CONTROL1); + vip_control2 = READ_VIP32 (VIP_CONTROL2); + + /* READ ERROR DETECTION, CURRENT FIELD AND CURRENT VSYNC */ + /* These flags are used to indicate the ways in which the VIP signal can */ + /* be considered 'lost'. */ + + buffer->vip_signal_loss = vip_control1 & VIP_CONTROL1_VDE_FF_MASK; + buffer->field_to_vg = vip_control2 & VIP_CONTROL2_FIELD2VG_MASK; + buffer->vsync_to_vg = vip_control2 & VIP_CONTROL2_SYNC2VG_MASK; + + /* GENLOCK TIMEOUT ENABLE */ + + buffer->enable_timeout = 0; + if (genlk_ctl & DC3_GC_GENLOCK_TO_ENABLE) + buffer->enable_timeout = 1; + + /* GENLOCK SKEW */ + + buffer->genlock_skew = genlk_ctl & DC3_GC_GENLOCK_SKEW_MASK; + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_get_genlock_enable + * + * This routine returns the current enable status of genlock in the VG. + *---------------------------------------------------------------------------*/ + +int vip_get_genlock_enable (void) +{ + if (READ_REG32 (DC3_GENLK_CTL) & DC3_GC_GENLOCK_ENABLE) + return 1; + + return 0; +} + +/*--------------------------------------------------------------------------- + * vip_is_buffer_update_latched + * + * This routine indicates whether changes to the VIP offsets have been latched by + * the hardware. + *---------------------------------------------------------------------------*/ + +int vip_is_buffer_update_latched (void) +{ + return (!(READ_VIP32(VIP_STATUS) & VIP_STATUS_BASEREG_NOTUPDT)); +} + +/*--------------------------------------------------------------------------- + * vip_get_capture_state + * + * This routine reads the current capture status of the VIP hardware. + *---------------------------------------------------------------------------*/ + +unsigned long vip_get_capture_state (void) +{ + return ((READ_VIP32(VIP_CONTROL1) & VIP_CONTROL1_RUNMODE_MASK) >> VIP_CONTROL1_RUNMODE_SHIFT); +} + +/*--------------------------------------------------------------------------- + * vip_get_current_line + * + * This routine returns the current line that is being processed. + *---------------------------------------------------------------------------*/ + +unsigned long vip_get_current_line (void) +{ + return (READ_VIP32(VIP_CURRENT_TARGET) & VIP_CTARGET_CLINE_MASK); +} + +/*--------------------------------------------------------------------------- + * vip_read_fifo + * + * This routine reads from the specified fifo address. As the fifo access + * enable should be disabled when running in normal vip mode, this routine + * enables and disables access around the read. + * DIAGNOSTIC USE ONLY + *---------------------------------------------------------------------------*/ + +unsigned long vip_read_fifo(unsigned long dwFifoAddress) +{ + unsigned long fifo_data; + + /* ENABLE FIFO ACCESS */ + + vip_enable_fifo_access (1); + + /* NOW READ THE DATA */ + + WRITE_VIP32(VIP_FIFO_ADDRESS, dwFifoAddress); + fifo_data = READ_VIP32(VIP_FIFO_DATA); + + /* DISABLE FIFO ACCESS */ + + vip_enable_fifo_access (0); + + return fifo_data; +} + +/*--------------------------------------------------------------------------- + * vip_write_fifo + * + * SYNOPSIS: + * This routine writes to the specified fifo address. As the fifo access + * enable should be disabled when running in normal vip mode, this routine + * enables and disables access around the write. + * DIAGNOSTIC USE ONLY + *---------------------------------------------------------------------------*/ + +int vip_write_fifo (unsigned long dwFifoAddress, unsigned long dwFifoData) +{ + /* ENABLE FIFO ACCESS */ + + vip_enable_fifo_access(1); + + /* WRITE THE FIFO DATA */ + + WRITE_VIP32(VIP_FIFO_ADDRESS, dwFifoAddress); + WRITE_VIP32(VIP_FIFO_DATA, dwFifoData); + + /* DISABLE FIFO ACCESS */ + + vip_enable_fifo_access(0); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_enable_fifo_access + * + * This routine enables/disables access to the vip fifo. + * DIAGNOSTIC USE ONLY + *---------------------------------------------------------------------------*/ + +int vip_enable_fifo_access (int enable) +{ + unsigned long cw2; + + cw2 = READ_VIP32(VIP_CONTROL2); + + if (enable) cw2 |= VIP_CONTROL2_FIFO_ACCESS; + else cw2 &= ~VIP_CONTROL2_FIFO_ACCESS; + + WRITE_VIP32(VIP_CONTROL2, cw2); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_get_power_characteristics + * + * This routine returns the current VIP clock gating state in a VIPPOWERBUFFER. + *---------------------------------------------------------------------------*/ + +int vip_get_power_characteristics(VIPPOWERBUFFER *buffer) +{ + Q_WORD q_word; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + /* READ THE EXISTING STATE */ + + msr_read64(MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_PM, &q_word); + + /* DECODE THE CLOCK GATING BITS */ + + buffer->glink_clock_mode = (int)(q_word.low & VIP_MSR_POWER_GLINK); + buffer->vip_clock_mode = (int)(q_word.low & VIP_MSR_POWER_CLOCK); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_get_priority_characteristics + * + * This routine returns the priority characteristics in the supplied + * VIPPRIORITYBUFFER. + *---------------------------------------------------------------------------*/ + +int vip_get_priority_characteristics(VIPPRIORITYBUFFER *buffer) +{ + Q_WORD q_word; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + /* READ THE CURRENT STATE */ + + msr_read64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_CONFIG, &q_word); + + /* DECODE THE PRIORITIES */ + + buffer->secondary = (q_word.low & VIP_MSR_MCR_SECOND_PRIORITY_MASK) >> VIP_MSR_MCR_SECOND_PRIORITY_SHIFT; + buffer->primary = (q_word.low & VIP_MSR_MCR_PRIMARY_PRIORITY_MASK) >> VIP_MSR_MCR_PRIMARY_PRIORITY_SHIFT; + buffer->pid = q_word.low & VIP_MSR_MCR_PID_MASK; + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vip_get_capability_characteristics + * + * This routine returns revision information for the device. + *---------------------------------------------------------------------------*/ + +int vip_get_capability_characteristics(VIPCAPABILITIESBUFFER *buffer) +{ + Q_WORD q_word ; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + /* READ THE CURRENT MSR CONTENTS */ + + msr_read64 (MSR_DEVICE_GEODELX_VIP, MSR_GEODELINK_CAP, &q_word); + + /* DECODE THE REVISIONS */ + + buffer->revision_id = (q_word.low & VIP_MSR_CAP_REVID_MASK) >> VIP_MSR_CAP_REVID_SHIFT; + buffer->device_id = (q_word.low & VIP_MSR_CAP_DEVID_MASK) >> VIP_MSR_CAP_DEVID_SHIFT; + buffer->n_clock_domains = (q_word.low & VIP_MSR_CAP_NCLK_MASK) >> VIP_MSR_CAP_NCLK_SHIFT; + buffer->n_smi_registers = (q_word.low & VIP_MSR_CAP_NSMI_MASK) >> VIP_MSR_CAP_NSMI_SHIFT; + + return CIM_STATUS_OK; +} + + + +#endif --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_vop.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_vop.c 2005-12-14 11:37:53.000000000 -0700 @@ -0,0 +1,581 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron VOP configuration routines. + * */ + +/*--------------------------------------------------------------------------- + * vop_set_vbi_window + * + * This routine configures the output position and location in memory of + * VBI data. + *---------------------------------------------------------------------------*/ + +int vop_set_vbi_window (VOPVBIWINDOWBUFFER *buffer) +{ + unsigned long unlock, temp; + unsigned long hstart, hstop; + unsigned long htotal, hsyncstart; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + unlock = READ_REG32 (DC3_UNLOCK); + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + + /* PROGRAM HORIZONTAL POSITION */ + /* The horizontal position is a little tricky. The counter for the horizontal */ + /* timings is reused for the VBI counter. Consequently, the horizontal start */ + /* and stop values are based off the beginning of active data. However, the */ + /* VG has a quirk. If the counter start position is before the beginning of */ + /* HSync, it applies to the previous line. If the counter is after the */ + /* beginning of HSync it applies to the current line. So, for one line */ + /* the real range can be thought of as HSync_start to (HSync_start + htotal - 1). */ + /* However, the counters must be between 0 and htotal - 1. When placing VBI */ + /* data before the start of active data, the horizontal end position will thus */ + /* be *less* than the horizontal start. */ + + htotal = ((READ_REG32 (DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + hsyncstart = (READ_REG32 (DC3_H_SYNC_TIMING) & 0xFFF) + 1; + + if (buffer->horz_from_hsync) + { + /* VERIFY THAT THE INPUT IS VALID */ + + if (buffer->horz_start < 0 || (buffer->horz_start + buffer->vbi_width) > htotal) + return CIM_STATUS_INVALIDPARAMS; + + hstart = buffer->horz_start + hsyncstart; + } + else + { + /* VERIFY THAT THE INPUT IS VALID */ + + if (buffer->horz_start < ((long)hsyncstart - (long)htotal) || + buffer->horz_start > (long)hsyncstart || + buffer->vbi_width > htotal) + { + return CIM_STATUS_INVALIDPARAMS; + } + + hstart = buffer->horz_start + htotal; + } + + hstop = hstart + buffer->vbi_width; + if (hstart > htotal) hstart -= htotal; + if (hstop > htotal) hstop -= htotal; + hstart--; + hstop--; + WRITE_REG32 (DC3_VBI_HOR, ((hstop << DC3_VBI_HOR_END_SHIFT) & DC3_VBI_HOR_END_MASK) | + (hstart & DC3_VBI_HOR_START_MASK)); + + /* WRITE LINE CAPTURE MASKS */ + + WRITE_REG32 (DC3_VBI_LN_ODD, ((buffer->odd_line_offset << DC3_VBI_ODD_LINE_SHIFT) & DC3_VBI_ODD_LINE_MASK) | + (buffer->odd_line_capture_mask & DC3_VBI_ODD_ENABLE_MASK)); + + WRITE_REG32 (DC3_VBI_LN_EVEN, ((buffer->even_line_offset << DC3_VBI_EVEN_LINE_SHIFT) & DC3_VBI_EVEN_LINE_MASK) | + (buffer->even_line_capture_mask & DC3_VBI_EVEN_ENABLE_MASK)); + + /* PROGRAM SOURCE OFFSETS */ + /* Start with the even offsets. Note that we always enable 16-bit VBI, as this */ + /* is the only way to get VBI data on each VOP clock. */ + + temp = READ_REG32 (DC3_VBI_EVEN_CTL) & ~DC3_VBI_EVEN_CTL_OFFSET_MASK; + temp |= DC3_VBI_EVEN_CTL_ENABLE_16; + if (buffer->enable_upscale) + temp |= DC3_VBI_EVEN_CTL_UPSCALE; + WRITE_REG32 (DC3_VBI_EVEN_CTL, temp | (buffer->even_address_offset & DC3_VBI_EVEN_CTL_OFFSET_MASK)); + + /* ODD OFFSET */ + + temp = READ_REG32 (DC3_VBI_ODD_CTL) & ~DC3_VBI_ODD_CTL_OFFSET_MASK; + WRITE_REG32 (DC3_VBI_ODD_CTL, temp | (buffer->odd_address_offset & DC3_VBI_ODD_CTL_OFFSET_MASK)); + + /* PITCH */ + + temp = ((buffer->data_size >> 3) << 16) | ((buffer->data_pitch >> 3) & 0x0000FFFF); + WRITE_REG32(DC3_VBI_PITCH, temp); + + WRITE_REG32 (DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vop_enable_vbi_output + * + * This routine enables/disables VBI fetching inside the video generator. + *---------------------------------------------------------------------------*/ + +int vop_enable_vbi_output (int enable) +{ + unsigned long unlock, temp; + + unlock = READ_REG32 (DC3_UNLOCK); + temp = READ_REG32 (DC3_VBI_EVEN_CTL); + + if (enable) temp |= DC3_VBI_ENABLE; + else temp &= ~DC3_VBI_ENABLE; + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_VBI_EVEN_CTL, temp); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vop_set_configuration + * + * This routine is passed a VOP_CONFIGURATION structure that contains all + * the necessary information to configure VOP output. + *---------------------------------------------------------------------------*/ + +int vop_set_configuration (VOPCONFIGURATIONBUFFER *config) +{ + unsigned long vop_config = 0; + unsigned long alpha, control2; + unsigned long unlock; + unsigned long delta; + Q_WORD msr_value; + int rgb = 0; + + if (!config) + return CIM_STATUS_INVALIDPARAMS; + + unlock = READ_REG32 (DC3_UNLOCK); + delta = READ_REG32 (DC3_VID_DS_DELTA) & DC3_DS_DELTA_MASK; + + /* OVERRIDE THE OUTPUT SETTINGS TO ENABLE VOP OUTPUT */ + + if (config->mode != VOP_MODE_DISABLED) + { + msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &msr_value); + msr_value.low &= ~DF_CONFIG_OUTPUT_MASK; + msr_value.low |= DF_OUTPUT_VOP; + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &msr_value); + } + + /* SET THE UNIVERSAL VOP OPTIONS */ + + if (config->flags & VOP_FLAG_SWAP_UV) vop_config |= VOP_CONFIG_SWAPUV; + if (config->flags & VOP_FLAG_SWAP_VBI) vop_config |= VOP_CONFIG_SWAPVBI; + + /* SET THE MODE SPECIFIC PARAMETERS */ + + if (config->mode == VOP_MODE_601) + { + vop_config |= config->vop601.flags; + vop_config |= config->vop601.vsync_shift; + vop_config |= VOP_CONFIG_ENABLE_601 | VOP_CONFIG_VIP2_0; + + switch (config->vop601.output_mode) + { + case VOP_601_YUV_16BIT: + vop_config |= VOP_CONFIG_VIP2_16BIT; + break; + case VOP_601_YUV_4_4_4: + vop_config |= VOP_CONFIG_DISABLE_DECIMATE; + break; + case VOP_601_RGB_8_8_8: + vop_config |= VOP_CONFIG_DISABLE_DECIMATE | VOP_CONFIG_RGBMODE; + rgb = 1; + break; + } + + if (config->vop601.vsync_shift == VOP_VSYNC_LATER_BY_X) + { + delta |= (config->vop601.vsync_shift_count & DC3_601_VSYNC_SHIFT_MASK); + delta |= DC3_601_VSYNC_SHIFT_ENABLE; + } + } + else + { + if (config->flags & VOP_FLAG_VBI) vop_config |= VOP_CONFIG_VBI; + if (config->flags & VOP_FLAG_TASK) vop_config |= VOP_CONFIG_TASK; + if (config->flags & VOP_FLAG_SINGLECHIPCOMPAT) vop_config |= VOP_CONFIG_SC_COMPATIBLE; + if (config->flags & VOP_FLAG_EXTENDEDSAV) vop_config |= VOP_CONFIG_EXTENDED_SAV; + + switch (config->mode) + { + case VOP_MODE_DISABLED: + vop_config |= VOP_CONFIG_DISABLED; + break; + case VOP_MODE_VIP11: + vop_config |= VOP_CONFIG_VIP1_1; + break; + case VOP_MODE_CCIR656: + vop_config |= VOP_CONFIG_CCIR656; + break; + case VOP_MODE_VIP20_8BIT: + vop_config |= VOP_CONFIG_VIP2_0; + break; + case VOP_MODE_VIP20_16BIT: + vop_config |= VOP_CONFIG_VIP2_0 | VOP_CONFIG_VIP2_16BIT; + break; + } + } + + /* SET THE 4:4:4 TO 4:2:2 DECIMATION ALGORITHM */ + + vop_config |= (config->conversion_mode); + + /* SET THE VSYNC OUT OPTIONS */ + + control2 = READ_VIP32 (VIP_CONTROL2) & ~VIP_CONTROL2_SYNC2PIN_MASK; + control2 |= config->vsync_out; + WRITE_VIP32 (VIP_CONTROL2, control2); + + /* FORCE THE CORRECT VOP COLOR SPACE */ + /* The output of the mixer will be either RGB or YUV. We must enable */ + /* or disable the VOP CSC based on the desired output format. */ + + alpha = READ_VID32 (DF_VID_ALPHA_CONTROL); + if (!(alpha & DF_CSC_GRAPHICS_RGB_TO_YUV)) + { + /* RGB OUTPUT FROM THE MIXER */ + + if (!rgb) alpha |= DF_CSC_VOP_RGB_TO_YUV; + else alpha &= ~DF_CSC_VOP_RGB_TO_YUV; + } + else + { + /* YUV OUTPUT FROM THE MIXER */ + /* As there is no YUV->RGB VOP conversion, we simply disable the */ + /* VOP CSC and trust that the user is competent. */ + + alpha &= ~DF_CSC_VOP_RGB_TO_YUV; + } + + /* AND WRITE THE CONFIGURATION */ + + WRITE_VID32 (DF_VID_ALPHA_CONTROL, alpha); + WRITE_VOP32(VOP_CONFIGURATION, vop_config); + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_VID_DS_DELTA, delta); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vop_save_state + * + * This routine saves the necessary register contents in order to restore + * at a later point to the same state. Note that the capture state is + * forced to OFF in this routine. + *---------------------------------------------------------------------------*/ + +int vop_save_state (VOPSTATEBUFFER *save_buffer) +{ + if (!save_buffer) + return CIM_STATUS_INVALIDPARAMS; + + save_buffer->config = READ_VOP32(VOP_CONFIGURATION); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vop_restore_state + * + * This routine restores the state of the vop registers - which were + * previously saved using vop_save_state. + *---------------------------------------------------------------------------*/ + +int vop_restore_state (VOPSTATEBUFFER *restore_buffer) +{ + if (!restore_buffer) + return CIM_STATUS_INVALIDPARAMS; + + WRITE_VOP32(VOP_CONFIGURATION, restore_buffer->config); + + return CIM_STATUS_OK; +} + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * CIMARRON VOP READ ROUTINES + * These routines are included for use in diagnostics or when debugging. They + * can be optionally excluded from a project. + *+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ + +#if CIMARRON_INCLUDE_VOP_READ_ROUTINES + +/*--------------------------------------------------------------------------- + * vop_get_current_mode + * + * This routine reads the current VIP operating mode and stores it in the + * passed VOP_CONFIGURATION structure. + *---------------------------------------------------------------------------*/ + +int vop_get_current_mode (VOPCONFIGURATIONBUFFER *config) +{ + unsigned long vop_config = 0; + unsigned long alpha; + + if (!config) + return CIM_STATUS_INVALIDPARAMS; + + vop_config = READ_VOP32 (VOP_CONFIGURATION); + alpha = READ_VID32 (DF_VID_ALPHA_CONTROL); + + /* READ THE CURRENT MODE */ + + switch (vop_config & VOP_CONFIG_MODE_MASK) + { + case VOP_CONFIG_DISABLED: config->mode = VOP_MODE_DISABLED; break; + case VOP_CONFIG_VIP1_1: config->mode = VOP_MODE_VIP11; break; + case VOP_CONFIG_CCIR656: config->mode = VOP_MODE_CCIR656; break; + case VOP_CONFIG_VIP2_0: + + if (vop_config & VOP_CONFIG_ENABLE_601) + config->mode = VOP_MODE_601; + else if (vop_config & VOP_CONFIG_VIP2_16BIT) + config->mode = VOP_MODE_VIP20_16BIT; + else + config->mode = VOP_MODE_VIP20_8BIT; + break; + } + + /* READ 601 SETTINGS */ + + config->vop601.flags = vop_config & (VOP_CONFIG_INVERT_DISPE | + VOP_CONFIG_INVERT_HSYNC | VOP_CONFIG_INVERT_VSYNC); + + config->vop601.vsync_shift = vop_config & VOP_CONFIG_VSYNC_MASK; + config->vop601.vsync_shift_count = READ_REG32 (DC3_VID_DS_DELTA) & DC3_601_VSYNC_SHIFT_MASK; + + if ((alpha & DF_CSC_GRAPHICS_RGB_TO_YUV) || + (alpha & DF_CSC_VOP_RGB_TO_YUV)) + { + /* YUV OUTPUT */ + + if (vop_config & VOP_CONFIG_DISABLE_DECIMATE) + config->vop601.output_mode = VOP_601_YUV_4_4_4; + else if (vop_config & VOP_CONFIG_VIP2_16BIT) + config->vop601.output_mode = VOP_601_YUV_16BIT; + else + config->vop601.output_mode = VOP_601_YUV_8BIT; + } + else + { + config->vop601.output_mode = VOP_601_RGB_8_8_8; + } + + config->flags = 0; + + /* READ THE UNIVERSAL VOP OPTIONS */ + + if (vop_config & VOP_CONFIG_SWAPUV) config->flags |= VOP_FLAG_SWAP_UV; + if (vop_config & VOP_CONFIG_SWAPVBI) config->flags |= VOP_FLAG_SWAP_VBI; + if (vop_config & VOP_CONFIG_VBI) config->flags |= VOP_FLAG_VBI; + if (vop_config & VOP_CONFIG_TASK) config->flags |= VOP_FLAG_TASK; + if (vop_config & VOP_CONFIG_SC_COMPATIBLE) config->flags |= VOP_FLAG_SINGLECHIPCOMPAT; + if (vop_config & VOP_CONFIG_EXTENDED_SAV) config->flags |= VOP_FLAG_EXTENDEDSAV; + + config->conversion_mode = vop_config & VOP_CONFIG_422_MASK; + + config->vsync_out = READ_VIP32 (VIP_CONTROL2) & VIP_CONTROL2_SYNC2PIN_MASK; + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vop_get_vbi_window + * + * This routine reads the current VBI configuration for VOP output. + *---------------------------------------------------------------------------*/ + +int vop_get_vbi_configuration (VOPVBIWINDOWBUFFER *buffer) +{ + unsigned long temp; + unsigned long hstart, hstop; + unsigned long htotal, hsyncstart; + + if (!buffer) + return CIM_STATUS_INVALIDPARAMS; + + htotal = ((READ_REG32 (DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + hsyncstart = (READ_REG32 (DC3_H_SYNC_TIMING) & 0xFFF) + 1; + + /* DECODE HORIZONTAL POSITION */ + /* This is done according to the requested horizontal origin */ + + temp = READ_REG32 (DC3_VBI_HOR); + hstart = (temp & DC3_VBI_HOR_START_MASK) + 1; + hstop = ((temp & DC3_VBI_HOR_END_MASK) >> DC3_VBI_HOR_END_SHIFT) + 1; + if (buffer->horz_from_hsync) + { + buffer->horz_start = hstart + htotal - hsyncstart; + if (buffer->horz_start >= (long)htotal) + buffer->horz_start -= htotal; + } + else + { + if (hstart > hsyncstart) + buffer->horz_start = (long)hstart - (long)htotal; + else + buffer->horz_start = hstart; + } + + if (hstop > hstart) + buffer->vbi_width = hstop - hstart; + else + buffer->vbi_width = (htotal - hstart) + hstop; + + /* READ LINE MASKS */ + + temp = READ_REG32 (DC3_VBI_LN_ODD); + buffer->odd_line_offset = (temp & DC3_VBI_ODD_LINE_MASK) >> DC3_VBI_ODD_LINE_SHIFT; + buffer->odd_line_capture_mask = (temp & DC3_VBI_ODD_ENABLE_MASK); + + temp = READ_REG32 (DC3_VBI_LN_EVEN); + buffer->even_line_offset = (temp & DC3_VBI_EVEN_LINE_MASK) >> DC3_VBI_EVEN_LINE_SHIFT; + buffer->even_line_capture_mask = (temp & DC3_VBI_EVEN_ENABLE_MASK); + + /* READ VBI UPSCALE SETTINGS */ + + buffer->enable_upscale = 0; + temp = READ_REG32 (DC3_VBI_EVEN_CTL); + if (temp & DC3_VBI_EVEN_CTL_UPSCALE) + buffer->enable_upscale = 1; + + /* READ SOURCE OFFSETS */ + + buffer->even_address_offset = temp & DC3_VBI_EVEN_CTL_OFFSET_MASK; + buffer->odd_address_offset = READ_REG32 (DC3_VBI_ODD_CTL) & DC3_VBI_ODD_CTL_OFFSET_MASK; + + /* PITCH AND SIZE */ + + temp = READ_REG32 (DC3_VBI_PITCH); + buffer->data_size = (temp >> 16) << 3; + buffer->data_pitch = (temp & 0xFFFF); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vop_get_vbi_enable + * + * This routine reads the current enable status of VBI output. + *---------------------------------------------------------------------------*/ + +int vop_get_vbi_enable (void) +{ + if (READ_REG32 (DC3_VBI_EVEN_CTL) & DC3_VBI_ENABLE) + return 1; + + return 0; +} + +/*--------------------------------------------------------------------------- + * vop_get_crc + * + * This routine returns a CRC of the current VOP data + ---------------------------------------------------------------------------*/ + +unsigned long vop_get_crc(void) +{ + unsigned long crc; + unsigned long config = READ_VOP32(VOP_CONFIGURATION); + unsigned long timeout = 1000; + + if (!(READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_TGEN)) + return 0xFFFFFFFF; + + /* RESET CRC */ + + WRITE_VOP32 (VOP_CONFIGURATION, config & ~VOP_CONFIG_ENABLE_SIGNATURE); + + /* WAIT FOR THE RESET TO BE LATCHED */ + + while ((READ_VOP32 (VOP_SIGNATURE) != 0x00000001) && timeout) + timeout--; + + WRITE_VOP32 (VOP_CONFIGURATION, config | VOP_CONFIG_ENABLE_SIGNATURE); + + /* WAIT UNTIL NOT ACTIVE, THEN ACTIVE, NOT ACTIVE, THEN ACTIVE */ + + while (!(READ_VOP32 (VOP_CONFIGURATION) & VOP_CONFIG_SIGVAL)) + ; + + crc = READ_VOP32 (VOP_SIGNATURE); + + return crc; +} + +/*--------------------------------------------------------------------------- + * vop_read_vbi_crc + * + * This routine returns a CRC of the current VBI data + ---------------------------------------------------------------------------*/ + +unsigned long vop_read_vbi_crc(void) +{ + unsigned long gcfg, unlock, vbi_even; + unsigned long crc; + + if (!(READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_TGEN) || + !(READ_REG32 (DC3_VBI_EVEN_CTL) & DC3_VBI_ENABLE)) + { + return 0xFFFFFFFF; + } + + unlock = READ_REG32 (DC3_UNLOCK); + gcfg = READ_REG32 (DC3_GENERAL_CFG); + vbi_even = READ_REG32 (DC3_VBI_EVEN_CTL); + + gcfg |= DC3_GCFG_SGRE | DC3_GCFG_CRC_MODE; + gcfg &= ~(DC3_GCFG_SGFR | DC3_GCFG_SIG_SEL); + vbi_even |= DC3_VBI_EVEN_ENABLE_CRC; + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_VBI_EVEN_CTL, vbi_even); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg & ~DC3_GCFG_SIGE); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg | DC3_GCFG_SIGE); + + /* WAIT FOR THE CRC TO BE COMPLETED */ + + while (!(READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_SIGC)) + ; + + /* READ THE COMPLETED CRC */ + + crc = READ_REG32 (DC3_PAL_DATA); + + /* RESTORE THE PALETTE SETTINGS */ + + gcfg &= ~DC3_GCFG_SGRE; + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return crc; +} + +#endif --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_parm.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_parm.h 2005-12-14 11:38:42.000000000 -0700 @@ -0,0 +1,1285 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron user definitions. + * */ + +#ifndef _cim_parm_h +#define _cim_parm_h + +/*===================================================*/ +/* CIMARRON RETURN VALUE DEFINITIONS */ +/*===================================================*/ + +#define CIM_STATUS_OK 0x00000000 +#define CIM_STATUS_ERROR 0x00000001 +#define CIM_STATUS_INVALIDPARAMS 0x00000002 +#define CIM_STATUS_DEVNOTFOUND 0x00000004 +#define CIM_STATUS_INVALIDSCALE 0x00000008 +#define CIM_STATUS_INEXACTMATCH 0x00000010 +#define CIM_STATUS_NOLOCK 0x00000020 +#define CIM_STATUS_CPUNOTFOUND 0x00000040 +#define CIM_STATUS_DISPLAYUNAVAILABLE 0x00000080 +#define CIM_STATUS_NOTFOUND 0x00000100 + +/*===================================================*/ +/* CIMARRON CPU DEFINITIONS */ +/*===================================================*/ + +#define CIM_CPU_GEODEGX 0x00000001 +#define CIM_CPU_GEODELX 0x00000002 + +#define CIM_SB_5535 0x00000001 +#define CIM_SB_5536 0x00000002 + +/*===================================================*/ +/* MSR PARAMETERS */ +/*===================================================*/ + +/*-------------------------------------------------------------*/ +/* GEODELINK DEVICE IDS */ +/* These values uniquely identify all known GeodeLink devices */ +/* in GeodeLX and its companion, 5535/6. For multiple devices */ +/* of the same class (GLIU, USB, etc.) the table order is used */ +/* to to identify the expected device order, in terms of on */ +/* which GLIU the device is found, and on which port. */ +/*-------------------------------------------------------------*/ + +#define MSR_DEVICE_GEODELX_GLIU0 0x00 +#define MSR_DEVICE_GEODELX_GLIU1 0x01 +#define MSR_DEVICE_5535_GLIU 0x02 +#define MSR_DEVICE_GEODELX_GLCP 0x03 +#define MSR_DEVICE_5535_GLCP 0x04 +#define MSR_DEVICE_GEODELX_MPCI 0x05 +#define MSR_DEVICE_5535_MPCI 0x06 +#define MSR_DEVICE_GEODELX_MC 0x07 +#define MSR_DEVICE_GEODELX_GP 0x08 +#define MSR_DEVICE_GEODELX_VG 0x09 +#define MSR_DEVICE_GEODELX_VIP 0x0A +#define MSR_DEVICE_GEODELX_AES 0x0B +#define MSR_DEVICE_GEODELX_DF 0x0C +#define MSR_DEVICE_GEODELX_FG 0x0D +#define MSR_DEVICE_GEODELX_VAIL 0x0E +#define MSR_DEVICE_5536_USB_2_0 0x0F +#define MSR_DEVICE_5535_USB2 0x10 +#define MSR_DEVICE_5535_USB1 0x11 +#define MSR_DEVICE_5535_ATAC 0x12 +#define MSR_DEVICE_5535_MDD 0x13 +#define MSR_DEVICE_5535_ACC 0x14 +#define MSR_DEVICE_EMPTY 0x15 +#define MSR_DEVICE_REFLECTIVE 0x16 +#define MSR_DEVICE_PRESENT 0x17 +#define MSR_DEVICE_NOTFOUND 0x18 + +/*---------------------------------------------*/ +/* GEODELINK TABLE ENTRY */ +/* The following structure represents one port */ +/* on a GeodeLink Interface Unit (GLIU) */ +/*---------------------------------------------*/ + +typedef struct tagGeodeLinkNode +{ + unsigned long address_from_cpu; + unsigned long device_id; + +} GEODELINK_NODE; + +/*---------------------------------------------*/ +/* QWORD DATA STRUCTURE */ +/* 64-bit data structure for MSR acess. */ +/*---------------------------------------------*/ + +typedef struct tagQ_WORD +{ + unsigned long high; + unsigned long low; + +} Q_WORD; + +/*===================================================*/ +/* INITIALIZATION USER PARAMETERS */ +/*===================================================*/ + +typedef struct tagInitBaseAddresses +{ + unsigned long framebuffer_base; + unsigned long gp_register_base; + unsigned long vg_register_base; + unsigned long df_register_base; + unsigned long vip_register_base; + unsigned long framebuffer_size; + +} INIT_BASE_ADDRESSES; + +/*===================================================*/ +/* GP USER PARAMETER DEFINITIONS */ +/*===================================================*/ + +/*---------------------------*/ +/* GP_DECLARE_BLT PARAMETERS */ +/*---------------------------*/ + +#define CIMGP_BLTFLAGS_PRES_LUT 0x0001 +#define CIMGP_BLTFLAGS_PRES_COLOR_PAT 0x0002 +#define CIMGP_ENABLE_PREFETCH 0x0004 +#define CIMGP_BLTFLAGS_HAZARD 0x0008 +#define CIMGP_BLTFLAGS_INVERTMONO 0x0010 +#define CIMGP_BLTFLAGS_LIMITBUFFER 0x0020 + +/*-----------------------------------*/ +/* GP_SET_ALPHA_OPERATION PARAMETERS */ +/*-----------------------------------*/ + +#define CIMGP_APPLY_BLEND_TO_RGB 1 +#define CIMGP_APPLY_BLEND_TO_ALPHA 2 +#define CIMGP_APPLY_BLEND_TO_ALL 3 + +#define CIMGP_ALPHA_TIMES_A 0 +#define CIMGP_BETA_TIMES_B 1 +#define CIMGP_A_PLUS_BETA_B 2 +#define CIMGP_ALPHA_A_PLUS_BETA_B 3 + +#define CIMGP_CHANNEL_A_ALPHA 0 +#define CIMGP_CHANNEL_B_ALPHA 1 +#define CIMGP_CONSTANT_ALPHA 2 +#define CIMGP_ALPHA_EQUALS_ONE 3 +#define CIMGP_ALPHA_FROM_RGB_A 4 +#define CIMGP_ALPHA_FROM_RGB_B 5 +#define CIMGP_CONVERTED_ALPHA 6 + +#define CIMGP_CHANNEL_A_SOURCE 0 +#define CIMGP_CHANNEL_A_DEST 1 + +/*---------------------------------*/ +/* GP_SET_SOURCE_FORMAT PARAMETERS */ +/*---------------------------------*/ + +#define CIMGP_SOURCE_FMT_3_3_2 0x00 +#define CIMGP_SOURCE_FMT_8BPP_INDEXED 0x01 +#define CIMGP_SOURCE_FMT_4_4_4_4 0x04 +#define CIMGP_SOURCE_FMT_12BPP_BGR 0x14 +#define CIMGP_SOURCE_FMT_1_5_5_5 0x05 +#define CIMGP_SOURCE_FMT_15BPP_BGR 0x15 +#define CIMGP_SOURCE_FMT_0_5_6_5 0x06 +#define CIMGP_SOURCE_FMT_16BPP_BGR 0x16 +#define CIMGP_SOURCE_FMT_YUYV 0x07 +#define CIMGP_SOURCE_FMT_UYVY 0x17 +#define CIMGP_SOURCE_FMT_8_8_8_8 0x08 +#define CIMGP_SOURCE_FMT_32BPP_BGR 0x18 +#define CIMGP_SOURCE_FMT_24BPP 0x0B +#define CIMGP_SOURCE_FMT_4BPP_INDEXED 0x0D + +/*------------------------------------*/ +/* GP_SCREEN_TO_SCREEN_BLT PARAMETERS */ +/*------------------------------------*/ + +#define CIMGP_NEGXDIR 1 +#define CIMGP_NEGYDIR 2 + +/*------------------------------------*/ +/* GP_BRESENHAM_LINE PARAMETERS */ +/*------------------------------------*/ + +#define CIMGP_YMAJOR 1 +#define CIMGP_POSMAJOR 2 +#define CIMGP_POSMINOR 4 + +/*----------------------------------------------*/ +/* USER STRUCTURE FOR SAVING/RESTORING GP STATE */ +/*----------------------------------------------*/ + +typedef struct tagGPSaveRestore +{ + unsigned long base_offset; + unsigned long cmd_top; + unsigned long cmd_bottom; + unsigned long cmd_base; + unsigned long cmd_read; + +} GP_SAVE_RESTORE; + +/*===================================================*/ +/* VG USER PARAMETER DEFINITIONS */ +/*===================================================*/ + +/*-------------------------------------------*/ +/* SUPPORTED TV ENCODERS */ +/*-------------------------------------------*/ + +#define VG_ENCODER_ADV7171 0x0001 +#define VG_ENCODER_SAA7127 0x0002 +#define VG_ENCODER_FS454 0x0003 +#define VG_ENCODER_ADV7300 0x0004 + +/*-------------------------------------------*/ +/* SUPPORTED TV RESOLUTIONS */ +/*-------------------------------------------*/ + +#define VG_TVMODE_NTSC 0x00000000 +#define VG_TVMODE_PAL 0x00000001 +#define VG_TVMODE_480P 0x00000002 +#define VG_TVMODE_720P 0x00000003 +#define VG_TVMODE_1080I 0x00000004 +#define VG_TVMODE_6X4_NTSC 0x00000005 +#define VG_TVMODE_8X6_NTSC 0x00000006 +#define VG_TVMODE_10X7_NTSC 0x00000007 +#define VG_TVMODE_6X4_PAL 0x00000008 +#define VG_TVMODE_8X6_PAL 0x00000009 +#define VG_TVMODE_10X7_PAL 0x0000000A + +/*-------------------------------------------*/ +/* USER STRUCTURE FOR SETTING A DISPLAY MODE */ +/*-------------------------------------------*/ + +#define VG_SUPPORTFLAG_8BPP 0x00000001 +#define VG_SUPPORTFLAG_12BPP 0x00000002 +#define VG_SUPPORTFLAG_15BPP 0x00000004 +#define VG_SUPPORTFLAG_16BPP 0x00000008 +#define VG_SUPPORTFLAG_24BPP 0x00000010 +#define VG_SUPPORTFLAG_32BPP 0x00000020 +#define VG_SUPPORTFLAG_56HZ 0x00000040 +#define VG_SUPPORTFLAG_60HZ 0x00000080 +#define VG_SUPPORTFLAG_70HZ 0x00000100 +#define VG_SUPPORTFLAG_72HZ 0x00000200 +#define VG_SUPPORTFLAG_75HZ 0x00000400 +#define VG_SUPPORTFLAG_85HZ 0x00000800 +#define VG_SUPPORTFLAG_90HZ 0x00001000 +#define VG_SUPPORTFLAG_100HZ 0x00002000 +#define VG_SUPPORTFLAG_HZMASK 0x00003FC0 +#define VG_SUPPORTFLAG_ADV7171 0x00004000 +#define VG_SUPPORTFLAG_SAA7127 0x00008000 +#define VG_SUPPORTFLAG_FS454 0x00010000 +#define VG_SUPPORTFLAG_ADV7300 0x00020000 +#define VG_SUPPORTFLAG_ENCODERMASK 0x0003C000 +#define VG_SUPPORTFLAG_PANEL 0x00040000 +#define VG_SUPPORTFLAG_TVOUT 0x00080000 +#define VG_SUPPORTFLAG_NTSC 0x00000000 +#define VG_SUPPORTFLAG_PAL 0x00100000 +#define VG_SUPPORTFLAG_480P 0x00200000 +#define VG_SUPPORTFLAG_720P 0x00300000 +#define VG_SUPPORTFLAG_1080I 0x00400000 +#define VG_SUPPORTFLAG_6X4_NTSC 0x00500000 +#define VG_SUPPORTFLAG_8X6_NTSC 0x00600000 +#define VG_SUPPORTFLAG_10X7_NTSC 0x00700000 +#define VG_SUPPORTFLAG_6X4_PAL 0x00800000 +#define VG_SUPPORTFLAG_8X6_PAL 0x00900000 +#define VG_SUPPORTFLAG_10X7_PAL 0x00A00000 +#define VG_SUPPORTFLAG_TVMODEMASK 0x00F00000 + +#define VG_MODEFLAG_NEG_HSYNC 0x00000001 +#define VG_MODEFLAG_NEG_VSYNC 0x00000002 +#define VG_MODEFLAG_INTERLACED 0x00000004 +#define VG_MODEFLAG_PANELOUT 0x00000008 +#define VG_MODEFLAG_CENTERED 0x00000010 +#define VG_MODEFLAG_LINEARPITCH 0x00000020 +#define VG_MODEFLAG_TVOUT 0x00000040 +#define VG_MODEFLAG_HALFCLOCK 0x00000080 +#define VG_MODEFLAG_QVGA 0x00000100 +#define VG_MODEFLAG_EXCLUDEPLL 0x00000200 +#define VG_MODEFLAG_NOPANELTIMINGS 0x00000400 +#define VG_MODEFLAG_XVGA_TFT 0x00000800 +#define VG_MODEFLAG_CUSTOM_PANEL 0x00001000 +#define VG_MODEFLAG_CRT_AND_FP 0x00002000 +#define VG_MODEFLAG_LOW_BAND 0x00000000 +#define VG_MODEFLAG_AVG_BAND 0x00004000 +#define VG_MODEFLAG_HIGH_BAND 0x00008000 +#define VG_MODEFLAG_LEGACY_BAND 0x0000C000 +#define VG_MODEFLAG_BANDWIDTHMASK 0x0000C000 +#define VG_MODEFLAG_OVERRIDE_BAND 0x00010000 +#define VG_MODEFLAG_INT_ADDRESS 0x00000000 +#define VG_MODEFLAG_INT_LINEDOUBLE 0x00020000 +#define VG_MODEFLAG_INT_FLICKER 0x00040000 +#define VG_MODEFLAG_INT_MASK 0x00060000 +#define VG_MODEFLAG_INT_OVERRIDE 0x00080000 +#define VG_MODEFLAG_INVERT_SHFCLK 0x00100000 +#define VG_MODEFLAG_MANUAL_FREQUENCY 0x00200000 +#define VG_MODEFLAG_PLL_BYPASS 0x00400000 +#define VG_MODEFLAG_VIP_TO_DOT_CLOCK 0x00800000 + +#define VG_MODEFLAG_VALIDUSERFLAGS (VG_MODEFLAG_CRT_AND_FP | \ + VG_MODEFLAG_XVGA_TFT | \ + VG_MODEFLAG_NOPANELTIMINGS | \ + VG_MODEFLAG_EXCLUDEPLL | \ + VG_MODEFLAG_LINEARPITCH) + +typedef struct tagVGDisplayMode +{ + /* DISPLAY MODE FLAGS */ + /* Includes BPP, refresh rate information, interlacing, etc. */ + + unsigned long internal_flags; + unsigned long flags; + + /* SOURCE RESOLUTION */ + /* The following values reflect the resolution of the data in the frame */ + /* buffer. These values are used to enable scaling and filtering. */ + + unsigned long src_width; + unsigned long src_height; + + /* PANEL SETTINGS */ + /* These allow a user to set a panel mode through the vg_set_custom_mode */ + /* routine. These values are only relevant if the VG_MODEFLAG_PANEL is */ + /* also set. */ + + unsigned long mode_width; + unsigned long mode_height; + unsigned long panel_width; + unsigned long panel_height; + unsigned long panel_tim1; + unsigned long panel_tim2; + unsigned long panel_dither_ctl; + unsigned long panel_pad_sel_low; + unsigned long panel_pad_sel_high; + + /* OUTPUT TIMINGS */ + /* If the active width and height do not match the source */ + /* dimensions the graphics data will be scaled. */ + + unsigned long hactive; + unsigned long hblankstart; + unsigned long hsyncstart; + unsigned long hsyncend; + unsigned long hblankend; + unsigned long htotal; + + unsigned long vactive; + unsigned long vblankstart; + unsigned long vsyncstart; + unsigned long vsyncend; + unsigned long vblankend; + unsigned long vtotal; + + unsigned long vactive_even; + unsigned long vblankstart_even; + unsigned long vsyncstart_even; + unsigned long vsyncend_even; + unsigned long vblankend_even; + unsigned long vtotal_even; + + /* CLOCK FREQUENCY */ + + unsigned long frequency; + +} VG_DISPLAY_MODE; + +/*-------------------------------------------*/ +/* PLL FLAGS */ +/*-------------------------------------------*/ + +#define VG_PLL_DIVIDE_BY_2 0x00000001 +#define VG_PLL_DIVIDE_BY_4 0x00000002 +#define VG_PLL_BYPASS 0x00000004 +#define VG_PLL_MANUAL 0x00000008 +#define VG_PLL_VIP_CLOCK 0x00000010 + +/*-------------------------------------------*/ +/* USER STRUCTURE FOR QUERYING DISPLAY MODES */ +/*-------------------------------------------*/ + +typedef struct tagQueryDisplayMode +{ + int interlaced; + int halfclock; + unsigned long active_width; + unsigned long active_height; + unsigned long panel_width; + unsigned long panel_height; + unsigned long total_width; + unsigned long total_height; + unsigned long bpp; + unsigned long hz; + unsigned long frequency; + unsigned long query_flags; + unsigned long encoder; + unsigned long tvmode; + +} VG_QUERY_MODE; + +/*-------------------------------------------*/ +/* USER STRUCTURE FOR QUERYING CURSOR DATA */ +/*-------------------------------------------*/ + +typedef struct tagCursorData +{ + int enable; + int color_cursor; + unsigned long cursor_offset; + unsigned long cursor_x; + unsigned long cursor_y; + unsigned long clipx; + unsigned long clipy; + unsigned long mono_color0; + unsigned long mono_color1; + unsigned long flags; + +} VG_CURSOR_DATA; + +/*------------------------------------------------*/ +/* VG INTERRUPT STATUS SOURCES */ +/*------------------------------------------------*/ + +#define VG_INT_LINE_MATCH 0x00010000 +#define VG_INT_VSYNC_LOSS 0x00020000 + +/*------------------------------------------------*/ +/* USER STRUCTURE FOR SETTING COMPRESSION DATA */ +/*------------------------------------------------*/ + +typedef struct tagCompressionData +{ + unsigned long compression_offset; + unsigned long pitch; + unsigned long size; + unsigned long flags; + +} VG_COMPRESSION_DATA; + +/*-------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING LINE INTERRUPTS */ +/*-------------------------------------------------*/ + +typedef struct tagInterruptInfo +{ + unsigned long line; + unsigned long flags; + int enable; + +} VG_INTERRUPT_PARAMS; + +/*-------------------------------------------------*/ +/* USER STRUCTURE FOR PANNING THE DESKTOP */ +/*-------------------------------------------------*/ + +typedef struct tagPanningInfo +{ + unsigned long start_x; + unsigned long start_y; + int start_updated; + +} VG_PANNING_COORDINATES; + +/*--------------------------------------------------*/ +/* USER STRUCTURE FOR SAVING/RESTORING THE VG STATE */ +/*--------------------------------------------------*/ + +typedef struct tagVGSaveRestore +{ + /* VG REGISTERS */ + + unsigned long unlock; + unsigned long gcfg; + unsigned long dcfg; + unsigned long arb_cfg; + unsigned long fb_offset; + unsigned long cb_offset; + unsigned long cursor_offset; + unsigned long video_y_offset; + unsigned long video_u_offset; + unsigned long video_v_offset; + unsigned long dv_top; + unsigned long line_size; + unsigned long gfx_pitch; + unsigned long video_yuv_pitch; + unsigned long h_active; + unsigned long h_blank; + unsigned long h_sync; + unsigned long v_active; + unsigned long v_blank; + unsigned long v_sync; + unsigned long fb_active; + unsigned long cursor_x; + unsigned long cursor_y; + unsigned long vid_ds_delta; + unsigned long fb_base; + unsigned long dv_ctl; + unsigned long gfx_scale; + unsigned long irq_ctl; + unsigned long vbi_even_ctl; + unsigned long vbi_odd_ctl; + unsigned long vbi_hor_ctl; + unsigned long vbi_odd_line_enable; + unsigned long vbi_even_line_enable; + unsigned long vbi_pitch; + unsigned long color_key; + unsigned long color_key_mask; + unsigned long color_key_x; + unsigned long color_key_y; + unsigned long irq; + unsigned long genlk_ctl; + unsigned long vid_y_even_offset; + unsigned long vid_u_even_offset; + unsigned long vid_v_even_offset; + unsigned long vactive_even; + unsigned long vblank_even; + unsigned long vsync_even; + unsigned long h_coeff[512]; + unsigned long v_coeff[256]; + unsigned long palette[261]; + unsigned long cursor_data[3072]; + unsigned long dot_pll; + unsigned long pll_flags; + + /* VG MSRS */ + + Q_WORD msr_cap; + Q_WORD msr_config; + Q_WORD msr_smi; + Q_WORD msr_error; + Q_WORD msr_pm; + Q_WORD msr_diag; + Q_WORD msr_spare; + Q_WORD msr_ram_ctl; + +} VG_SAVE_RESTORE; + +/*-------------------------------------------*/ +/* VG_GET_DISPLAY_MODE_INDEX PARAMETERS */ +/*-------------------------------------------*/ + +#define VG_QUERYFLAG_ACTIVEWIDTH 0x00000001 +#define VG_QUERYFLAG_ACTIVEHEIGHT 0x00000002 +#define VG_QUERYFLAG_TOTALWIDTH 0x00000004 +#define VG_QUERYFLAG_TOTALHEIGHT 0x00000008 +#define VG_QUERYFLAG_BPP 0x00000010 +#define VG_QUERYFLAG_REFRESH 0x00000020 +#define VG_QUERYFLAG_PIXELCLOCK 0x00000040 +#define VG_QUERYFLAG_PIXELCLOCK_APPROX 0x00000080 +#define VG_QUERYFLAG_PANEL 0x00000100 +#define VG_QUERYFLAG_PANELWIDTH 0x00000200 +#define VG_QUERYFLAG_PANELHEIGHT 0x00000400 +#define VG_QUERYFLAG_TVOUT 0x00000800 +#define VG_QUERYFLAG_INTERLACED 0x00001000 +#define VG_QUERYFLAG_HALFCLOCK 0x00002000 +#define VG_QUERYFLAG_ENCODER 0x00004000 +#define VG_QUERYFLAG_TVMODE 0x00008000 + +/*-----------------------------------------------*/ +/* VG FLICKER FILTER SETTINGS */ +/*-----------------------------------------------*/ + +#define VG_FLICKER_FILTER_NONE 0x00000000 +#define VG_FLICKER_FILTER_1_16 0x10000000 +#define VG_FLICKER_FILTER_1_8 0x20000000 +#define VG_FLICKER_FILTER_1_4 0x40000000 +#define VG_FLICKER_FILTER_5_16 0x50000000 +#define VG_FLICKER_FILTER_MASK 0xF0000000 + +/*-----------------------------------------------*/ +/* VG CRC SOURCES */ +/*-----------------------------------------------*/ + +#define VG_CRC_SOURCE_PREFILTER 0x00000000 +#define VG_CRC_SOURCE_PREFLICKER 0x00000001 +#define VG_CRC_SOURCE_POSTFLICKER 0x00000002 +#define VG_CRC_SOURCE_PREFILTER_EVEN 0x00000010 +#define VG_CRC_SOURCE_PREFLICKER_EVEN 0x00000011 +#define VG_CRC_SOURCE_POSTFLICKER_EVEN 0x00000012 +#define VG_CRC_SOURCE_EVEN 0x00000010 + +/*===================================================*/ +/* DISPLAY FILTER PARAMETERS */ +/*===================================================*/ + +/*-----------------------------------------------*/ +/* VIDEO FORMAT DEFINITIONS */ +/*-----------------------------------------------*/ + +#define DF_VIDFMT_UYVY 0x0000 +#define DF_VIDFMT_Y2YU 0x0001 +#define DF_VIDFMT_YUYV 0x0002 +#define DF_VIDFMT_YVYU 0x0003 +#define DF_VIDFMT_Y0Y1Y2Y3 0x0004 +#define DF_VIDFMT_Y3Y2Y1Y0 0x0005 +#define DF_VIDFMT_Y1Y0Y3Y2 0x0006 +#define DF_VIDFMT_Y1Y2Y3Y0 0x0007 +#define DF_VIDFMT_RGB 0x0008 +#define DF_VIDFMT_P2M_P2L_P1M_P1L 0x0009 +#define DF_VIDFMT_P1M_P1L_P2M_P2L 0x000A +#define DF_VIDFMT_P1M_P2L_P2M_P1L 0x000B + +/*-----------------------------------------------*/ +/* CRT ENABLE STATES */ +/*-----------------------------------------------*/ + +#define DF_CRT_DISABLE 0x0000 +#define DF_CRT_ENABLE 0x0001 +#define DF_CRT_STANDBY 0x0002 +#define DF_CRT_SUSPEND 0x0003 + +/*-----------------------------------------------*/ +/* VIDEO SCALING FLAGS */ +/*-----------------------------------------------*/ + +#define DF_SCALEFLAG_CHANGEX 0x0001 +#define DF_SCALEFLAG_CHANGEY 0x0002 + +/*-----------------------------------------------*/ +/* DISPLAY FILTER COLOR SPACES */ +/*-----------------------------------------------*/ + +#define DF_OUTPUT_RGB 0x0001 +#define DF_OUTPUT_ARGB 0x0002 +#define DF_OUTPUT_SDTV 0x0003 +#define DF_OUTPUT_HDTV 0x0004 + +/*-----------------------------------------------*/ +/* DISPLAY FILTER OUTPUT PATHS */ +/*-----------------------------------------------*/ + +#define DF_DISPLAY_CRT 0x0001 +#define DF_DISPLAY_FP 0x0002 +#define DF_DISPLAY_CRT_FP 0x0003 +#define DF_DISPLAY_VOP 0x0004 +#define DF_DISPLAY_DRGB 0x0005 +#define DF_DISPLAY_CRT_DRGB 0x0006 + +/*-----------------------------------------------*/ +/* WINDOWED CRC DATA SOURCES */ +/*-----------------------------------------------*/ + +#define DF_CRC_SOURCE_GFX_DATA 0x0000 +#define DF_CRC_SOURCE_CRT_RGB 0x0001 +#define DF_CRC_SOURCE_FP_DATA 0x0002 + +/*-----------------------------------------------*/ +/* VIDEO ENABLE FLAGS */ +/*-----------------------------------------------*/ + +#define DF_ENABLEFLAG_NOCOLORKEY 0x0001 + +/*-----------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING A VIDEO SOURCE */ +/*-----------------------------------------------*/ + +#define DF_SOURCEFLAG_HDTVSOURCE 0x0001 +#define DF_SOURCEFLAG_IMPLICITSCALING 0x0002 + +typedef struct tagVideoSourceInfo +{ + unsigned long video_format; + unsigned long y_offset; + unsigned long u_offset; + unsigned long v_offset; + unsigned long y_pitch; + unsigned long uv_pitch; + unsigned long width; + unsigned long height; + unsigned long flags; + +} DF_VIDEO_SOURCE_PARAMS; + +/*---------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING THE VIDEO POSITION */ +/*---------------------------------------------------*/ + +#define DF_POSFLAG_DIRECTCLIP 0x0001 +#define DF_POSFLAG_INCLUDEBORDER 0x0002 + +typedef struct tagVideoPosition +{ + long x; + long y; + unsigned long width; + unsigned long height; + unsigned long left_clip; + unsigned long dst_clip; + unsigned long flags; + +} DF_VIDEO_POSITION; + +/*-------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING THE VIDEO CURSOR */ +/*-------------------------------------------------*/ + +typedef struct tagVideoCursorInfo +{ + unsigned long key; + unsigned long mask; + unsigned long color1; + unsigned long color2; + unsigned long select_color2; + unsigned long flags; + +} DF_VIDEO_CURSOR_PARAMS; + +/*-------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING AN ALPHA REGION */ +/*-------------------------------------------------*/ + +#define DF_ALPHAFLAG_COLORENABLED 0x0001 +#define DF_ALPHAFLAG_PERPIXELENABLED 0x0002 + +typedef struct tagAlphaRegionInfo +{ + unsigned long x; + unsigned long y; + unsigned long width; + unsigned long height; + unsigned long alpha_value; + unsigned long priority; + unsigned long color; + unsigned long flags; + long delta; + +} DF_ALPHA_REGION_PARAMS; + +/*-------------------------------------------------*/ +/* USER STRUCTURE FOR SAVING/RESTORING DF DATA */ +/*-------------------------------------------------*/ + +typedef struct tagDFSaveRestore +{ + unsigned long vcfg; + unsigned long dcfg; + unsigned long video_x; + unsigned long video_y; + unsigned long video_scaler; + unsigned long video_color_key; + unsigned long video_color_mask; + unsigned long sat_limit; + unsigned long vid_misc; + unsigned long video_yscale; + unsigned long video_xscale; + unsigned long vid_alpha_control; + unsigned long cursor_key; + unsigned long cursor_mask; + unsigned long cursor_color1; + unsigned long cursor_color2; + unsigned long alpha_xpos1; + unsigned long alpha_ypos1; + unsigned long alpha_color1; + unsigned long alpha_control1; + unsigned long alpha_xpos2; + unsigned long alpha_ypos2; + unsigned long alpha_color2; + unsigned long alpha_control2; + unsigned long alpha_xpos3; + unsigned long alpha_ypos3; + unsigned long alpha_color3; + unsigned long alpha_control3; + unsigned long vid_request; + unsigned long vid_ypos_even; + unsigned long alpha_ypos_even1; + unsigned long alpha_ypos_even2; + unsigned long alpha_ypos_even3; + unsigned long panel_tim1; + unsigned long panel_tim2; + unsigned long panel_pm; + unsigned long panel_dither; + + unsigned long palette[256]; + unsigned long coefficients[512]; + + /* DF MSRS */ + + Q_WORD msr_cap; + Q_WORD msr_config; + Q_WORD msr_smi; + Q_WORD msr_error; + Q_WORD msr_pm; + Q_WORD msr_diag; + Q_WORD msr_df_diag; + Q_WORD msr_pad_sel; + +} DF_SAVE_RESTORE; + +/*-----------------------------------------------*/ +/* DF CRC SOURCES */ +/*-----------------------------------------------*/ + +#define DF_CRC_SOURCE_ODD_FIELD 0x00000100 +#define DF_CRC_SOURCE_EVEN_FIELD 0x00001000 +#define DF_CRC_SOURCE_EVEN 0x00001000 + +/*===================================================*/ +/* VIP USER PARAMETER DEFINITIONS */ +/*===================================================*/ + +#define VIP_MODEFLAG_VSYNCACTIVEHIGH 0x00000001 +#define VIP_MODEFLAG_HSYNCACTIVEHIGH 0x00000002 + +/*---------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING 601 SETTINGS */ +/*---------------------------------------------*/ + +typedef struct _TAG_VIP601PARAMS +{ + unsigned long flags; + unsigned long horz_start; + unsigned long width; + unsigned long vert_start_even; + unsigned long even_height; + unsigned long vert_start_odd; + unsigned long odd_height; + unsigned long vbi_start; + unsigned long vbi_height; + unsigned long odd_detect_start; + unsigned long odd_detect_end; + +} VIP_601PARAMS; + +/*-------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING A VIP MODE */ +/*-------------------------------------------*/ + +/* VIP MODE FLAGS */ + +#define VIP_MODEFLAG_PLANARCAPTURE 0x00000001 +#define VIP_MODEFLAG_INVERTPOLARITY 0x00000002 +#define VIP_MODEFLAG_PROGRESSIVE 0x00000004 +#define VIP_MODEFLAG_DISABLEZERODETECT 0x00000008 +#define VIP_MODEFLAG_ENABLEREPEATFLAG 0x00000010 +#define VIP_MODEFLAG_10BITANCILLARY 0x00000020 +#define VIP_MODEFLAG_TOGGLEEACHFIELD 0x00000040 +#define VIP_MODEFLAG_INVERTTASKPOLARITY 0x00000080 +#define VIP_MODEFLAG_FLIPMESSAGEWHENFULL 0x00000100 + +/* VIP CAPTURE ENABLE FLAGS */ + +#define VIP_ENABLE_TASKA 0x00000100 +#define VIP_ENABLE_TASKA_VBI 0x00000200 +#define VIP_ENABLE_TASKB 0x00000400 +#define VIP_ENABLE_TASKB_VBI 0x00000800 +#define VIP_ENABLE_ANCILLARY 0x00001000 +#define VIP_ENABLE_ALL 0x00001F00 + +/* VIP CAPTURE MODE FLAGS */ + +#define VIP_MODE_IDLE 0x00000000 +#define VIP_MODE_VIP2_8BIT 0x00000002 +#define VIP_MODE_VIP2_16BIT 0x00000004 +#define VIP_MODE_VIP1_8BIT 0x00000006 +#define VIP_MODE_MSG 0x00000008 +#define VIP_MODE_DATA 0x0000000A +#define VIP_MODE_8BIT601 0x0000000C +#define VIP_MODE_16BIT601 0x0000000E + +/* 4:2:0 PLANAR CAPTURE METHODS */ + +#define VIP_420CAPTURE_EVERYLINE 0x00000001 +#define VIP_420CAPTURE_ALTERNATINGLINES 0x00000002 +#define VIP_420CAPTURE_ALTERNATINGFIELDS 0x00000003 + +typedef struct _TAG_SETMODEBUFFER +{ + unsigned long flags; + unsigned long stream_enables; + unsigned long operating_mode; + unsigned long planar_capture; + VIP_601PARAMS vip601_settings; + +} VIPSETMODEBUFFER; + +/*-----------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING VG/VIP GENLOCK */ +/*-----------------------------------------------*/ + +/* LOSS OF VIDEO DETECTION FLAGS */ + +#define VIP_VDE_RUNAWAY_LINE 0x00800000 +#define VIP_VDE_VERTICAL_TIMING 0x00400000 +#define VIP_VDE_CLOCKS_PER_LINE 0x00200000 +#define VIP_VDE_LOST_CLOCK 0x00100000 + +/* VIP VSYNC SELECT FOR THE VG */ + +#define VIP_VGSYNC_NONE 0x00000000 +#define VIP_VGSYNC_START_FRAME 0x00000001 +#define VIP_VGSYNC_FALLING_EDGE_VBLANK 0x00000002 +#define VIP_VGSYNC_RISING_EDGE_VBLANK 0x00000003 +#define VIP_VGSYNC_FALLING_EDGE_FIELD 0x00000004 +#define VIP_VGSYNC_RISING_EDGE_FIELD 0x00000005 +#define VIP_VGSYNC_VIP_CURRENT_LINE 0x00000006 +#define VIP_VGSYNC_MSG_INT 0x00000007 + +/* VIP FIELD SELECT FOR THE VG */ + +#define VIP_VGFIELD_INPUT 0x00000000 +#define VIP_VGFIELD_INPUT_INV 0x00000008 +#define VIP_VGFIELD_ACTIVE_PAGE 0x00000010 +#define VIP_VGFIELD_ACTIVE_PAGE_IN 0x00000018 + +/*--------------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING THE VG VSYNC GENLOCK */ +/*--------------------------------------------------------*/ + +typedef struct _TAG_GENLOCKBUFFER +{ + unsigned long vip_signal_loss; + unsigned long vsync_to_vg; + unsigned long field_to_vg; + unsigned long genlock_skew; + int enable_timeout; + +} VIPGENLOCKBUFFER; + +/*------------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING VIP ANCILLARY CAPTURE */ +/*------------------------------------------------------*/ + +typedef struct _TAG_ANCILLARYBUFFER +{ + unsigned long msg1_base; + unsigned long msg2_base; + unsigned long msg_size; + +} VIPANCILLARYBUFFER; + +/*----------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING VIP CAPTURE BUFFERS */ +/*----------------------------------------------------*/ + +#define VIP_INPUTFLAG_VBI 0x00000001 +#define VIP_INPUTFLAG_INVERTPOLARITY 0x00000002 +#define VIP_INPUTFLAG_PLANAR 0x00000004 + +#define VIP_MAX_BUFFERS 10 + +#define VIP_BUFFER_TASK_A 0x0000 +#define VIP_BUFFER_TASK_B 0x0001 +#define VIP_BUFFER_MAX_TASKS 0x0002 + +#define VIP_BUFFER_A 0x0000 +#define VIP_BUFFER_B 0x0001 +#define VIP_BUFFER_ANC 0x0002 +#define VIP_BUFFER_MSG 0x0003 +#define VIP_BUFFER_601 0x0004 +#define VIP_BUFFER_A_ODD 0x0005 +#define VIP_BUFFER_A_EVEN 0x0006 +#define VIP_BUFFER_B_ODD 0x0007 +#define VIP_BUFFER_B_EVEN 0x0008 + +typedef struct _TAG_INPUTBUFFER_ADDR +{ + unsigned long even_base[VIP_MAX_BUFFERS]; + unsigned long odd_base[VIP_MAX_BUFFERS]; + unsigned long y_pitch; + unsigned long uv_pitch; + unsigned long odd_uoffset; + unsigned long odd_voffset; + unsigned long even_uoffset; + unsigned long even_voffset; + unsigned long vbi_even_base; + unsigned long vbi_odd_base; + +} VIPINPUTBUFFER_ADDR; + +typedef struct _TAG_SETINPUTBUFFER +{ + unsigned long flags; + VIPINPUTBUFFER_ADDR offsets[VIP_BUFFER_MAX_TASKS]; + unsigned long current_buffer; + + VIPANCILLARYBUFFER ancillaryData; + +} VIPINPUTBUFFER; + +/*------------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING VIP SUBWINDOW CAPTURE */ +/*------------------------------------------------------*/ + +typedef struct _TAG_SUBWINDOWBUFFER +{ + int enable; + unsigned long start; + unsigned long stop; + +} VIPSUBWINDOWBUFFER; + +/*--------------------------------------------------------*/ +/* USER STRUCTURE FOR SAVING/RESTORING VIP REGISTERS */ +/*--------------------------------------------------------*/ + +typedef struct _TAG_VIPSTATEBUFFER +{ + unsigned long control1; + unsigned long control2; + unsigned long vip_int; + unsigned long current_target; + unsigned long max_address; + unsigned long taska_evenbase; + unsigned long taska_oddbase; + unsigned long taska_vbi_evenbase; + unsigned long taska_vbi_oddbase; + unsigned long taska_data_pitch; + unsigned long control3; + unsigned long taska_v_oddoffset; + unsigned long taska_u_oddoffset; + unsigned long taskb_evenbase; + unsigned long taskb_oddbase; + unsigned long taskb_vbi_evenbase; + unsigned long taskb_vbi_oddbase; + unsigned long taskb_pitch; + unsigned long taskb_voffset; + unsigned long taskb_uoffset; + unsigned long msg1_base; + unsigned long msg2_base; + unsigned long msg_size; + unsigned long page_offset; + unsigned long vert_start_stop; + unsigned long vsync_err_count; + unsigned long taska_u_evenoffset; + unsigned long taska_v_evenoffset; + + Q_WORD msr_config; + Q_WORD msr_smi; + Q_WORD msr_pm; + Q_WORD msr_diag; + +} VIPSTATEBUFFER; + +/*--------------------------------------------------------*/ +/* VIP_SET_CAPTURE_STATE USER PARAMETERS */ +/*--------------------------------------------------------*/ + +#define VIP_STOPCAPTURE 0x0000 +#define VIP_STOPCAPTUREATLINEEND 0x0001 +#define VIP_STOPCAPTUREATFIELDEND 0x0002 +#define VIP_STOPCAPTUREATFRAMEEND 0x0003 +#define VIP_STARTCAPTUREATNEXTLINE 0x0004 +#define VIP_STARTCAPTUREATNEXTFIELD 0x0005 +#define VIP_STARTCAPTUREATNEXTFRAME 0x0006 +#define VIP_STARTCAPTURE 0x0007 + +/*--------------------------------------------------------*/ +/* VIP_CONFIGURE_FIFO USER PARAMETERS */ +/*--------------------------------------------------------*/ + +#define VIP_VIDEOTHRESHOLD 0x3000 +#define VIP_ANCILLARYTHRESHOLD 0x3001 +#define VIP_VIDEOFLUSH 0x3002 +#define VIP_ANCILLARYFLUSH 0x3003 + +/*--------------------------------------------------------*/ +/* VIP_SET_INTERRUPT_ENABLE USER DEFINITIONS */ +/*--------------------------------------------------------*/ + +#define VIP_INT_FIFO_ERROR 0x80000000 +#define VIP_INT_FIFO_WRAP 0x40000000 +#define VIP_INT_FIFO_OVERFLOW 0x20000000 +#define VIP_INT_FIFO_THRESHOLD 0x10000000 +#define VIP_INT_LONGLINE 0x08000000 +#define VIP_INT_VERTICAL_TIMING 0x04000000 +#define VIP_INT_ACTIVE_PIXELS 0x02000000 +#define VIP_INT_CLOCK_INPUT 0x01000000 +#define VIP_INT_ANC_CHECKSUM_PARITY 0x00800000 +#define VIP_INT_MSG_BUFFER_FULL 0x00400000 +#define VIP_INT_END_VBLANK 0x00200000 +#define VIP_INT_START_VBLANK 0x00100000 +#define VIP_INT_START_EVEN 0x00080000 +#define VIP_INT_START_ODD 0x00040000 +#define VIP_INT_LINE_MATCH_TARGET 0x00020000 +#define VIP_ALL_INTERRUPTS 0xFFFE0000 + +/*--------------------------------------------------------*/ +/* VIP_GET_CURRENT_FIELD RETURN VALUES */ +/*--------------------------------------------------------*/ + +#define VIP_ODD_FIELD 1 +#define VIP_EVEN_FIELD 0 + +/*-------------------------------------------------*/ +/* USER STRUCTURE FOR QUERYING VIP CAPABILITIES */ +/*-------------------------------------------------*/ + +typedef struct _TAG_CAPABILITIESBUFFER +{ + unsigned long revision_id; + unsigned long device_id; + unsigned long n_clock_domains; + unsigned long n_smi_registers; + +} VIPCAPABILITIESBUFFER; + +/*-------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING VIP POWER */ +/*-------------------------------------------------*/ + +typedef struct _TAG_POWERBUFFER +{ + int glink_clock_mode; + int vip_clock_mode; + +} VIPPOWERBUFFER; + +/*-------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING VIP PRIORITIES */ +/*-------------------------------------------------*/ + +typedef struct _TAG_PRIORITYBUFFER +{ + unsigned long secondary; + unsigned long primary; + unsigned long pid; + +} VIPPRIORITYBUFFER; + +/*--------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING VIP DEBUG OUTPUTS */ +/*--------------------------------------------------*/ + +#define VIP_DIAG_UPPER_GLINK_MASTER 0x00010000 +#define VIP_DIAG_UPPER_GLINK_SLAVE 0x00020000 +#define VIP_DIAG_UPPER_GLINK_SLAVE_MMREG 0x00040000 +#define VIP_DIAG_UPPER_Y_BUFFER 0x00080000 +#define VIP_DIAG_UPPER_A_BUFFER 0x00100000 +#define VIP_DIAG_UPPER_FIFO_OUTPUT 0x00200000 +#define VIP_DIAG_UPPER_FIFO_INPUT 0x01000000 +#define VIP_DIAG_UPPER_FORMATTER 0x02000000 +#define VIP_DIAG_UPPER_INPUT_CONTROL 0x04000000 + +#define VIP_DIAG_LOWER_GLINK_MASTER 0x00000001 +#define VIP_DIAG_LOWER_GLINK_SLAVE 0x00000002 +#define VIP_DIAG_LOWER_GLINK_SLAVE_MMREG 0x00000004 +#define VIP_DIAG_LOWER_Y_BUFFER 0x00000008 +#define VIP_DIAG_LOWER_A_BUFFER 0x00000010 +#define VIP_DIAG_LOWER_FIFO_OUTPUT 0x00000020 +#define VIP_DIAG_LOWER_FIFO_INPUT 0x00000100 +#define VIP_DIAG_LOWER_FORMATTER 0x00000200 +#define VIP_DIAG_LOWER_INPUT_CONTROL 0x00000400 + +typedef struct _TAG_DEBUGBUFFER +{ + unsigned long bist; + unsigned long enable_upper; + unsigned long select_upper; + unsigned long enable_lower; + unsigned long select_lower; + +} VIPDEBUGBUFFER; + + +/*===================================================*/ +/* VOP USER PARAMETER DEFINITIONS */ +/*===================================================*/ + +/*------------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING VBI CAPTURE */ +/*------------------------------------------------------*/ + +typedef struct _TAG_VBIWINDOWBUFFER +{ + long horz_start; + unsigned long vbi_width; + unsigned long odd_line_capture_mask; + unsigned long even_line_capture_mask; + unsigned long odd_line_offset; + unsigned long even_line_offset; + unsigned long even_address_offset; + unsigned long odd_address_offset; + unsigned long data_size; + unsigned long data_pitch; + int enable_upscale; + int horz_from_hsync; + +} VOPVBIWINDOWBUFFER; + +/*------------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING 601 FOR VOP */ +/*------------------------------------------------------*/ + +#define VOP_601_INVERT_DISPE 0x00080000 +#define VOP_601_INVERT_VSYNC 0x00040000 +#define VOP_601_INVERT_HSYNC 0x00020000 + +#define VOP_VSYNC_EARLIER_BY4 0x00000000 +#define VOP_VSYNC_EARLIER_BY2 0x00004000 +#define VOP_VSYNC_NOSHIFT 0x00008000 +#define VOP_VSYNC_LATER_BY_X 0x0000C000 + +#define VOP_601_YUV_8BIT 0x00000000 +#define VOP_601_YUV_16BIT 0x00000001 +#define VOP_601_RGB_8_8_8 0x00000002 +#define VOP_601_YUV_4_4_4 0x00000003 + +typedef struct _TAG_VOP601 +{ + unsigned long flags; + unsigned long vsync_shift; + unsigned long vsync_shift_count; + unsigned long output_mode; + +} VOP_601DATA; + +/*------------------------------------------------------*/ +/* USER STRUCTURE FOR CONFIGURING VOP OUTPUT */ +/*------------------------------------------------------*/ + +/* VOP FLAGS */ + +#define VOP_FLAG_SINGLECHIPCOMPAT 0x00000001 +#define VOP_FLAG_EXTENDEDSAV 0x00000002 +#define VOP_FLAG_VBI 0x00000008 +#define VOP_FLAG_TASK 0x00000010 +#define VOP_FLAG_SWAP_UV 0x00000020 +#define VOP_FLAG_SWAP_VBI 0x00000040 + +/* 4:4:2 TO 4:2:2 DECIMATION */ + +#define VOP_422MODE_COSITED 0x00000000 +#define VOP_422MODE_INTERSPERSED 0x00000010 +#define VOP_422MODE_ALTERNATING 0x00000020 + +/* VOP OPERATING MODES */ + +#define VOP_MODE_DISABLED 0x00000000 +#define VOP_MODE_VIP11 0x00000001 +#define VOP_MODE_CCIR656 0x00000002 +#define VOP_MODE_VIP20_8BIT 0x00000003 +#define VOP_MODE_VIP20_16BIT 0x00000004 +#define VOP_MODE_601 0x00000005 + +/* VSYNC OUT SELECT FLAGS */ + +#define VOP_MB_SYNCSEL_DISABLED 0x00000000 +#define VOP_MB_SYNCSEL_VG 0x00000020 +#define VOP_MB_SYNCSEL_VG_INV 0x00000040 +#define VOP_MB_SYNCSEL_STATREG17 0x00000060 +#define VOP_MB_SYNCSEL_STATREG17_INV 0x00000080 + +typedef struct _TAG_VOPMODECONFIGURATIONBUFFER +{ + unsigned long flags; + unsigned long mode; + unsigned long conversion_mode; + unsigned long vsync_out; + VOP_601DATA vop601; + +} VOPCONFIGURATIONBUFFER; + +/*--------------------------------------------------------*/ +/* USER STRUCTURE FOR SAVING/RESTORING VOP REGISTERS */ +/*--------------------------------------------------------*/ + +typedef struct _TAG_VOPSTATEBUFFER +{ + unsigned long config; +} VOPSTATEBUFFER; + +#endif --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_regs.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_regs.h 2005-12-14 11:38:35.000000000 -0700 @@ -0,0 +1,1250 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron register definitions + * */ + +#ifndef _cim_regs_h +#define _cim_regs_h + +/*----------------------------------------------------------------*/ +/* GRAPHICS PROCESSOR DEFINITIONS */ +/*----------------------------------------------------------------*/ + +/*----------------------------*/ +/* COMMAND BUFFER DEFINITIONS */ +/*----------------------------*/ + +#define GP3_BLT_COMMAND_SIZE 68 /* 18 DWORDS */ +#define GP3_VECTOR_COMMAND_SIZE 56 /* 14 DWORDS */ +#define GP3_4BPP_LUT_COMMAND_SIZE 76 /* 16 DWORDS + 3 CMD DWORDS */ +#define GP3_8BPP_LUT_COMMAND_SIZE 1036 /* 256 DWORDS + 3 CMD DWORDS */ +#define GP3_VECTOR_PATTERN_COMMAND_SIZE 20 /* 2 DWORDS + 3 CMD DWORDS */ +#define GP3_MAX_COMMAND_SIZE 9000 /* 8K + WORKAROUND SPACE */ +#define GP3_SCRATCH_BUFFER_SIZE 0x100000 /* 1MB SCRATCH BUFFER */ +#define GP3_BLT_1PASS_SIZE 0xC7F8 /* (50K - 8) is largest 1-Pass load size */ + +/*-------------------------------------*/ +/* BLT COMMAND BUFFER REGISTER OFFSETS */ +/*-------------------------------------*/ + +#define GP3_BLT_CMD_HEADER 0x00000000 +#define GP3_BLT_RASTER_MODE 0x00000004 +#define GP3_BLT_DST_OFFSET 0x00000008 +#define GP3_BLT_SRC_OFFSET 0x0000000C +#define GP3_BLT_STRIDE 0x00000010 +#define GP3_BLT_WID_HEIGHT 0x00000014 +#define GP3_BLT_SRC_COLOR_FG 0x00000018 +#define GP3_BLT_SRC_COLOR_BG 0x0000001C +#define GP3_BLT_PAT_COLOR_0 0x00000020 +#define GP3_BLT_PAT_COLOR_1 0x00000024 +#define GP3_BLT_PAT_DATA_0 0x00000028 +#define GP3_BLT_PAT_DATA_1 0x0000002C +#define GP3_BLT_CH3_OFFSET 0x00000030 +#define GP3_BLT_CH3_MODE_STR 0x00000034 +#define GP3_BLT_CH3_WIDHI 0x00000038 +#define GP3_BLT_BASE_OFFSET 0x0000003C +#define GP3_BLT_MODE 0x00000040 + +/*-----------------------------------------------------------------*/ +/* VECTOR COMMAND BUFFER REGISTER OFFSETS */ +/* Some of these are identical to the BLT registers (and we will */ +/* be assumed to be such in the Cimarron code, but they are listed */ +/* here for clarity and for future changes. */ +/*-----------------------------------------------------------------*/ + +#define GP3_VEC_CMD_HEADER 0x00000000 +#define GP3_VECTOR_RASTER_MODE 0x00000004 +#define GP3_VECTOR_DST_OFFSET 0x00000008 +#define GP3_VECTOR_VEC_ERR 0x0000000C +#define GP3_VECTOR_STRIDE 0x00000010 +#define GP3_VECTOR_VEC_LEN 0x00000014 +#define GP3_VECTOR_SRC_COLOR_FG 0x00000018 +#define GP3_VECTOR_PAT_COLOR_0 0x0000001C +#define GP3_VECTOR_PAT_COLOR_1 0x00000020 +#define GP3_VECTOR_PAT_DATA_0 0x00000024 +#define GP3_VECTOR_PAT_DATA_1 0x00000028 +#define GP3_VECTOR_CH3_MODE_STR 0x0000002C +#define GP3_VECTOR_BASE_OFFSET 0x00000030 +#define GP3_VECTOR_MODE 0x00000034 + +/*---------------------------------------------------*/ +/* GP REGISTER DEFINITIONS */ +/* Addresses for writing or reading directly to/from */ +/* the graphics processor. */ +/*---------------------------------------------------*/ + +#define GP3_DST_OFFSET 0x00000000 +#define GP3_SRC_OFFSET 0x00000004 +#define GP3_VEC_ERR 0x00000004 +#define GP3_STRIDE 0x00000008 +#define GP3_WID_HEIGHT 0x0000000C +#define GP3_VEC_LEN 0x0000000C +#define GP3_SRC_COLOR_FG 0x00000010 +#define GP3_SRC_COLOR_BG 0x00000014 +#define GP3_PAT_COLOR_0 0x00000018 +#define GP3_PAT_COLOR_1 0x0000001C +#define GP3_PAT_COLOR_2 0x00000020 +#define GP3_PAT_COLOR_3 0x00000024 +#define GP3_PAT_COLOR_4 0x00000028 +#define GP3_PAT_COLOR_5 0x0000002C +#define GP3_PAT_DATA_0 0x00000030 +#define GP3_PAT_DATA_1 0x00000034 +#define GP3_RASTER_MODE 0x00000038 +#define GP3_VEC_MODE 0x0000003C +#define GP3_BLT_MODE 0x00000040 +#define GP3_BLT_STATUS 0x00000044 +#define GP3_HST_SRC 0x00000048 +#define GP3_BASE_OFFSET 0x0000004C +#define GP3_CMD_TOP 0x00000050 +#define GP3_CMD_BOT 0x00000054 +#define GP3_CMD_READ 0x00000058 +#define GP3_CMD_WRITE 0x0000005C +#define GP3_CH3_OFFSET 0x00000060 +#define GP3_CH3_MODE_STR 0x00000064 +#define GP3_CH3_WIDHI 0x00000068 +#define GP3_CH3_HST_SRC 0x0000006C +#define GP3_LUT_ADDRESS 0x00000070 +#define GP3_LUT_DATA 0x00000074 +#define GP3_INT_CTL 0x00000078 +#define GP3_HST_SRC_RANGE 0x00000100 + +/*------------------------*/ +/* REGISTER BIT FIELDS */ +/*------------------------*/ + +/* GP3_BLT_CMD_HEADER BIT DEFINITIONS */ + +#define GP3_BLT_HDR_WRAP 0x80000000 +#define GP3_BLT_HDR_TYPE 0x00000000 +#define GP3_BLT_HDR_HAZARD_ENABLE 0x10000000 +#define GP3_BLT_HDR_RASTER_ENABLE 0x00000001 +#define GP3_BLT_HDR_DST_OFF_ENABLE 0x00000002 +#define GP3_BLT_HDR_SRC_OFF_ENABLE 0x00000004 +#define GP3_BLT_HDR_STRIDE_ENABLE 0x00000008 +#define GP3_BLT_HDR_WIDHI_ENABLE 0x00000010 +#define GP3_BLT_HDR_SRC_FG_ENABLE 0x00000020 +#define GP3_BLT_HDR_SRC_BG_ENABLE 0x00000040 +#define GP3_BLT_HDR_PAT_CLR0_ENABLE 0x00000080 +#define GP3_BLT_HDR_PAT_CLR1_ENABLE 0x00000100 +#define GP3_BLT_HDR_PAT_DATA0_ENABLE 0x00000200 +#define GP3_BLT_HDR_PAT_DATA1_ENABLE 0x00000400 +#define GP3_BLT_HDR_CH3_OFF_ENABLE 0x00000800 +#define GP3_BLT_HDR_CH3_STR_ENABLE 0x00001000 +#define GP3_BLT_HDR_CH3_WIDHI_ENABLE 0x00002000 +#define GP3_BLT_HDR_BASE_OFFSET_ENABLE 0x00004000 +#define GP3_BLT_HDR_BLT_MODE_ENABLE 0x00008000 + +/* GP3_VEC_CMD_HEADER BIT DEFINITIONS */ + +#define GP3_VEC_HDR_WRAP 0x80000000 +#define GP3_VEC_HDR_TYPE 0x20000000 +#define GP3_VEC_HDR_HAZARD_ENABLE 0x10000000 +#define GP3_VEC_HDR_RASTER_ENABLE 0x00000001 +#define GP3_VEC_HDR_DST_OFF_ENABLE 0x00000002 +#define GP3_VEC_HDR_VEC_ERR_ENABLE 0x00000004 +#define GP3_VEC_HDR_STRIDE_ENABLE 0x00000008 +#define GP3_VEC_HDR_VEC_LEN_ENABLE 0x00000010 +#define GP3_VEC_HDR_SRC_FG_ENABLE 0x00000020 +#define GP3_VEC_HDR_PAT_CLR0_ENABLE 0x00000040 +#define GP3_VEC_HDR_PAT_CLR1_ENABLE 0x00000080 +#define GP3_VEC_HDR_PAT_DATA0_ENABLE 0x00000100 +#define GP3_VEC_HDR_PAT_DATA1_ENABLE 0x00000200 +#define GP3_VEC_HDR_CH3_STR_ENABLE 0x00000400 +#define GP3_VEC_HDR_BASE_OFFSET_ENABLE 0x00000800 +#define GP3_VEC_HDR_VEC_MODE_ENABLE 0x00001000 + +/* GP3_RASTER_MODE BIT DEFINITIONS */ + +#define GP3_RM_BPPFMT_332 0x00000000 /* 8 BPP, palettized */ +#define GP3_RM_BPPFMT_4444 0x40000000 /* 16 BPP, 4:4:4:4 */ +#define GP3_RM_BPPFMT_1555 0x50000000 /* 16 BPP, 1:5:5:5 */ +#define GP3_RM_BPPFMT_565 0x60000000 /* 16 BPP, 5:6:5 */ +#define GP3_RM_BPPFMT_8888 0x80000000 /* 32 BPP, 8:8:8:8 */ +#define GP3_RM_ALPHA_ALL 0x00C00000 /* Alpha enable */ +#define GP3_RM_ALPHA_TO_RGB 0x00400000 /* Alpha applies to RGB */ +#define GP3_RM_ALPHA_TO_ALPHA 0x00800000 /* Alpha applies to alpha */ +#define GP3_RM_ALPHA_OP_MASK 0x00300000 /* Alpha operation */ +#define GP3_RM_ALPHA_TIMES_A 0x00000000 /* Alpha * A */ +#define GP3_RM_BETA_TIMES_B 0x00100000 /* (1-alpha) * B */ +#define GP3_RM_A_PLUS_BETA_B 0x00200000 /* A + (1-alpha) * B */ +#define GP3_RM_ALPHA_A_PLUS_BETA_B 0x00300000 /* alpha * A + (1 - alpha)B */ +#define GP3_RM_ALPHA_SELECT 0x000E0000 /* Alpha Select */ +#define GP3_RM_SELECT_ALPHA_A 0x00000000 /* Alpha from channel A */ +#define GP3_RM_SELECT_ALPHA_B 0x00020000 /* Alpha from channel B */ +#define GP3_RM_SELECT_ALPHA_R 0x00040000 /* Registered alpha */ +#define GP3_RM_SELECT_ALPHA_1 0x00060000 /* Constant 1 */ +#define GP3_RM_SELECT_ALPHA_CHAN_A 0x00080000 /* RGB Values from A */ +#define GP3_RM_SELECT_ALPHA_CHAN_B 0x000A0000 /* RGB Values from B */ +#define GP3_RM_SELECT_ALPHA_CHAN_3 0x000C0000 /* Alpha from channel 3 */ +#define GP3_RM_DEST_FROM_CHAN_A 0x00010000 /* Alpha channel select */ +#define GP3_RM_PATTERN_INVERT 0x00001000 /* Invert monochrome pat */ +#define GP3_RM_SOURCE_INVERT 0x00002000 /* Invert monochrome src */ +#define GP3_RM_PAT_FLAGS 0x00000700 /* pattern related bits */ +#define GP3_RM_PAT_MONO 0x00000100 /* monochrome pattern */ +#define GP3_RM_PAT_COLOR 0x00000200 /* color pattern */ +#define GP3_RM_PAT_TRANS 0x00000400 /* pattern transparency */ +#define GP3_RM_SRC_TRANS 0x00000800 /* source transparency */ + +/* GP3_VECTOR_MODE REGISTER DESCRIPTIONS */ + +#define GP3_VM_DST_REQ 0x00000008 /* dst data required */ +#define GP3_VM_THROTTLE 0x00000010 /* sync to VBLANK */ + +/* GP3_BLT_MODE REGISTER DEFINITIONS */ + +#define GP3_BM_SRC_FB 0x00000001 /* src = frame buffer */ +#define GP3_BM_SRC_HOST 0x00000002 /* src = host register */ +#define GP3_BM_DST_REQ 0x00000004 /* dst data required */ +#define GP3_BM_SRC_MONO 0x00000040 /* monochrome source data */ +#define GP3_BM_SRC_BP_MONO 0x00000080 /* Byte-packed monochrome */ +#define GP3_BM_NEG_YDIR 0x00000100 /* negative Y direction */ +#define GP3_BM_NEG_XDIR 0x00000200 /* negative X direction */ +#define GP3_BM_THROTTLE 0x00000400 /* sync to VBLANK */ + +/* GP3_BLT_STATUS REGISTER DEFINITIONS */ + +#define GP3_BS_BLT_BUSY 0x00000001 /* GP is not idle */ +#define GP3_BS_BLT_PENDING 0x00000004 /* second BLT is pending */ +#define GP3_BS_HALF_EMPTY 0x00000008 /* src FIFO half empty */ +#define GP3_BS_CB_EMPTY 0x00000010 /* Command buffer empty. */ + +/* GP3_CH3_MODE_STR REGISTER DEFINITIONS */ + +#define GP3_CH3_C3EN 0x80000000 +#define GP3_CH3_REPLACE_SOURCE 0x40000000 +#define GP3_CH3_NEG_XDIR 0x20000000 +#define GP3_CH3_NEG_YDIR 0x10000000 +#define GP3_CH3_SRC_FMT_MASK 0x0f000000 +#define GP3_CH3_SRC_3_3_2 0x00000000 +#define GP3_CH3_SRC_8BPP_INDEXED 0x01000000 +#define GP3_CH3_SRC_8BPP_ALPHA 0x02000000 +#define GP3_CH3_SRC_4_4_4_4 0x04000000 +#define GP3_CH3_SRC_1_5_5_5 0x05000000 +#define GP3_CH3_SRC_0_5_6_5 0x06000000 +#define GP3_CH3_SRC_Y_U_V 0x07000000 +#define GP3_CH3_SRC_8_8_8_8 0x08000000 +#define GP3_CH3_SRC_24BPP_PACKED 0x0B000000 +#define GP3_CH3_SRC_4BPP_INDEXED 0x0D000000 +#define GP3_CH3_SRC_4BPP_ALPHA 0x0E000000 +#define GP3_CH3_SRC_MASK 0x0F000000 +#define GP3_CH3_ROTATE_ENABLE 0x00800000 +#define GP3_CH3_BGR_ORDER 0x00400000 +#define GP3_CH3_COLOR_PAT_ENABLE 0x00200000 +#define GP3_CH3_PRESERVE_LUT 0x00100000 +#define GP3_CH3_PREFETCH_ENABLE 0x00080000 +#define GP3_CH3_HST_SRC_ENABLE 0x00040000 +#define GP3_CH3_STRIDE_MASK 0x0000FFFF + +/* DATA AND LUT LOAD BIT DEFINITIONS */ + +#define GP3_LUT_HDR_WRAP 0x80000000 +#define GP3_LUT_HDR_TYPE 0x40000000 +#define GP3_LUT_HDR_DATA_ENABLE 0x00000003 +#define GP3_DATA_LOAD_HDR_WRAP 0x80000000 +#define GP3_DATA_LOAD_HDR_TYPE 0x60000000 +#define GP3_DATA_LOAD_HDR_ENABLE 0x00000001 + +#define GP3_HOST_SOURCE_TYPE 0x00000000 +#define GP3_CH3_HOST_SOURCE_TYPE 0x20000000 +#define GP3_OLD_PATTERN_COLORS 0x40000000 +#define GP3_LUT_DATA_TYPE 0x60000000 + +#define GP3_BASE_OFFSET_DSTMASK 0xFFC00000 +#define GP3_BASE_OFFSET_SRCMASK 0x003FF000 +#define GP3_BASE_OFFSET_CH3MASK 0x00000FFC + +/*----------------------------------------------------------------*/ +/* VIDEO GENERATOR DEFINITIONS */ +/*----------------------------------------------------------------*/ + +#define DC3_UNLOCK 0x00000000 /* Unlock register */ +#define DC3_GENERAL_CFG 0x00000004 /* Config registers */ +#define DC3_DISPLAY_CFG 0x00000008 +#define DC3_ARB_CFG 0x0000000C + +#define DC3_FB_ST_OFFSET 0x00000010 /* Frame buffer start offset */ +#define DC3_CB_ST_OFFSET 0x00000014 /* Compression start offset */ +#define DC3_CURS_ST_OFFSET 0x00000018 /* Cursor buffer start offset */ +#define DC3_VID_Y_ST_OFFSET 0x00000020 /* Video Y Buffer start offset */ +#define DC3_VID_U_ST_OFFSET 0x00000024 /* Video U Buffer start offset */ +#define DC3_VID_V_ST_OFFSET 0x00000028 /* Video V Buffer start offset */ +#define DC3_DV_TOP 0x0000002C /* DV Ram Limit Register */ +#define DC3_LINE_SIZE 0x00000030 /* Video, CB, and FB line sizes */ +#define DC3_GFX_PITCH 0x00000034 /* FB and DB skip counts */ +#define DC3_VID_YUV_PITCH 0x00000038 /* Y, U and V buffer skip counts */ + +#define DC3_H_ACTIVE_TIMING 0x00000040 /* Horizontal timings */ +#define DC3_H_BLANK_TIMING 0x00000044 +#define DC3_H_SYNC_TIMING 0x00000048 +#define DC3_V_ACTIVE_TIMING 0x00000050 /* Vertical Timings */ +#define DC3_V_BLANK_TIMING 0x00000054 +#define DC3_V_SYNC_TIMING 0x00000058 +#define DC3_FB_ACTIVE 0x0000005C + +#define DC3_CURSOR_X 0x00000060 /* Cursor X position */ +#define DC3_CURSOR_Y 0x00000064 /* Cursor Y Position */ +#define DC3_LINE_CNT_STATUS 0x0000006C + +#define DC3_PAL_ADDRESS 0x00000070 /* Palette Address */ +#define DC3_PAL_DATA 0x00000074 /* Palette Data */ +#define DC3_DFIFO_DIAG 0x00000078 /* Display FIFO diagnostic */ +#define DC3_CFIFO_DIAG 0x0000007C /* Compression FIFO diagnostic */ + +#define DC3_VID_DS_DELTA 0x00000080 /* Vertical Downscaling fraction */ + +#define DC3_PHY_MEM_OFFSET 0x00000084 /* VG Base Address Register */ +#define DC3_DV_CTL 0x00000088 /* Dirty-Valid Control Register */ +#define DC3_DV_ACC 0x0000008C /* Dirty-Valid RAM Access */ + +#define DC3_GFX_SCALE 0x00000090 /* Graphics Scaling */ +#define DC3_IRQ_FILT_CTL 0x00000094 /* VBlank interrupt and filters */ +#define DC3_FILT_COEFF1 0x00000098 +#define DC3_FILT_COEFF2 0x0000009C + +#define DC3_VBI_EVEN_CTL 0x000000A0 /* VBI Data Buffer Controls */ +#define DC3_VBI_ODD_CTL 0x000000A4 +#define DC3_VBI_HOR 0x000000A8 +#define DC3_VBI_LN_ODD 0x000000AC +#define DC3_VBI_LN_EVEN 0x000000B0 +#define DC3_VBI_PITCH 0x000000B4 + +#define DC3_COLOR_KEY 0x000000B8 /* Graphics color key */ +#define DC3_COLOR_MASK 0x000000BC /* Graphics color key mask */ +#define DC3_CLR_KEY_X 0x000000C0 +#define DC3_CLR_KEY_Y 0x000000C4 + +#define DC3_IRQ 0x000000C8 +#define DC3_GENLK_CTL 0x000000D4 + +#define DC3_VID_EVEN_Y_ST_OFFSET 0x000000D8 /* Even field video buffers */ +#define DC3_VID_EVEN_U_ST_OFFSET 0x000000DC +#define DC3_VID_EVEN_V_ST_OFFSET 0x000000E0 + +#define DC3_V_ACTIVE_EVEN 0x000000E4 /* Even field timing registers */ +#define DC3_V_BLANK_EVEN 0x000000E8 +#define DC3_V_SYNC_EVEN 0x000000EC + +/* UNLOCK VALUE */ + +#define DC3_UNLOCK_VALUE 0x00004758 /* used to unlock DC regs */ + +/* VG GEODELINK DEVICE SMI MSR FIELDS */ + +#define DC3_VG_BL_MASK 0x00000001 +#define DC3_MISC_MASK 0x00000002 +#define DC3_ISR0_MASK 0x00000004 +#define DC3_VGA_BL_MASK 0x00000008 +#define DC3_CRTCIO_MSK 0x00000010 +#define DC3_VG_BLANK_SMI 0x00000001 +#define DC3_MISC_SMI 0x00000002 +#define DC3_ISR0_SMI 0x00000004 +#define DC3_VGA_BLANK_SMI 0x00000008 +#define DC3_CRTCIO_SMI 0x00000010 + +/* DC3_GENERAL_CFG BIT FIELDS */ + +#define DC3_GCFG_DBUG 0x80000000 +#define DC3_GCFG_DBSL 0x40000000 +#define DC3_GCFG_CFRW 0x20000000 +#define DC3_GCFG_DIAG 0x10000000 +#define DC3_GCFG_CRC_MODE 0x08000000 +#define DC3_GCFG_SGFR 0x04000000 +#define DC3_GCFG_SGRE 0x02000000 +#define DC3_GCFG_SIGE 0x01000000 +#define DC3_GCFG_SIG_SEL 0x00800000 +#define DC3_GCFG_YUV_420 0x00100000 +#define DC3_GCFG_VDSE 0x00080000 +#define DC3_GCFG_VGAFT 0x00040000 +#define DC3_GCFG_FDTY 0x00020000 +#define DC3_GCFG_STFM 0x00010000 +#define DC3_GCFG_DFHPEL_MASK 0x0000F000 +#define DC3_GCFG_DFHPSL_MASK 0x00000F00 +#define DC3_GCFG_VGAE 0x00000080 +#define DC3_GCFG_DECE 0x00000040 +#define DC3_GCFG_CMPE 0x00000020 +#define DC3_GCFG_FILT_SIG_SEL 0x00000010 +#define DC3_GCFG_VIDE 0x00000008 +#define DC3_GCFG_CLR_CUR 0x00000004 +#define DC3_GCFG_CURE 0x00000002 +#define DC3_GCFG_DFLE 0x00000001 + +/* DC3_DISPLAY_CFG BIT FIELDS */ + +#define DC3_DCFG_VISL 0x08000000 +#define DC3_DCFG_FRLK 0x04000000 +#define DC3_DCFG_PALB 0x02000000 +#define DC3_DCFG_DCEN 0x01000000 +#define DC3_DCFG_VFHPEL_MASK 0x000F0000 +#define DC3_DCFG_VFHPSL_MASK 0x0000F000 +#define DC3_DCFG_16BPP_MODE_MASK 0x00000C00 +#define DC3_DCFG_16BPP 0x00000000 +#define DC3_DCFG_15BPP 0x00000400 +#define DC3_DCFG_12BPP 0x00000800 +#define DC3_DCFG_DISP_MODE_MASK 0x00000300 +#define DC3_DCFG_DISP_MODE_8BPP 0x00000000 +#define DC3_DCFG_DISP_MODE_16BPP 0x00000100 +#define DC3_DCFG_DISP_MODE_24BPP 0x00000200 +#define DC3_DCFG_DISP_MODE_32BPP 0x00000300 +#define DC3_DCFG_TRUP 0x00000040 +#define DC3_DCFG_VDEN 0x00000010 +#define DC3_DCFG_GDEN 0x00000008 +#define DC3_DCFG_TGEN 0x00000001 + +/* DC3_ARB_CFG BIT FIELDS */ + +#define DC3_ACFG_LB_LOAD_WM_EN 0x00100000 +#define DC3_ACFG_LB_LOAD_WM_MASK 0x000F0000 +#define DC3_ACFG_LPEN_END_COUNT_MASK 0x0000FE00 +#define DC3_ACFG_HPEN_SBINV 0x00000100 +#define DC3_ACFG_HPEN_FB_INV_HALFSB 0x00000080 +#define DC3_ACFG_HPEN_FB_INV_SBRD 0x00000040 +#define DC3_ACFG_HPEN_FB_INV 0x00000020 +#define DC3_ACFG_HPEN_1LB_INV 0x00000010 +#define DC3_ACFG_HPEN_2LB_INV 0x00000008 +#define DC3_ACFG_HPEN_3LB_INV 0x00000004 +#define DC3_ACFG_HPEN_LB_FILL 0x00000002 +#define DC3_ACFG_LPEN_VSYNC 0x00000001 + +/* DC3_FB_ST_OFFSET BIT FIELDS */ + +#define DC3_FB_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_CB_ST_OFFSET BIT FIELDS */ + +#define DC3_CB_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_CURS_ST_OFFSET BIT FIELDS */ + +#define DC3_CURS_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_ICON_ST_OFFSET BIT FIELDS */ + +#define DC3_ICON_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_VID_Y_ST_OFFSET BIT FIELDS */ + +#define DC3_VID_Y_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_VID_U_ST_OFFSET BIT FIELDS */ + +#define DC3_VID_U_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_VID_V_ST_OFFSET BIT FIELDS */ + +#define DC3_VID_V_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_DV_TOP BIT FIELDS */ + +#define DC3_DVTOP_ENABLE 0x00000001 +#define DC3_DVTOP_MAX_MASK 0x00FFFC00 +#define DC3_DVTOP_MAX_SHIFT 10 + +/* DC3_LINE_SIZE BIT FIELDS */ + +#define DC3_LINE_SIZE_VLS_MASK 0x3FF00000 +#define DC3_LINE_SIZE_CBLS_MASK 0x0007F000 +#define DC3_LINE_SIZE_FBLS_MASK 0x000003FF +#define DC3_LINE_SIZE_CB_SHIFT 12 +#define DC3_LINE_SIZE_VB_SHIFT 20 + +/* DC3_GFX_PITCH BIT FIELDS */ + +#define DC3_GFX_PITCH_CBP_MASK 0xFFFF0000 +#define DC3_GFX_PITCH_FBP_MASK 0x0000FFFF + +/* DC3_VID_YUV_PITCH BIT FIELDS */ + +#define DC3_YUV_PITCH_UVP_MASK 0xFFFF0000 +#define DC3_YUV_PITCH_YBP_MASK 0x0000FFFF + +/* DC3_H_ACTIVE_TIMING BIT FIELDS */ + +#define DC3_HAT_HT_MASK 0x0FF80000 +#define DC3_HAT_HA_MASK 0x00000FF8 + +/* DC3_H_BLANK_TIMING BIT FIELDS */ + +#define DC3_HBT_HBE_MASK 0x0FF80000 +#define DC3_HBT_HBS_MASK 0x00000FF8 + +/* DC3_H_SYNC_TIMING BIT FIELDS */ + +#define DC3_HST_HSE_MASK 0x0FF80000 +#define DC3_HST_HSS_MASK 0x00000FF8 + +/* DC3_V_ACTIVE_TIMING BIT FIELDS */ + +#define DC3_VAT_VT_MASK 0x07FF0000 +#define DC3_VAT_VA_MASK 0x000007FF + +/* DC3_V_BLANK_TIMING BIT FIELDS */ + +#define DC3_VBT_VBE_MASK 0x07FF0000 +#define DC3_VBT_VBS_MASK 0x000007FF + +/* DC3_V_SYNC_TIMING BIT FIELDS */ + +#define DC3_VST_VSE_MASK 0x07FF0000 +#define DC3_VST_VSS_MASK 0x000007FF + +/* DC3_LINE_CNT_STATUS BIT FIELDS */ + +#define DC3_LNCNT_DNA 0x80000000 +#define DC3_LNCNT_VNA 0x40000000 +#define DC3_LNCNT_VSA 0x20000000 +#define DC3_LNCNT_VINT 0x10000000 +#define DC3_LNCNT_FLIP 0x08000000 +#define DC3_LNCNT_V_LINE_CNT 0x07FF0000 +#define DC3_LNCNT_VFLIP 0x00008000 +#define DC3_LNCNT_SIGC 0x00004000 +#define DC3_LNCNT_EVEN_FIELD 0x00002000 +#define DC3_LNCNT_SS_LINE_CMP 0x000007FF + +/* DC3_VID_DS_DELTA BIT FIELDS */ + +#define DC3_DS_DELTA_MASK 0xFFFC0000 +#define DC3_601_VSYNC_SHIFT_MASK 0x00000FFF +#define DC3_601_VSYNC_SHIFT_ENABLE 0x00008000 + +/* DC3_DV_CTL BIT DEFINITIONS */ + +#define DC3_DV_LINE_SIZE_MASK 0x00000C00 +#define DC3_DV_LINE_SIZE_1024 0x00000000 +#define DC3_DV_LINE_SIZE_2048 0x00000400 +#define DC3_DV_LINE_SIZE_4096 0x00000800 +#define DC3_DV_LINE_SIZE_8192 0x00000C00 + +/* DC3_IRQ_FILT_CTL DEFINITIONS */ + +#define DC3_IRQFILT_LB_MASK 0x80000200 +#define DC3_IRQFILT_LB_COEFF 0x00000000 +#define DC3_IRQFILT_SCALER_FILTER 0x00000200 +#define DC3_IRQFILT_SYNCHRONIZER 0x80000000 +#define DC3_IRQFILT_FLICKER_FILTER 0x80000200 +#define DC3_IRQFILT_LB_SEL_MASK 0x60000000 +#define DC3_IRQFILT_INTL_ADDR 0x10000000 +#define DC3_IRQFILT_LINE_MASK 0x07FF0000 +#define DC3_IRQFILT_ALPHA_FILT_EN 0x00004000 +#define DC3_IRQFILT_GFX_FILT_EN 0x00001000 +#define DC3_IRQFILT_INTL_EN 0x00000800 +#define DC3_IRQFILT_H_FILT_SEL 0x00000400 +#define DC3_IRQFILT_LB_ADDR 0x00000100 + +/* DC3_VBI_EVEN_CTL DEFINITIONS */ + +#define DC3_VBI_EVEN_ENABLE_CRC (1L << 31) +#define DC3_VBI_EVEN_CTL_ENABLE_16 (1L << 30) +#define DC3_VBI_EVEN_CTL_UPSCALE (1L << 29) +#define DC3_VBI_ENABLE (1L << 28) +#define DC3_VBI_EVEN_CTL_OFFSET_MASK 0x0FFFFFFF + +/* DC3_VBI_ODD_CTL DEFINITIONS */ + +#define DC3_VBI_ODD_CTL_OFFSET_MASK 0x0FFFFFFF + +/* DC3_VBI_HOR BIT DEFINITIONS */ + +#define DC3_VBI_HOR_END_SHIFT 16 +#define DC3_VBI_HOR_END_MASK 0x0FFF0000 +#define DC3_VBI_HOR_START_MASK 0x00000FFF + +/* DC3_VBI_LN_ODD BIT DEFINITIONS */ + +#define DC3_VBI_ODD_ENABLE_SHIFT 2 +#define DC3_VBI_ODD_ENABLE_MASK 0x01FFFFFC +#define DC3_VBI_ODD_LINE_SHIFT 25 +#define DC3_VBI_ODD_LINE_MASK 0xFE000000 + +/* DC3_VBI_LN_EVEN BIT DEFINITIONS */ + +#define DC3_VBI_EVEN_ENABLE_SHIFT 2 +#define DC3_VBI_EVEN_ENABLE_MASK 0x01FFFFFC +#define DC3_VBI_EVEN_LINE_SHIFT 25 +#define DC3_VBI_EVEN_LINE_MASK 0xFE000000 + +/* DC3_COLOR_KEY DEFINITIONS */ + +#define DC3_CLR_KEY_DATA_MASK 0x00FFFFFF +#define DC3_CLR_KEY_ENABLE 0x01000000 + +/* DC3_IRQ DEFINITIONS */ + +#define DC3_IRQ_MASK 0x00000001 +#define DC3_VSYNC_IRQ_MASK 0x00000002 +#define DC3_IRQ_STATUS 0x00010000 +#define DC3_VSYNC_IRQ_STATUS 0x00020000 + +/* DC3_GENLK_CTL DEFINITIONS */ + +#define DC3_GC_FLICKER_FILTER_NONE 0x00000000 +#define DC3_GC_FLICKER_FILTER_1_16 0x10000000 +#define DC3_GC_FLICKER_FILTER_1_8 0x20000000 +#define DC3_GC_FLICKER_FILTER_1_4 0x40000000 +#define DC3_GC_FLICKER_FILTER_5_16 0x50000000 +#define DC3_GC_FLICKER_FILTER_MASK 0xF0000000 +#define DC3_GC_ALPHA_FLICK_ENABLE 0x02000000 +#define DC3_GC_FLICKER_FILTER_ENABLE 0x01000000 +#define DC3_GC_VIP_VID_OK 0x00800000 +#define DC3_GC_GENLK_ACTIVE 0x00400000 +#define DC3_GC_SKEW_WAIT 0x00200000 +#define DC3_GC_VSYNC_WAIT 0x00100000 +#define DC3_GC_GENLOCK_TO_ENABLE 0x00080000 +#define DC3_GC_GENLOCK_ENABLE 0x00040000 +#define DC3_GC_GENLOCK_SKEW_MASK 0x0003FFFF + +/* VGA DEFINITIONS */ + +#define DC3_SEQUENCER_INDEX 0x03C4 +#define DC3_SEQUENCER_DATA 0x03C5 +#define DC3_SEQUENCER_RESET 0x00 +#define DC3_SEQUENCER_CLK_MODE 0x01 + +#define DC3_RESET_VGA_DISP_ENABLE 0x03 +#define DC3_CLK_MODE_SCREEN_OFF 0x20 + +/* DOT CLOCK FREQUENCY STRUCTURE */ +/* Note that m, n and p refer to the register m, n and p */ +/* and not the m, n and p from the PLL equation. The PLL */ +/* equation adds 1 to each value. */ + +typedef struct tagPLLFrequency +{ + unsigned long pll_value; + unsigned long frequency; + +} PLL_FREQUENCY; + +/* VG MSRS */ + +#define DC3_SPARE_MSR 0x2011 +#define DC3_RAM_CTL 0x2012 + +/* DC3_SPARE_MSR DEFINITIONS */ + +#define DC3_SPARE_DISABLE_CFIFO_HGO 0x00000800 +#define DC3_SPARE_VFIFO_ARB_SELECT 0x00000400 +#define DC3_SPARE_WM_LPEN_OVRD 0x00000200 +#define DC3_SPARE_LOAD_WM_LPEN_MASK 0x00000100 +#define DC3_SPARE_DISABLE_INIT_VID_PRI 0x00000080 +#define DC3_SPARE_DISABLE_VFIFO_WM 0x00000040 +#define DC3_SPARE_DISABLE_CWD_CHECK 0x00000020 +#define DC3_SPARE_PIX8_PAN_FIX 0x00000010 +#define DC3_SPARE_FIRST_REQ_MASK 0x00000002 + +/* VG DIAG DEFINITIONS */ + +#define DC3_MBD_DIAG_EN0 0x00008000 +#define DC3_MBD_DIAG_EN1 0x80000000 +#define DC3_DIAG_DOT_CRTC_DP 0x00000082 +#define DC3_DIAG_DOT_CRTC_DP_HIGH 0x00820000 +#define DC3_DIAG_EVEN_FIELD 0x00002000 + +/*----------------------------------------------------------------*/ +/* DISPLAY FILTER DEFINITIONS */ +/*----------------------------------------------------------------*/ + +#define DF_VIDEO_CONFIG 0x00000000 +#define DF_DISPLAY_CONFIG 0x00000008 +#define DF_VIDEO_X_POS 0x00000010 +#define DF_VIDEO_Y_POS 0x00000018 +#define DF_VIDEO_SCALER 0x00000020 +#define DF_VIDEO_COLOR_KEY 0x00000028 +#define DF_VIDEO_COLOR_MASK 0x00000030 +#define DF_PALETTE_ADDRESS 0x00000038 +#define DF_PALETTE_DATA 0x00000040 +#define DF_SATURATION_LIMIT 0x00000048 +#define DF_VID_MISC 0x00000050 +#define DF_VIDEO_YSCALE 0x00000060 +#define DF_VIDEO_XSCALE 0x00000068 +#define DF_VID_CRC 0x00000088 +#define DF_VID_CRC32 0x00000090 +#define DF_VID_ALPHA_CONTROL 0x00000098 +#define DF_CURSOR_COLOR_KEY 0x000000A0 +#define DF_CURSOR_COLOR_MASK 0x000000A8 +#define DF_CURSOR_COLOR_1 0x000000B0 +#define DF_CURSOR_COLOR_2 0x000000B8 +#define DF_ALPHA_XPOS_1 0x000000C0 +#define DF_ALPHA_YPOS_1 0x000000C8 +#define DF_ALPHA_COLOR_1 0x000000D0 +#define DF_ALPHA_CONTROL_1 0x000000D8 +#define DF_ALPHA_XPOS_2 0x000000E0 +#define DF_ALPHA_YPOS_2 0x000000E8 +#define DF_ALPHA_COLOR_2 0x000000F0 +#define DF_ALPHA_CONTROL_2 0x000000F8 +#define DF_ALPHA_XPOS_3 0x00000100 +#define DF_ALPHA_YPOS_3 0x00000108 +#define DF_ALPHA_COLOR_3 0x00000110 +#define DF_ALPHA_CONTROL_3 0x00000118 +#define DF_VIDEO_REQUEST 0x00000120 +#define DF_ALPHA_WATCH 0x00000128 +#define DF_VIDEO_TEST_MODE 0x00000130 +#define DF_VID_YPOS_EVEN 0x00000138 +#define DF_VID_ALPHA_Y_EVEN_1 0x00000140 +#define DF_VID_ALPHA_Y_EVEN_2 0x00000148 +#define DF_VID_ALPHA_Y_EVEN_3 0x00000150 +#define DF_VIDEO_PANEL_TIM1 0x00000400 +#define DF_VIDEO_PANEL_TIM2 0x00000408 +#define DF_POWER_MANAGEMENT 0x00000410 +#define DF_DITHER_CONTROL 0x00000418 +#define DF_DITHER_ACCESS 0x00000448 +#define DF_DITHER_DATA 0x00000450 +#define DF_PANEL_CRC 0x00000458 +#define DF_PANEL_CRC32 0x00000468 +#define DF_COEFFICIENT_BASE 0x00001000 + +/* DF_VIDEO_CONFIG BIT DEFINITIONS */ + +#define DF_VCFG_VID_EN 0x00000001 +#define DF_VCFG_VID_INP_FORMAT 0x0000000C +#define DF_VCFG_SC_BYP 0x00000020 +#define DF_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 +#define DF_VCFG_INIT_READ_MASK 0x01FF0000 +#define DF_VCFG_LINE_SIZE_BIT8 0x08000000 +#define DF_VCFG_LINE_SIZE_BIT9 0x04000000 +#define DF_VCFG_4_2_0_MODE 0x10000000 +#define DF_VCFG_UYVY_FORMAT 0x00000000 +#define DF_VCFG_Y2YU_FORMAT 0x00000004 +#define DF_VCFG_YUYV_FORMAT 0x00000008 +#define DF_VCFG_YVYU_FORMAT 0x0000000C + +/* DF_DISPLAY_CONFIG BIT DEFINITIONS */ + +#define DF_DCFG_DIS_EN 0x00000001 +#define DF_DCFG_HSYNC_EN 0x00000002 +#define DF_DCFG_VSYNC_EN 0x00000004 +#define DF_DCFG_DAC_BL_EN 0x00000008 +#define DF_DCFG_CRT_HSYNC_POL 0x00000100 +#define DF_DCFG_CRT_VSYNC_POL 0x00000200 +#define DF_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 +#define DF_DCFG_CRT_SYNC_SKW_INIT 0x00010000 +#define DF_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 +#define DF_DCFG_PWR_SEQ_DLY_INIT 0x00080000 +#define DF_DCFG_VG_CK 0x00100000 +#define DF_DCFG_GV_PAL_BYP 0x00200000 +#define DF_DAC_VREF 0x04000000 + +/* DF_VID_MISC BIT DEFINITIONS */ + +#define DF_GAMMA_BYPASS_BOTH 0x00000001 +#define DF_DAC_POWER_DOWN 0x00000400 +#define DF_ANALOG_POWER_DOWN 0x00000800 +#define DF_USER_IMPLICIT_SCALING 0x00001000 + +/* DF_VID_ALPHA_CONTROL DEFINITIONS */ + +#define DF_HD_VIDEO 0x00000040 +#define DF_YUV_CSC_EN 0x00000080 +#define DF_NO_CK_OUTSIDE_ALPHA 0x00000100 +#define DF_HD_GRAPHICS 0x00000200 +#define DF_CSC_VIDEO_YUV_TO_RGB 0x00000400 +#define DF_CSC_GRAPHICS_RGB_TO_YUV 0x00000800 +#define DF_CSC_VOP_RGB_TO_YUV 0x00001000 +#define DF_VIDEO_INPUT_IS_RGB 0x00002000 +#define DF_VID_ALPHA_EN 0x00004000 +#define DF_ALPHA_DRGB 0x00008000 + +/* VIDEO CURSOR COLOR KEY DEFINITIONS */ + +#define DF_CURSOR_COLOR_KEY_ENABLE 0x20000000 + +/* ALPHA COLOR BIT DEFINITION */ + +#define DF_ALPHA_COLOR_ENABLE 0x01000000 + +/* ALPHA CONTROL BIT DEFINITIONS */ + +#define DF_ACTRL_WIN_ENABLE 0x00010000 +#define DF_ACTRL_LOAD_ALPHA 0x00020000 +#define DF_ACTRL_PERPIXEL_EN 0x00040000 + +/* DF_VIDEO_SCALER DEFINITIONS */ + +#define DF_SCALE_128_PHASES 0x00002000 +#define DF_SCALE_DOUBLE_H_DOWNSCALE 0x00004000 + +/* DEFAULT PANEL TIMINGS DEFINITIONS */ + +#define DF_DEFAULT_TFT_PMTIM1 0x00000000 +#define DF_DEFAULT_XVGA_PMTIM1 0x00000000 +#define DF_DEFAULT_TFT_PMTIM2 0x08C00000 +#define DF_DEFAULT_XVGA_PMTIM2 0x08C10000 +#define DF_DEFAULT_TFT_PAD_SEL_LOW 0xDFFFFFFF +#define DF_DEFAULT_TFT_PAD_SEL_HIGH 0x0000003F +#define DF_DEFAULT_XVGA_PAD_SEL_LOW 0x00000000 +#define DF_DEFAULT_XVGA_PAD_SEL_HIGH 0x00000000 +#define DF_DEFAULT_DITHCTL 0x00000070 +#define DF_DEFAULT_TV_PAD_SEL_HIGH 0x000000BF +#define DF_DEFAULT_TV_PAD_SEL_LOW 0xDFFFFFFF +#define DF_INVERT_VOP_CLOCK 0x00000080 + +/* DF_VIDEO_PANEL_TIM2 DEFINITIONS */ + +#define DF_PMTIM2_TFT_PASSHTHROUGH 0x40000000 + +/* DF_POWER_MANAGEMENT DEFINITIONS */ + +#define DF_PM_PANEL_ON 0x01000000 +#define DF_PM_INVERT_SHFCLK 0x00002000 + +/* DISPLAY FILTER MSRS */ + +#define DF_MBD_MSR_DIAG_DF 0x2010 +#define DF_MSR_PAD_SEL 0x2011 +#define DF_DIAG_32BIT_CRC 0x80000000 + +#define DF_OUTPUT_CRT 0x00000000 +#define DF_OUTPUT_PANEL 0x00000008 +#define DF_OUTPUT_VOP 0x00000030 +#define DF_OUTPUT_DRGB 0x00000038 +#define DF_SIMULTANEOUS_CRT_FP 0x00008000 +#define DF_CONFIG_OUTPUT_MASK 0x00000038 + +/*----------------------------------------------------------------*/ +/* MSR DEFINITIONS */ +/*----------------------------------------------------------------*/ + +/*----------------------------*/ +/* STATIC GEODELINK ADRESSES */ +/*----------------------------*/ + +#define MSR_ADDRESS_GLIU0 0x10000000 +#define MSR_ADDRESS_GLIU1 0x40000000 +#define MSR_ADDRESS_GLIU2 0x51010000 +#define MSR_ADDRESS_5535MPCI 0x51000000 +#define MSR_ADDRESS_VAIL 0x00000000 + +/*----------------------------*/ +/* UNIVERSAL DEVICE MSRS */ +/*----------------------------*/ + +#define MSR_GEODELINK_CAP 0x2000 +#define MSR_GEODELINK_CONFIG 0x2001 +#define MSR_GEODELINK_SMI 0x2002 +#define MSR_GEODELINK_ERROR 0x2003 +#define MSR_GEODELINK_PM 0x2004 +#define MSR_GEODELINK_DIAG 0x2005 + +/*----------------------------*/ +/* DEVICE CLASS CODES */ +/*----------------------------*/ + +#define MSR_CLASS_CODE_GLIU 0x01 +#define MSR_CLASS_CODE_GLCP 0x02 +#define MSR_CLASS_CODE_MPCI 0x05 +#define MSR_CLASS_CODE_MC 0x20 +#define MSR_CLASS_CODE_GP 0x3D +#define MSR_CLASS_CODE_VG 0x3E +#define MSR_CLASS_CODE_DF 0x3F +#define MSR_CLASS_CODE_FG 0xF0 +#define MSR_CLASS_CODE_VAIL 0x86 +#define MSR_CLASS_CODE_USB 0x42 +#define MSR_CLASS_CODE_USB2 0x43 +#define MSR_CLASS_CODE_ATAC 0x47 +#define MSR_CLASS_CODE_MDD 0xDF +#define MSR_CLASS_CODE_ACC 0x33 +#define MSR_CLASS_CODE_AES 0x30 +#define MSR_CLASS_CODE_VIP 0x3C +#define MSR_CLASS_CODE_REFLECTIVE 0xFFF +#define MSR_CLASS_CODE_UNPOPULATED 0x7FF + +/*----------------------------*/ +/* GLIU MSR DEFINITIONS */ +/*----------------------------*/ + +#define MSR_GLIU_CAP 0x0086 +#define MSR_GLIU_WHOAMI 0x008B + +#define NUM_PORTS_MASK 0x00380000 +#define NUM_PORTS_SHIFT 19 +#define WHOAMI_MASK 0x07 + +/*----------------------------*/ +/* GLCP MSR DEFINITIONS */ +/*----------------------------*/ + +#define GLCP_CLKOFF 0x0010 +#define GLCP_CLKACTIVE 0x0011 +#define GLCP_CLKDISABLE 0x0012 +#define GLCP_CLK4ACK 0x0013 +#define GLCP_SYS_RSTPLL 0x0014 +#define GLCP_DOTPLL 0x0015 +#define GLCP_DBGCLKCTL 0x0016 +#define GLCP_REVID 0x0017 +#define GLCP_RAW_DIAG 0x0028 +#define GLCP_SETM0CTL 0x0040 +#define GLCP_SETN0CTL 0x0048 +#define GLCP_CMPVAL0 0x0050 +#define GLCP_CMPMASK0 0x0051 +#define GLCP_REGA 0x0058 +#define GLCP_REGB 0x0059 +#define GLCP_REGAMASK 0x005A +#define GLCP_REGAVAL 0x005B +#define GLCP_REGBMASK 0x005C +#define GLCP_REGBVAL 0x005D +#define GLCP_FIFOCTL 0x005E +#define GLCP_DIAGCTL 0x005F +#define GLCP_H0CTL 0x0060 +#define GLCP_XSTATE 0x0066 +#define GLCP_YSTATE 0x0067 +#define GLCP_ACTION0 0x0068 + +/* GLCP_DOTPLL DEFINITIONS */ + +#define GLCP_DOTPLL_RESET 0x00000001 +#define GLCP_DOTPLL_BYPASS 0x00008000 +#define GLCP_DOTPLL_HALFPIX 0x01000000 +#define GLCP_DOTPLL_LOCK 0x02000000 +#define GLCP_DOTPLL_VIPCLK 0x00008000 +#define GLCP_DOTPLL_DIV4 0x00010000 + +/* GLCP DIAG DEFINITIONS */ + +#define GLCP_MBD_DIAG_SEL0 0x00000007 +#define GLCP_MBD_DIAG_EN0 0x00008000 +#define GLCP_MBD_DIAG_SEL1 0x00070000 +#define GLCP_MBD_DIAG_EN1 0x80000000 + +/*--------------------------------*/ +/* DISPLAY FILTER MSR DEFINITIONS */ +/*--------------------------------*/ + +/* DISPLAY FILTER MBD_MSR_DIAG DEFINITIONS */ + +#define DF_MBD_DIAG_SEL0 0x00007FFF +#define DF_MBD_DIAG_EN0 0x00008000 +#define DF_MBD_DIAG_SEL1 0x7FFF0000 +#define DF_MBD_DIAG_EN1 0x80000000 + +/* DISPLAY FILTER MBD_MSR_CONFIG DEFINITIONS */ + +#define DF_CONFIG_FMT_MASK 0x00000038 +#define DF_CONFIG_FMT_CRT 0x00000000 +#define DF_CONFIG_FMT_FP 0x00000008 + +/*----------------------------------------------------------------*/ +/* PCI DEFINITIONS */ +/*----------------------------------------------------------------*/ + +#define PCI_VENDOR_DEVICE_GEODEGX 0x0028100B +#define PCI_VENDOR_DEVICE_GEODEGX_VIDEO 0x0030100B +#define PCI_VENDOR_DEVICE_GEODELX 0x20801022 +#define PCI_VENDOR_DEVICE_GEODELX_VIDEO 0x20811022 +#define PCI_VENDOR_5535 0x002B100B +#define PCI_VENDOR_5536 0x20901022 + +/*----------------------------------------------------------------*/ +/* VIP DEFINITIONS */ +/*----------------------------------------------------------------*/ + +#define VIP_CONTROL1 0x00000000 +#define VIP_CONTROL2 0x00000004 +#define VIP_STATUS 0x00000008 +#define VIP_INTERRUPT 0x0000000C +#define VIP_CURRENT_TARGET 0x00000010 +#define VIP_MAX_ADDRESS 0x00000014 +#define VIP_TASKA_VID_EVEN_BASE 0x00000018 +#define VIP_TASKA_VID_ODD_BASE 0x0000001C +#define VIP_TASKA_VBI_EVEN_BASE 0x00000020 +#define VIP_TASKA_VBI_ODD_BASE 0x00000024 +#define VIP_TASKA_VID_PITCH 0x00000028 +#define VIP_CONTROL3 0x0000002C +#define VIP_TASKA_V_OFFSET 0x00000030 +#define VIP_TASKA_U_OFFSET 0x00000034 +#define VIP_TASKB_VID_EVEN_BASE 0x00000038 +#define VIP_601_HORZ_END 0x00000038 +#define VIP_TASKB_VID_ODD_BASE 0x0000003C +#define VIP_601_HORZ_START 0x0000003C +#define VIP_TASKB_VBI_EVEN_BASE 0x00000040 +#define VIP_601_VBI_END 0x00000040 +#define VIP_TASKB_VBI_ODD_BASE 0x00000044 +#define VIP_601_VBI_START 0x00000044 +#define VIP_TASKB_VID_PITCH 0x00000048 +#define VIP_601_EVEN_START_STOP 0x00000048 +#define VIP_TASKB_V_OFFSET 0x00000050 +#define VIP_ODD_FIELD_DETECT 0x00000050 +#define VIP_TASKB_U_OFFSET 0x00000054 +#define VIP_ANC_MSG1_BASE 0x00000058 +#define VIP_ANC_MSG2_BASE 0x0000005C +#define VIP_ANC_MSG_SIZE 0x00000060 +#define VIP_PAGE_OFFSET 0x00000068 +#define VIP_VERTICAL_START_STOP 0x0000006C +#define VIP_601_ODD_START_STOP 0x0000006C +#define VIP_FIFO_ADDRESS 0x00000070 +#define VIP_FIFO_DATA 0x00000074 +#define VIP_VSYNC_ERR_COUNT 0x00000078 +#define VIP_TASKA_U_EVEN_OFFSET 0x0000007C +#define VIP_TASKA_V_EVEN_OFFSET 0x00000080 + +/* INDIVIDUAL REGISTER BIT DEFINITIONS */ +/* Multibit register subsets are expressed as a mask and shift. */ +/* Single bit values are represented as a mask. */ + +/* VIP_CONTROL1 REGISTER DEFINITIONS */ + +#define VIP_CONTROL1_DEFAULT_ANC_FF 2 +#define VIP_CONTROL1_ANC_FF_MASK 0xE0000000 +#define VIP_CONTROL1_ANC_FF_SHIFT 29 + +#define VIP_CONTROL1_DEFAULT_VID_FF 2 +#define VIP_CONTROL1_VID_FF_MASK 0x1F000000 +#define VIP_CONTROL1_VID_FF_SHIFT 24 + +#define VIP_CONTROL1_VDE_FF_MASK 0x00F00000 +#define VIP_CONTROL1_VDE_FF_SHIFT 20 + +#define VIP_CONTROL1_NON_INTERLACED (1L << 19) +#define VIP_CONTROL1_MSG_STRM_CTRL (1L << 18) +#define VIP_CONTROL1_DISABLE_ZERO_DETECT (1L << 17) +#define VIP_CONTROL1_DISABLE_DECIMATION (1L << 16) + +#define VIP_CONTROL1_CAPTURE_ENABLE_MASK 0x0000FF00 +#define VIP_CONTROL1_CAPTURE_ENABLE_SHIFT 8 + +#define VIP_CONTROL1_RUNMODE_MASK 0x000000E0 +#define VIP_CONTROL1_RUNMODE_SHIFT 5 + +#define VIP_CONTROL1_PLANAR (1L << 4) + +#define VIP_CONTROL1_MODE_MASK 0x0000000E +#define VIP_CONTROL1_MODE_SHIFT 1 + +#define VIP_CONTROL1_RESET 0x00000001 + +/* VIP_CONTROL2 REGISTER DEFINITIONS */ + +#define VIP_CONTROL2_INVERT_POLARITY (1L << 31) +#define VIP_CONTROL2_ADD_ERROR_ENABLE (1L << 30) +#define VIP_CONTROL2_REPEAT_ENABLE (1L << 29) +#define VIP_CONTROL2_SWC_ENABLE (1L << 28) +#define VIP_CONTROL2_ANC10 (1L << 27) +#define VIP_CONTROL2_ANCPEN (1L << 26) +#define VIP_CONTROL2_LOOPBACK_ENABLE (1L << 25) +#define VIP_CONTROL2_FIFO_ACCESS (1L << 24) +#define VIP_CONTROL2_VERTERROR_ENABLE (1L << 15) + +#define VIP_CONTROL2_PAGECNT_MASK 0x00E00000 +#define VIP_CONTROL2_PAGECNT_SHIFT 21 + +#define VIP_CONTROL2_DEFAULT_ANCTH 5 +#define VIP_CONTROL2_ANCTH_MASK 0x001F0000 +#define VIP_CONTROL2_ANCTH_SHIFT 16 + +#define VIP_CONTROL2_DEFAULT_VIDTH_420 19 +#define VIP_CONTROL2_DEFAULT_VIDTH_422 19 +#define VIP_CONTROL2_VIDTH_MASK 0x00007F00 +#define VIP_CONTROL2_VIDTH_SHIFT 8 + +#define VIP_CONTROL2_SYNC2PIN_MASK 0x000000E0 +#define VIP_CONTROL2_SYNC2PIN_SHIFT 5 + +#define VIP_CONTROL2_FIELD2VG_MASK 0x00000018 +#define VIP_CONTROL2_FIELD2VG_SHIFT 3 + +#define VIP_CONTROL2_SYNC2VG_MASK 0x00000007 +#define VIP_CONTROL2_SYNC2VG_SHIFT 0 + +/* VIP_CONTROL3 REGISTER DEFINITIONS */ + +#define VIP_CONTROL3_PLANAR_DEINT 0x00000400 +#define VIP_CONTROL3_BASE_UPDATE 0x00000200 +#define VIP_CONTROL3_DISABLE_OVERFLOW 0x00000100 +#define VIP_CONTROL3_DECIMATE_EVEN 0x00000080 +#define VIP_CONTROL3_TASK_POLARITY 0x00000040 +#define VIP_CONTROL3_VSYNC_POLARITY 0x00000020 +#define VIP_CONTROL3_HSYNC_POLARITY 0x00000010 +#define VIP_CONTROL3_FIFO_RESET 0x00000001 + +/* VIP_STATUS REGISTER DEFINITIONS */ + +#define VIP_STATUS_ANC_COUNT_MASK 0xFF000000 +#define VIP_STATUS_ANC_COUNT_SHIFT 24 + +#define VIP_STATUS_FIFO_ERROR 0x00700000 +#define VIP_STATUS_ERROR_SHIFT 20 +#define VIP_STATUS_DEC_COUNT (1L << 18) +#define VIP_STATUS_SYNCOUT (1L << 17) +#define VIP_STATUS_BASEREG_NOTUPDT (1L << 16) +#define VIP_STATUS_MSGBUFF_ERR (1L << 14) +#define VIP_STATUS_MSGBUFF2_FULL (1L << 13) +#define VIP_STATUS_MSGBUFF1_FULL (1L << 12) +#define VIP_STATUS_WRITES_COMPLETE (1L << 9) +#define VIP_STATUS_FIFO_EMPTY (1L << 8) +#define VIP_STATUS_FIELD (1L << 4) +#define VIP_STATUS_VBLANK (1L << 3) + +#define VIP_STATUS_RUN_MASK 0x00000007 +#define VIP_STATUS_RUN_SHIFT 0 + +/* VIP_CURRENT_TARGET REGISTER DEFINITIONS */ + +#define VIP_CTARGET_TLINE_MASK 0xFFFF0000 +#define VIP_CTARGET_TLINE_SHIFT 16 + +#define VIP_CTARGET_CLINE_MASK 0x0000FFFF +#define VIP_CTARGET_CLINE_SHIFT 0 + +/* VIP_MAX_ADDRESS REGISTER DEFINITIONS */ + +#define VIP_MAXADDR_MASK 0xFFFFFFFF +#define VIP_MAXADDR_SHIFT 0 + +/* VIP BUFFER PITCH DEFINITIONS */ + +#define VIP_TASK_PITCH_MASK 0x0000FFFF +#define VIP_TASK_PITCH_SHIFT 0 + +/* VERTICAL START/STOP */ + +#define VIP_VSTART_VERTEND_MASK 0x0FFF0000 +#define VIP_VSTART_VERTEND_SHIFT 16 + +#define VIP_VSTART_VERTSTART_MASK 0x00000FFF +#define VIP_VSTART_VERTSTART_SHIFT 0 + +/* VIP FIFO ADDRESS DEFINITIONS */ + +#define VIP_FIFO_ADDRESS_MASK 0x000000FF +#define VIP_FIFO_ADDRESS_SHIFT 0 + +/* VIP VSYNC ERROR DEFINITIONS */ + +#define VIP_VSYNC_ERR_WINDOW_MASK 0xFF000000 +#define VIP_VSYNC_ERR_WINDOW_SHIFT 24 + +#define VIP_VSYNC_ERR_COUNT_MASK 0x00FFFFFF +#define VIP_VSYNC_ERR_COUNT_SHIFT 0 + +/*---------------------*/ +/* VIP MSR DEFINITIONS */ +/*---------------------*/ + +/* CAPABILITIES */ + +#define VIP_MSR_CAP_NSMI_MASK 0xF8000000 +#define VIP_MSR_CAP_NSMI_SHIFT 27 +#define VIP_MSR_CAP_NCLK_MASK 0x07000000 +#define VIP_MSR_CAP_NCLK_SHIFT 24 +#define VIP_MSR_CAP_DEVID_MASK 0x00FFFF00 +#define VIP_MSR_CAP_DEVID_SHIFT 8 +#define VIP_MSR_CAP_REVID_MASK 0x000000FF +#define VIP_MSR_CAP_REVID_SHIFT 0 + +/* MASTER CONFIG */ + +#define VIP_MSR_MCR_SECOND_PRIORITY_MASK 0x00000700 +#define VIP_MSR_MCR_SECOND_PRIORITY_SHIFT 8 +#define VIP_MSR_MCR_PRIMARY_PRIORITY_MASK 0x00000070 +#define VIP_MSR_MCR_PRIMARY_PRIORITY_SHIFT 4 +#define VIP_MSR_MCR_PID_MASK 0x00000007 +#define VIP_MSR_MCR_PID_SHIFT 0 + +/* VIP SMI */ + +#define VIP_MSR_SMI_FIFO_OVERFLOW (1L << 29) +#define VIP_MSR_SMI_FIFO_THRESHOLD (1L << 28) +#define VIP_MSR_SMI_LONGLINE (1L << 27) +#define VIP_MSR_SMI_VERTICAL_TIMING (1L << 26) +#define VIP_MSR_SMI_ACTIVE_PIXELS (1L << 25) +#define VIP_MSR_SMI_CLOCK_INPUT (1L << 24) +#define VIP_MSR_SMI_ANC_CHECKSUM_PARITY (1L << 23) +#define VIP_MSR_SMI_MSG_BUFFER_FULL (1L << 22) +#define VIP_MSR_SMI_END_VBLANK (1L << 21) +#define VIP_MSR_SMI_START_VBLANK (1L << 20) +#define VIP_MSR_SMI_START_EVEN (1L << 19) +#define VIP_MSR_SMI_START_ODD (1L << 18) +#define VIP_MSR_SMI_LINE_MATCH_TARGET (1L << 17) +#define VIP_MSR_SMI_GLINK (1L << 16) + +/* VIP ERROR */ + +#define VIP_MSR_ERROR_ADDRESS_MASK (1L << 17) +#define VIP_MSR_ERROR_ADDRESS_SHIFT 17 +#define VIP_MSR_ERROR_ADDRESS_ENABLE (1L << 1) +#define VIP_MSR_ERROR_ADDRESS_EN_SHIFT 1 +#define VIP_MSR_ERROR_TYPE_MASK (1L << 16) +#define VIP_MSR_ERROR_TYPE_SHIFT 16 +#define VIP_MSR_ERROR_TYPE_ENABLE 1 +#define VIP_MSR_ERROR_TYPE_EN_SHIFT 0 + +/* VIP POWER */ + +#define VIP_MSR_POWER_GLINK (1L << 0) +#define VIP_MSR_POWER_CLOCK (1L << 2) + +/* VIP DIAG */ + +#define VIP_MSR_DIAG_BIST_WMASK 0x00000003 +#define VIP_MSR_DIAG_BIST_RMASK 0x00000007 +#define VIP_MSR_DIAG_BIST_SHIFT 0 + +#define VIP_MSR_DIAG_MSB_ENABLE (1L << 31) +#define VIP_MSR_DIAG_SEL_UPPER_MASK 0x7FFF0000 +#define VIP_MSR_DIAG_SEL_UPPER_SHIFT 16 +#define VIP_MSR_DIAG_LSB_ENABLE (1L << 15) +#define VIP_MSR_DIAG_SEL_LOWER_MASK 0x00007FFF +#define VIP_MSR_DIAG_SEL_LOWER_SHIFT 0 + +/*----------------------------------------------------------------*/ +/* VOP DEFINITIONS */ +/*----------------------------------------------------------------*/ + +#define VOP_CONFIGURATION 0x00000800 +#define VOP_SIGNATURE 0x00000808 + +/* VOP_CONFIGURATION BIT DEFINITIONS */ + +#define VOP_CONFIG_SWAPVBI 0x01000000 +#define VOP_CONFIG_RGBMODE 0x00200000 +#define VOP_CONFIG_SIGVAL 0x00100000 +#define VOP_CONFIG_INVERT_DISPE 0x00080000 +#define VOP_CONFIG_INVERT_VSYNC 0x00040000 +#define VOP_CONFIG_INVERT_HSYNC 0x00020000 +#define VOP_CONFIG_SWAPUV 0x00010000 +#define VOP_CONFIG_VSYNC_MASK 0x0000C000 +#define VOP_CONFIG_DISABLE_DECIMATE 0x00002000 +#define VOP_CONFIG_ENABLE_601 0x00001000 +#define VOP_CONFIG_VBI 0x00000800 +#define VOP_CONFIG_TASK 0x00000200 +#define VOP_CONFIG_SIG_FREE_RUN 0x00000100 +#define VOP_CONFIG_ENABLE_SIGNATURE 0x00000080 +#define VOP_CONFIG_SC_COMPATIBLE 0x00000040 +#define VOP_CONFIG_422_COSITED 0x00000000 +#define VOP_CONFIG_422_INTERSPERSED 0x00000010 +#define VOP_CONFIG_422_ALTERNATING 0x00000020 +#define VOP_CONFIG_422_MASK 0x00000030 +#define VOP_CONFIG_EXTENDED_SAV 0x00000008 +#define VOP_CONFIG_VIP2_16BIT 0x00000004 +#define VOP_CONFIG_DISABLED 0x00000000 +#define VOP_CONFIG_VIP1_1 0x00000001 +#define VOP_CONFIG_VIP2_0 0x00000002 +#define VOP_CONFIG_CCIR656 0x00000003 +#define VOP_CONFIG_MODE_MASK 0x00000003 + + +#endif --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_rtns.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_rtns.h 2005-12-14 11:38:27.000000000 -0700 @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron function prototypes. + * */ + +#ifndef _cim_rtns_h +#define _cim_rtns_h + +/* INCLUDE USER PARAMETER DEFINITIONS */ + +#include "cim_parm.h" + +/* COMPILER OPTION FOR C++ PROGRAMS */ + +#ifdef __cplusplus +extern "C" { +#endif + +/*--------------------------*/ +/* CIMARRON MEMORY POINTERS */ +/*--------------------------*/ + +extern unsigned char *cim_gp_ptr; +extern unsigned char *cim_fb_ptr; +extern unsigned char *cim_cmd_base_ptr; +extern unsigned char *cim_cmd_ptr; +extern unsigned char *cim_vid_ptr; +extern unsigned char *cim_vip_ptr; +extern unsigned char *cim_vg_ptr; + +/*----------------------------------------*/ +/* INITIALIZATION ROUTINE DEFINITIONS */ +/*----------------------------------------*/ + +int init_detect_cpu (unsigned long *cpu_revision, unsigned long *companion_revision); +unsigned long init_read_pci (unsigned long address); +int init_read_base_addresses (INIT_BASE_ADDRESSES *base_addresses); +int init_read_cpu_frequency (unsigned long *cpu_frequency); + +/*----------------------------------------*/ +/* GRAPHICS PROCESSOR ROUTINE DEFINITIONS */ +/*----------------------------------------*/ + +void gp_set_limit_on_buffer_lead (unsigned long lead); +void gp_set_command_buffer_base (unsigned long address, unsigned long start, + unsigned long stop); +void gp_set_frame_buffer_base (unsigned long address, unsigned long size); +void gp_set_bpp (int bpp); +void gp_declare_blt (unsigned long flags); +void gp_declare_vector (unsigned long flags); +void gp_write_parameters (void); +void gp_set_raster_operation (unsigned char ROP); +void gp_set_alpha_operation (int alpha_operation, int alpha_type, int channel, + int apply_alpha, unsigned char alpha); +void gp_set_solid_pattern (unsigned long color); +void gp_set_mono_pattern (unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, int transparent, int x, int y); +void gp_set_pattern_origin (int x, int y); +void gp_set_color_pattern (unsigned long *pattern, int format, int x, int y); +void gp_set_mono_source (unsigned long bgcolor, unsigned long fgcolor, + int transparent); +void gp_set_solid_source (unsigned long color); +void gp_set_source_transparency (unsigned long color, unsigned long mask); +void gp_program_lut (unsigned long *colors, int full_lut); +void gp_set_vector_pattern (unsigned long pattern, unsigned long color, int length); +void gp_set_strides (unsigned long dst_stride, unsigned long src_stride); +void gp_set_source_format (int format); +void gp_pattern_fill (unsigned long dstoffset, unsigned long width, unsigned long height); +void gp_screen_to_screen_blt (unsigned long dstoffset, unsigned long srcoffset, + unsigned long width, unsigned long height, int flags); +void gp_screen_to_screen_convert (unsigned long dstoffset, unsigned long srcoffset, + unsigned long width, unsigned long height, int nibble); +void gp_color_bitmap_to_screen_blt (unsigned long dstoffset, unsigned long srcx, + unsigned long width, unsigned long height, unsigned char *data, long pitch); +void gp_color_convert_blt (unsigned long dstoffset, unsigned long srcx, + unsigned long width, unsigned long height, unsigned char *data, long pitch); +void gp_custom_convert_blt (unsigned long dstoffset, unsigned long srcx, + unsigned long width, unsigned long height, unsigned char *data, long pitch); +void gp_rotate_blt (unsigned long dstoffset, unsigned long srcoffset, + unsigned long width, unsigned long height, int degrees); +void gp_mono_bitmap_to_screen_blt (unsigned long dstoffset, unsigned long srcx, + unsigned long width, unsigned long height, unsigned char *data, long stride); +void gp_text_blt (unsigned long dstoffset, unsigned long width, + unsigned long height, unsigned char *data); +void gp_mono_expand_blt (unsigned long dstoffset, unsigned long srcoffset, + unsigned long srcx, unsigned long width, unsigned long height, int byte_packed); +void gp_antialiased_text (unsigned long dstoffset, unsigned long srcx, + unsigned long width, unsigned long height, unsigned char *data, long stride, + int fourbpp); +void gp_masked_blt (unsigned long dstoffset, unsigned long width, + unsigned long height, unsigned long mono_srcx, unsigned long color_srcx, + unsigned char *mono_mask, unsigned char *color_data, long mono_pitch, + long color_pitch); +void gp_screen_to_screen_masked (unsigned long dstoffset, unsigned long srcoffset, + unsigned long width, unsigned long height, unsigned long mono_srcx, + unsigned char *mono_mask, long mono_pitch); +void gp_bresenham_line (unsigned long dstoffset, unsigned short length, + unsigned short initerr, unsigned short axialerr, unsigned short diagerr, + unsigned long flags); +void gp_line_from_endpoints (unsigned long dstoffset, unsigned long x0, + unsigned long y0, unsigned long x1, unsigned long y1, int inclusive); + +int gp_test_blt_pending (void); +void gp_wait_blt_pending (void); +void gp_wait_until_idle (void); +int gp_test_blt_busy (void); +void gp_save_state (GP_SAVE_RESTORE *gp_state); +void gp_restore_state (GP_SAVE_RESTORE *gp_state); + +/*----------------------------------------*/ +/* VIDEO GENERATOR ROUTINE DEFINITIONS */ +/*----------------------------------------*/ + +int vg_delay_milliseconds (unsigned long ms); +int vg_set_display_mode (unsigned long src_width, unsigned long src_height, + unsigned long dst_width, unsigned long dst_height, int bpp, int hz, + unsigned long flags); +int vg_set_panel_mode (unsigned long src_width, unsigned long src_height, + unsigned long dst_width, unsigned long dst_height, + unsigned long panel_width, unsigned long panel_height, + int bpp, unsigned long flags); +int vg_set_tv_mode (unsigned long *src_width, unsigned long *src_height, + unsigned long encoder, unsigned long tvres, int bpp, unsigned long flags, + unsigned long h_overscan, unsigned long v_overscan); +int vg_set_custom_mode (VG_DISPLAY_MODE *mode_params, int bpp); +int vg_set_display_bpp (int bpp); +int vg_get_display_mode_index (VG_QUERY_MODE *query); +int vg_get_display_mode_information (unsigned int index, VG_DISPLAY_MODE *vg_mode); +int vg_get_display_mode_count (void); +int vg_get_current_display_mode (VG_DISPLAY_MODE *current_display, int *bpp); +int vg_set_scaler_filter_coefficients (long h_taps[][5], long v_taps[][3]); +int vg_configure_flicker_filter (unsigned long flicker_strength, int flicker_alpha); +int vg_set_clock_frequency (unsigned long frequency, unsigned long pll_flags); +int vg_set_border_color (unsigned long border_color); +int vg_set_cursor_enable(int enable); +int vg_set_mono_cursor_colors (unsigned long bkcolor, unsigned long fgcolor); +int vg_set_cursor_position(long xpos, long ypos, VG_PANNING_COORDINATES *panning); +int vg_set_mono_cursor_shape32(unsigned long memoffset, unsigned long *andmask, + unsigned long *xormask, unsigned long x_hotspot, unsigned long y_hotspot); +int vg_set_mono_cursor_shape64(unsigned long memoffset, unsigned long *andmask, + unsigned long *xormask, unsigned long x_hotspot, unsigned long y_hotspot); +int vg_set_color_cursor_shape (unsigned long memoffset, unsigned char *data, + unsigned long width, unsigned long height, long pitch, + unsigned long x_hotspot, unsigned long y_hotspot); +int vg_pan_desktop (unsigned long x, unsigned long y, VG_PANNING_COORDINATES *panning); +int vg_set_display_offset (unsigned long address); +int vg_set_display_pitch (unsigned long pitch); +int vg_set_display_palette_entry (unsigned long index, unsigned long palette); +int vg_set_display_palette (unsigned long *palette); +int vg_set_compression_enable (int enable); +int vg_configure_compression (VG_COMPRESSION_DATA *comp_data); +int vg_test_timing_active (void); +int vg_test_vertical_active (void); +int vg_wait_vertical_blank(void); +int vg_test_even_field(void); +int vg_configure_line_interrupt (VG_INTERRUPT_PARAMS *interrupt_info); +unsigned long vg_test_and_clear_interrupt (void); +unsigned long vg_test_flip_status (void); +int vg_save_state (VG_SAVE_RESTORE *vg_state); +int vg_restore_state (VG_SAVE_RESTORE *vg_state); + +/*----------------------------------------*/ +/* VIDEO GENERATOR READ ROUTINES */ +/*----------------------------------------*/ + +unsigned long vg_read_graphics_crc (int crc_source); +unsigned long vg_read_window_crc (int crc_source, unsigned long x, unsigned long y, + unsigned long width, unsigned long height); +int vg_get_scaler_filter_coefficients (long h_taps[][5], long v_taps[][3]); +int vg_get_flicker_filter_configuration (unsigned long *strength, int *flicker_alpha); +unsigned long vg_get_display_pitch (void); +unsigned long vg_get_frame_buffer_line_size (void); +unsigned long vg_get_current_vline (void); +unsigned long vg_get_display_offset (void); +int vg_get_cursor_info (VG_CURSOR_DATA *cursor_data); +int vg_get_display_palette_entry (unsigned long index, unsigned long *entry); +unsigned long vg_get_border_color (void); +int vg_get_display_palette (unsigned long *palette); +int vg_get_compression_info (VG_COMPRESSION_DATA *comp_data); +int vg_get_compression_enable (void); +int vg_get_valid_bit (int line); + +/*----------------------------------------*/ +/* DISPLAY FILTER ROUTINE DEFINITIONS */ +/*----------------------------------------*/ + +int df_set_crt_enable (int crt_output); +int df_set_panel_enable (int panel_output); +int df_configure_video_source (DF_VIDEO_SOURCE_PARAMS *video_source_odd, + DF_VIDEO_SOURCE_PARAMS *video_source_even); +int df_set_video_offsets (int even, unsigned long y_offset, + unsigned long u_offset, unsigned long v_offset); +int df_set_video_scale (unsigned long src_width, unsigned long src_height, + unsigned long dst_width, unsigned long dst_height, unsigned long flags); +int df_set_video_position (DF_VIDEO_POSITION *video_window); +int df_set_video_filter_coefficients (long taps[][4], int phase256); +int df_set_video_enable (int enable, unsigned long flags); +int df_set_video_color_key (unsigned long key, unsigned long mask, int graphics); +int df_set_video_palette (unsigned long *palette); +int df_set_video_palette_entry (unsigned long index, unsigned long palette); +int df_configure_video_cursor_color_key (DF_VIDEO_CURSOR_PARAMS *cursor_color_key); +int df_set_video_cursor_color_key_enable (int enable); +int df_configure_alpha_window (int window, DF_ALPHA_REGION_PARAMS *alpha_data); +int df_set_alpha_window_enable (int window, int enable); +int df_set_no_ck_outside_alpha (int enable); +int df_set_video_request (unsigned long x, unsigned long y); +int df_set_output_color_space (int color_space); +int df_set_output_path (int format); +unsigned long df_test_video_flip_status (void); +int df_save_state (DF_SAVE_RESTORE *gp_state); +int df_restore_state (DF_SAVE_RESTORE *gp_state); + +/*----------------------------------------*/ +/* DISPLAY FILTER READ ROUTINES */ +/*----------------------------------------*/ + +unsigned long df_read_composite_crc (int crc_source); +unsigned long df_read_composite_window_crc (unsigned long x, unsigned long y, + unsigned long width, unsigned long height, int source); +unsigned long df_read_panel_crc (void); +int df_get_video_enable (int *enable, unsigned long *flags); +int df_get_video_source_configuration (DF_VIDEO_SOURCE_PARAMS *video_source_odd, + DF_VIDEO_SOURCE_PARAMS *video_source_even); +int df_get_video_position (DF_VIDEO_POSITION *video_window); +int df_get_video_scale (unsigned long *x_scale, unsigned long *y_scale); +int df_get_video_filter_coefficients (long taps[][4], int *phase256); +int df_get_video_color_key (unsigned long *key, unsigned long *mask, int *graphics); +int df_get_video_palette_entry(unsigned long index, unsigned long *palette); +int df_get_video_palette (unsigned long *palette); +int df_get_video_cursor_color_key (DF_VIDEO_CURSOR_PARAMS *cursor_color_key); +int df_get_video_cursor_color_key_enable (void); +int df_get_alpha_window_configuration (int window, DF_ALPHA_REGION_PARAMS *alpha_data); +int df_get_alpha_window_enable (int window); +int df_get_video_request (unsigned long *x, unsigned long *y); +int df_get_output_color_space (int *color_space); + +/*----------------------------------------*/ +/* MSR ROUTINE DEFINITIONS */ +/*----------------------------------------*/ + +int msr_init_table (void); +int msr_create_geodelink_table (GEODELINK_NODE *gliu_nodes); +int msr_create_device_list (GEODELINK_NODE *gliu_nodes, int max_devices); +int msr_read64 (unsigned long device, unsigned long msr_register, + Q_WORD *msr_value); +int msr_write64 (unsigned long device, unsigned long msr_register, + Q_WORD *msr_value); + +/*----------------------------------------*/ +/* VIP ROUTINE DEFINITIONS */ +/*----------------------------------------*/ + +int vip_initialize (VIPSETMODEBUFFER *buffer); +int vip_update_601_params (VIP_601PARAMS *buffer); +int vip_terminate (void); +int vip_configure_capture_buffers (int buffer_type, VIPINPUTBUFFER *buffer); +int vip_toggle_video_offsets (int buffer_type, VIPINPUTBUFFER *buffer); +int vip_max_address_enable (unsigned long max_address, int enable); +int vip_set_interrupt_enable (unsigned long mask, int enable); +unsigned long vip_get_interrupt_state (void); +int vip_set_capture_state (unsigned long state); +int vip_set_vsync_error (unsigned long vertical_count, unsigned long window_before, + unsigned long window_after, int enable); +int vip_configure_fifo (unsigned long fifo_type, unsigned long fifo_size); +int vip_set_loopback_enable (int bEnable); +int vip_configure_genlock (VIPGENLOCKBUFFER *buffer); +int vip_set_genlock_enable (int bEnable); +int vip_configure_pages (int page_count, unsigned long page_offset); +int vip_set_interrupt_line (int line); +int vip_reset (void); +int vip_set_subwindow_enable (VIPSUBWINDOWBUFFER *buffer); +int vip_reset_interrupt_state (unsigned long interrupt_mask); + +int vip_save_state(VIPSTATEBUFFER *save_buffer); +int vip_restore_state(VIPSTATEBUFFER *restore_buffer); +int vip_set_power_characteristics (VIPPOWERBUFFER *buffer); +int vip_set_priority_characteristics (VIPPRIORITYBUFFER *buffer); +int vip_set_debug_characteristics (VIPDEBUGBUFFER *buffer); +int vip_test_genlock_active (void); +int vip_test_signal_status (void); +unsigned long vip_get_current_field (void); + +/*----------------------------------------*/ +/* VIP READ ROUTINES */ +/*----------------------------------------*/ + +int vip_get_current_mode (VIPSETMODEBUFFER *buffer); +int vip_get_601_configuration (VIP_601PARAMS *buffer); +int vip_get_buffer_configuration (int buffer_type, VIPINPUTBUFFER *buffer); +int vip_get_genlock_configuration (VIPGENLOCKBUFFER *buffer); +int vip_get_genlock_enable (void); +int vip_is_buffer_update_latched (void); +unsigned long vip_get_capture_state (void); +unsigned long vip_get_current_line (void); +unsigned long vip_read_fifo (unsigned long fifo_address); +int vip_write_fifo (unsigned long fifo_address, unsigned long fifo_data); +int vip_enable_fifo_access (int enable); +int vip_get_capability_characteristics (VIPCAPABILITIESBUFFER *buffer); +int vip_get_power_characteristics (VIPPOWERBUFFER *buffer); +int vip_get_priority_characteristics (VIPPRIORITYBUFFER *buffer); + +/*----------------------------------------*/ +/* VOP ROUTINE DEFINITIONS */ +/*----------------------------------------*/ + +int vop_set_vbi_window (VOPVBIWINDOWBUFFER *buffer); +int vop_enable_vbi_output (int enable); +int vop_set_configuration (VOPCONFIGURATIONBUFFER *config); +int vop_save_state(VOPSTATEBUFFER *save_buffer); +int vop_restore_state(VOPSTATEBUFFER *save_buffer); + +/*----------------------------------------*/ +/* VOP READ ROUTINES */ +/*----------------------------------------*/ + +int vop_get_current_mode (VOPCONFIGURATIONBUFFER *config); +int vop_get_vbi_configuration (VOPVBIWINDOWBUFFER *buffer); +int vop_get_vbi_enable (void); +unsigned long vop_get_crc (void); +unsigned long vop_read_vbi_crc(void); + +/* CLOSE BRACKET FOR C++ COMPLILATION */ + +#ifdef __cplusplus +} +#endif + +#endif + --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_df.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_df.c 2005-12-14 11:39:33.000000000 -0700 @@ -0,0 +1,2561 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron display filter routines. These routines program the video hardware. + * */ + +/*--------------------------------------------------------------------------- + * df_set_crt_enable + * + * This routine enables or disables CRT output. + *---------------------------------------------------------------------------*/ + +int df_set_crt_enable (int crt_output) +{ + unsigned long config, misc; + + config = READ_VID32 (DF_DISPLAY_CONFIG); + misc = READ_VID32 (DF_VID_MISC); + + switch (crt_output) + { + /* DISABLE DISPLAY */ + + case DF_CRT_DISABLE: + + config &= ~(DF_DCFG_DIS_EN | DF_DCFG_HSYNC_EN | + DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN); + misc |= DF_DAC_POWER_DOWN; + break; + + /* ENABLE THE DISPLAY */ + + case DF_CRT_ENABLE: + + config |= (DF_DCFG_DIS_EN | DF_DCFG_HSYNC_EN | + DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN); + misc &= ~(DF_DAC_POWER_DOWN | DF_ANALOG_POWER_DOWN); + break; + + /* HSYNC:OFF VSYNC:ON */ + + case DF_CRT_STANDBY: + + config = (config & ~(DF_DCFG_DIS_EN | DF_DCFG_HSYNC_EN | DF_DCFG_DAC_BL_EN)) | + DF_DCFG_VSYNC_EN; + misc |= DF_DAC_POWER_DOWN; + break; + + /* HSYNC:ON VSYNC:OFF */ + + case DF_CRT_SUSPEND: + + config = (config & ~(DF_DCFG_DIS_EN | DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN)) | + DF_DCFG_HSYNC_EN; + misc |= DF_DAC_POWER_DOWN; + break; + + default: + return CIM_STATUS_INVALIDPARAMS; + } + + WRITE_VID32 (DF_DISPLAY_CONFIG, config); + WRITE_VID32 (DF_VID_MISC, misc); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_panel_enable + * + * This routine enables or disables panel output. + *---------------------------------------------------------------------------*/ + +int df_set_panel_enable (int enable) +{ + unsigned long pm; + + pm = READ_VID32 (DF_POWER_MANAGEMENT); + + if (enable) pm |= DF_PM_PANEL_ON; + else pm &= ~DF_PM_PANEL_ON; + + WRITE_VID32 (DF_POWER_MANAGEMENT, pm); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_configure_video_source + * + * This routine initializes all aspects of the source buffer for a video overlay. + *---------------------------------------------------------------------------*/ + +int df_configure_video_source (DF_VIDEO_SOURCE_PARAMS *video_source_odd, + DF_VIDEO_SOURCE_PARAMS *video_source_even) +{ + unsigned long pitch, ctrl, vcfg; + unsigned long lock, vg_line, gcfg; + unsigned long width, size, scale; + unsigned long misc; + + lock = READ_REG32 (DC3_UNLOCK); + vg_line = READ_REG32 (DC3_LINE_SIZE); + gcfg = READ_REG32 (DC3_GENERAL_CFG); + vcfg = READ_VID32 (DF_VIDEO_CONFIG); + ctrl = READ_VID32 (DF_VID_ALPHA_CONTROL); + scale = READ_VID32 (DF_VIDEO_SCALER); + + /* STORE THE DESIRED SCALING PROCEDURE */ + /* Cimarron supports two modes when programming the scale and position */ + /* of the video window. The first mode is designed to implicitly apply */ + /* the graphics scale to any video operations. The second applys the */ + /* video unchanged, allowing complete control by the user. To allow */ + /* visibility between modules, the current mode is stored in a spare */ + /* bit in the DF miscellaneous register. */ + + misc = READ_VID32 (DF_VID_MISC); + if (video_source_odd->flags & DF_SOURCEFLAG_IMPLICITSCALING) + misc |= DF_USER_IMPLICIT_SCALING; + else + misc &= DF_USER_IMPLICIT_SCALING; + WRITE_VID32 (DF_VID_MISC, misc); + + /* PARAMETER - VIDEO PITCH */ + + pitch = (video_source_odd->y_pitch >> 3) | ((video_source_odd->uv_pitch >> 3) << 16); + + /* PARAMETER - VIDEO FORMAT */ + + gcfg &= ~DC3_GCFG_YUV_420; + vcfg &= ~(DF_VCFG_VID_INP_FORMAT | DF_VCFG_4_2_0_MODE); + ctrl &= ~(DF_VIDEO_INPUT_IS_RGB | DF_CSC_VIDEO_YUV_TO_RGB | DF_HD_VIDEO | + DF_YUV_CSC_EN); + + /* SELECT PIXEL ORDERING */ + + switch (video_source_odd->video_format & 3) + { + case 0: vcfg |= DF_VCFG_UYVY_FORMAT; break; + case 1: vcfg |= DF_VCFG_Y2YU_FORMAT; break; + case 2: vcfg |= DF_VCFG_YUYV_FORMAT; break; + case 3: vcfg |= DF_VCFG_YVYU_FORMAT; break; + } + + /* SELECT SOURCE FORMAT (4:2:2, 4:2:0, RGB) */ + + switch (video_source_odd->video_format >> 2) + { + case 0: ctrl |= DF_CSC_VIDEO_YUV_TO_RGB; break; + + case 1: ctrl |= DF_CSC_VIDEO_YUV_TO_RGB; + vcfg |= DF_VCFG_4_2_0_MODE; + gcfg |= DC3_GCFG_YUV_420; + break; + + case 2: ctrl |= DF_VIDEO_INPUT_IS_RGB; break; + + default: return CIM_STATUS_INVALIDPARAMS; + } + + /* ALIGN TO APPROPRIATE OUTPUT COLOR SPACE */ + /* We have assumed until this point that the output color space is RGB */ + /* and the input (if YUV) is always SDTV video. */ + + if (video_source_odd->flags & DF_SOURCEFLAG_HDTVSOURCE) + ctrl |= DF_HD_VIDEO; + + if (ctrl & DF_CSC_GRAPHICS_RGB_TO_YUV) + { + /* YUV OUTPUT - DISABLE YUV->RGB AND ENABLE YUV->YUV */ + + ctrl &= ~DF_CSC_VIDEO_YUV_TO_RGB; + + if ((!(ctrl & DF_HD_VIDEO) && (ctrl & DF_HD_GRAPHICS)) || + ((ctrl & DF_HD_VIDEO) && !(ctrl & DF_HD_GRAPHICS))) + { + ctrl |= DF_YUV_CSC_EN; + } + } + + /* PARAMETER - DISPLAY FILTER BUFFER SIZE */ + /* The line size in the video generator must be 32-byte aligned. */ + /* However, smaller alignments are managed by setting the */ + /* appropriate pitch and clipping the video window. */ + + vcfg &= ~(DF_VCFG_LINE_SIZE_LOWER_MASK | DF_VCFG_LINE_SIZE_BIT8 | + DF_VCFG_LINE_SIZE_BIT9); + + size = ((video_source_odd->width >> 1) + 7) & 0xFFF8; + + vcfg |= (size & 0x00FF) << 8; + if (size & 0x0100) vcfg |= DF_VCFG_LINE_SIZE_BIT8; + if (size & 0x0200) vcfg |= DF_VCFG_LINE_SIZE_BIT9; + + scale = (scale & ~0x7FF) | video_source_odd->height; + + /* PARAMETER - VIDEO GENERATOR BUFFER SIZE */ + + vg_line &= ~DC3_LINE_SIZE_VLS_MASK; + + if (gcfg & DC3_GCFG_YUV_420) + width = ((video_source_odd->width >> 1) + 7) & 0xFFF8; + else + width = ((video_source_odd->width << 1) + 31) & 0xFFE0; + + vg_line |= (width >> 3) << DC3_LINE_SIZE_VB_SHIFT; + + /* WRITE ALL PARAMETERS AT ONCE */ + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_VID32 (DF_VIDEO_CONFIG, vcfg); + WRITE_VID32 (DF_VID_ALPHA_CONTROL, ctrl); + WRITE_VID32 (DF_VIDEO_SCALER, scale); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + WRITE_REG32 (DC3_LINE_SIZE, vg_line); + WRITE_REG32 (DC3_VID_YUV_PITCH, pitch); + + /* WRITE EVEN OR ODD BUFFER OFFSETS */ + /* The even buffer is only valid inside an interlaced display. */ + + if (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN) + { + WRITE_REG32 (DC3_VID_EVEN_Y_ST_OFFSET, video_source_even->y_offset); + WRITE_REG32 (DC3_VID_EVEN_U_ST_OFFSET, video_source_even->u_offset); + WRITE_REG32 (DC3_VID_EVEN_V_ST_OFFSET, video_source_even->v_offset); + } + + WRITE_REG32 (DC3_VID_Y_ST_OFFSET, video_source_odd->y_offset); + WRITE_REG32 (DC3_VID_U_ST_OFFSET, video_source_odd->u_offset); + WRITE_REG32 (DC3_VID_V_ST_OFFSET, video_source_odd->v_offset); + + WRITE_REG32 (DC3_UNLOCK, lock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_video_offsets + * + * This routine sets the starting offset for the video buffer(s). The buffers + * can also be configured inside df_configure_video_source, but a separate + * routine is provided here to allow quick buffer flipping. + *---------------------------------------------------------------------------*/ + +int df_set_video_offsets (int even, unsigned long y_offset, + unsigned long u_offset, unsigned long v_offset) +{ + unsigned long lock = READ_REG32 (DC3_UNLOCK); + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + + if (even) + { + WRITE_REG32 (DC3_VID_EVEN_Y_ST_OFFSET, y_offset); + WRITE_REG32 (DC3_VID_EVEN_U_ST_OFFSET, u_offset); + WRITE_REG32 (DC3_VID_EVEN_V_ST_OFFSET, v_offset); + } + else + { + WRITE_REG32 (DC3_VID_Y_ST_OFFSET, y_offset); + WRITE_REG32 (DC3_VID_U_ST_OFFSET, u_offset); + WRITE_REG32 (DC3_VID_V_ST_OFFSET, v_offset); + } + + WRITE_REG32 (DC3_UNLOCK, lock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_video_scale + * + * This routine programs the horizontal/vertical scale factors for video. To + * disable scaling/filtering, this routine should be called with identical source + * and destination dimensions. + *---------------------------------------------------------------------------*/ + +int df_set_video_scale (unsigned long src_width, unsigned long src_height, + unsigned long dst_width, unsigned long dst_height, unsigned long flags) +{ + unsigned long temp, misc; + unsigned long scale, gfxscale; + unsigned long fbactive, src; + unsigned long size, downscale; + unsigned long vcfg, gcfg, unlock; + + /* APPLY THE GRAPHICS SCALE */ + /* When requested by the user, we will adjust the video scale by the */ + /* current graphics scale factor. This allows video to be programmed */ + /* in terms of the graphics source resolution. */ + + misc = READ_VID32 (DF_VID_MISC); + if (misc & DF_USER_IMPLICIT_SCALING) + { + gfxscale = READ_REG32 (DC3_GFX_SCALE); + fbactive = READ_REG32 (DC3_FB_ACTIVE); + + /* REVERSE ENGINEER THE SCALE FACTOR */ + /* The graphics scale factor is (source / (dst - 1)), so a little */ + /* math is performed to reverse engineer the correct scale for */ + /* video. */ + /* */ + /* F = (0x4000*S)/(D-1) -> (D/S) = (((0x4000*S)/F)+1)/S */ + + scale = gfxscale & 0xFFFF; + src = (fbactive >> 16) + 1; + if (scale != 0x4000) + { + dst_width = dst_width * (((0x4000 * src) / scale) + 1); + dst_width /= src; + } + + scale = gfxscale >> 16; + src = (fbactive & 0xFFFF) + 1; + if (scale != 0x4000) + { + dst_height = dst_height * (((0x4000 * src) / scale) + 1); + dst_height /= src; + } + } + + /* CHECK FOR VALID SCALING FACTOR */ + /* The display filter/video generator can support up to 8:1 */ + /* horizontal downscale and up to 4:1 vertical downscale. */ + /* Scale factors above 4:1 horizontal and 2:1 horizontal */ + /* will have a quality impact. However, at such large scale */ + /* factors, it might not matter, */ + + if (((flags & DF_SCALEFLAG_CHANGEX) && dst_width < (src_width >> 3)) || + ((flags & DF_SCALEFLAG_CHANGEY) && dst_height < (src_height >> 2))) + { + return CIM_STATUS_INVALIDSCALE; + } + + /* ENABLE OR DISABLE ADVANCED SCALING FEATURES */ + /* Scaling above 2:1 vertical and 4:1 horizontal relies */ + /* on mechanisms beside the line filter. */ + + if (flags & DF_SCALEFLAG_CHANGEX) + { + scale = READ_VID32 (DF_VIDEO_SCALER); + vcfg = READ_VID32 (DF_VIDEO_CONFIG); + vcfg &= ~(DF_VCFG_LINE_SIZE_LOWER_MASK | DF_VCFG_LINE_SIZE_BIT8 | + DF_VCFG_LINE_SIZE_BIT9); + + if (dst_width < (src_width >> 2)) + { + src_width >>= 1; + WRITE_VID32 (DF_VIDEO_SCALER, scale | DF_SCALE_DOUBLE_H_DOWNSCALE); + } + else + { + WRITE_VID32 (DF_VIDEO_SCALER, scale & ~DF_SCALE_DOUBLE_H_DOWNSCALE); + } + + /* PROGRAM A NEW LINE SIZE */ + /* The line size must be updated when using the Double Horizontal */ + /* Downscale (DHD) bit. This is because the amount of VFIFO space */ + /* consumed is effectively half in this mode. */ + + size = ((src_width >> 1) + 7) & 0xFFF8; + vcfg |= (size & 0x00FF) << 8; + if (size & 0x0100) vcfg |= DF_VCFG_LINE_SIZE_BIT8; + if (size & 0x0200) vcfg |= DF_VCFG_LINE_SIZE_BIT9; + WRITE_VID32 (DF_VIDEO_CONFIG, vcfg); + WRITE_VID32 (DF_VIDEO_XSCALE, ((0x10000 * src_width) / dst_width)); + } + if (flags & DF_SCALEFLAG_CHANGEY) + { + unlock = READ_REG32 (DC3_UNLOCK); + gcfg = READ_REG32 (DC3_GENERAL_CFG) & ~DC3_GCFG_VDSE; + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + if (dst_height < (src_height >> 1)) + { + gcfg |= DC3_GCFG_VDSE; + downscale = READ_REG32 (DC3_VID_DS_DELTA) & ~DC3_DS_DELTA_MASK; + if (dst_height == (src_height >> 2)) + downscale |= (0x3FFF << 18); + else + downscale |= (((src_height >> 1) << 14) / dst_height) << 18; + + WRITE_REG32 (DC3_VID_DS_DELTA, downscale); + WRITE_VID32 (DF_VIDEO_YSCALE, 0x20000); + } + else + { + WRITE_VID32 (DF_VIDEO_YSCALE, ((0x10000 * src_height) / dst_height)); + } + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + WRITE_REG32 (DC3_UNLOCK, unlock); + } + + /* CHECK IF SCALING IS DISABLED */ + /* If no scaling occurs, we disable the hardware filter. */ + + temp = READ_VID32 (DF_VIDEO_CONFIG); + if ((READ_VID32 (DF_VIDEO_XSCALE) == 0x10000) && + (READ_VID32 (DF_VIDEO_YSCALE) == 0x10000)) + { + WRITE_VID32 (DF_VIDEO_CONFIG, (temp | DF_VCFG_SC_BYP)); + } + else + WRITE_VID32 (DF_VIDEO_CONFIG, (temp & ~DF_VCFG_SC_BYP)); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_video_position + * + * This routine programs the position of the video window on the display. + * An indent parameter is also passed to this program to prevent artifacts + * when the video window is moved beyond the left edge of the screen. + *---------------------------------------------------------------------------*/ + +int df_set_video_position (DF_VIDEO_POSITION *video_window) +{ + unsigned long vblankstart_even, vblankend_even, vsyncend_even, vtotal_even, vactive_even; + unsigned long hblankstart, hblankend, hsyncend, htotal, hactive; + unsigned long vblankstart, vblankend, vsyncend, vtotal, vactive; + unsigned long width, height, height_even; + unsigned long adjust, border_x, border_y, border_y_even; + unsigned long xstart, xend; + unsigned long ystart, yend; + unsigned long ckey_x, ckey_y; + unsigned long x_copy, y_copy; + unsigned long width_copy, height_copy; + unsigned long vcfg, initread; + unsigned long xscale, dst_clip; + unsigned long ypos, ypos_even; + unsigned long y, gfxscale; + unsigned long misc, fbactive; + unsigned long scale, src; + unsigned long irq_ctl; + unsigned long unlock; + + hsyncend = ((READ_REG32 (DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1; + vsyncend = ((READ_REG32 (DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1; + vblankend = ((READ_REG32 (DC3_V_BLANK_TIMING) >> 16) & 0xFFF) + 1; + hblankend = ((READ_REG32 (DC3_H_BLANK_TIMING) >> 16) & 0xFFF) + 1; + htotal = ((READ_REG32 (DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + vtotal = ((READ_REG32 (DC3_V_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + vblankstart = (READ_REG32 (DC3_V_BLANK_TIMING) & 0xFFF) + 1; + hblankstart = (READ_REG32 (DC3_H_BLANK_TIMING) & 0xFFF) + 1; + hactive = (READ_REG32 (DC3_H_ACTIVE_TIMING) & 0xFFF) + 1; + vactive = (READ_REG32 (DC3_V_ACTIVE_TIMING) & 0xFFF) + 1; + unlock = READ_REG32 (DC3_UNLOCK); + + /* INCLUDE BORDER IF REQUESTED */ + + if (video_window->flags & DF_POSFLAG_INCLUDEBORDER) + { + border_x = htotal - hblankend; + border_y = vtotal - vblankend; + hactive = hblankstart + htotal - hblankend; + vactive = vblankstart + vtotal - vblankend; + } + else + { + border_x = border_y = 0; + } + + /* APPLY THE GRAPHICS SCALE */ + /* Do not alter the input data. */ + + width_copy = video_window->width; + height_copy = video_window->height; + x_copy = video_window->x; + y_copy = video_window->y; + + misc = READ_VID32 (DF_VID_MISC); + if (misc & DF_USER_IMPLICIT_SCALING) + { + gfxscale = READ_REG32 (DC3_GFX_SCALE); + fbactive = READ_REG32 (DC3_FB_ACTIVE); + + /* REVERSE ENGINEER THE SCALE FACTOR */ + + scale = gfxscale & 0xFFFF; + src = (fbactive >> 16) + 1; + if (scale != 0x4000) + { + width_copy = width_copy * (((0x4000 * src) / scale) + 1); + width_copy /= src; + x_copy = x_copy * (((0x4000 * src) / scale) + 1); + x_copy /= src; + } + + scale = gfxscale >> 16; + src = (fbactive & 0xFFFF) + 1; + if (scale != 0x4000) + { + height_copy = height_copy * (((0x4000 * src) / scale) + 1); + height_copy /= src; + y_copy = y_copy * (((0x4000 * src) / scale) + 1); + y_copy /= src; + } + } + + /* HANDLE INTERLACING */ + /* When the output is interlaced, we must set the position and height */ + /* on the fields and not on the composite image. */ + + if ((irq_ctl = READ_REG32 (DC3_IRQ_FILT_CTL)) & DC3_IRQFILT_INTL_EN) + { + vsyncend_even = ((READ_REG32 (DC3_V_SYNC_EVEN) >> 16) & 0xFFF) + 1; + vtotal_even = ((READ_REG32 (DC3_V_ACTIVE_EVEN) >> 16) & 0xFFF) + 1; + vblankend_even = ((READ_REG32 (DC3_V_BLANK_EVEN) >> 16) & 0xFFF) + 1; + vactive_even = (READ_REG32 (DC3_V_ACTIVE_EVEN) & 0xFFF) + 1; + vblankstart_even = (READ_REG32 (DC3_V_BLANK_EVEN) & 0xFFF) + 1; + + if (video_window->flags & DF_POSFLAG_INCLUDEBORDER) + { + border_y_even = vtotal_even- vblankend_even; + vactive_even = vblankstart_even + vtotal_even - vblankend_even; + } + else + border_y_even = 0; + + /* THE ODD FIELD MUST ALWAYS PRECEDE THE EVEN FIELD */ + /* This implies that we can never start video on an odd y position */ + /* in the composite image. This is required because the only way to */ + /* accomplish an odd y start would be to switch the buffer offsets, */ + /* which could have serious repercussions for genlocked VIP. */ + + y = y_copy >> 1; + + /* CALCULATE Y POSITION FOR ODD FIELD */ + /* Clip the video window to the odd field timings. Note that the */ + /* height in the odd field may be greater if the video height is */ + /* odd. */ + + height = (height_copy + 1) >> 1; + if ((y + height) > vactive) + height = vactive - y; + + ystart = y + vtotal_even - vsyncend_even + 1; + if (video_window->flags & DF_POSFLAG_INCLUDEBORDER) + ystart -= border_y_even; + + yend = ystart + height; + ypos = (yend << 16) | ystart; + + /* CALCULATE Y POSITION FOR EVEN FIELD */ + + height_even = height_copy >> 1; + if ((y + height_even) > vactive_even) + height_even = vactive_even - y; + + ystart = y + vtotal - vsyncend + 1; + if (video_window->flags & DF_POSFLAG_INCLUDEBORDER) + ystart -= border_y; + + yend = ystart + height_even; + ypos_even = (yend << 16) | ystart; + + /* CALCULATE ACTUAL FRAME BUFFER HEIGHT */ + /* The y position and height are used to determine the actual */ + /* placement of the color key region. The region will either be */ + /* the sum of the even and odd fields (for interlaced addressing */ + /* or flicker filtering) or it will be the union of the two (for */ + /* line doubling). We must also adjust the region such that the */ + /* origin (0, 0) is centered on the beginning of graphics data. */ + /* This is only a problem if video is being displayed over the */ + /* overscan area. */ + + if ((READ_REG32 (DC3_GENLK_CTL) & DC3_GC_FLICKER_FILTER_ENABLE) || + (irq_ctl & DC3_IRQFILT_INTL_ADDR)) + { + y <<= 1; + height += height_even; + adjust = border_y + border_y_even; + } + else + { + adjust = border_y; + if (height_even > height) + height = height_even; + } + if (video_window->flags & DF_POSFLAG_INCLUDEBORDER) + { + if (y > adjust) + { + y -= adjust; + adjust = 0; + } + else + { + adjust -= y; + if (height > adjust) + height -= adjust; + else + height = 0; + } + } + + } + else + { + y = y_copy; + + height = height_copy; + if ((y + height) > vactive) + height = vactive - y; + + ystart = y + vtotal - vsyncend + 1; + if (video_window->flags & DF_POSFLAG_INCLUDEBORDER) + ystart -= border_y; + + yend = ystart + height; + ypos = (yend << 16) | ystart; + ypos_even = 0; + } + + /* HORIZONTAL POSITION */ + /* The horizontal values are identical for the even and odd field. */ + + width = width_copy; + xstart = x_copy + htotal - hsyncend - 14; + if (video_window->flags & DF_POSFLAG_INCLUDEBORDER) + xstart -= border_x; + + /* RIGHT CLIPPING */ + + if ((x_copy + width) > hactive) + width = hactive - x_copy; + + xend = xstart + width; + + /* CALCULATE LEFT CLIPPING PARAMETER */ + /* The value passed in can be interpreted as destination pixels, in which */ + /* case the video scale is factored in, or as source pixels, in which case */ + /* the value is written directly. Also, the display filter's initial read */ + /* address value is only programmable on 4-pixel increments. However, we */ + /* can achieve an arbitrary left clip by adjusting the xstart value, as */ + /* there is a 14-clock delay in which to play. Also, according to the */ + /* designers, 4:2:0 and 4:2:2 behave identically when setting the initial */ + /* read address. The addition of scaling further complicates the */ + /* algorithm. When setting the initial read address, it is in terms of */ + /* source pixels, while adjusting the xstart value is in destination pixels */ + /* We may thus not be able to achieve a perfect clipping fit for scaled */ + /* video. We compensate by including two clipping parameters in our */ + /* structure. This allows us the user additional control and it allows us */ + /* to accurately convey to the user the state of clipping on the machine. */ + + initread = video_window->left_clip; + dst_clip = 0; + if (!(video_window->flags & DF_POSFLAG_DIRECTCLIP)) + { + xscale = READ_VID32 (DF_VIDEO_XSCALE) & 0xFFFFF; + initread = (initread * xscale) / 0x10000; + if (xscale) + dst_clip = ((initread & 3) * 0x10000) / xscale; + } + else + dst_clip = video_window->dst_clip; + + /* LIMIT THE CLIP */ + /* We technically have a 14 pixel window in which to play. However, taking */ + /* the entire 14 pixels makes the video timing a little hairy... Also note */ + /* that we cannot do this when performing panel centering, as the video */ + /* would then exceed the mode size. */ + + if (dst_clip > 4) + dst_clip = 4; + if (READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_DCEN) + dst_clip = 0; + + xstart -= dst_clip; + + vcfg = READ_VID32 (DF_VIDEO_CONFIG); + vcfg &= ~DF_VCFG_INIT_READ_MASK; + vcfg |= (initread >> 2) << 16; + + /* SET COLOR KEY REGION */ + /* We are assuming that color keying will never be desired outside */ + /* of the video region. We adjust the color key region for graphics */ + /* scaling. */ + + gfxscale = READ_REG32 (DC3_GFX_SCALE); + + ckey_x = ((x_copy * (gfxscale & 0xFFFF)) / 0x4000) | + ((((x_copy + width) * (gfxscale & 0xFFFF)) / 0x4000) << 16); + ckey_y = ((y * (gfxscale >> 16)) / 0x4000) | + ((((y + height) * (gfxscale >> 16)) / 0x4000) << 16); + + /* WRITE ALL PARAMETERS AT ONCE */ + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_CLR_KEY_X, ckey_x); + WRITE_REG32 (DC3_CLR_KEY_Y, ckey_y); + WRITE_VID32 (DF_VIDEO_X_POS, (xend << 16) | xstart); + WRITE_VID32 (DF_VIDEO_Y_POS, ypos); + WRITE_VID32 (DF_VID_YPOS_EVEN, ypos_even); + WRITE_VID32 (DF_VIDEO_CONFIG, vcfg); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_video_filter_coefficients + * + * This routine sets the horizontal and vertical filter coefficients for video + * scaling. These coefficients are used for upscaling and downscaling video. + * If the phase256 parameter is 1, the coefficient arrays are used as single + * arrays of 256 phases for both vertical and horizontal scaling. If the + * phase256 parameter is clear, the coefficient arrays are used as two 128-phase + * arrays. The first 128 entries represent the phases for vertical scaling. + * The last 128 entries represent the phases for horizontal scaling. + *---------------------------------------------------------------------------*/ + +int df_set_video_filter_coefficients (long taps[][4], int phase256) +{ + unsigned long scale, coeff0, coeff1; + unsigned long i; + long (*defaults)[2]; + + /* SET PHASE COUNT AND CHOOSE COEFFICIENT ARRAY */ + + scale = READ_VID32 (DF_VIDEO_SCALER); + if (phase256) + { + WRITE_VID32 (DF_VIDEO_SCALER, (scale & ~DF_SCALE_128_PHASES)); + defaults = CimarronVideoFilter256; + } + else + { + WRITE_VID32 (DF_VIDEO_SCALER, (scale | DF_SCALE_128_PHASES)); + defaults = CimarronVideoFilter128; + } + + /* PROGRAM COEFFICIENTS */ + + for (i = 0; i < 256; i++) + { + if (!taps) + { + coeff0 = defaults[i][0]; + coeff1 = defaults[i][1]; + } + else + { + if (taps[i][1] < 0) coeff0 = -taps[i][1] | 0x8000; + else coeff0 = taps[i][1]; + + coeff0 <<= 16; + + if (taps[i][0] < 0) coeff0 |= -taps[i][0] | 0x8000; + else coeff0 |= taps[i][0]; + + + + if (taps[i][3] < 0) coeff1 = -taps[i][3] | 0x8000; + else coeff1 = taps[i][3]; + + coeff1 <<= 16; + + if (taps[i][2] < 0) coeff1 |= -taps[i][2] | 0x8000; + else coeff1 |= taps[i][2]; + } + + WRITE_VID32 ((DF_COEFFICIENT_BASE + (i << 3)), coeff0); + WRITE_VID32 ((DF_COEFFICIENT_BASE + (i << 3) + 4), coeff1); + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_video_enable + * + * This routine enables or disables the video overlay. + *---------------------------------------------------------------------------*/ + +int df_set_video_enable (int enable, unsigned long flags) +{ + unsigned long vcfg, lock, gcfg; + unsigned long dcfg, vg_ckey, fifo = 0; + + vcfg = READ_VID32 (DF_VIDEO_CONFIG); + lock = READ_REG32 (DC3_UNLOCK); + gcfg = READ_REG32 (DC3_GENERAL_CFG); + + /* SET VIDEO FIFO END WATERMARK */ + /* The video FIFO end watermark is set to 0 when video is disabled */ + /* to allow low priority transactions in the VG. Otherwise, the */ + /* priority will be forced high until the VG fills the video FIFO */ + /* by not fetching video. That could take a while... Note that */ + /* we set the end priority to be 4 greater than the start. We */ + /* assume that the start priority has been configured by a modeset. */ + + dcfg = READ_REG32 (DC3_DISPLAY_CFG) & ~DC3_DCFG_VFHPEL_MASK; + if (enable) + { + fifo = ((dcfg >> 12) & 0x0000000F) + 4; + if (fifo > 0xF) + fifo = 0xF; + } + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_DISPLAY_CFG, dcfg | (fifo << 16)); + + /* ENABLE OR DISABLE VIDEO */ + /* The mechanism to fetch video data is enabled first and */ + /* disabled last. */ + + if (enable) + { + WRITE_REG32 (DC3_GENERAL_CFG, (gcfg | DC3_GCFG_VIDE)); + WRITE_VID32 (DF_VIDEO_CONFIG, (vcfg | DF_VCFG_VID_EN)); + + /* DISABLE COLOR KEYING IF REQUESTED BY THE USER */ + + if (flags & DF_ENABLEFLAG_NOCOLORKEY) + { + /* OVERRIDE THE MODE TO COLOR KEYING */ + + dcfg = READ_VID32 (DF_DISPLAY_CONFIG); + WRITE_VID32 (DF_DISPLAY_CONFIG, (dcfg & ~DF_DCFG_VG_CK)); + + /* DISABLE COLOR KEYING IN THE VG */ + + vg_ckey = READ_REG32 (DC3_COLOR_KEY); + WRITE_REG32 (DC3_COLOR_KEY, (vg_ckey & ~DC3_CLR_KEY_ENABLE)); + } + else if (!(READ_VID32 (DF_DISPLAY_CONFIG) & DF_DCFG_VG_CK)) + { + /* OTHERWISE RE-ENABLE COLOR KEYING */ + + vg_ckey = READ_REG32 (DC3_COLOR_KEY); + WRITE_REG32 (DC3_COLOR_KEY, (vg_ckey | DC3_CLR_KEY_ENABLE)); + } + } + else + { + WRITE_VID32 (DF_VIDEO_CONFIG, (vcfg & ~DF_VCFG_VID_EN)); + WRITE_REG32 (DC3_GENERAL_CFG, (gcfg & ~DC3_GCFG_VIDE)); + + /* DISABLE COLOR KEY WINDOW WHEN VIDEO IS INACTIVE */ + /* To mimic legacy functionality, we disble color keying */ + /* when the video window is not active. We will restore */ + /* the enable when video is re-enabled if the appropriate */ + /* bit is set in display config. */ + + vg_ckey = READ_REG32 (DC3_COLOR_KEY); + WRITE_REG32 (DC3_COLOR_KEY, (vg_ckey & ~DC3_CLR_KEY_ENABLE)); + } + WRITE_REG32 (DC3_UNLOCK, lock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_video_color_key + * + * This routine configures the video color/chroma key mechanism. + *---------------------------------------------------------------------------*/ + +int df_set_video_color_key (unsigned long key, unsigned long mask, int graphics) +{ + unsigned long lock, vg_ckey, df_dcfg; + + vg_ckey = READ_REG32 (DC3_COLOR_KEY); + lock = READ_REG32 (DC3_UNLOCK); + df_dcfg = READ_VID32 (DF_DISPLAY_CONFIG); + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + + if (graphics) + { + /* COLOR KEY - USE VG HARDWARE */ + /* Note that color key is never enabled unless a video window */ + /* is active. This is to match legacy behavior. */ + + df_dcfg &= ~DF_DCFG_VG_CK; + vg_ckey = (vg_ckey & 0xFF000000) | (key & 0xFFFFFF); + if (READ_VID32 (DF_VIDEO_CONFIG) & DF_VCFG_VID_EN) + vg_ckey |= DC3_CLR_KEY_ENABLE; + else + vg_ckey &= ~DC3_CLR_KEY_ENABLE; + + WRITE_VID32 (DF_DISPLAY_CONFIG, df_dcfg); + WRITE_REG32 (DC3_COLOR_KEY, vg_ckey); + WRITE_REG32 (DC3_COLOR_MASK, (mask & 0xFFFFFF)); + } + else + { + /* CHROMA KEY - USE DF HARDWARE */ + + df_dcfg |= DF_DCFG_VG_CK; + vg_ckey &= ~DC3_CLR_KEY_ENABLE; + + WRITE_REG32 (DC3_COLOR_KEY, vg_ckey); + WRITE_VID32 (DF_DISPLAY_CONFIG, df_dcfg); + WRITE_VID32 (DF_VIDEO_COLOR_KEY, (key & 0xFFFFFF)); + WRITE_VID32 (DF_VIDEO_COLOR_MASK, (mask & 0xFFFFFF)); + } + + WRITE_REG32 (DC3_UNLOCK, lock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_video_palette + * + * This routine loads the video hardware palette. If a NULL pointer is + * specified, the palette is bypassed. + *--------------------------------------------------------------------------*/ + +int df_set_video_palette (unsigned long *palette) +{ + unsigned long i, entry; + unsigned long misc, dcfg; + + /* LOAD GEODE LX VIDEO PALETTE */ + + WRITE_VID32 (DF_PALETTE_ADDRESS, 0); + for (i = 0; i < 256; i++) + { + if (palette) entry = palette[i]; + else entry = i | (i << 8) | (i << 16); + WRITE_VID32 (DF_PALETTE_DATA, entry); + } + + /* ENABLE THE VIDEO PALETTE */ + /* Ensure that the video palette has an effect by routing video data */ + /* through the palette RAM and clearing the 'Bypass Both' bit. */ + + dcfg = READ_VID32 (DF_DISPLAY_CONFIG); + misc = READ_VID32 (DF_VID_MISC); + + dcfg |= DF_DCFG_GV_PAL_BYP; + misc &= ~DF_GAMMA_BYPASS_BOTH; + + WRITE_VID32 (DF_DISPLAY_CONFIG, dcfg); + WRITE_VID32 (DF_VID_MISC, misc); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_video_palette_entry + * + * This routine loads a single entry of the video hardware palette. + *--------------------------------------------------------------------------*/ + +int df_set_video_palette_entry (unsigned long index, unsigned long palette) +{ + unsigned long misc, dcfg; + + if (index > 0xFF) + return CIM_STATUS_INVALIDPARAMS; + + /* SET A SINGLE ENTRY */ + + WRITE_VID32 (DF_PALETTE_ADDRESS, index); + WRITE_VID32 (DF_PALETTE_DATA, palette); + + /* ENABLE THE VIDEO PALETTE */ + /* Ensure that the video palette has an effect by routing video data */ + /* through the palette RAM and clearing the 'Bypass Both' bit. */ + + dcfg = READ_VID32 (DF_DISPLAY_CONFIG); + misc = READ_VID32 (DF_VID_MISC); + + dcfg |= DF_DCFG_GV_PAL_BYP; + misc &= ~DF_GAMMA_BYPASS_BOTH; + + WRITE_VID32 (DF_DISPLAY_CONFIG, dcfg); + WRITE_VID32 (DF_VID_MISC, misc); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_configure_video_cursor_color_key + * + * This routine configures the hardware video cursor color key mechanism. + *--------------------------------------------------------------------------*/ + +int df_configure_video_cursor_color_key (DF_VIDEO_CURSOR_PARAMS *cursor_color_key) +{ + unsigned long key; + + if (cursor_color_key->select_color2 >= 24) + return CIM_STATUS_INVALIDPARAMS; + + key = READ_VID32 (DF_CURSOR_COLOR_KEY) & DF_CURSOR_COLOR_KEY_ENABLE; + key = key | (cursor_color_key->key & 0xFFFFFF) | (cursor_color_key->select_color2 << 24); + + WRITE_VID32 (DF_CURSOR_COLOR_KEY, key); + WRITE_VID32 (DF_CURSOR_COLOR_MASK, (cursor_color_key->mask & 0xFFFFFF)); + WRITE_VID32 (DF_CURSOR_COLOR_1, (cursor_color_key->color1 & 0xFFFFFF)); + WRITE_VID32 (DF_CURSOR_COLOR_2, (cursor_color_key->color2 & 0xFFFFFF)); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_video_cursor_color_key_enable + * + * This routine enables or disables the video cursor color key. + *--------------------------------------------------------------------------*/ + +int df_set_video_cursor_color_key_enable (int enable) +{ + unsigned long temp = READ_VID32 (DF_CURSOR_COLOR_KEY); + + if (enable) temp |= DF_CURSOR_COLOR_KEY_ENABLE; + else temp &= ~DF_CURSOR_COLOR_KEY_ENABLE; + + WRITE_VID32 (DF_CURSOR_COLOR_KEY, temp); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_configure_alpha_window + * + * This routine configures one of the three hardware alpha regions. + *--------------------------------------------------------------------------*/ + +int df_configure_alpha_window (int window, DF_ALPHA_REGION_PARAMS *alpha_data) +{ + unsigned long vsyncend_even, vtotal_even, vactive_even; + unsigned long hsyncend, htotal, hactive; + unsigned long vsyncend, vtotal, vactive; + unsigned long alpha_ctl, pos; + unsigned long hadjust, vadjust; + unsigned long y, height; + unsigned long xstart, xend; + unsigned long ystart, yend; + unsigned long x_copy, width_copy; + unsigned long y_copy, height_copy; + unsigned long scale, src, misc; + unsigned long gfxscale, fbactive; + unsigned long color; + + if (window > 2) + return CIM_STATUS_INVALIDPARAMS; + + hsyncend = ((READ_REG32 (DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1; + vsyncend = ((READ_REG32 (DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1; + htotal = ((READ_REG32 (DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + vtotal = ((READ_REG32 (DC3_V_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + hactive = (READ_REG32 (DC3_H_ACTIVE_TIMING) & 0xFFF) + 1; + vactive = (READ_REG32 (DC3_V_ACTIVE_TIMING) & 0xFFF) + 1; + + /* APPLY THE GRAPHICS SCALE */ + + width_copy = alpha_data->width; + height_copy = alpha_data->height; + x_copy = alpha_data->x; + y_copy = alpha_data->y; + + misc = READ_VID32 (DF_VID_MISC); + if (misc & DF_USER_IMPLICIT_SCALING) + { + gfxscale = READ_REG32 (DC3_GFX_SCALE); + fbactive = READ_REG32 (DC3_FB_ACTIVE); + + /* REVERSE ENGINEER THE SCALE FACTOR */ + + scale = gfxscale & 0xFFFF; + src = (fbactive >> 16) + 1; + if (scale != 0x4000) + { + width_copy = width_copy * (((0x4000 * src) / scale) + 1); + width_copy /= src; + x_copy = x_copy * (((0x4000 * src) / scale) + 1); + x_copy /= src; + } + + scale = gfxscale >> 16; + src = (fbactive & 0xFFFF) + 1; + if (scale != 0x4000) + { + height_copy = height_copy * (((0x4000 * src) / scale) + 1); + height_copy /= src; + y_copy = y_copy * (((0x4000 * src) / scale) + 1); + y_copy /= src; + } + } + + /* SET PRIORITY */ + /* Priority is the only alpha parameter that is not in a register that */ + /* can be indexed based on the alpha window number. */ + + pos = 16 + (window << 1); + alpha_ctl = READ_VID32 (DF_VID_ALPHA_CONTROL) & ~(3L << pos); + alpha_ctl |= (alpha_data->priority & 3) << pos; + WRITE_VID32 (DF_VID_ALPHA_CONTROL, alpha_ctl); + + /* HANDLE INTERLACED MODES */ + + if (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN) + { + vsyncend_even = ((READ_REG32 (DC3_V_SYNC_EVEN) >> 16) & 0xFFF) + 1; + vtotal_even = ((READ_REG32 (DC3_V_ACTIVE_EVEN) >> 16) & 0xFFF) + 1; + vactive_even = (READ_REG32 (DC3_V_ACTIVE_EVEN) & 0xFFF) + 1; + + y = y_copy >> 1; + + /* SET Y POSITION FOR ODD FIELD */ + + height = (height_copy + 1) >> 1; + vadjust = vtotal_even - vsyncend_even + 1; + + ystart = y + vadjust; + yend = y + vadjust + height; + + if (yend > (vactive + vadjust)) + yend = vactive + vadjust; + + WRITE_VID32 ((DF_ALPHA_YPOS_1 + (window << 5)), (ystart | (yend << 16))); + + /* SET Y POSITION FOR EVEN FIELD */ + + height = height_copy >> 1; + vadjust = vtotal - vsyncend + 1; + + ystart = y + vadjust; + yend = y + vadjust + height; + + if (yend > (vactive_even + vadjust)) + yend = vactive_even + vadjust; + + WRITE_VID32 ((DF_VID_ALPHA_Y_EVEN_1 + (window << 3)), (ystart | (yend << 16))); + } + else + { + y = y_copy; + height = height_copy; + vadjust = vtotal - vsyncend + 1; + + ystart = y + vadjust; + yend = y + vadjust + height; + + if (yend > (vactive + vadjust)) + yend = vactive + vadjust; + + WRITE_VID32 ((DF_ALPHA_YPOS_1 + (window << 5)), (ystart | (yend << 16))); + } + + /* SET ALPHA X POSITION */ + /* The x position is the same for both the odd and even fields. */ + + hadjust = htotal - hsyncend - 2; + + xstart = x_copy + hadjust; + xend = x_copy + hadjust + width_copy; + + if (xend > (hactive + hadjust)) + xend = hactive + hadjust; + + WRITE_VID32 ((DF_ALPHA_XPOS_1 + (window << 5)), (xstart | (xend << 16))); + + /* SET COLOR REGISTER */ + + color = alpha_data->color & 0xFFFFFF; + if (alpha_data->flags & DF_ALPHAFLAG_COLORENABLED) + color |= DF_ALPHA_COLOR_ENABLE; + + WRITE_VID32 ((DF_ALPHA_COLOR_1 + (window << 5)), color); + + /* SET ALPHA VALUE, DELTA AND PER PIXEL */ + + alpha_ctl = READ_VID32 (DF_ALPHA_CONTROL_1 + (window << 5)) & DF_ACTRL_WIN_ENABLE; + alpha_ctl |= (alpha_data->alpha_value & 0xFF) | DF_ACTRL_LOAD_ALPHA | + (((unsigned long)alpha_data->delta & 0xFF) << 8); + if (alpha_data->flags & DF_ALPHAFLAG_PERPIXELENABLED) + alpha_ctl |= DF_ACTRL_PERPIXEL_EN; + + WRITE_VID32 ((DF_ALPHA_CONTROL_1 + (window << 5)), alpha_ctl); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_alpha_window_enable + * + * This routine enables or disables one of the three hardware alpha regions. + *--------------------------------------------------------------------------*/ + +int df_set_alpha_window_enable (int window, int enable) +{ + unsigned long alpha_ctl; + + if (window > 2) + return CIM_STATUS_INVALIDPARAMS; + + alpha_ctl = READ_VID32 (DF_ALPHA_CONTROL_1 + (window << 5)); + if (enable) alpha_ctl |= DF_ACTRL_WIN_ENABLE; + else alpha_ctl &= ~DF_ACTRL_WIN_ENABLE; + WRITE_VID32 ((DF_ALPHA_CONTROL_1 + (window << 5)), alpha_ctl); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_no_ck_outside_alpha + * + * This function affects how color/chroma keying is performed inside the video + * window. + * + * If enable is 1, color/chroma key comparison is performed only inside + * the enabled alpha windows. Outside the enabled alpha windows, video + * is displayed if color keying is enabled, or graphics is displayed if + * chroma keying is enabled. + * If enable is 0, color/chroma key comparison is performed inside the + * entire video window. + *--------------------------------------------------------------------------*/ + +int df_set_no_ck_outside_alpha (int enable) +{ + unsigned long value; + + value = READ_VID32 (DF_VID_ALPHA_CONTROL); + if (enable) value |= DF_NO_CK_OUTSIDE_ALPHA; + else value &= ~DF_NO_CK_OUTSIDE_ALPHA; + WRITE_VID32 (DF_VID_ALPHA_CONTROL, value); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_video_request + * + * This routine sets the horizontal (pixel) and vertical (line) video request + * values. + *--------------------------------------------------------------------------*/ + +int df_set_video_request (unsigned long x, unsigned long y) +{ + unsigned long htotal, hsyncend; + unsigned long vtotal, vsyncend; + + hsyncend = ((READ_REG32 (DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1; + vsyncend = ((READ_REG32 (DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1; + htotal = ((READ_REG32 (DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + vtotal = ((READ_REG32 (DC3_V_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + + /* SET DISPLAY FILTER VIDEO REQUEST */ + + x += htotal - hsyncend - 2; + y += vtotal - vsyncend + 1; + + if (x >= 0x1000 || y >= 0x800) + return CIM_STATUS_INVALIDPARAMS; + + WRITE_VID32(DF_VIDEO_REQUEST, (y | (x << 16))); + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_output_color_space + * + * This routine sets the color space used when combining graphics and video. + *--------------------------------------------------------------------------*/ + +int df_set_output_color_space (int color_space) +{ + unsigned long alpha_ctl; + + alpha_ctl = READ_VID32 (DF_VID_ALPHA_CONTROL); + + alpha_ctl &= ~(DF_CSC_GRAPHICS_RGB_TO_YUV | DF_CSC_VIDEO_YUV_TO_RGB | + DF_HD_GRAPHICS | DF_YUV_CSC_EN | DF_ALPHA_DRGB); + + /* OUTPUT IS RGB */ + /* Enable YUV->RGB CSC if necessary and enable alpha output if */ + /* requested. */ + + if (color_space == DF_OUTPUT_RGB || color_space == DF_OUTPUT_ARGB) + { + if (!(alpha_ctl & DF_VIDEO_INPUT_IS_RGB)) + alpha_ctl |= DF_CSC_VIDEO_YUV_TO_RGB; + + if (color_space == DF_OUTPUT_ARGB) + alpha_ctl |= DF_ALPHA_DRGB; + } + + /* OUTPUT IS YUV */ + /* Enable YUV->YUV CSC if necessary and enable RGB->YUV CSC. */ + + else if (color_space == DF_OUTPUT_SDTV || color_space == DF_OUTPUT_HDTV) + { + alpha_ctl |= DF_CSC_GRAPHICS_RGB_TO_YUV; + + if ( ((alpha_ctl & DF_HD_VIDEO) && color_space == DF_OUTPUT_SDTV) || + (!(alpha_ctl & DF_HD_VIDEO) && color_space == DF_OUTPUT_HDTV)) + { + alpha_ctl |= DF_YUV_CSC_EN; + } + + if (color_space == DF_OUTPUT_HDTV) + alpha_ctl |= DF_HD_GRAPHICS; + } + else + return CIM_STATUS_INVALIDPARAMS; + + WRITE_VID32 (DF_VID_ALPHA_CONTROL, alpha_ctl); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_set_output_path + * + * This routine changes the current output path in the display filter. + *--------------------------------------------------------------------------*/ + +int df_set_output_path (int format) +{ + unsigned long panel_tim2, panel_pm; + unsigned long output = 0; + Q_WORD msr_value; + + msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &msr_value); + msr_value.low &= ~(DF_SIMULTANEOUS_CRT_FP | DF_CONFIG_OUTPUT_MASK); + panel_tim2 = READ_VID32 (DF_VIDEO_PANEL_TIM2); + panel_pm = READ_VID32 (DF_POWER_MANAGEMENT); + + if (format == DF_DISPLAY_CRT) + { + /* SiBZ #4188 */ + /* When CRT output is selected, the DF drives the DISP_EN signal */ + /* with the CRT display enable. As a consequence, systems that */ + /* wire the DISP_EN signal to the TFT backlight control will not */ + /* be able to set CRT-only output without leaving the backlight */ + /* enabled. To workaround this issue, we are setting simultaneous */ + /* TFT/CRT and disabling the TFT logic. The only caveat to this */ + /* is that some TFT pins are shared with VIP 601 pins. VIP 601 */ + /* will thus not work when in this pseudo-CRT mode. To address */ + /* THAT issue, normal CRT mode sets (in cim_vg.c) will set CRT */ + /* as the DF output format. This will allow VIP 601 on CRT-only */ + /* systems without a TFT attached. */ + + panel_pm &= ~DF_PM_PANEL_ON; + panel_tim2 |= DF_PMTIM2_TFT_PASSHTHROUGH; + output = DF_OUTPUT_PANEL | DF_SIMULTANEOUS_CRT_FP; + } + else if (format == DF_DISPLAY_FP || format == DF_DISPLAY_CRT_FP) + { + panel_pm |= DF_PM_PANEL_ON; + panel_tim2 &= ~DF_PMTIM2_TFT_PASSHTHROUGH; + + if (format == DF_DISPLAY_FP) + output = DF_OUTPUT_PANEL; + else if (format == DF_DISPLAY_CRT_FP) + output = DF_OUTPUT_PANEL | DF_SIMULTANEOUS_CRT_FP; + } + else + { + switch (format) + { + case DF_DISPLAY_VOP: output = DF_OUTPUT_VOP; break; + case DF_DISPLAY_DRGB: output = DF_OUTPUT_DRGB; break; + case DF_DISPLAY_CRT_DRGB: output = DF_OUTPUT_DRGB | DF_SIMULTANEOUS_CRT_FP; break; + default: + return CIM_STATUS_INVALIDPARAMS; + } + } + msr_value.low |= output; + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &msr_value); + WRITE_VID32 (DF_VIDEO_PANEL_TIM2, panel_tim2); + WRITE_VID32 (DF_POWER_MANAGEMENT, panel_pm); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_test_video_flip_status + * + * This routine tests if a new video offset has been latched. + *--------------------------------------------------------------------------*/ + +unsigned long df_test_video_flip_status (void) +{ + return (READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VFLIP); +} + +/*--------------------------------------------------------------------------- + * df_save_state + * + * This routine saves all persistent DF state information. + *---------------------------------------------------------------------------*/ + +int df_save_state (DF_SAVE_RESTORE *df_state) +{ + unsigned long i; + + /* READ ALL DF REGISTERS */ + + df_state->vcfg = READ_VID32 (DF_VIDEO_CONFIG); + df_state->dcfg = READ_VID32 (DF_DISPLAY_CONFIG); + df_state->video_x = READ_VID32 (DF_VIDEO_X_POS); + df_state->video_y = READ_VID32 (DF_VIDEO_Y_POS); + df_state->video_scaler = READ_VID32 (DF_VIDEO_SCALER); + df_state->video_color_key = READ_VID32 (DF_VIDEO_COLOR_KEY); + df_state->video_color_mask = READ_VID32 (DF_VIDEO_COLOR_MASK); + df_state->sat_limit = READ_VID32 (DF_SATURATION_LIMIT); + df_state->vid_misc = READ_VID32 (DF_VID_MISC); + df_state->video_yscale = READ_VID32 (DF_VIDEO_YSCALE); + df_state->video_xscale = READ_VID32 (DF_VIDEO_XSCALE); + df_state->vid_alpha_control = READ_VID32 (DF_VID_ALPHA_CONTROL); + df_state->cursor_key = READ_VID32 (DF_CURSOR_COLOR_KEY); + df_state->cursor_mask = READ_VID32 (DF_CURSOR_COLOR_MASK); + df_state->cursor_color1 = READ_VID32 (DF_CURSOR_COLOR_1); + df_state->cursor_color2 = READ_VID32 (DF_CURSOR_COLOR_2); + df_state->alpha_xpos1 = READ_VID32 (DF_ALPHA_XPOS_1); + df_state->alpha_ypos1 = READ_VID32 (DF_ALPHA_YPOS_1); + df_state->alpha_color1 = READ_VID32 (DF_ALPHA_COLOR_1); + df_state->alpha_control1 = READ_VID32 (DF_ALPHA_CONTROL_1); + df_state->alpha_xpos2 = READ_VID32 (DF_ALPHA_XPOS_2); + df_state->alpha_ypos2 = READ_VID32 (DF_ALPHA_YPOS_2); + df_state->alpha_color2 = READ_VID32 (DF_ALPHA_COLOR_2); + df_state->alpha_control2 = READ_VID32 (DF_ALPHA_CONTROL_2); + df_state->alpha_xpos3 = READ_VID32 (DF_ALPHA_XPOS_3); + df_state->alpha_ypos3 = READ_VID32 (DF_ALPHA_YPOS_3); + df_state->alpha_color3 = READ_VID32 (DF_ALPHA_COLOR_3); + df_state->alpha_control3 = READ_VID32 (DF_ALPHA_CONTROL_3); + df_state->vid_request = READ_VID32 (DF_VIDEO_REQUEST); + df_state->vid_ypos_even = READ_VID32 (DF_VID_YPOS_EVEN); + df_state->alpha_ypos_even1 = READ_VID32 (DF_VID_ALPHA_Y_EVEN_1); + df_state->alpha_ypos_even2 = READ_VID32 (DF_VID_ALPHA_Y_EVEN_2); + df_state->alpha_ypos_even3 = READ_VID32 (DF_VID_ALPHA_Y_EVEN_3); + df_state->panel_tim1 = READ_VID32 (DF_VIDEO_PANEL_TIM1); + df_state->panel_tim2 = READ_VID32 (DF_VIDEO_PANEL_TIM2); + df_state->panel_pm = READ_VID32 (DF_POWER_MANAGEMENT); + df_state->panel_dither = READ_VID32 (DF_DITHER_CONTROL); + + /* READ DF PALETTE */ + + WRITE_VID32 (DF_PALETTE_ADDRESS, 0); + for (i = 0; i < 256; i++) + df_state->palette[i] = READ_VID32 (DF_PALETTE_DATA); + + /* READ FILTER COEFFICIENTS */ + + for (i = 0; i < 512; i++) + df_state->coefficients[i] = READ_VID32 (DF_COEFFICIENT_BASE + (i << 2)); + + /* READ ALL DF MSRS */ + + msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CAP, &(df_state->msr_cap)); + msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &(df_state->msr_config)); + msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_SMI, &(df_state->msr_smi)); + msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_ERROR, &(df_state->msr_error)); + msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_PM, &(df_state->msr_pm)); + msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_DIAG, &(df_state->msr_diag)); + msr_read64 (MSR_DEVICE_GEODELX_DF, DF_MBD_MSR_DIAG_DF, &(df_state->msr_df_diag)); + msr_read64 (MSR_DEVICE_GEODELX_DF, DF_MSR_PAD_SEL, &(df_state->msr_pad_sel)); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_restore_state + * + * This routine restores all persistent DF state information. + *---------------------------------------------------------------------------*/ + +int df_restore_state (DF_SAVE_RESTORE *df_state) +{ + unsigned long i; + + /* CLEAR VCFG AND DCFG */ + + WRITE_VID32 (DF_VIDEO_CONFIG, 0); + WRITE_VID32 (DF_DISPLAY_CONFIG, 0); + + /* RESTORE DF MSRS */ + + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CAP, &(df_state->msr_cap)); + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &(df_state->msr_config)); + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_SMI, &(df_state->msr_smi)); + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_ERROR, &(df_state->msr_error)); + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_PM, &(df_state->msr_pm)); + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_DIAG, &(df_state->msr_diag)); + msr_write64 (MSR_DEVICE_GEODELX_DF, DF_MBD_MSR_DIAG_DF, &(df_state->msr_df_diag)); + msr_write64 (MSR_DEVICE_GEODELX_DF, DF_MSR_PAD_SEL, &(df_state->msr_pad_sel)); + + /* RESTORE ALL DF REGISTERS */ + + WRITE_VID32 (DF_VIDEO_X_POS, df_state->video_x); + WRITE_VID32 (DF_VIDEO_Y_POS, df_state->video_y); + WRITE_VID32 (DF_VIDEO_SCALER, df_state->video_scaler); + WRITE_VID32 (DF_VIDEO_COLOR_KEY, df_state->video_color_key); + WRITE_VID32 (DF_VIDEO_COLOR_MASK, df_state->video_color_mask); + WRITE_VID32 (DF_SATURATION_LIMIT, df_state->sat_limit); + WRITE_VID32 (DF_VID_MISC, df_state->vid_misc); + WRITE_VID32 (DF_VIDEO_YSCALE, df_state->video_yscale); + WRITE_VID32 (DF_VIDEO_XSCALE, df_state->video_xscale); + WRITE_VID32 (DF_VID_ALPHA_CONTROL, df_state->vid_alpha_control); + WRITE_VID32 (DF_CURSOR_COLOR_KEY, df_state->cursor_key); + WRITE_VID32 (DF_CURSOR_COLOR_MASK, df_state->cursor_mask); + WRITE_VID32 (DF_CURSOR_COLOR_1, df_state->cursor_color1); + WRITE_VID32 (DF_CURSOR_COLOR_2, df_state->cursor_color2); + WRITE_VID32 (DF_ALPHA_XPOS_1, df_state->alpha_xpos1); + WRITE_VID32 (DF_ALPHA_YPOS_1, df_state->alpha_ypos1); + WRITE_VID32 (DF_ALPHA_COLOR_1, df_state->alpha_color1); + WRITE_VID32 (DF_ALPHA_CONTROL_1, df_state->alpha_control1); + WRITE_VID32 (DF_ALPHA_XPOS_2, df_state->alpha_xpos2); + WRITE_VID32 (DF_ALPHA_YPOS_2, df_state->alpha_ypos2); + WRITE_VID32 (DF_ALPHA_COLOR_2, df_state->alpha_color2); + WRITE_VID32 (DF_ALPHA_CONTROL_2, df_state->alpha_control1); + WRITE_VID32 (DF_ALPHA_XPOS_3, df_state->alpha_xpos3); + WRITE_VID32 (DF_ALPHA_YPOS_3, df_state->alpha_ypos3); + WRITE_VID32 (DF_ALPHA_COLOR_3, df_state->alpha_color3); + WRITE_VID32 (DF_ALPHA_CONTROL_3, df_state->alpha_control3); + WRITE_VID32 (DF_VIDEO_REQUEST, df_state->vid_request); + WRITE_VID32 (DF_VID_YPOS_EVEN, df_state->vid_ypos_even); + WRITE_VID32 (DF_VID_ALPHA_Y_EVEN_1, df_state->alpha_ypos_even1); + WRITE_VID32 (DF_VID_ALPHA_Y_EVEN_2, df_state->alpha_ypos_even2); + WRITE_VID32 (DF_VID_ALPHA_Y_EVEN_3, df_state->alpha_ypos_even3); + WRITE_VID32 (DF_VIDEO_PANEL_TIM1, df_state->panel_tim1); + WRITE_VID32 (DF_VIDEO_PANEL_TIM2, df_state->panel_tim2); + WRITE_VID32 (DF_POWER_MANAGEMENT, df_state->panel_pm); + WRITE_VID32 (DF_DITHER_CONTROL, df_state->panel_dither); + + /* RESTORE DF PALETTE */ + + WRITE_VID32 (DF_PALETTE_ADDRESS, 0); + for (i = 0; i < 256; i++) + WRITE_VID32 (DF_PALETTE_DATA, df_state->palette[i]); + + /* RESTORE FILTER COEFFICIENTS */ + + for (i = 0; i < 512; i++) + WRITE_VID32 (DF_COEFFICIENT_BASE + (i << 2), df_state->coefficients[i]); + + /* RESTORE DCFG AND VCFG */ + + WRITE_VID32 (DF_DISPLAY_CONFIG, df_state->dcfg); + WRITE_VID32 (DF_VIDEO_CONFIG, df_state->vcfg); + + return CIM_STATUS_OK; +} + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * CIMARRON DF READ ROUTINES + * These routines are included for use in diagnostics or when debugging. They + * can be optionally excluded from a project. + *+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ + +#if CIMARRON_INCLUDE_DF_READ_ROUTINES + +/*--------------------------------------------------------------------------- + * df_read_composite_crc + * + * This routine reads the CRC of the combination of graphics/video data. This + * CRC checks data immediately before the CRT DACs. + *---------------------------------------------------------------------------*/ + +unsigned long df_read_composite_crc (int crc_source) +{ + Q_WORD msr_value; + unsigned long crc; + unsigned long interlaced; + unsigned long line, field; + unsigned long timeout = 1000; + + if (!(READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_TGEN)) + return 0xFFFFFFFF; + + /* ENABLE 32-BIT CRCS */ + + msr_read64 (MSR_DEVICE_GEODELX_DF, DF_MBD_MSR_DIAG_DF, &msr_value); + msr_value.low |= DF_DIAG_32BIT_CRC; + msr_write64 (MSR_DEVICE_GEODELX_DF, DF_MBD_MSR_DIAG_DF, &msr_value); + + /* RESET THE CRC */ + + WRITE_VID32 (DF_VID_CRC, 0); + + /* WAIT FOR THE RESET TO BE LATCHED */ + + while ((READ_VID32 (DF_VID_CRC32) != 0x00000001) && timeout) + timeout--; + + /* WAIT FOR THE CORRECT FIELD */ + /* We use the VG line count and field indicator to determine when */ + /* to kick off a CRC. */ + + if (crc_source & DF_CRC_SOURCE_EVEN) field = 0; + else field = DC3_LNCNT_EVEN_FIELD; + + if ((interlaced = (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN))) + { + /* WAIT FOR THE BEGINNING OF THE FIELD (LINE 1-5) */ + /* Note that we wait for the field to be odd when CRCing the even */ + /* field and vice versa. This is because the CRC will not begin */ + /* until the following field. */ + + do + { + line = READ_REG32 (DC3_LINE_CNT_STATUS); + } while ((line & DC3_LNCNT_EVEN_FIELD) != field || + ((line & DC3_LNCNT_V_LINE_CNT) >> 16) < 10 || + ((line & DC3_LNCNT_V_LINE_CNT) >> 16) > 15); + } + else + { + /* NON-INTERLACED - EVEN FIELD CRCS ARE INVALID */ + + if (crc_source & DF_CRC_SOURCE_EVEN) + return 0xFFFFFFFF; + } + + /* ENABLE THE CRC */ + + WRITE_VID32 (DF_VID_CRC, 1); + + /* WAIT FOR THE CRC TO BE COMPLETED */ + + while (!(READ_VID32 (DF_VID_CRC) & 4)) + ; + + crc = READ_VID32 (DF_VID_CRC32); + + return crc; +} + +/*--------------------------------------------------------------------------- + * df_read_composite_window_crc + * + * This routine reads the CRC of a rectangular subsection of the combination + * of graphics/video data. + *---------------------------------------------------------------------------*/ + +unsigned long df_read_composite_window_crc (unsigned long x, unsigned long y, + unsigned long width, unsigned long height, int source) +{ + Q_WORD msr_value; + unsigned long interlaced; + unsigned long line, field; + unsigned long crc = 0; + unsigned long hsyncend, htotal, hsyncstart; + unsigned long vsyncend, vtotal, vsyncstart; + unsigned long hblankstart, hactive; + unsigned long vblankstart, vactive; + + hsyncend = ((READ_REG32 (DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1; + htotal = ((READ_REG32 (DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + hsyncstart = (READ_REG32 (DC3_H_SYNC_TIMING) & 0xFFF) + 1; + hactive = (READ_REG32 (DC3_H_ACTIVE_TIMING) & 0xFFF) + 1; + hblankstart = (READ_REG32 (DC3_H_BLANK_TIMING) & 0xFFF) + 1; + if ((interlaced = (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN)) && + !(source & DF_CRC_SOURCE_EVEN)) + { + vsyncend = ((READ_REG32 (DC3_V_SYNC_EVEN) >> 16) & 0xFFF) + 1; + vtotal = ((READ_REG32 (DC3_V_ACTIVE_EVEN) >> 16) & 0xFFF) + 1; + vsyncstart = (READ_REG32 (DC3_V_SYNC_EVEN) & 0xFFF) + 1; + vactive = (READ_REG32 (DC3_V_ACTIVE_EVEN) & 0xFFF) + 1; + vblankstart = (READ_REG32 (DC3_V_BLANK_EVEN) & 0xFFF) + 1; + } + else + { + vsyncend = ((READ_REG32 (DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1; + vtotal = ((READ_REG32 (DC3_V_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + vsyncstart = (READ_REG32 (DC3_V_SYNC_TIMING) & 0xFFF) + 1; + vactive = (READ_REG32 (DC3_V_ACTIVE_TIMING) & 0xFFF) + 1; + vblankstart = (READ_REG32 (DC3_V_BLANK_TIMING) & 0xFFF) + 1; + } + + /* TIMINGS MUST BE ACTIVE */ + + if (!(READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_TGEN)) + return 0xFFFFFFFF; + + /* DISABLE GLCP ACTIONS */ + + msr_value.low = 0; + msr_value.high = 0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DIAGCTL, &msr_value); + + /* ENABLE HW CLOCK GATING AND SET GLCP CLOCK TO DOT CLOCK */ + + msr_value.low = 5; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, MSR_GEODELINK_PM, &msr_value); + msr_value.low = 0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DBGCLKCTL, &msr_value); + msr_value.low = 3; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DBGCLKCTL, &msr_value); + + /* USE H4 FUNCTION A FOR HSYNC AND H4 FUNCTION B FOR NOT HSYNC */ + /* HSYNC is bit 30 for the DF */ + + msr_value.high = 0x00000001; + msr_value.low = 0xE0000FF0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_H0CTL + 4, &msr_value); + + /* USE H3 FUNCTION A FOR VSYNC AND H3 FUNCTION B FOR NOT VSYNC */ + /* VSYNC is bit 54 for VG and bit 29 for DF */ + + msr_value.high = 0x00000000; + msr_value.low = 0x001D55AA; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_H0CTL + 3, &msr_value); + + /* M4 (XSTATE = 00 AND VSYNC HIGH) */ + /* Goto state 01 */ + /* Note: VSync = H3A */ + + msr_value.high = 0x00000001; + msr_value.low = 0x000000A0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETM0CTL + 4, &msr_value); + + /* N0 (XSTATE = 01 AND VSYNC LOW) */ + /* Goto state 02 */ + /* Note: VSync low = H3B */ + + msr_value.high = 0x00040000; + msr_value.low = 0x000000C0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL, &msr_value); + + /* M5 (XSTATE = 10 AND VSYNC HIGH) */ + /* Goto state 11 */ + + msr_value.high = 0x00000001; + msr_value.low = 0x00000120; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETM0CTL + 5, &msr_value); + + /* N1 (XSTATE = 10 and HSYNC LOW) */ + /* Increment H. Counter */ + /* Note: HSync = H4 */ + + msr_value.high = 0x00080000; + msr_value.low = 0x00000120; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL + 1, &msr_value); + + /* M0 (XSTATE = 10 and H. COUNTER == LIMIT) */ + /* Clear H. Counter and increment V. Counter */ + + msr_value.high = 0x00000000; + msr_value.low = 0x00000122; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETM0CTL, &msr_value); + + /* N4 (XSTATE = 10 && CMP0 <= H. COUNTER <= CMP1 && CMP2 <= V. COUNTER <= CMP3) */ + /* CRC into REGB */ + + msr_value.high = 0x00000000; + msr_value.low = 0x10C20120; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL + 4, &msr_value); + + /* COMPARATOR 0 VALUE */ + /* Value = xstart + (htotal - hsync_end) - 1 */ + /* The value will be adjusted for a border if necessary */ + + msr_value.low = x + htotal - hsyncend - 1; + if (READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_DCEN) + msr_value.low -= hblankstart - hactive; + msr_value.low--; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPVAL0, &msr_value); + + /* COMPARATOR 1 VALUE */ + /* Value = xstart + (htotal - hsync_end - 1) - 1 + width */ + + msr_value.low += width - 1; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPVAL0 + 2, &msr_value); + + /* COMPARATOR 2 VALUE */ + /* Value = ystart + vtotal - vsyncend */ + + msr_value.low = (y + vtotal - vsyncend) << 16; + if (READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_DCEN) + msr_value.low -= (vblankstart - vactive) << 16; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPVAL0 + 4, &msr_value); + + /* COMPARATOR 3 VALUE */ + /* Value = ystart + vtotal - vsyncend + height - 1 */ + + msr_value.low += (height - 1) << 16; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPVAL0 + 6, &msr_value); + + /* COMPARATOR MASKS */ + /* Comparators 0 and 1 refer to lower 16 bits of RegB */ + + msr_value.low = 0x0000FFFF; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPMASK0, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPMASK0 + 2, &msr_value); + + /* Comparators 2 and 3 refer to upper 16 bits of RegB */ + + msr_value.low = 0xFFFF0000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPMASK0 + 4, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPMASK0 + 6, &msr_value); + + /* SET REGB MASK */ + /* We set the mask such that all only 24 bits of data are CRCed */ + + msr_value.low = 0x00FFFFFF; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_REGBMASK, &msr_value); + + /* SET REGA LIMITS */ + /* Lower counter uses htotal - sync_time - 1. */ + /* Upper counter is 0xFFFF to prevent rollover. */ + + msr_value.low = 0xFFFF0000 | (htotal - (hsyncend - hsyncstart) - 1); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_REGAVAL, &msr_value); + + /* ACTIONS */ + + /* STATE 00->01 (SET 4M) */ + + msr_value.low = 0x000C0000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 14, &msr_value); + + /* STATE 01->10 (SET 0N) */ + + msr_value.low = 0x0000000A; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 15, &msr_value); + + /* STATE 10->11 (SET 5M) */ + + msr_value.low = 0x00C00000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 16, &msr_value); + + /* CLEAR REGA WHEN TRANSITIONING TO STATE 10 */ + /* Do not clear RegB as the initial value must be 0x00000001 */ + + msr_value.low = 0x0000000A; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0, &msr_value); + + /* REGISTER ACTION 1 */ + /* CRC into RegB if cmp0 <= h.counter <= cmp1 && cmp2 <= v. counter < cmp3 && 7 xstate = 10 8 */ + /* Increment h.counter if xstate = 10 and HSync is low. */ + + msr_value.low = 0x000A00A0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 1, &msr_value); + + /* REGISTER ACTION 2 */ + /* Increment V. Counter in REGA */ + + msr_value.low = 0x0000000C; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 2, &msr_value); + + /* SET REGB TO 0x00000001 */ + + msr_value.low = 0x00000001; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_REGB, &msr_value); + + /* SET XSTATE TO 0 */ + + msr_value.low = 0x00000000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_XSTATE, &msr_value); + + /* CLEAR ALL OTHER ACTIONS */ + /* This prevents side-effects from previous accesses to the GLCP */ + /* debug logic. */ + + msr_value.low = 0x00000000; + msr_value.high = 0x00000000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 3, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 4, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 5, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 6, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 7, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 8, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 9, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 10, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 11, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 12, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 13, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 17, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 18, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 19, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 20, &msr_value); + + /* WAIT FOR THE CORRECT FIELD */ + /* We use the VG line count and field indicator to determine when */ + /* to kick off a CRC. */ + + if (source & DF_CRC_SOURCE_EVEN) field = 0; + else field = DC3_LNCNT_EVEN_FIELD; + + if (interlaced) + { + /* WAIT FOR THE BEGINNING OF THE FIELD (LINE 1-5) */ + /* Note that we wait for the field to be odd when CRCing the even */ + /* field and vice versa. This is because the CRC will not begin */ + /* until the following field. */ + + do + { + line = READ_REG32 (DC3_LINE_CNT_STATUS); + } while ((line & DC3_LNCNT_EVEN_FIELD) != field || + ((line & DC3_LNCNT_V_LINE_CNT) >> 16) < 1 || + ((line & DC3_LNCNT_V_LINE_CNT) >> 16) > 5); + } + else + { + /* NON-INTERLACED - EVEN FIELD CRCS ARE INVALID */ + + if (source & DF_CRC_SOURCE_EVEN) + return 0xFFFFFFFF; + } + + /* CONFIGURE DISPLAY FILTER TO LOAD DATA ONTO LOWER 32-BITS */ + + msr_value.high = 0; + msr_value.low = 0x0000800B; + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_DIAG, &msr_value); + + /* CONFIGURE DIAG CONTROL */ + /* Set RegA action1 to increment lower 16 bits and clear at limit. (5) */ + /* Set RegA action2 to increment upper 16 bits. (6) */ + /* Set RegB action1 to CRC32 (1) */ + /* Set all comparators to REGA override (0,1 lower mbus, 2,3 upper mbus) */ + /* Enable all actions */ + + msr_value.low = 0x80EA20A0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DIAGCTL, &msr_value); + + /* DELAY TWO FRAMES */ + + while (READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VNA); + while (!(READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VNA)); + while (READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VNA); + while (!(READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VNA)); + while (READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VNA); + + /* VERIFY THAT XSTATE = 11 */ + + msr_read64 (MSR_DEVICE_GEODELX_GLCP, GLCP_XSTATE, &msr_value); + if ((msr_value.low & 3) == 3) + { + msr_read64 (MSR_DEVICE_GEODELX_GLCP, GLCP_REGB, &msr_value); + + crc = msr_value.low; + } + + /* DISABLE DF DIAG BUS OUTPUTS */ + + msr_value.low = 0x00000000; + msr_value.high = 0x00000000; + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_DIAG, &msr_value); + + /* DISABLE GLCP ACTIONS */ + + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DIAGCTL, &msr_value); + + return crc; +} + +/*--------------------------------------------------------------------------- + * df_read_panel_crc + * + * This routine reads the CRC for a frame of data after the panel dithering + * logic. + *---------------------------------------------------------------------------*/ + +unsigned long df_read_panel_crc (void) +{ + Q_WORD msr_value; + unsigned long timeout = 1000; + + if (!(READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_TGEN)) + return 0xFFFFFFFF; + + /* ENABLE 32-BIT CRCS */ + + msr_read64 (MSR_DEVICE_GEODELX_DF, DF_MBD_MSR_DIAG_DF, &msr_value); + msr_value.low |= DF_DIAG_32BIT_CRC; + msr_write64 (MSR_DEVICE_GEODELX_DF, DF_MBD_MSR_DIAG_DF, &msr_value); + + /* RESET CRC */ + + WRITE_VID32 (DF_PANEL_CRC, 0); + + /* WAIT FOR THE RESET TO BE LATCHED */ + + while ((READ_VID32 (DF_PANEL_CRC32) != 0x00000001) && timeout) + timeout--; + + WRITE_VID32 (DF_PANEL_CRC, 1); + + /* WAIT FOR THE CRC TO BE COMPLETED */ + + while (!(READ_VID32 (DF_PANEL_CRC) & 4)) + ; + + return READ_VID32 (DF_PANEL_CRC32); +} + +/*--------------------------------------------------------------------------- + * df_get_video_enable + * + * This routine reads the enable status of the video overlay. + *---------------------------------------------------------------------------*/ + +int df_get_video_enable (int *enable, unsigned long *flags) +{ + *enable = 0; + *flags = 0; + if (READ_VID32 (DF_VIDEO_CONFIG) & DF_VCFG_VID_EN) + { + *enable = 1; + + /* CHECK FOR COLOR KEY DISABLED */ + /* Color keying can be completely disabled when video is enabled to */ + /* allow unhindered per-pixel alpha blending. As color keying is */ + /* always disabled when video is disabled, it is only possible to */ + /* test for this condition when video is enabled. */ + + if (!(READ_VID32 (DF_DISPLAY_CONFIG) & DF_DCFG_VG_CK) && + !(READ_REG32 (DC3_COLOR_KEY) & DC3_CLR_KEY_ENABLE)) + { + *flags = DF_ENABLEFLAG_NOCOLORKEY; + } + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_get_video_source_configuration + * + * This routine reads the current configuration of the source buffers for the + * video overlay. + *---------------------------------------------------------------------------*/ + +int df_get_video_source_configuration (DF_VIDEO_SOURCE_PARAMS *video_source_odd, + DF_VIDEO_SOURCE_PARAMS *video_source_even) +{ + unsigned long format, temp; + unsigned long size; + + /* READ VIDEO FORMAT */ + + temp = READ_VID32 (DF_VIDEO_CONFIG); + + format = (temp >> 2) & 3; + if (temp & DF_VCFG_4_2_0_MODE) + format |= 4; + else if (READ_VID32 (DF_VID_ALPHA_CONTROL) & DF_VIDEO_INPUT_IS_RGB) + format |= 8; + video_source_odd->video_format = format; + + /* CHECK IF SOURCE IS HD VIDEO */ + + if (READ_VID32 (DF_VID_ALPHA_CONTROL) & DF_HD_VIDEO) + video_source_odd->flags = DF_SOURCEFLAG_HDTVSOURCE; + else + video_source_odd->flags = 0; + + /* READ SCALING ALGORITHM */ + + if (READ_VID32 (DF_VID_MISC) & DF_USER_IMPLICIT_SCALING) + video_source_odd->flags |= DF_SOURCEFLAG_IMPLICITSCALING; + + /* READ VIDEO PITCH */ + + temp = READ_REG32 (DC3_VID_YUV_PITCH); + video_source_odd->y_pitch = (temp & 0xFFFF) << 3; + video_source_odd->uv_pitch = (temp >> 16) << 3; + + /* READ VIDEO SIZE */ + + temp = READ_VID32 (DF_VIDEO_CONFIG); + size = (temp >> 8) & 0xFF; + if (temp & DF_VCFG_LINE_SIZE_BIT8) size |= 0x100; + if (temp & DF_VCFG_LINE_SIZE_BIT9) size |= 0x200; + + video_source_odd->width = size << 1; + video_source_odd->height = READ_VID32 (DF_VIDEO_SCALER) & 0x7FF; + + /* READ VIDEO OFFSETS */ + + video_source_odd->y_offset = READ_REG32 (DC3_VID_Y_ST_OFFSET) & 0xFFFFFFF; + video_source_odd->u_offset = READ_REG32 (DC3_VID_U_ST_OFFSET) & 0xFFFFFFF; + video_source_odd->v_offset = READ_REG32 (DC3_VID_V_ST_OFFSET) & 0xFFFFFFF; + + if (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN) + { + video_source_even->y_offset = READ_REG32 (DC3_VID_EVEN_Y_ST_OFFSET) & 0xFFFFFFF; + video_source_even->u_offset = READ_REG32 (DC3_VID_EVEN_U_ST_OFFSET) & 0xFFFFFFF; + video_source_even->v_offset = READ_REG32 (DC3_VID_EVEN_V_ST_OFFSET) & 0xFFFFFFF; + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_get_video_position + * + * This routine reads the current position of the video overlay. + *---------------------------------------------------------------------------*/ + +int df_get_video_position (DF_VIDEO_POSITION *video_window) +{ + unsigned long xreg, yreg, dst_clip, clip; + unsigned long height; + unsigned long xend, yend; + unsigned long hsyncend, htotal; + unsigned long vsyncend, vtotal; + unsigned long hadjust, vadjust; + unsigned long misc, gfxscale; + unsigned long temp; + long xstart, ystart; + + video_window->flags = DF_POSFLAG_DIRECTCLIP; + + hsyncend = ((READ_REG32 (DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1; + htotal = ((READ_REG32 (DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + + /* ODD FIELD START COUNTS FROM THE EVEN FIELD TIMINGS */ + /* We assume that the even field y position is always programmed */ + /* to be just after the odd field. */ + + if (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN) + { + vsyncend = ((READ_REG32 (DC3_V_SYNC_EVEN) >> 16) & 0xFFF) + 1; + vtotal = ((READ_REG32 (DC3_V_ACTIVE_EVEN) >> 16) & 0xFFF) + 1; + } + else + { + vsyncend = ((READ_REG32 (DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1; + vtotal = ((READ_REG32 (DC3_V_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + } + + hadjust = htotal - hsyncend - 14; + vadjust = vtotal - vsyncend + 1; + + xreg = READ_VID32 (DF_VIDEO_X_POS); + yreg = READ_VID32 (DF_VIDEO_Y_POS); + + xstart = (xreg & 0xFFF) - hadjust; + ystart = (yreg & 0x7FF) - vadjust; + xend = ((xreg >> 16) & 0xFFF) - hadjust; + yend = ((yreg >> 16) & 0x7FF) - vadjust; + + height = yend - ystart; + + if (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN) + { + /* Y COORDINATE IS ACTUALLY 2X THE ODD FIELD START */ + + ystart <<= 1; + + /* CALCULATE THE EXACT VIDEO HEIGHT */ + /* The height of the video window is the sum of the */ + /* odd and even field heights. */ + + yreg = READ_VID32 (DF_VID_YPOS_EVEN); + height += ((yreg >> 16) & 0x7FF) - (yreg & 0x7FF); + } + + clip = ((READ_VID32 (DF_VIDEO_CONFIG) >> 16) & 0x1FF) << 2; + + /* ADJUST FOR CLIPPING VALUES THAT ARE NOT FOUR-PIXEL ALIGNED */ + + dst_clip = 0; + if (xstart < 0) + { + dst_clip += -xstart; + xstart = 0; + } + + /* REVERSE THE GRAPHICS SCALE */ + + misc = READ_VID32 (DF_VID_MISC); + if (misc & DF_USER_IMPLICIT_SCALING) + { + gfxscale = READ_REG32 (DC3_GFX_SCALE); + + if (gfxscale != 0x40004000) + { + temp = ystart + height; + temp = (temp * (gfxscale >> 16)) / 0x4000; + + xstart = (xstart * (gfxscale & 0xFFFF)) / 0x4000; + xend = (xend * (gfxscale & 0xFFFF)) / 0x4000; + ystart = (ystart * (gfxscale >> 16)) / 0x4000; + height = temp - ystart; + } + } + + video_window->left_clip = clip; + video_window->dst_clip = dst_clip; + video_window->x = xstart; + video_window->y = ystart; + video_window->width = xend - xstart; + video_window->height = height; + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_get_video_scale + * + * This routine reads the current scale values for video scaling. + *---------------------------------------------------------------------------*/ + +int df_get_video_scale (unsigned long *x_scale, unsigned long *y_scale) +{ + *x_scale = READ_VID32 (DF_VIDEO_XSCALE) & 0x000FFFFF; + *y_scale = READ_VID32 (DF_VIDEO_YSCALE) & 0x000FFFFF; + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_get_video_filter_coefficients + * + * This routine reads the coefficients for the video scaler/filter. + *---------------------------------------------------------------------------*/ + +int df_get_video_filter_coefficients (long taps[][4], int *phase256) +{ + unsigned long i, temp; + long coeff; + + if (READ_VID32 (DF_VIDEO_SCALER) & DF_SCALE_128_PHASES) + *phase256 = 0; + else + *phase256 = 1; + + for (i = 0; i < 256; i++) + { + temp = READ_VID32 (DF_COEFFICIENT_BASE + (i << 3)); + + /* TAP 0 */ + + coeff = temp & 0x7FFF; + if (temp & 0x8000) coeff = -coeff; + taps[i][0] = coeff; + + /* TAP 1 */ + + temp >>= 16; + coeff = temp & 0x7FFF; + if (temp & 0x8000) coeff = -coeff; + taps[i][1] = coeff; + + temp = READ_VID32 (DF_COEFFICIENT_BASE + (i << 3) + 4); + + /* TAP 2 */ + + coeff = temp & 0x7FFF; + if (temp & 0x8000) coeff = -coeff; + taps[i][2] = coeff; + + /* TAP 3 */ + + temp >>= 16; + coeff = temp & 0x7FFF; + if (temp & 0x8000) coeff = -coeff; + taps[i][3] = coeff; + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_get_video_color_key + * + * This routine reads the current settings for hardware color/chroma keying. + *---------------------------------------------------------------------------*/ + +int df_get_video_color_key (unsigned long *key, unsigned long *mask, int *graphics) +{ + unsigned long chroma = READ_VID32 (DF_DISPLAY_CONFIG) & DF_DCFG_VG_CK; + + if (chroma) + { + /* CHROMA KEY - READ KEY AND MASK FROM DF */ + + *graphics = 0; + *key = READ_VID32 (DF_VIDEO_COLOR_KEY) & 0xFFFFFF; + *mask = READ_VID32 (DF_VIDEO_COLOR_MASK) & 0xFFFFFF; + } + else + { + *graphics = 1; + + *key = READ_REG32 (DC3_COLOR_KEY) & 0xFFFFFF; + *mask = READ_REG32 (DC3_COLOR_MASK) & 0xFFFFFF; + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_get_video_palette_entry + * + * This routine returns a single palette entry. + *---------------------------------------------------------------------------*/ + +int df_get_video_palette_entry(unsigned long index, unsigned long *palette) +{ + if (index > 0xFF) + return CIM_STATUS_INVALIDPARAMS; + + /* READ A SINGLE ENTRY */ + + WRITE_VID32 (DF_PALETTE_ADDRESS, index); + *palette = READ_VID32 (DF_PALETTE_DATA); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_get_video_palette + * + * This routine returns the entire video palette. + *---------------------------------------------------------------------------*/ + +int df_get_video_palette (unsigned long *palette) +{ + unsigned long i; + + WRITE_VID32 (DF_PALETTE_ADDRESS, 0); + for (i = 0; i < 256; i++) + palette[i] = READ_VID32 (DF_PALETTE_DATA); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_get_video_cursor_color_key + * + * This routine returns the current configuration for the hardware video cursor + * color key. + *---------------------------------------------------------------------------*/ + +int df_get_video_cursor_color_key (DF_VIDEO_CURSOR_PARAMS *cursor_color_key) +{ + unsigned long key; + + cursor_color_key->flags = 0; + cursor_color_key->color1 = READ_VID32 (DF_CURSOR_COLOR_1) & 0xFFFFFF; + cursor_color_key->color2 = READ_VID32 (DF_CURSOR_COLOR_2) & 0xFFFFFF; + cursor_color_key->mask = READ_VID32 (DF_CURSOR_COLOR_MASK) & 0xFFFFFF; + + key = READ_VID32 (DF_CURSOR_COLOR_KEY); + cursor_color_key->key = key & 0xFFFFFF; + cursor_color_key->select_color2 = (key >> 24) & 0x1F; + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_get_video_cursor_color_key_enable + * + * This routine returns the current enable status of the hardware video cursor + * color key. + *---------------------------------------------------------------------------*/ + +int df_get_video_cursor_color_key_enable (void) +{ + if (READ_VID32 (DF_CURSOR_COLOR_KEY) & DF_CURSOR_COLOR_KEY_ENABLE) + return 1; + + return 0; +} + +/*--------------------------------------------------------------------------- + * df_get_alpha_window_configuration + * + * This routine reads the current configuration for one of the three hardware + * alpha regions. + *---------------------------------------------------------------------------*/ + +int df_get_alpha_window_configuration (int window, DF_ALPHA_REGION_PARAMS *alpha_data) +{ + unsigned long pos, color, alpha_ctl; + unsigned long hsyncend, htotal; + unsigned long vsyncend, vtotal; + unsigned long hadjust, vadjust; + unsigned long xreg, yreg; + unsigned long misc, gfxscale; + unsigned long temp; + char delta; + + if (window > 2) + return CIM_STATUS_INVALIDPARAMS; + + hsyncend = ((READ_REG32 (DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1; + htotal = ((READ_REG32 (DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + if (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN) + { + vtotal = ((READ_REG32 (DC3_V_ACTIVE_EVEN) >> 16) & 0xFFF) + 1; + vsyncend = ((READ_REG32 (DC3_V_SYNC_EVEN) >> 16) & 0xFFF) + 1; + } + else + { + vtotal = ((READ_REG32 (DC3_V_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + vsyncend = ((READ_REG32 (DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1; + } + + /* GET PRIORITY */ + + pos = 16 + (window << 1); + alpha_data->priority = (READ_VID32 (DF_VID_ALPHA_CONTROL) >> pos) & 3L; + + /* GET ALPHA WINDOW */ + + hadjust = htotal - hsyncend - 2; + vadjust = vtotal - vsyncend + 1; + + xreg = READ_VID32 (DF_ALPHA_XPOS_1 + (window << 5)); + yreg = READ_VID32 (DF_ALPHA_YPOS_1 + (window << 5)); + alpha_data->width = ((xreg >> 16) & 0xFFF) - (xreg & 0xFFF); + alpha_data->height = ((yreg >> 16) & 0x7FF) - (yreg & 0x7FF); + alpha_data->x = (xreg & 0xFFF) - hadjust; + alpha_data->y = (yreg & 0x7FF) - vadjust; + + /* REVERSE THE GRAPHICS SCALE */ + + misc = READ_VID32 (DF_VID_MISC); + if (misc & DF_USER_IMPLICIT_SCALING) + { + gfxscale = READ_REG32 (DC3_GFX_SCALE); + if (gfxscale != 0x40004000) + { + temp = alpha_data->y + alpha_data->height; + temp = (temp * (gfxscale >> 16)) / 0x4000; + + alpha_data->x = (alpha_data->x * (gfxscale & 0xFFFF)) / 0x4000; + alpha_data->width = (alpha_data->width * (gfxscale & 0xFFFF)) / 0x4000; + alpha_data->y = (alpha_data->y * (gfxscale >> 16)) / 0x4000; + alpha_data->height = temp - alpha_data->y; + } + } + + if (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN) + { + /* Y COORDINATE IS ACTUALLY 2X THE ODD FIELD START */ + + alpha_data->y <<= 1; + + /* CALCULATE THE EXACT VIDEO HEIGHT */ + /* The height of the video window is the sum of the */ + /* odd and even field heights. */ + + yreg = READ_VID32 (DF_VID_ALPHA_Y_EVEN_1 + (window << 3)); + alpha_data->height += ((yreg >> 16) & 0x7FF) - (yreg & 0x7FF); + } + + /* GET COLOR REGISTER */ + + color = READ_VID32 (DF_ALPHA_COLOR_1 + (window << 5)); + alpha_data->color = color & 0xFFFFFF; + if (color & DF_ALPHA_COLOR_ENABLE) + alpha_data->flags = DF_ALPHAFLAG_COLORENABLED; + else + alpha_data->flags = 0; + + /* GET ALPHA VALUE, DELTA AND PER PIXEL */ + + alpha_ctl = READ_VID32 (DF_ALPHA_CONTROL_1 + (window << 5)); + alpha_data->alpha_value = alpha_ctl & 0xFF; + if (alpha_ctl & DF_ACTRL_PERPIXEL_EN) + alpha_data->flags |= DF_ALPHAFLAG_PERPIXELENABLED; + + delta = (char)((alpha_ctl >> 8) & 0xFF); + alpha_data->delta = (long)delta; + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_get_alpha_window_enable + * + * This routine reads the current enable status of one of the three hardware + * alpha regions. + *---------------------------------------------------------------------------*/ + +int df_get_alpha_window_enable (int window) +{ + if (window > 2) + return 0; + + if (READ_VID32 (DF_ALPHA_CONTROL_1 + (window << 5)) & DF_ACTRL_WIN_ENABLE) + return 1; + + return 0; +} + +/*--------------------------------------------------------------------------- + * df_get_video_request + * + * This routine reads the horizontal (pixel) and vertical (line) video request + * values. + *--------------------------------------------------------------------------*/ + +int df_get_video_request (unsigned long *x, unsigned long *y) +{ + unsigned long request; + unsigned long hsyncend, htotal; + unsigned long vsyncend, vtotal; + + hsyncend = ((READ_REG32 (DC3_H_SYNC_TIMING) >> 16) & 0xFFF) + 1; + vsyncend = ((READ_REG32 (DC3_V_SYNC_TIMING) >> 16) & 0xFFF) + 1; + htotal = ((READ_REG32 (DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + vtotal = ((READ_REG32 (DC3_V_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + + request = READ_VID32 (DF_VIDEO_REQUEST); + *x = ((request >> 16) & 0xFFF) - (htotal - hsyncend - 2); + *y = (request & 0x7FF) - (vtotal - vsyncend + 1); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * df_get_output_color_space + * + * This routine sets the color space used when combining graphics and video. + *--------------------------------------------------------------------------*/ + +int df_get_output_color_space (int *color_space) +{ + unsigned long alpha_ctl; + + alpha_ctl = READ_VID32 (DF_VID_ALPHA_CONTROL); + + if ((alpha_ctl & DF_CSC_VIDEO_YUV_TO_RGB) || + !(alpha_ctl & DF_CSC_GRAPHICS_RGB_TO_YUV)) + { + if (alpha_ctl & DF_ALPHA_DRGB) + *color_space = DF_OUTPUT_ARGB; + else + *color_space = DF_OUTPUT_RGB; + } + else + { + *color_space = DF_OUTPUT_SDTV; + + if (alpha_ctl & DF_HD_GRAPHICS) + *color_space = DF_OUTPUT_HDTV; + } + + return CIM_STATUS_OK; +} + +#endif --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_gp.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_gp.c 2005-12-14 11:39:17.000000000 -0700 @@ -0,0 +1,3459 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron graphics processor routines. These routines program the graphics + * hardware using the graphics command buffer. + * */ + +/*---------------------*/ +/* CIMARRON GP GLOBALS */ +/*---------------------*/ + +CIMARRON_STATIC unsigned long gp3_bpp = 0; +CIMARRON_STATIC unsigned long gp3_ch3_bpp = 0; +CIMARRON_STATIC unsigned long gp3_pat_origin = 0; +CIMARRON_STATIC unsigned long gp3_buffer_lead = 0; +CIMARRON_STATIC unsigned long gp3_cmd_header; +CIMARRON_STATIC unsigned long gp3_cmd_top; +CIMARRON_STATIC unsigned long gp3_cmd_bottom; +CIMARRON_STATIC unsigned long gp3_cmd_current; +CIMARRON_STATIC unsigned long gp3_cmd_next; +CIMARRON_STATIC unsigned long gp3_blt_mode; +CIMARRON_STATIC unsigned long gp3_vec_mode; +CIMARRON_STATIC unsigned long gp3_raster_mode; +CIMARRON_STATIC unsigned long gp3_pix_shift; +CIMARRON_STATIC unsigned long gp3_ch3_pat; +CIMARRON_STATIC unsigned long gp3_blt; +CIMARRON_STATIC unsigned long gp3_blt_flags; +CIMARRON_STATIC unsigned long gp3_src_stride; +CIMARRON_STATIC unsigned long gp3_dst_stride; +CIMARRON_STATIC unsigned long gp3_src_format; +CIMARRON_STATIC unsigned long gp3_src_pix_shift; +CIMARRON_STATIC unsigned long gp3_pat_format; +CIMARRON_STATIC unsigned long gp3_pat_pix_shift; +CIMARRON_STATIC unsigned long gp3_fb_base; +CIMARRON_STATIC unsigned long gp3_vector_pattern_color; +CIMARRON_STATIC unsigned long gp3_scratch_base; +CIMARRON_STATIC unsigned long gp3_base_register; +CIMARRON_STATIC unsigned long gp3_vec_pat; + +/*--------------------------------------------------------------------------- + * gp_set_limit_on_buffer_lead + * + * This routine is used to specify the maximum number of bytes in the command + * buffer by which software can lead the graphics processor. When declaring + * a BLT with the CIMGP_BLTFLAGS_LIMITBUFFER flag set, Cimarron will wait until + * the command buffer read and write pointers differ by no more than 'lead' + * bytes. This can be useful to limit the time lag possible when creating a + * command buffer full of simple BLT commands. + *-------------------------------------------------------------------------*/ + +void gp_set_limit_on_buffer_lead (unsigned long lead) +{ + gp3_buffer_lead = lead; +} + +/*--------------------------------------------------------------------------- + * gp_set_command_buffer_base + * + * This routine is used to program the command buffer region in physical + * memory. The command buffer start address must be 1MB aligned. start and + * stop refer to endpoints within the associated 16MB region. Command buffers + * larger than 16MB are not supported. + *-------------------------------------------------------------------------*/ + +void gp_set_command_buffer_base (unsigned long address, unsigned long start, + unsigned long stop) +{ + Q_WORD msr_value; + + /* WAIT FOR IDLE */ + /* Obviously, we cannot change the command buffer pointer while the GP */ + /* is currently fetching commands. */ + + gp_wait_until_idle(); + + /* WRITE THE COMMAND BUFFER BASE */ + + msr_read64 (MSR_DEVICE_GEODELX_GP, MSR_GEODELINK_CONFIG, &msr_value); + msr_value.low &= 0xF000FFFF; + msr_value.low |= (address >> 4) & 0x0FFF0000; + msr_write64 (MSR_DEVICE_GEODELX_GP, MSR_GEODELINK_CONFIG, &msr_value); + + /* WRITE THE BASE OFFSETS */ + /* We also reset the write and read pointers. The hardware will */ + /* automatically update the write pointer when the read pointer */ + /* is updated to prevent the hardware from getting confused when */ + /* initializing a new command buffer. */ + + WRITE_GP32 (GP3_CMD_TOP, start); + WRITE_GP32 (GP3_CMD_BOT, stop); + WRITE_GP32 (GP3_CMD_READ, start); + + /* SAVE THE BASE ADDRESSES */ + /* These are used to determine the appropriate wrap point. */ + + gp3_cmd_current = gp3_cmd_top = start; + gp3_cmd_bottom = stop; +} + +/*--------------------------------------------------------------------------- + * gp_set_frame_buffer_base + * + * This routine is used to program the base address of the frame buffer in + * physical memory. The frame buffer address must be 16MB aligned. Cimarron + * tracks the base address because the maximum frame buffer size may exceed + * 16MB. Any primitive will thus program the corresponding 16MB region into all + * base offset registers as well as program the offset into the 16MB region. + * The size parameter is provided to allow Cimarron to claim the last 1MB of + * space to be used as a scratch area for workarounds or expanded functionality. + *-------------------------------------------------------------------------*/ + +void gp_set_frame_buffer_base (unsigned long address, unsigned long size) +{ + gp3_scratch_base = size - GP3_SCRATCH_BUFFER_SIZE; + gp3_fb_base = address >> 24; + gp3_base_register = (gp3_fb_base << 24) | (gp3_fb_base << 14) | (gp3_fb_base << 4); + WRITE_GP32 (GP3_BASE_OFFSET, gp3_base_register); +} + +/*--------------------------------------------------------------------------- + * gp_set_bpp + * + * This routine sets the output BPP of the GP. The BPP used by the GP does + * not have to match the display BPP, but that is usually the case. The + * supported BPP values are as follows: + * + * 8 - palettized 8BPP + * 12 - 4:4:4:4 + * 15 - 1:5:5:5 + * 16 - 0:5:6:5 + * 32 - 8:8:8:8 + *-------------------------------------------------------------------------*/ + +void gp_set_bpp (int bpp) +{ + /* STORE BPP */ + /* The bpp is not updated until the next call to gp_set_raster_mode. */ + /* This allows the gp_set_bpp call to happen outside of a BLT. It */ + /* also implies that no registers need be written in this routine. */ + + switch(bpp) + { + case 8: + gp3_bpp = GP3_RM_BPPFMT_332; + gp3_ch3_bpp = GP3_CH3_SRC_3_3_2; + gp3_pix_shift = 0; + break; + case 12: + gp3_bpp = GP3_RM_BPPFMT_4444; + gp3_ch3_bpp = GP3_CH3_SRC_4_4_4_4; + gp3_pix_shift = 1; + break; + case 15: + gp3_bpp = GP3_RM_BPPFMT_1555; + gp3_ch3_bpp = GP3_CH3_SRC_1_5_5_5; + gp3_pix_shift = 1; + break; + case 16: + gp3_bpp = GP3_RM_BPPFMT_565; + gp3_ch3_bpp = GP3_CH3_SRC_0_5_6_5; + gp3_pix_shift = 1; + break; + case 24: + case 32: + gp3_bpp = GP3_RM_BPPFMT_8888; + gp3_ch3_bpp = GP3_CH3_SRC_8_8_8_8; + gp3_pix_shift = 2; + break; + default: + gp3_bpp = GP3_RM_BPPFMT_332; + gp3_ch3_bpp = GP3_CH3_SRC_3_3_2; + gp3_pix_shift = 0; + break; + } +} + +/*--------------------------------------------------------------------------- + * gp_declare_blt + * + * This routine is used to prepare for a 2D BLT. Its primary function + * is to verify that enough room is available in the command buffer + * to hold a BLT command. This command can be called multiple times if + * necessary. For example, if a function calls this routine on entry, but + * later realizes that a LUT load command must be executed before the BLT, + * the application could call gp_set_color_pattern and then call + * gp_declare_blt to declare the BLT. This is possible because the hardware + * buffer pointer is not updated until a new BLT is actually executed. An + * application must take care not to call any routines that perform a buffer + * command, (such as gp_set_color_pattern) between gp_declare_blt and the + * routines used to program the BLT parameters. In addition to checking for + * available space, this routine also performs the following actions: + * - Sets the wrap bit if this BLT will pass close to the end of the buffer. + * - Writes the command header. + * + * The available flags are defined as follows: + * 0x01 - Preserve the LUT + * 0x02 - Preserve the color pattern. + * 0x04 - Enable prefetch. + *-------------------------------------------------------------------------*/ + +void gp_declare_blt (unsigned long flags) +{ + unsigned long temp; + + gp3_blt = 1; + gp3_blt_flags = flags; + + /* SET ADDRESS OF NEXT COMMAND */ + /* A summary of the command buffer logic is as follows: */ + /* - If after a basic BLT we will not have room for the largest */ + /* command (a full line of host source data), we set the wrap */ + /* bit. This will waste up to a whopping 8K of command buffer */ + /* space, but it simplifies the logic for all commands. */ + /* - If we are wrapping, we have extra logic to ensure that we */ + /* don't skip over the current GP read pointer. */ + + gp3_cmd_next = gp3_cmd_current + GP3_BLT_COMMAND_SIZE; + + /* CHECK WRAP CONDITION */ + + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + gp3_cmd_header = GP3_BLT_HDR_TYPE | GP3_BLT_HDR_WRAP; + + /* WAIT FOR HARDWARE */ + /* When wrapping, we must take steps to ensure that we do not */ + /* wrap over the current hardware read pointer. We do this by */ + /* verifying that the hardware is not between us and the end of */ + /* the command buffer. We also have a special case to make sure */ + /* that the hardware is not currently reading the top of the */ + /* command buffer. */ + + GP3_WAIT_WRAP(temp); + } + else + { + gp3_cmd_header = GP3_BLT_HDR_TYPE; + + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + } + + if (flags & CIMGP_BLTFLAGS_LIMITBUFFER) + { + while (1) + { + temp = READ_GP32 (GP3_CMD_READ); + if (((gp3_cmd_current >= temp) && ((gp3_cmd_current - temp) <= gp3_buffer_lead)) || + ((gp3_cmd_current < temp) && ((gp3_cmd_current + (gp3_cmd_bottom - temp)) <= gp3_buffer_lead))) + { + break; + } + } + } + + /* SET THE CURRENT BUFFER POINTER */ + /* We initialize a pointer to the current buffer base to avoid an */ + /* extra addition for every buffer write. */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* SET THE HAZARD BIT */ + + if (flags & CIMGP_BLTFLAGS_HAZARD) + gp3_cmd_header |= GP3_BLT_HDR_HAZARD_ENABLE; +} + +/*--------------------------------------------------------------------------- + * gp_declare_vector + * + * This routine is used to prepare for a 2D vector. It has no other function + * except to verify that enough room is available in the command buffer + * to hold a vector command. The same rules that apply to BLTs apply to + * vectors. (See the documentation for gp_declare_blt). + *-------------------------------------------------------------------------*/ + +void gp_declare_vector (unsigned long flags) +{ + unsigned long temp; + + gp3_blt = 0; + gp3_blt_flags = flags; + + /* SET ADDRESS OF NEXT COMMAND */ + /* The logic to force a wrap during a vector is identical */ + /* to the BLT logic. */ + + /* ALLOCATE SPACE FOR AN ADDITIONAL VECTOR TO CLEAR THE BYTE ENABLES */ + + gp3_cmd_next = gp3_cmd_current + GP3_VECTOR_COMMAND_SIZE + GP3_VECTOR_COMMAND_SIZE + 32; + + /* CHECK WRAP CONDITION */ + + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + gp3_cmd_header = GP3_VEC_HDR_TYPE | GP3_VEC_HDR_WRAP; + + /* CHECK WRAP CONDITION */ + + GP3_WAIT_WRAP(temp); + } + else + { + gp3_cmd_header = GP3_VEC_HDR_TYPE; + + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + + gp3_cmd_next -= GP3_VECTOR_COMMAND_SIZE + 32; + } + + if (flags & CIMGP_BLTFLAGS_LIMITBUFFER) + { + while (1) + { + temp = READ_GP32 (GP3_CMD_READ); + if (((gp3_cmd_current >= temp) && ((gp3_cmd_current - temp) <= gp3_buffer_lead)) || + ((gp3_cmd_current < temp) && ((gp3_cmd_current + (gp3_cmd_bottom - temp)) <= gp3_buffer_lead))) + { + break; + } + } + } + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* SET THE HAZARD BIT */ + + if (flags & CIMGP_BLTFLAGS_HAZARD) + gp3_cmd_header |= GP3_VEC_HDR_HAZARD_ENABLE; +} + +/*--------------------------------------------------------------------------- + * gp_write_parameters + * + * This routine is called to write all recent parameters to the hardware. + * This routine is necessary for any implementation that performs the setup + * for a BLT separate from the actual BLT. An example would be a driver + * that prepares for multiple pattern fills by programming the ROP, + * pattern color and destination stride. The driver might then perform + * repeated pattern fills with minimal effort. + *-------------------------------------------------------------------------*/ + +void gp_write_parameters (void) +{ + /* WRITE THE COMMAND HEADER */ + /* Command header is at offset 0 for BLTs and vectors */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + + /* INCREMENT THE CURRENT WRITE POINTER */ + + gp3_cmd_current = gp3_cmd_next; + + /* UPDATE THE GP WRITE POINTER */ + + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_current); +} + +/*--------------------------------------------------------------------------- + * gp_set_raster_operation + * + * This is generally the first routine called when programming a BLT. This + * routine performs the following functions: + * - Sets the initial value of the GP3_RASTER_MODE register in the buffer. + * - Clears any 8x8 pattern if the ROP does not involve pattern data. + *-------------------------------------------------------------------------*/ + +void gp_set_raster_operation (unsigned char ROP) +{ + gp3_cmd_header |= GP3_BLT_HDR_RASTER_ENABLE; + + /* WRITE THE RASTER MODE REGISTER */ + /* This register is in the same location in BLT and vector commands */ + + gp3_raster_mode = gp3_bpp | (unsigned long)ROP; + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_raster_mode); + + /* CHECK IF DESTINATION IS REQUIRED */ + + if ((ROP & 0x55) ^ ((ROP >> 1) & 0x55)) + { + gp3_blt_mode = GP3_BM_DST_REQ; + gp3_vec_mode = GP3_VM_DST_REQ; + } + else + { + gp3_blt_mode = gp3_vec_mode = 0; + } +} + +/*---------------------------------------------------------------------------- + * gp_set_alpha_operation + * + * BLTs are generally one of two types, a ROPed BLT or a BLT composited using + * alpha blending. For the latter, this routine is used to configure the + * mathematical function used to create the blended output. This routine + * should generally be called first when programming a BLT. The available + * parameters mirror the hardware and are described as follows: + * + * alpha_operation = + * 0 - alpha * A + * 1 - (1 - alpha) * B + * 2 - A + (1 - alpha)*B + * 3 - alpha*A + (1 - alpha)*B + * + * alpha_type = + * 0 - alpha component of channel A + * 1 - alpha component of channel B + * 2 - Constant alpha + * 3 - Constant 1 + * 4 - The color components of channel A + * 5 - The color components of channel B + * 6 - Alpha comes from the alpha channel of the source before the source undergoes + * color conversion. + * + * channel = + * 0 - Channel A = source, channel B = destination + * 1 - Channel B = source, channel A = destination + * + * apply_alpha = + * 1 - Apply alpha blend to only the RGB portion of the pixel. This must be + * set when the source or destination format do not include an alpha channel. + * 2 - Apply alpha blend only to the alpha portion of the pixel. This implies + * that both destination and source include an alpha channel. + * 3 - Apply alpha blend to both the RGB and alpha portions of the pixel. + * + * Alpha-blended vectors are not currently supported. + *-------------------------------------------------------------------------*/ + +void gp_set_alpha_operation (int alpha_operation, int alpha_type, int channel, + int apply_alpha, unsigned char alpha) +{ + gp3_cmd_header |= GP3_BLT_HDR_RASTER_ENABLE; + + /* THE AVAILABLE ALPHA DEFINITIONS FOLLOW THE HARDWARE */ + /* This allows us to avoid giant switch structures, but it */ + /* also implies that there is no mechanism to detect invalid */ + /* parameters. */ + + gp3_raster_mode = gp3_bpp | (unsigned long)alpha | + ((unsigned long)apply_alpha << 22) | + ((unsigned long)alpha_operation << 20) | + ((unsigned long)alpha_type << 17) | + ((unsigned long)channel << 16); + + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_raster_mode); + + /* CHECK IF DESTINATION IS REQUIRED */ + + if ( (alpha_operation == CIMGP_ALPHA_TIMES_A && + channel == CIMGP_CHANNEL_A_SOURCE && + alpha_type != CIMGP_CHANNEL_B_ALPHA && + alpha_type != CIMGP_ALPHA_FROM_RGB_B) || + (alpha_operation == CIMGP_BETA_TIMES_B && + channel == CIMGP_CHANNEL_A_DEST && + alpha_type != CIMGP_CHANNEL_A_ALPHA && + alpha_type != CIMGP_ALPHA_FROM_RGB_A)) + { + gp3_blt_mode = 0; + } + else + gp3_blt_mode = GP3_BM_DST_REQ; +} + +/*--------------------------------------------------------------------------- + * gp_set_solid_pattern + * + * This routine is called to program the hardware for a solid pattern. It need + * not be called for any other reason. As a side effect, this routine will + * clear any 8x8 pattern data. + *-------------------------------------------------------------------------*/ + +void gp_set_solid_pattern (unsigned long color) +{ + /* CHANNEL 3 IS NOT NEEDED FOR SOLID PATTERNS */ + + gp3_ch3_pat = 0; + + /* SET SOLID PATTERN IN COMMAND BUFFER */ + /* We are assuming that only one pattern type is ever set for a */ + /* BLT. We are also assuming that gp_set_raster_operation will */ + /* be called before this routine. With these assumptions, we */ + /* will thus never have to change the raster mode register for */ + /* solid patterns. */ + + if (gp3_blt) + { + gp3_cmd_header |= GP3_BLT_HDR_PAT_CLR0_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_PAT_COLOR_0, color); + } + else + { + gp3_cmd_header |= GP3_VEC_HDR_PAT_CLR0_ENABLE; + + WRITE_COMMAND32 (GP3_VECTOR_PAT_COLOR_0, color); + } +} + +/*--------------------------------------------------------------------------- + * gp_set_mono_pattern + * + * This routine is called to program the hardware for a monochrome pattern. + * As a side effect, this routine will clear any 8x8 pattern data. + *-------------------------------------------------------------------------*/ + +void gp_set_mono_pattern (unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, int transparent, int x, int y) +{ + /* CHANNEL 3 IS NOT NEEDED FOR MONOCHROME PATTERNS */ + + gp3_ch3_pat = 0; + + /* UPDATE RASTER MODE REGISTER */ + + if (transparent) gp3_raster_mode |= GP3_RM_PAT_MONO | GP3_RM_PAT_TRANS; + else gp3_raster_mode |= GP3_RM_PAT_MONO; + + gp3_cmd_header |= GP3_BLT_HDR_RASTER_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_raster_mode); + + /* SET MONOCHROME PATTERN DATA AND COLORS */ + + if (gp3_blt) + { + gp3_cmd_header |= (GP3_BLT_HDR_PAT_CLR0_ENABLE | GP3_BLT_HDR_PAT_CLR1_ENABLE | + GP3_BLT_HDR_PAT_DATA0_ENABLE | GP3_BLT_HDR_PAT_DATA1_ENABLE); + + WRITE_COMMAND32 (GP3_BLT_PAT_COLOR_0, bgcolor); + WRITE_COMMAND32 (GP3_BLT_PAT_COLOR_1, fgcolor); + WRITE_COMMAND32 (GP3_BLT_PAT_DATA_0, data0); + WRITE_COMMAND32 (GP3_BLT_PAT_DATA_1, data1); + } + else + { + gp3_cmd_header |= (GP3_VEC_HDR_PAT_CLR0_ENABLE | GP3_VEC_HDR_PAT_CLR1_ENABLE | + GP3_VEC_HDR_PAT_DATA0_ENABLE | GP3_VEC_HDR_PAT_DATA1_ENABLE); + + WRITE_COMMAND32 (GP3_VECTOR_PAT_COLOR_0, bgcolor); + WRITE_COMMAND32 (GP3_VECTOR_PAT_COLOR_1, fgcolor); + WRITE_COMMAND32 (GP3_VECTOR_PAT_DATA_0, data0); + WRITE_COMMAND32 (GP3_VECTOR_PAT_DATA_1, data1); + } + + /* SAVE PATTERN ORIGIN */ + + gp3_pat_origin = ((unsigned long)y << 29) | (((unsigned long)x & 7) << 26); +} + +/*--------------------------------------------------------------------------- + * gp_set_pattern_origin + * + * This routine overrides the pattern origins set in gp_set_mono_pattern or + * gp_set_color_pattern. It is generally used to override the original + * pattern origin due to a change in clipping. + *-------------------------------------------------------------------------*/ + +void gp_set_pattern_origin (int x, int y) +{ + /* SAVE PATTERN ORIGIN */ + + gp3_pat_origin = ((unsigned long)y << 29) | (((unsigned long)x & 7) << 26); +} + +/*--------------------------------------------------------------------------- + * gp_set_color_pattern + * + * This routine is called to program a 8x8 color pattern into the LUT hardware. + * Unlike the other pattern routines, this routine must be called before + * any gp_declare_xxxx routines. The pattern that is programmed into the + * hardware will stay persistent for all subsequent primitives until one of + * the following conditions happens. + * - Another pattern type is programmed. + * - A color-conversion BLT rotation BLT. + *-------------------------------------------------------------------------*/ + +void gp_set_color_pattern (unsigned long *pattern, int format, int x, int y) +{ + unsigned long size_dwords, temp; + + gp3_ch3_pat = 1; + + /* SAVE COLOR PATTERN SOURCE INFO */ + /* Color patterns can be in a format different than the primary display. */ + /* 4BPP patterns are not supported. */ + + gp3_pat_pix_shift = (unsigned long)((format >> 2) & 3); + gp3_pat_format = (((unsigned long)format & 0xF) << 24) | + (((unsigned long)format & 0x10) << 17) | + GP3_CH3_COLOR_PAT_ENABLE | + GP3_CH3_C3EN; + + size_dwords = (64 << gp3_pat_pix_shift) >> 2; + + /* CHECK FOR WRAP AFTER LUT LOAD */ + /* Primitive size is 12 plus the amount of data. */ + + gp3_cmd_next = gp3_cmd_current + (size_dwords << 2) + 12; + + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + gp3_cmd_header = GP3_LUT_HDR_TYPE | GP3_LUT_HDR_WRAP | GP3_LUT_HDR_DATA_ENABLE; + + /* WAIT FOR HARDWARE */ + /* Same logic as BLT wrapping. */ + + GP3_WAIT_WRAP(temp); + } + else + { + gp3_cmd_header = GP3_LUT_HDR_TYPE | GP3_LUT_HDR_DATA_ENABLE; + + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + } + + /* SAVE CURRENT BUFFER POINTER */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* PREPARE FOR COMMAND BUFFER DATA WRITES */ + /* Pattern data is contiguous DWORDs at LUT address 0x100 */ + + WRITE_COMMAND32 (0, gp3_cmd_header); + WRITE_COMMAND32 (4, 0x100); + WRITE_COMMAND32 (8, size_dwords | GP3_LUT_DATA_TYPE); + + /* WRITE ALL DATA */ + + WRITE_COMMAND_STRING32 (12, pattern, 0, size_dwords); + + /* START OPERATION */ + + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + + /* SAVE PATTERN ORIGIN */ + + gp3_pat_origin = ((unsigned long)y << 29) | (((unsigned long)x & 7) << 26); +} + +/*--------------------------------------------------------------------------- + * gp_set_mono_source + * + * This routine is called to program the colors for monochrome source data. + *-------------------------------------------------------------------------*/ + +void gp_set_mono_source (unsigned long bgcolor, unsigned long fgcolor, + int transparent) +{ + /* UPDATE RASTER MODE REGISTER IF TRANSPARENT */ + + if (transparent) + { + gp3_cmd_header |= GP3_BLT_HDR_RASTER_ENABLE; + gp3_raster_mode |= GP3_RM_SRC_TRANS; + + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_raster_mode); + } + + /* SET MONOCHROME SOURCE COLORS */ + /* Note that this routine only sets the colors. The actual */ + /* source type is determined by the final output routine */ + /* (gp_mono_bitmap_xxx, gp_color_bitmap_xxx, etc.) */ + + gp3_cmd_header |= GP3_BLT_HDR_SRC_FG_ENABLE | GP3_BLT_HDR_SRC_BG_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_SRC_COLOR_FG, fgcolor); + WRITE_COMMAND32 (GP3_BLT_SRC_COLOR_BG, bgcolor); +} + +/*--------------------------------------------------------------------------- + * gp_set_solid_source + * + * This routine is called to program a solid source color. A solid source + * color is used primarily for vectors or antialiased text. + *-------------------------------------------------------------------------*/ + +void gp_set_solid_source (unsigned long color) +{ + /* SET SOLID SOURCE COLOR */ + /* The solid source register is in the same place for both BLTs and */ + /* vectors. */ + + gp3_cmd_header |= GP3_BLT_HDR_SRC_FG_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_SRC_COLOR_FG, color); +} + +/*--------------------------------------------------------------------------- + * gp_set_source_transparency + * + * This routine sets the source transparency and mask to be used in future + * rendering operations. Transparency is cleared by gp_set_raster_operation, + * so this routine should never be called first. + *-------------------------------------------------------------------------*/ + +void gp_set_source_transparency (unsigned long color, unsigned long mask) +{ + gp3_raster_mode |= GP3_RM_SRC_TRANS; + gp3_cmd_header |= GP3_BLT_HDR_RASTER_ENABLE | GP3_BLT_HDR_SRC_FG_ENABLE | + GP3_BLT_HDR_SRC_BG_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_raster_mode); + WRITE_COMMAND32 (GP3_BLT_SRC_COLOR_FG, color); + WRITE_COMMAND32 (GP3_BLT_SRC_COLOR_BG, mask); +} + +/*--------------------------------------------------------------------------- + * gp_program_lut + * + * This routine is called to program the hardware LUT with color-conversion + * information. This routine should be called before any gp_declare_xxxx + * routines. + * + * colors - Pointer to an array of DWORDs for color expansion. + * + * full_lut - Selector between 4BPP and 8BPP expansion. The hardware is + * initialized with 16 dwords for 4BPP expansion and 256 dwords + * for 8BPP expansion. + *-------------------------------------------------------------------------*/ + +void gp_program_lut (unsigned long *colors, int full_lut) +{ + unsigned long size_dwords, temp; + + /* SIZE IS EITHER 16 DWORDS (4BPP) or 256 DWORDS (8BPP) */ + + if (full_lut) size_dwords = 256; + else size_dwords = 16; + + /* CHECK FOR WRAP AFTER LUT LOAD */ + /* Primitive size is 12 plus the amount of data. */ + + gp3_cmd_next = gp3_cmd_current + (size_dwords << 2) + 12; + + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + gp3_cmd_header = GP3_LUT_HDR_TYPE | GP3_LUT_HDR_WRAP | GP3_LUT_HDR_DATA_ENABLE; + + /* WAIT FOR HARDWARE */ + /* Same logic as BLT wrapping. */ + + GP3_WAIT_WRAP(temp); + } + else + { + gp3_cmd_header = GP3_LUT_HDR_TYPE | GP3_LUT_HDR_DATA_ENABLE; + + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + } + + /* SAVE CURRENT BUFFER POINTER */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* PREPARE FOR COMMAND BUFFER DATA WRITES */ + /* Pattern data is contiguous DWORDs at LUT address 0 */ + + WRITE_COMMAND32 (0, gp3_cmd_header); + WRITE_COMMAND32 (4, 0); + WRITE_COMMAND32 (8, (size_dwords | GP3_LUT_DATA_TYPE)); + + /* WRITE ALL DATA */ + + WRITE_COMMAND_STRING32 (12, colors, 0, size_dwords); + + /* START OPERATION */ + + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; +} + +/*--------------------------------------------------------------------------- + * gp_set_vector_pattern + * + * This routine is called to program the hardware LUT with a vector pattern. + * A vector pattern is programmed as a 32-bit mask that specifies a + * transparency pattern. A length parameter is used to specify patterns + * smaller than 32. Note that vectors in Geode LX do not continue across corners. + * The beginning of each vector will always begin with bit 0 of the vector + * pattern. It is the responsibility of the caller to update the pattern + * if an alternate behavior is desired. + * + * This routine faces the same restrictions of all routines that program + * the LUT, in that it must be called before any gp_declare_xxxx routines, + * it cannot be combined with an 8x8 color pattern, color conversion or + * rotation. + *-------------------------------------------------------------------------*/ + +void gp_set_vector_pattern (unsigned long pattern, unsigned long color, int length) +{ + unsigned long temp, mask; + + gp3_ch3_pat = 1; + gp3_vector_pattern_color = color; + + /* CREATE SUITABLE PATTERN MASK */ + /* The GP requires a minimum of four pixels in a vector pattern. We */ + /* can get around this restriction by doubling any patterns smaller */ + /* than 4 pixels. */ + + while (length < 4) + { + mask = 0xFFFFFFFF >> (32 - length); + pattern = (pattern << length) | (pattern & mask); + length <<= 1; + } + mask = 0xFFFFFFFF >> (32 - length); + + gp3_vec_pat = pattern; + + /* CHECK FOR WRAP AFTER LUT LOAD */ + + gp3_cmd_next = gp3_cmd_current + GP3_VECTOR_PATTERN_COMMAND_SIZE; + + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + gp3_cmd_header = GP3_LUT_HDR_TYPE | GP3_LUT_HDR_WRAP | GP3_LUT_HDR_DATA_ENABLE; + + /* WAIT FOR HARDWARE */ + /* Same logic as BLT wrapping. */ + + GP3_WAIT_WRAP(temp); + } + else + { + gp3_cmd_header = GP3_LUT_HDR_TYPE | GP3_LUT_HDR_DATA_ENABLE; + + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + } + + /* SAVE CURRENT BUFFER POINTER */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* PREPARE FOR COMMAND BUFFER DATA WRITES */ + /* Pattern data is 2 DWORDs at 0x100 and 0x101 */ + + WRITE_COMMAND32 (0, gp3_cmd_header); + WRITE_COMMAND32 (4, 0x100); + WRITE_COMMAND32 (8, (2 | GP3_LUT_DATA_TYPE)); + WRITE_COMMAND32 (12, pattern); + WRITE_COMMAND32 (16, mask); + + /* START OPERATION */ + + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; +} + +/*--------------------------------------------------------------------------- + * gp_set_strides + * + * This routine is called to program the pitch between successive lines of + * data in the frame buffer. The strides should be DWORD aligned and less + * than 64K. These restrictions are not checked by the API. + *-------------------------------------------------------------------------*/ + +void gp_set_strides (unsigned long dst_stride, unsigned long src_stride) +{ + /* SAVE STRIDES */ + /* The source stride may be needed later for channel 3 source data and */ + /* we may need to use these strides in calculations. */ + + gp3_src_stride = src_stride; + gp3_dst_stride = dst_stride; + + /* ENABLE STRIDES */ + /* The stride register is in the same place for BLTs and vectors */ + + gp3_cmd_header |= GP3_BLT_HDR_STRIDE_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_STRIDE, ((src_stride << 16) | dst_stride)); +} + +/*--------------------------------------------------------------------------- + * gp_set_source_format + * + * This routine is used to program the format of source data used in subsequent + * color-conversion or rotation operations. Note that 4BPP indexed and 8BPP + * indexed source formats cannot be used when rotating, as the LUT will be + * destroyed. These formats also cannot be combined with an 8x8 color pattern. + * The supported formats mirror the hardware and are described as follows: + * + * 0 - 8BPP 3:3:2 + * 1 - 8BPP indexed + * 4 - 16BPP 4:4:4:4 + * 5 - 16BPP 1:5:5:5 + * 6 - 16BPP 5:6:5 + * 7 - 16BPP YUV + * 8 - 32BPP 8:8:8:8 + * 13 - 4BPP indexed + * 20 - 16BPP 4:4:4:4 BGR + * 21 - 16BPP 1:5:5:5 BGR + * 22 - 16BPP 0:5:6:5 BGR + * 24 - 32BPP 8:8:8:8 BGR + *-------------------------------------------------------------------------*/ + +void gp_set_source_format (int format) +{ + /* SAVE FORMAT */ + /* We will combine the source format later when doing color conversion. */ + /* We also save the pixel size for host source calculations. */ + /* Conveniently, the source formats are organized such that the upper */ + /* two bits of the nibble represent the pixel shift, with a pixel shift */ + /* of 3 being a special case for 4BPP data. Clever, yes? Even more */ + /* clever, bit 4 indicates BGR ordering. */ + + gp3_src_pix_shift = (unsigned long)((format >> 2) & 3); + gp3_src_format = (((unsigned long)format & 0xF) << 24) | + (((unsigned long)format & 0x10) << 18); +} + +/*--------------------------------------------------------------------------- + * gp_pattern_fill + * + * This routine is called to perform a simple pattern fill. The pattern + * can be solid, monochrome or a preprogrammed 8x8 color pattern. If + * the ROP involves source data, that source data will be constant. + *-------------------------------------------------------------------------*/ + +void gp_pattern_fill (unsigned long dstoffset, unsigned long width, unsigned long height) +{ + unsigned long base_register; + + base_register = (gp3_base_register & ~GP3_BASE_OFFSET_DSTMASK) | + ((gp3_fb_base << 24) + (dstoffset & 0xFFC00000)); + + /* ENABLE RELEVANT REGISTERS */ + /* Note that we always enable and write the channel 3 mode, if only */ + /* to turn it off. Cimarron also always writes the base offset */ + /* register to allow operation with frame buffers larger than 16MB. */ + + gp3_cmd_header |= GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + /* WRITE THE REGISTERS COMMON TO ALL PATTERN TYPES */ + /* The destination base is the frame buffer base plus whatever */ + /* 4MB segment we happen to be BLTing to. */ + + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, ((width << 16) | height)); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base_register); + + /* CHECK 8X8 COLOR PATTERN CASE */ + + if (gp3_ch3_pat) + { + /* SET CHANNEL 3 PATTERN ORIGINS */ + + gp3_cmd_header |= GP3_BLT_HDR_CH3_OFF_ENABLE; + + /* INITIALIZE CHANNEL 3 PARAMETERS */ + + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, ((width << 16) | height)); + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, gp3_pat_origin); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, dstoffset & 0x3FFFFF); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, gp3_pat_format); + } + else + { + /* DISABLE CHANNEL 3 AND USE NORMAL PATTERN ORIGINS */ + + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, 0); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, ((dstoffset & 0x3FFFFF) | gp3_pat_origin)); + } + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_COMMAND32 (GP3_BLT_MODE, gp3_blt_mode); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; +} + +/*--------------------------------------------------------------------------- + * gp_screen_to_screen_blt + * + * This routine is called to perform a BLT from one location inside video + * memory to another location inside video memory. The source and destination + * formats are assumed to be the current BPP. Whenever possible, this routine + * tries to use channel 3 to fetch source data. The BLT flags can affect this + * behavior in the following ways: + * CIMGP_BLTFLAGS_PRES_COLOR_PAT + * A color pattern is being stored in the channel 3 buffer. It is either + * being stored for a later BLT or being combined with the current source + * data. Channel 3 cannot be used to fetch source data or the pattern + * will be overwritten. + * CIMGP_BLTFLAGS_PRES_LUT + * If the first flag is not set, this flag will limit the use of the + * channel 3 buffer to 1K. + *-------------------------------------------------------------------------*/ + +void gp_screen_to_screen_blt (unsigned long dstoffset, unsigned long srcoffset, + unsigned long width, unsigned long height, int flags) +{ + unsigned long base; + unsigned long ch3_flags = 0; + unsigned long blt_mode = gp3_blt_mode; + unsigned long size = ((width << 16) | height); + unsigned long dstbase, srcbase; + + /* CALCULATE BASE OFFSETS */ + /* We need to set the 4MB aligned base offsets before we add offsets */ + /* for negative BLTs. */ + + srcbase = srcoffset & 0xFFC00000; + dstbase = dstoffset & 0xFFC00000; + srcoffset &= 0x3FFFFF; + dstoffset &= 0x3FFFFF; + + /* ADJUST OFFSETS BASED ON FLAGS */ + /* We adjust the source and destination offsets to point to the first */ + /* byte of the first pixel of the BLT. This routine assumes that the */ + /* source and destination regions do not wrap past the end of a 16MB */ + /* region. */ + + if (flags & CIMGP_NEGXDIR) + { + srcoffset += (width << gp3_pix_shift) - 1; + dstoffset += (width << gp3_pix_shift) - 1; + blt_mode |= GP3_BM_NEG_XDIR; + ch3_flags |= GP3_CH3_NEG_XDIR; + } + if (flags & CIMGP_NEGYDIR) + { + srcoffset += (height - 1) * gp3_src_stride; + dstoffset += (height - 1) * gp3_dst_stride; + blt_mode |= GP3_BM_NEG_YDIR; + ch3_flags |= GP3_CH3_NEG_YDIR; + } + + /* BRANCH BASED ON CHANNEL 3 */ + /* If a color pattern is not being saved or used, channel 3 will */ + /* be used to fetch source for maximum throughput. Channel 3 */ + /* is not used if transparency or alpha blending is enabled. */ + + if (!(gp3_blt_flags & CIMGP_BLTFLAGS_PRES_COLOR_PAT) && + !(gp3_raster_mode & GP3_RM_SRC_TRANS) && + !(flags & CIMGP_NEGYDIR)) + { + base = ((gp3_fb_base << 24) + dstbase) | + ((gp3_fb_base << 4) + (srcbase >> 20)) | + (gp3_base_register & GP3_BASE_OFFSET_SRCMASK); + + gp3_cmd_header |= GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, (dstoffset | gp3_pat_origin)); + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, srcoffset); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, size); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, size); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, + GP3_CH3_C3EN | + GP3_CH3_REPLACE_SOURCE | + gp3_ch3_bpp | + gp3_src_stride | + ch3_flags | + ((gp3_blt_flags & CIMGP_ENABLE_PREFETCH) << 17) | + ((gp3_blt_flags & CIMGP_BLTFLAGS_PRES_LUT) << 20)); + } + else + { + /* CALCULATE BASE OFFSET REGISTER */ + + base = ((gp3_fb_base << 24) + dstbase) | + ((gp3_fb_base << 14) + (srcbase >> 10)) | + (gp3_base_register & GP3_BASE_OFFSET_CH3MASK); + + /* PROGRAM THE NORMAL SOURCE CHANNEL REGISTERS */ + /* We assume that a color pattern is being ROPed with source */ + /* data if the pattern type is color and the preserve pattern */ + /* was set. */ + + blt_mode |= GP3_BM_SRC_FB; + + gp3_cmd_header |= GP3_BLT_HDR_SRC_OFF_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + if (gp3_ch3_pat) + { + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, gp3_pat_origin); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, dstoffset); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, gp3_pat_format | ch3_flags); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, size); + } + else + { + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, dstoffset | gp3_pat_origin); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, 0); + } + + WRITE_COMMAND32 (GP3_BLT_SRC_OFFSET, srcoffset); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, size); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base); + } + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_COMMAND32 (GP3_BLT_MODE, blt_mode); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; +} + +/*--------------------------------------------------------------------------- + * gp_screen_to_screen_convert + * + * This routine is called to color-convert a rectangular region of the frame + * buffer into the current BPP. The format of the source region is programmed + * by gp_set_source_format. + *-------------------------------------------------------------------------*/ + +void gp_screen_to_screen_convert (unsigned long dstoffset, unsigned long srcoffset, + unsigned long width, unsigned long height, int nibble) +{ + unsigned long size = ((width << 16) | height); + unsigned long ch3_offset = srcoffset & 0x3FFFFF; + unsigned long ch3_size, base; + + base = ((gp3_fb_base << 24) + (dstoffset & 0xFFC00000)) | + ((gp3_fb_base << 4) + ((srcoffset & 0xFFC00000) >> 20)) | + (gp3_base_register & GP3_BASE_OFFSET_SRCMASK); + + /* SET NIBBLE FOR 4BPP */ + /* 4BPP is a special case in that it requires subpixel addressing. The */ + /* user must supply this information via the nibble parameter. This */ + /* parameter is ignored for every other source format. */ + + ch3_size = size; + if (gp3_src_pix_shift == 3) + ch3_offset |= ((nibble & 1) << 25); + else if ((gp3_src_format & GP3_CH3_SRC_MASK) == GP3_CH3_SRC_24BPP_PACKED) + ch3_size = ((((width * 3) + 3) >> 2) << 16) | height; + + /* SET APPROPRIATE ENABLES */ + + gp3_cmd_header |= GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + /* WRITE ALL BLT REGISTERS */ + + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, (dstoffset & 0x3FFFFF) | gp3_pat_origin); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, size); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, ch3_size); + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, ch3_offset); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, + GP3_CH3_C3EN | + GP3_CH3_REPLACE_SOURCE | + gp3_src_format | + ((gp3_blt_flags & CIMGP_BLTFLAGS_PRES_LUT) << 20) | + ((gp3_blt_flags & CIMGP_ENABLE_PREFETCH) << 17) | + gp3_src_stride); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base); + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_COMMAND32 (GP3_BLT_MODE, gp3_blt_mode); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; +} + +/*--------------------------------------------------------------------------- + * gp_color_bitmap_to_screen_blt + * + * This routine is called to BLT data from system memory into the frame buffer. + * 'srcy' is deliberately omitted to prevent extra calculations for simple + * applications that have no source indexes. + *-------------------------------------------------------------------------*/ + +void gp_color_bitmap_to_screen_blt (unsigned long dstoffset, unsigned long srcx, + unsigned long width, unsigned long height, unsigned char *data, long pitch) +{ + unsigned long indent, temp; + unsigned long total_dwords, size_dwords; + unsigned long dword_count, byte_count; + unsigned long size = ((width << 16) | height); + unsigned long srcoffset; + + /* ASSUME BITMAPS ARE DWORD ALIGNED */ + /* We will offset into the source data in DWORD increments. We */ + /* set the source index to the remaining byte offset and */ + /* increment the size of each line to account for the dont-care */ + /* pixel(s). */ + + indent = srcx << gp3_pix_shift; + srcoffset = (indent & ~3L); + indent &= 3; + + /* PROGRAM THE NORMAL SOURCE CHANNEL REGISTERS */ + /* We assume that a color pattern is being ROPed with source */ + /* data if the pattern type is color and the preserve pattern */ + /* was set. */ + + gp3_cmd_header |= GP3_BLT_HDR_SRC_OFF_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + if (gp3_ch3_pat) + { + gp3_cmd_header |= GP3_BLT_HDR_CH3_OFF_ENABLE | GP3_BLT_HDR_CH3_WIDHI_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, gp3_pat_origin); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, (dstoffset & 0x3FFFFF)); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, gp3_pat_format); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, size); + } + else + { + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, ((dstoffset & 0x3FFFFF) | gp3_pat_origin)); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, 0); + } + + WRITE_COMMAND32 (GP3_BLT_SRC_OFFSET, indent); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, size); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, + ((gp3_fb_base << 24) + (dstoffset & 0xFFC00000))); + WRITE_COMMAND32 (GP3_BLT_MODE, gp3_blt_mode | GP3_BM_SRC_HOST); + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + + /* CALCULATE THE SIZE OF ONE LINE */ + + size = (width << gp3_pix_shift) + indent; + total_dwords = (size + 3) >> 2; + size_dwords = (total_dwords << 2) + 8; + dword_count = (size >> 2); + byte_count = (size & 3); + + /* CHECK FOR SMALL BLT CASE */ + + if (((total_dwords << 2) * height) <= GP3_BLT_1PASS_SIZE && + (gp3_cmd_bottom - gp3_cmd_current) > (GP3_BLT_1PASS_SIZE + 72)) + { + /* UPDATE THE COMMAND POINTER */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + ((total_dwords << 2) * height) + 8; + + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_HOST_SOURCE_TYPE | (total_dwords * height)); + + while (height--) + { + /* WRITE DATA */ + + WRITE_COMMAND_STRING32 (8, data, srcoffset, dword_count); + WRITE_COMMAND_STRING8 (8 + (dword_count << 2), data, + srcoffset + (dword_count << 2), byte_count); + + srcoffset += pitch; + cim_cmd_ptr += total_dwords << 2; + } + + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } + else + { + /* WRITE DATA LINE BY LINE */ + /* Each line will be created as a separate command buffer entry to allow */ + /* line-by-line wrapping and to allow simultaneous rendering by the HW. */ + + while (height--) + { + /* UPDATE THE COMMAND POINTER */ + /* The WRITE_COMMANDXX macros use a pointer to the current buffer space. */ + /* This is created by adding gp3_cmd_current to the base pointer. */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + size_dwords; + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + /* WAIT FOR HARDWARE */ + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_HOST_SOURCE_TYPE | total_dwords); + + /* WRITE DATA */ + + WRITE_COMMAND_STRING32 (8, data, srcoffset, dword_count); + WRITE_COMMAND_STRING8 (8 + (dword_count << 2), data, + srcoffset + (dword_count << 2), byte_count); + + /* UPDATE POINTERS */ + + srcoffset += pitch; + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } + } +} + +/*--------------------------------------------------------------------------- + * gp_color_convert_blt + * + * This routine is called to convert data that is stored in system memory + * into the current graphics BPP. The source format is programmed in + * gp_set_source_format. + *-------------------------------------------------------------------------*/ + +void gp_color_convert_blt (unsigned long dstoffset, unsigned long srcx, + unsigned long width, unsigned long height, unsigned char *data, long pitch) +{ + unsigned long indent, temp; + unsigned long total_dwords, size_dwords; + unsigned long dword_count, byte_count; + unsigned long size = ((width << 16) | height); + unsigned long ch3_size; + unsigned long ch3_offset, srcoffset; + unsigned long base; + + /* ASSUME BITMAPS ARE DWORD ALIGNED */ + /* We will offset into the source data in DWORD increments. We */ + /* set the source index to the remaining byte offset and */ + /* increment the size of each line to account for the dont-care */ + /* pixel(s). For 4BPP source data, we also set the appropriate */ + /* nibble index. */ + + /* CALCULATE THE SIZE OF ONE LINE */ + + if ((gp3_src_format & GP3_CH3_SRC_MASK) == GP3_CH3_SRC_24BPP_PACKED) + { + /* HANDLE 24BPP */ + /* Note that we do not do anything to guarantee that the source data */ + /* is DWORD aligned. The logic here is that the source data will be */ + /* cacheable, in which case Geode LX will not lose any clocks for unaligned */ + /* moves. Also note that the channel 3 width is programmed as the */ + /* number of dwords, while the normal width is programmed as the number */ + /* of pixels. */ + + srcoffset = srcx * 3; + ch3_offset = 0; + temp = width * 3; + ch3_size = (((temp + 3) >> 2) << 16) | height; + } + else + { + ch3_size = size; + + if (gp3_src_pix_shift == 3) + { + /* CALCULATE INDENT AND SOURCE OFFSET */ + + indent = (srcx >> 1); + srcoffset = (indent & ~3L); + indent &= 3; + ch3_offset = indent | ((srcx & 1) << 25); + + temp = ((width + (srcx & 1) + 1) >> 1) + indent; + } + else + { + indent = (srcx << gp3_src_pix_shift); + srcoffset = (indent & ~3L); + indent &= 3; + ch3_offset = indent; + + temp = (width << gp3_src_pix_shift) + indent; + } + } + + total_dwords = (temp + 3) >> 2; + size_dwords = (total_dwords << 2) + 8; + dword_count = (temp >> 2); + byte_count = (temp & 3); + + base = ((gp3_fb_base << 24) + (dstoffset & 0xFFC00000)) | + (gp3_base_register & ~GP3_BASE_OFFSET_DSTMASK); + + /* SET APPROPRIATE ENABLES */ + + gp3_cmd_header |= GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, (dstoffset & 0x3FFFFF) | gp3_pat_origin); + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, ch3_offset); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, size); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, ch3_size); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, + GP3_CH3_C3EN | + GP3_CH3_REPLACE_SOURCE | + GP3_CH3_HST_SRC_ENABLE | + gp3_src_format | + ((gp3_blt_flags & CIMGP_BLTFLAGS_PRES_LUT) << 20)); + WRITE_COMMAND32 (GP3_BLT_MODE, gp3_blt_mode); + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + + if (((total_dwords << 2) * height) <= GP3_BLT_1PASS_SIZE && + (gp3_cmd_bottom - gp3_cmd_current) > (GP3_BLT_1PASS_SIZE + 72)) + { + /* UPDATE THE COMMAND POINTER */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + ((total_dwords << 2) * height) + 8; + + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_CH3_HOST_SOURCE_TYPE | (total_dwords * height)); + + while (height--) + { + /* WRITE DATA */ + + WRITE_COMMAND_STRING32 (8, data, srcoffset, dword_count); + WRITE_COMMAND_STRING8 (8 + (dword_count << 2), data, + srcoffset + (dword_count << 2), byte_count); + + srcoffset += pitch; + cim_cmd_ptr += total_dwords << 2; + } + + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } + else + { + /* WRITE DATA LINE BY LINE */ + /* Each line will be created as a separate command buffer entry to allow */ + /* line-by-line wrapping and to allow simultaneous rendering by the HW. */ + + while (height--) + { + /* UPDATE THE COMMAND POINTER */ + /* The WRITE_COMMANDXX macros use a pointer to the current buffer space. */ + /* This is created by adding gp3_cmd_current to the base pointer. */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + size_dwords; + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + /* WAIT FOR HARDWARE */ + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_CH3_HOST_SOURCE_TYPE | total_dwords); + + /* WRITE DATA */ + + WRITE_COMMAND_STRING32 (8, data, srcoffset, dword_count); + WRITE_COMMAND_STRING8 (8 + (dword_count << 2), data, + srcoffset + (dword_count << 2), byte_count); + + /* UPDATE POINTERS */ + + srcoffset += pitch; + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } + } +} + +/*--------------------------------------------------------------------------- + * gp_custom_convert_blt + * + * This routine is identical to gp_color_convert_blt, except that the macro + * to write data to the frame buffer has been replaced with a new macro. This + * allows a user to implement custom behavior when sending data, such as manually + * converting 24BPP to 32BPP, converting 2BPP to 4BPP or premultiplying alpha data. + *-------------------------------------------------------------------------*/ + +void gp_custom_convert_blt (unsigned long dstoffset, unsigned long srcx, + unsigned long width, unsigned long height, unsigned char *data, long pitch) +{ + unsigned long indent, temp; + unsigned long total_dwords, size_dwords; + unsigned long dword_count, byte_count; + unsigned long size = ((width << 16) | height); + unsigned long ch3_offset, srcoffset; + unsigned long ch3_size, base; + + /* ASSUME BITMAPS ARE DWORD ALIGNED */ + /* We will offset into the source data in DWORD increments. We */ + /* set the source index to the remaining byte offset and */ + /* increment the size of each line to account for the dont-care */ + /* pixel(s). For 4BPP source data, we also set the appropriate */ + /* nibble index. */ + + /* CALCULATE THE SIZE OF ONE LINE */ + + if ((gp3_src_format & GP3_CH3_SRC_MASK) == GP3_CH3_SRC_24BPP_PACKED) + { + /* HANDLE 24BPP */ + /* Note that we do not do anything to guarantee that the source data */ + /* is DWORD aligned. The logic here is that the source data will be */ + /* cacheable, in which case Geode LX will not lose any clocks for unaligned */ + /* moves. Also note that the channel 3 width is programmed as the */ + /* number of dwords, while the normal width is programmed as the number */ + /* of pixels. */ + + srcoffset = srcx * 3; + ch3_offset = 0; + temp = width * 3; + ch3_size = (((temp + 3) >> 2) << 16) | height; + } + else + { + ch3_size = size; + + if (gp3_src_pix_shift == 3) + { + /* CALCULATE INDENT AND SOURCE OFFSET */ + + indent = (srcx >> 1); + srcoffset = (indent & ~3L); + indent &= 3; + ch3_offset = indent | ((srcx & 1) << 25); + + temp = ((width + (srcx & 1) + 1) >> 1) + indent; + } + else + { + indent = (srcx << gp3_src_pix_shift); + srcoffset = (indent & ~3L); + indent &= 3; + ch3_offset = indent; + + temp = (width << gp3_src_pix_shift) + indent; + } + } + + total_dwords = (temp + 3) >> 2; + size_dwords = (total_dwords << 2) + 8; + dword_count = (temp >> 2); + byte_count = (temp & 3); + + base = ((gp3_fb_base << 24) + (dstoffset & 0xFFC00000)) | + (gp3_base_register & ~GP3_BASE_OFFSET_DSTMASK); + + /* SET APPROPRIATE ENABLES */ + + gp3_cmd_header |= GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, (dstoffset & 0x3FFFFF) | gp3_pat_origin); + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, ch3_offset); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, size); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, ch3_size); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, + GP3_CH3_C3EN | + GP3_CH3_REPLACE_SOURCE | + GP3_CH3_HST_SRC_ENABLE | + gp3_src_format | + ((gp3_blt_flags & CIMGP_BLTFLAGS_PRES_LUT) << 20)); + WRITE_COMMAND32 (GP3_BLT_MODE, gp3_blt_mode); + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + + if (((total_dwords << 2) * height) <= GP3_BLT_1PASS_SIZE && + (gp3_cmd_bottom - gp3_cmd_current) > (GP3_BLT_1PASS_SIZE + 72)) + { + /* UPDATE THE COMMAND POINTER */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + ((total_dwords << 2) * height) + 8; + + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_CH3_HOST_SOURCE_TYPE | (total_dwords * height)); + + while (height--) + { + /* WRITE DATA */ + + WRITE_CUSTOM_COMMAND_STRING32 (8, data, srcoffset, dword_count); + WRITE_CUSTOM_COMMAND_STRING8 (8 + (dword_count << 2), data, + srcoffset + (dword_count << 2), byte_count); + + srcoffset += pitch; + cim_cmd_ptr += total_dwords << 2; + } + + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } + else + { + /* WRITE DATA LINE BY LINE */ + /* Each line will be created as a separate command buffer entry to allow */ + /* line-by-line wrapping and to allow simultaneous rendering by the HW. */ + + while (height--) + { + /* UPDATE THE COMMAND POINTER */ + /* The WRITE_COMMANDXX macros use a pointer to the current buffer space. */ + /* This is created by adding gp3_cmd_current to the base pointer. */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + size_dwords; + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + /* WAIT FOR HARDWARE */ + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_CH3_HOST_SOURCE_TYPE | total_dwords); + + /* WRITE DATA */ + + WRITE_CUSTOM_COMMAND_STRING32 (8, data, srcoffset, dword_count); + WRITE_CUSTOM_COMMAND_STRING8 (8 + (dword_count << 2), data, + srcoffset + (dword_count << 2), byte_count); + + /* UPDATE POINTERS */ + + srcoffset += pitch; + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } + } +} + +/*--------------------------------------------------------------------------- + * gp_rotate_blt + * + * This routine is called to rotate a rectangular area of video memory. The + * data may be color converted during the rotation. 'Degrees' must be a + * multiple of 90 and indicates a clockwise rotation. Width and height + * refer to the width and the height of the source. The output + * destinations will be equal to the rotated dimensions. + *-------------------------------------------------------------------------*/ + +void gp_rotate_blt (unsigned long dstoffset, unsigned long srcoffset, + unsigned long width, unsigned long height, int degrees) +{ + unsigned long sizein, sizeout; + unsigned long ch3_flags; + unsigned long base; + + base = ((gp3_fb_base << 24) + (dstoffset & 0xFFC00000)) | + ((gp3_fb_base << 4) + ((srcoffset & 0xFFC00000) >> 20)) | + (gp3_base_register & GP3_BASE_OFFSET_SRCMASK); + + srcoffset &= 0x3FFFFF; + dstoffset &= 0x3FFFFF; + + /* SET ROTATION PARAMETERS */ + + switch (degrees) + { + case 90: + srcoffset += (height - 1) * gp3_src_stride; + sizein = ((width << 16) | height); + sizeout = ((height << 16) | width); + ch3_flags = GP3_CH3_C3EN | + GP3_CH3_REPLACE_SOURCE | + GP3_CH3_ROTATE_ENABLE | + GP3_CH3_NEG_YDIR; + break; + + case 180: + srcoffset += (height - 1) * gp3_src_stride; + srcoffset += (width << gp3_src_pix_shift) - 1; + sizein = sizeout = ((width << 16) | height); + ch3_flags = GP3_CH3_C3EN | + GP3_CH3_REPLACE_SOURCE | + GP3_CH3_NEG_YDIR | + GP3_CH3_NEG_XDIR; + break; + + case 270: + srcoffset += (width << gp3_src_pix_shift) - 1; + sizein = ((width << 16) | height); + sizeout = ((height << 16) | width); + ch3_flags = GP3_CH3_C3EN | + GP3_CH3_REPLACE_SOURCE | + GP3_CH3_ROTATE_ENABLE | + GP3_CH3_NEG_XDIR; + break; + + default: + sizein = sizeout = ((width << 16) | height); + ch3_flags = GP3_CH3_C3EN | + GP3_CH3_REPLACE_SOURCE; + break; + } + + /* SET APPROPRIATE ENABLES */ + /* We override the raster mode setting with a source */ + /* copy ROP. */ + + gp3_cmd_header |= GP3_BLT_HDR_RASTER_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + /* WRITE ALL BLT REGISTERS */ + + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_bpp | 0xCC); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, dstoffset); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, sizeout); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, sizein); + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, srcoffset); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, + ch3_flags | + gp3_src_format | + ((gp3_blt_flags & CIMGP_BLTFLAGS_PRES_LUT) << 20) | + ((gp3_blt_flags & CIMGP_ENABLE_PREFETCH) << 17) | + gp3_src_stride); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base); + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_COMMAND32 (GP3_BLT_MODE, gp3_blt_mode); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; +} + +/*--------------------------------------------------------------------------- + * gp_mono_bitmap_to_screen_blt + * + * This routine expands and BLTs a monchrome bitmap that is stored in system + * memory into the framebuffer. 'data' points to an array of monochrome data. + * 'stride' indicates the pitch between successive lines of monochrome data. + * 'srcx' indicates the x coordinate within each line of blend data + * corresponding to the first pixel. A y coordinate for the source is + * deliberately omitted to avoid extra calculation for simple cases that have + * no y index. The calling program must adjust the data pointer accordingly. + *-------------------------------------------------------------------------*/ + +void gp_mono_bitmap_to_screen_blt (unsigned long dstoffset, unsigned long srcx, + unsigned long width, unsigned long height, unsigned char *data, long stride) +{ + unsigned long indent, temp; + unsigned long total_dwords, size_dwords; + unsigned long dword_count, byte_count; + unsigned long size = ((width << 16) | height); + unsigned long srcoffset, src_value; + + /* ASSUME BITMAPS ARE DWORD ALIGNED */ + /* We will offset into the source data in DWORD increments. We */ + /* set the source index to the remaining byte offset and */ + /* increment the size of each line to account for the dont-care */ + /* pixel(s). */ + + indent = (srcx >> 3); + srcoffset = (indent & ~3L); + indent &= 3; + src_value = (indent | ((srcx & 7) << 26)); + + /* PROGRAM THE NORMAL SOURCE CHANNEL REGISTERS */ + /* We assume that a color pattern is being ROPed with source */ + /* data if the pattern type is color and the preserve pattern */ + /* was set. */ + + gp3_cmd_header |= GP3_BLT_HDR_SRC_OFF_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_RASTER_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + if (gp3_ch3_pat) + { + gp3_cmd_header |= GP3_BLT_HDR_CH3_OFF_ENABLE | GP3_BLT_HDR_CH3_WIDHI_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, gp3_pat_origin); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, (dstoffset & 0x3FFFFF)); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, gp3_pat_format); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, size); + } + else + { + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, ((dstoffset & 0x3FFFFF) | gp3_pat_origin)); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, 0); + } + if (gp3_blt_flags & CIMGP_BLTFLAGS_INVERTMONO) + { + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_raster_mode | GP3_RM_SOURCE_INVERT); + } + else + { + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_raster_mode & ~GP3_RM_SOURCE_INVERT); + } + WRITE_COMMAND32 (GP3_BLT_SRC_OFFSET, src_value); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, size); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, + ((gp3_fb_base << 24) + (dstoffset & 0xFFC00000))); + WRITE_COMMAND32 (GP3_BLT_MODE, gp3_blt_mode | GP3_BM_SRC_HOST | GP3_BM_SRC_MONO); + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + + /* CALCULATE THE SIZE OF ONE LINE */ + + size = ((width + (srcx & 7) + 7) >> 3) + indent; + total_dwords = (size + 3) >> 2; + size_dwords = (total_dwords << 2) + 8; + dword_count = (size >> 2); + byte_count = (size & 3); + + /* CHECK FOR SMALL BLT CASE */ + /* If the total amount of monochrome data is less than 50K and we have */ + /* room in the command buffer, we will do all data writes in a single */ + /* data packet. */ + + if (((total_dwords << 2) * height) <= GP3_BLT_1PASS_SIZE && + (gp3_cmd_bottom - gp3_cmd_current) > (GP3_BLT_1PASS_SIZE + 72)) + { + /* UPDATE THE COMMAND POINTER */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + ((total_dwords << 2) * height) + 8; + + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_HOST_SOURCE_TYPE | (total_dwords * height)); + + while (height--) + { + /* WRITE DATA */ + + WRITE_COMMAND_STRING32 (8, data, srcoffset, dword_count); + WRITE_COMMAND_STRING8 (8 + (dword_count << 2), data, + srcoffset + (dword_count << 2), byte_count); + + srcoffset += stride; + cim_cmd_ptr += total_dwords << 2; + } + + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } + else + { + /* WRITE DATA LINE BY LINE */ + /* Each line will be created as a separate command buffer entry to allow */ + /* line-by-line wrapping and to allow simultaneous rendering by the HW. */ + + while (height--) + { + /* UPDATE THE COMMAND POINTER */ + /* The WRITE_COMMANDXX macros use a pointer to the current buffer space. */ + /* This is created by adding gp3_cmd_current to the base pointer. */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + size_dwords; + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + /* WAIT FOR HARDWARE */ + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_HOST_SOURCE_TYPE | total_dwords); + + /* WRITE DATA */ + + WRITE_COMMAND_STRING32 (8, data, srcoffset, dword_count); + WRITE_COMMAND_STRING8 (8 + (dword_count << 2), data, + srcoffset + (dword_count << 2), byte_count); + + /* UPDATE POINTERS */ + + srcoffset += stride; + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } + } +} + +/*--------------------------------------------------------------------------- + * gp_text_blt + * + * This routine expands and BLTs byte-packed monochrome data to the screen. + * There is assumed to be no x clipping involved in the BLT. + *-------------------------------------------------------------------------*/ + +void gp_text_blt (unsigned long dstoffset, unsigned long width, + unsigned long height, unsigned char *data) +{ + unsigned long temp, dwords_total; + unsigned long dword_count, byte_count; + unsigned long size = ((width << 16) | height); + unsigned long srcoffset = 0; + + /* PROGRAM THE NORMAL SOURCE CHANNEL REGISTERS */ + /* We assume that a color pattern is being ROPed with source */ + /* data if the pattern type is color and the preserve pattern */ + /* was set. */ + + gp3_cmd_header |= GP3_BLT_HDR_SRC_OFF_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_RASTER_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + if (gp3_ch3_pat) + { + gp3_cmd_header |= GP3_BLT_HDR_CH3_OFF_ENABLE | GP3_BLT_HDR_CH3_WIDHI_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, gp3_pat_origin); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, (dstoffset & 0x3FFFFF)); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, gp3_pat_format); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, size); + } + else + { + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, ((dstoffset & 0x3FFFFF) | gp3_pat_origin)); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, 0); + } + if (gp3_blt_flags & CIMGP_BLTFLAGS_INVERTMONO) + { + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_raster_mode | GP3_RM_SOURCE_INVERT); + } + else + { + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_raster_mode & ~GP3_RM_SOURCE_INVERT); + } + + WRITE_COMMAND32 (GP3_BLT_SRC_OFFSET, 0); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, size); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, + ((gp3_fb_base << 24) + (dstoffset & 0xFFC00000))); + WRITE_COMMAND32 (GP3_BLT_MODE, gp3_blt_mode | GP3_BM_SRC_HOST | GP3_BM_SRC_BP_MONO); + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + + /* CALCULATE THE TOTAL NUMBER OF BYTES */ + + size = ((width + 7) >> 3) * height; + + /* WRITE ALL DATA IN CHUNKS */ + + do + { + /* UPDATE THE COMMAND POINTER */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + if (size > 8192) + { + dword_count = 2048; + byte_count = 0; + dwords_total = 2048; + size -= 8192; + } + else + { + dword_count = (size >> 2); + byte_count = (size & 3); + dwords_total = (size + 3) >> 2; + size = 0; + } + gp3_cmd_next = gp3_cmd_current + (dwords_total << 2) + 8; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + /* WAIT FOR HARDWARE */ + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_HOST_SOURCE_TYPE | dwords_total); + + /* WRITE DATA */ + + WRITE_COMMAND_STRING32 (8, data, srcoffset, dword_count); + WRITE_COMMAND_STRING8 (8 + (dword_count << 2), data, + srcoffset + (dword_count << 2), byte_count); + + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + + /* UPDATE THE SOURCE OFFSET */ + /* We add a constant value because the code will loop only if the */ + /* data exceeds 8192 bytes. */ + + srcoffset += 8192; + + } while (size); +} + +/*--------------------------------------------------------------------------- + * gp_mono_expand_blt + * + * This routine expands monochrome data that is stored in video memory into + * the current BPP. The source and destination regions are assumed not to + * overlap. The pitch of the source data is specified in gp_set_strides. + * 'srcy' is deliberately omitted to prevent extra calculations for simple + * applications that have no source indexes. + *-------------------------------------------------------------------------*/ + +void gp_mono_expand_blt (unsigned long dstoffset, unsigned long srcoffset, + unsigned long srcx, unsigned long width, unsigned long height, int byte_packed) +{ + unsigned long base; + unsigned long blt_mode; + unsigned long size = ((width << 16) | height); + + /* ADJUST SOURCE OFFSET */ + + srcoffset += (srcx >> 3); + srcx &= 7; + + /* CALCULATE BASE OFFSET REGISTER */ + + base = ((gp3_fb_base << 24) + (dstoffset & 0xFFC00000)) | + ((gp3_fb_base << 14) + ((srcoffset & 0xFFC00000) >> 10)) | + (gp3_base_register & GP3_BASE_OFFSET_CH3MASK); + + /* SET THE SOURCE TYPE */ + + if (byte_packed) + blt_mode = gp3_blt_mode | GP3_BM_SRC_FB | GP3_BM_SRC_BP_MONO; + else + blt_mode = gp3_blt_mode | GP3_BM_SRC_FB | GP3_BM_SRC_MONO; + + /* SET HEADER ENABLES */ + + gp3_cmd_header |= GP3_BLT_HDR_SRC_OFF_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_RASTER_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + /* ENABLE COLOR PATTERN IF APPLICABLE */ + + if (gp3_ch3_pat) + { + gp3_cmd_header |= GP3_BLT_HDR_CH3_OFF_ENABLE | GP3_BLT_HDR_CH3_WIDHI_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, gp3_pat_origin); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, (dstoffset & 0x3FFFFF)); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, gp3_pat_format); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, size); + } + else + { + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, ((dstoffset & 0x3FFFFF) | gp3_pat_origin)); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, 0); + } + if (gp3_blt_flags & CIMGP_BLTFLAGS_INVERTMONO) + { + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_raster_mode | GP3_RM_SOURCE_INVERT); + } + else + { + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_raster_mode & ~GP3_RM_SOURCE_INVERT); + } + + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base); + WRITE_COMMAND32 (GP3_BLT_SRC_OFFSET, + (srcoffset & 0x3FFFFF) | (srcx << 26)); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, size); + + /* WORKAROUND FOR SIBZ #3744 */ + /* Under extremely rare conditions, very narrow byte-packed mono BLTs can hang */ + /* the GP. Even under the rare case, the bad condition will only happen */ + /* once every 16 lines. The workaround is to break the offending BLT into a */ + /* a series of safer BLTs. This method is preferred over a two-pass approach */ + /* because it does not require saving and restoring any GP state, such as the */ + /* ROP or mono colors. */ + + if ((gp3_blt_mode & GP3_BM_DST_REQ) && byte_packed && (gp3_pix_shift < 2) && + (width < 5) && ((srcoffset & 0x1F) == 0x1F) && ((srcx + width) > 8)) + { + unsigned long dstoff1, size1, org1; + unsigned long dstoff2, size2, org2; + unsigned long tempheight; + + size1 = ((8 - srcx) << 16) | 1; + size2 = ((width + srcx - 8) << 16) | 1; + org1 = gp3_pat_origin; + org2 = (org1 & 0xE0000000) | ((org1 + ((8 - srcx) << 26)) & 0x1C000000); + dstoff1 = dstoffset & 0x3FFFFF; + dstoff2 = (dstoff1 + 8 - srcx) << gp3_pix_shift; + + while (height) + { + /* DIVIDE THE FIRST LINE INTO TWO SINGLE LINE BLTS */ + + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, size1); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, size1); + WRITE_COMMAND32 (GP3_BLT_SRC_OFFSET, (srcoffset & 0x3FFFFF) | (srcx << 26)); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, dstoff1 | org1); + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, org1); + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_COMMAND32 (GP3_BLT_MODE, blt_mode); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + gp_wait_until_idle(); + + gp_declare_blt (gp3_blt_flags); + gp3_cmd_header |= GP3_BLT_HDR_SRC_OFF_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE; + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, size2); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, size2); + WRITE_COMMAND32 (GP3_BLT_SRC_OFFSET, ((srcoffset + 1) & 0x3FFFFF)); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, dstoff2 | org2); + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, org2); + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_COMMAND32 (GP3_BLT_MODE, blt_mode); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + gp_wait_until_idle(); + + if (--height) + { + org1 += 0x20000000; + org2 += 0x20000000; + dstoff1 += gp3_dst_stride; + dstoff2 += gp3_dst_stride; + srcoffset += 2; + + /* THE NEXT 15 LINES ARE NOW 'SAFE' - THEY DO NOT SHOW THE PROBLEM */ + + tempheight = 15; + if (tempheight > height) + tempheight = height; + + gp_declare_blt (gp3_blt_flags); + gp3_cmd_header |= GP3_BLT_HDR_SRC_OFF_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE; + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, (width << 16) | tempheight); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, (width << 16) | tempheight); + WRITE_COMMAND32 (GP3_BLT_SRC_OFFSET, (srcoffset & 0x3FFFFF) | (srcx << 26)); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, dstoff1 | org1); + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, org1); + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_COMMAND32 (GP3_BLT_MODE, blt_mode); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + gp_wait_until_idle(); + + height -= tempheight; + + if (height) + { + gp_declare_blt (gp3_blt_flags); + gp3_cmd_header |= GP3_BLT_HDR_SRC_OFF_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE; + + /* ADJUST ORIGIN */ + /* If we get here, we added a full 15 lines which is equivalent */ + /* to subtracting one from the pattern y origin (adding 15). */ + + org1 -= 0x20000000; + org2 -= 0x20000000; + dstoff1 += (gp3_dst_stride * 15); + dstoff2 += (gp3_dst_stride * 15); + srcoffset += 30; + } + } + } + return; + } + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_COMMAND32 (GP3_BLT_MODE, blt_mode); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; +} + +/*--------------------------------------------------------------------------- + * gp_antialiased_text + * + * This routine implements alpha blending between a constant source color and + * a destination region. The degree of the blend is controlled by an array + * of 4BPP/8BPP values specified in 'data'. 'stride' indicates the pitch between + * successive lines of blend data. 'srcx' indicates the x coordinate within + * each line of blend data corresponding to the first pixel. A y coordinate + * for the source is deliberately omitted to avoid extra calculation for simple + * cases that have no y index. The calling program must adjust the data + * pointer accordingly. 'fourbpp' selects between 4BPP and 8BPP alpha. + *-------------------------------------------------------------------------*/ + +void gp_antialiased_text (unsigned long dstoffset, unsigned long srcx, + unsigned long width, unsigned long height, unsigned char *data, long stride, + int fourbpp) +{ + unsigned long indent, temp; + unsigned long total_dwords, size_dwords; + unsigned long dword_count, byte_count; + unsigned long size = ((width << 16) | height); + unsigned long ch3_offset, srcoffset; + unsigned long base, depth_flag; + + base = ((gp3_fb_base << 24) + (dstoffset & 0xFFC00000)) | + (gp3_base_register & ~GP3_BASE_OFFSET_DSTMASK); + + /* ENABLE ALL RELEVANT REGISTERS */ + /* We override the raster mode register to force the */ + /* correct alpha blend */ + + gp3_cmd_header |= GP3_BLT_HDR_RASTER_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + /* CALCULATIONS BASED ON ALPHA DEPTH */ + /* Although most antialiased text is 4BPP, the hardware supports */ + /* a full 8BPP. Either case is supported by this routine. */ + + if (fourbpp) + { + depth_flag = GP3_CH3_SRC_4BPP_ALPHA; + indent = (srcx >> 1); + srcoffset = (indent & ~3L); + indent &= 3; + ch3_offset = indent | ((srcx & 1) << 25); + + temp = ((width + (srcx & 1) + 1) >> 1) + indent; + } + else + { + depth_flag = GP3_CH3_SRC_8BPP_ALPHA; + indent = srcx; + srcoffset = (indent & ~3L); + indent &= 3; + ch3_offset = indent; + + temp = width + indent; + } + + total_dwords = (temp + 3) >> 2; + size_dwords = (total_dwords << 2) + 8; + dword_count = (temp >> 2); + byte_count = (temp & 3); + + /* SET RASTER MODE REGISTER */ + /* Alpha blending will only apply to RGB when no alpha component is present. */ + /* As 8BPP is not supported for this routine, the only alpha-less mode is */ + /* 5:6:5. */ + + if (gp3_bpp == GP3_RM_BPPFMT_565) + { + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, + gp3_bpp | + GP3_RM_ALPHA_TO_RGB | + GP3_RM_ALPHA_A_PLUS_BETA_B | + GP3_RM_SELECT_ALPHA_CHAN_3); + } + else + { + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, + gp3_bpp | + GP3_RM_ALPHA_ALL | + GP3_RM_ALPHA_A_PLUS_BETA_B | + GP3_RM_SELECT_ALPHA_CHAN_3); + } + + /* WRITE ALL REMAINING REGISTERS */ + + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, (dstoffset & 0x3FFFFF)); + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, ch3_offset); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, size); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, size); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, + GP3_CH3_C3EN | + GP3_CH3_HST_SRC_ENABLE | + depth_flag | + ((gp3_blt_flags & CIMGP_BLTFLAGS_PRES_LUT) << 20)); + WRITE_COMMAND32 (GP3_BLT_MODE, gp3_blt_mode | GP3_BM_DST_REQ); + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + + /* WRITE DATA LINE BY LINE */ + /* Each line will be created as a separate command buffer entry to allow */ + /* line-by-line wrapping and to allow simultaneous rendering by the HW. */ + + if (((total_dwords << 2) * height) <= GP3_BLT_1PASS_SIZE && + (gp3_cmd_bottom - gp3_cmd_current) > (GP3_BLT_1PASS_SIZE + 72)) + { + /* UPDATE THE COMMAND POINTER */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + ((total_dwords << 2) * height) + 8; + + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_CH3_HOST_SOURCE_TYPE | (total_dwords * height)); + + while (height--) + { + /* WRITE DATA */ + + WRITE_COMMAND_STRING32 (8, data, srcoffset, dword_count); + WRITE_COMMAND_STRING8 (8 + (dword_count << 2), data, + srcoffset + (dword_count << 2), byte_count); + + srcoffset += stride; + cim_cmd_ptr += total_dwords << 2; + } + + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } + else + { + while (height--) + { + /* UPDATE THE COMMAND POINTER */ + /* The WRITE_COMMANDXX macros use a pointer to the current buffer space. */ + /* This is created by adding gp3_cmd_current to the base pointer. */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + size_dwords; + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + /* WAIT FOR HARDWARE */ + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_CH3_HOST_SOURCE_TYPE | total_dwords); + + /* WRITE DATA */ + + WRITE_COMMAND_STRING32 (8, data, srcoffset, dword_count); + WRITE_COMMAND_STRING8 (8 + (dword_count << 2), data, + srcoffset + (dword_count << 2), byte_count); + + /* UPDATE POINTERS */ + + srcoffset += stride; + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } + } +} + +/*--------------------------------------------------------------------------- + * gp_masked_blt + * + * This routine copies source data to the screen. A monochrome mask is used + * to specify source transparency. + *-------------------------------------------------------------------------*/ + +void gp_masked_blt (unsigned long dstoffset, unsigned long width, + unsigned long height, unsigned long mono_srcx, unsigned long color_srcx, + unsigned char *mono_mask, unsigned char *color_data, long mono_pitch, + long color_pitch) +{ + unsigned long indent, temp; + unsigned long total_dwords, size_dwords; + unsigned long dword_count, byte_count; + unsigned long srcoffset, size; + unsigned long i, ch3_offset, base; + unsigned long flags = 0; + + if (gp3_blt_flags & CIMGP_BLTFLAGS_INVERTMONO) + flags = GP3_RM_SOURCE_INVERT; + + /* MONO CALCULATIONS */ + + indent = (mono_srcx >> 3); + srcoffset = (indent & ~3L); + indent &= 3; + + size = ((width + (mono_srcx & 7) + 7) >> 3) + indent; + total_dwords = (size + 3) >> 2; + size_dwords = (total_dwords << 2) + 8; + dword_count = (size >> 2); + byte_count = (size & 3); + + base = ((gp3_fb_base << 24) + (gp3_scratch_base & 0xFFC00000)) | + (gp3_base_register & ~GP3_BASE_OFFSET_DSTMASK); + + gp3_cmd_header |= GP3_BLT_HDR_RASTER_ENABLE | + GP3_BLT_HDR_STRIDE_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, GP3_RM_BPPFMT_8888 | 0xCC); + WRITE_COMMAND32 (GP3_BLT_STRIDE, (total_dwords << 2)); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, gp3_scratch_base & 0x3FFFFF); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, (total_dwords << 16) | height); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, (total_dwords << 16) | height); + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, 0); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, + GP3_CH3_C3EN | + GP3_CH3_REPLACE_SOURCE | + GP3_CH3_HST_SRC_ENABLE | + GP3_CH3_SRC_8_8_8_8 | + ((gp3_blt_flags & CIMGP_BLTFLAGS_PRES_LUT) << 20)); + WRITE_COMMAND32 (GP3_BLT_MODE, 0); + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + + /* START THE BLT */ + + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + + for (i = 0; i < height; i++) + { + /* UPDATE THE COMMAND POINTER */ + /* The WRITE_COMMANDXX macros use a pointer to the current buffer space. */ + /* This is created by adding gp3_cmd_current to the base pointer. */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + size_dwords; + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + /* WAIT FOR HARDWARE */ + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_CH3_HOST_SOURCE_TYPE | total_dwords); + + /* WRITE DATA */ + + WRITE_COMMAND_STRING32 (8, mono_mask, srcoffset, dword_count); + WRITE_COMMAND_STRING8 (8 + (dword_count << 2), mono_mask, + srcoffset + (dword_count << 2), byte_count); + + /* UPDATE POINTERS */ + + srcoffset += mono_pitch; + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } + + /* SECOND BLT */ + + gp_declare_blt (gp3_blt_flags | CIMGP_BLTFLAGS_HAZARD); + + base = ((gp3_fb_base << 24) + (dstoffset & 0xFFC00000)) | + ((gp3_fb_base << 14) + (((gp3_scratch_base + indent) & 0xFFC00000) >> 10)) | + (gp3_base_register & GP3_BASE_OFFSET_CH3MASK); + + gp3_cmd_header |= GP3_BLT_HDR_RASTER_ENABLE | + GP3_BLT_HDR_STRIDE_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_SRC_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + /* ENABLE TRANSPARENCY AND PATTERN COPY ROP */ + /* The monochrome data is used as a mask but is otherwise not involved in */ + /* the BLT. The color data is routed through the pattern channel. */ + + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_bpp | 0xF0 | GP3_RM_SRC_TRANS | flags); + WRITE_COMMAND32 (GP3_BLT_STRIDE, (total_dwords << 18) | gp3_dst_stride); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, dstoffset & 0x3FFFFF); + WRITE_COMMAND32 (GP3_BLT_SRC_OFFSET, + ((gp3_scratch_base + indent) & 0x3FFFFF ) | ((mono_srcx & 7) << 26)); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, (width << 16) | height); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, (width << 16) | height); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base); + + /* PROGRAM PARAMETERS FOR COLOR SOURCE DATA */ + /* Data may be color converted along the way. */ + + if ((gp3_src_format & GP3_CH3_SRC_MASK) == GP3_CH3_SRC_24BPP_PACKED) + { + srcoffset = color_srcx * 3; + ch3_offset = 0; + size = width * 3; + + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, (((size + 3) >> 2) << 16) | height); + } + else if (gp3_src_pix_shift == 3) + { + /* CALCULATE INDENT AND SOURCE OFFSET */ + + indent = (color_srcx >> 1); + srcoffset = (indent & ~3L); + indent &= 3; + ch3_offset = indent | ((color_srcx & 1) << 25); + + size = ((width + (color_srcx & 1) + 1) >> 1) + indent; + } + else + { + indent = (color_srcx << gp3_src_pix_shift); + srcoffset = (indent & ~3L); + indent &= 3; + ch3_offset = indent; + + size = (width << gp3_src_pix_shift) + indent; + } + + total_dwords = (size + 3) >> 2; + size_dwords = (total_dwords << 2) + 8; + dword_count = (size >> 2); + byte_count = (size & 3); + + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, ch3_offset); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, + GP3_CH3_C3EN | + GP3_CH3_HST_SRC_ENABLE | + gp3_src_format | + ((gp3_blt_flags & CIMGP_BLTFLAGS_PRES_LUT) << 20)); + WRITE_COMMAND32 (GP3_BLT_MODE, gp3_blt_mode | GP3_BM_SRC_MONO | GP3_BM_SRC_FB); + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + + /* WRITE DATA LINE BY LINE */ + + while (height--) + { + /* UPDATE THE COMMAND POINTER */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + size_dwords; + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_CH3_HOST_SOURCE_TYPE | total_dwords); + + /* WRITE COLOR DATA TO THE COMMAND BUFFER */ + + WRITE_COMMAND_STRING32 (8, color_data, srcoffset, dword_count); + WRITE_COMMAND_STRING8 (8 + (dword_count << 2), color_data, + srcoffset + (dword_count << 2), byte_count); + + /* UPDATE COMMAND BUFFER POINTERS */ + /* We do this before writing the monochrome data because otherwise */ + /* the GP could throttle the writes to the host source register */ + /* waiting for color data. If the command buffer has not been */ + /* updated to load the color data... */ + + srcoffset += color_pitch; + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } +} + +/*--------------------------------------------------------------------------- + * gp_screen_to_screen_masked + * + * This routine performs a screen to screen BLT, using a monochrome mask to + * specify source transparency. The source data is assumed to be in the + * current destination format and to not overlap the destination. + *-------------------------------------------------------------------------*/ + +void gp_screen_to_screen_masked (unsigned long dstoffset, unsigned long srcoffset, + unsigned long width, unsigned long height, unsigned long mono_srcx, + unsigned char *mono_mask, long mono_pitch) +{ + unsigned long indent, temp; + unsigned long total_dwords, size_dwords; + unsigned long dword_count, byte_count; + unsigned long srcoff, size; + unsigned long i, base; + unsigned long flags = 0; + + if (gp3_blt_flags & CIMGP_BLTFLAGS_INVERTMONO) + flags = GP3_RM_SOURCE_INVERT; + + /* MONO CALCULATIONS */ + + indent = (mono_srcx >> 3); + srcoff = (indent & ~3L); + indent &= 3; + + size = ((width + (mono_srcx & 7) + 7) >> 3) + indent; + total_dwords = (size + 3) >> 2; + size_dwords = (total_dwords << 2) + 8; + dword_count = (size >> 2); + byte_count = (size & 3); + + base = ((gp3_fb_base << 24) + (gp3_scratch_base & 0xFFC00000)) | + (gp3_base_register & ~GP3_BASE_OFFSET_DSTMASK); + + gp3_cmd_header |= GP3_BLT_HDR_RASTER_ENABLE | + GP3_BLT_HDR_STRIDE_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, GP3_RM_BPPFMT_8888 | 0xCC); + WRITE_COMMAND32 (GP3_BLT_STRIDE, (total_dwords << 2)); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, gp3_scratch_base & 0x3FFFFF); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, (total_dwords << 16) | height); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, (total_dwords << 16) | height); + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, 0); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, + GP3_CH3_C3EN | + GP3_CH3_REPLACE_SOURCE | + GP3_CH3_HST_SRC_ENABLE | + GP3_CH3_SRC_8_8_8_8 | + ((gp3_blt_flags & CIMGP_BLTFLAGS_PRES_LUT) << 20)); + WRITE_COMMAND32 (GP3_BLT_MODE, 0); + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + + /* START THE BLT */ + + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + + for (i = 0; i < height; i++) + { + /* UPDATE THE COMMAND POINTER */ + /* The WRITE_COMMANDXX macros use a pointer to the current buffer space. */ + /* This is created by adding gp3_cmd_current to the base pointer. */ + + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + /* CHECK IF A WRAP WILL BE NEEDED */ + + gp3_cmd_next = gp3_cmd_current + size_dwords; + if ((gp3_cmd_bottom - gp3_cmd_next) <= GP3_MAX_COMMAND_SIZE) + { + gp3_cmd_next = gp3_cmd_top; + + /* WAIT FOR HARDWARE */ + + GP3_WAIT_WRAP(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_WRAP | + GP3_DATA_LOAD_HDR_ENABLE); + } + else + { + /* WAIT FOR AVAILABLE SPACE */ + + GP3_WAIT_PRIMITIVE(temp); + WRITE_COMMAND32 (0, GP3_DATA_LOAD_HDR_TYPE | GP3_DATA_LOAD_HDR_ENABLE); + } + + /* WRITE DWORD COUNT */ + + WRITE_COMMAND32 (4, GP3_CH3_HOST_SOURCE_TYPE | total_dwords); + + /* WRITE DATA */ + + WRITE_COMMAND_STRING32 (8, mono_mask, srcoff, dword_count); + WRITE_COMMAND_STRING8 (8 + (dword_count << 2), mono_mask, + srcoff + (dword_count << 2), byte_count); + + /* UPDATE POINTERS */ + + srcoff += mono_pitch; + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + } + + /* SECOND BLT */ + + gp_declare_blt (gp3_blt_flags | CIMGP_BLTFLAGS_HAZARD); + + base = ((gp3_fb_base << 24) + (dstoffset & 0xFFC00000)) | + ((gp3_fb_base << 14) + (((gp3_scratch_base + indent) & 0xFFC00000) >> 10)) | + ((gp3_fb_base << 4) + ((srcoffset & 0xFFC00000) >> 20)); + + gp3_cmd_header |= GP3_BLT_HDR_RASTER_ENABLE | + GP3_BLT_HDR_STRIDE_ENABLE | + GP3_BLT_HDR_DST_OFF_ENABLE | + GP3_BLT_HDR_SRC_OFF_ENABLE | + GP3_BLT_HDR_WIDHI_ENABLE | + GP3_BLT_HDR_CH3_STR_ENABLE | + GP3_BLT_HDR_CH3_WIDHI_ENABLE | + GP3_BLT_HDR_BASE_OFFSET_ENABLE | + GP3_BLT_HDR_CH3_OFF_ENABLE | + GP3_BLT_HDR_BLT_MODE_ENABLE; + + /* ENABLE TRANSPARENCY AND PATTERN COPY ROP */ + /* The monochrome data is used as a mask but is otherwise not involved in */ + /* the BLT. The color data is routed through the pattern channel. */ + + WRITE_COMMAND32 (GP3_BLT_RASTER_MODE, gp3_bpp | 0xF0 | GP3_RM_SRC_TRANS | flags); + WRITE_COMMAND32 (GP3_BLT_STRIDE, (total_dwords << 18) | gp3_dst_stride); + WRITE_COMMAND32 (GP3_BLT_DST_OFFSET, dstoffset & 0x3FFFFF); + WRITE_COMMAND32 (GP3_BLT_SRC_OFFSET, + ((gp3_scratch_base + indent) & 0x3FFFFF ) | ((mono_srcx & 7) << 26)); + WRITE_COMMAND32 (GP3_BLT_WID_HEIGHT, (width << 16) | height); + WRITE_COMMAND32 (GP3_BLT_CH3_WIDHI, (width << 16) | height); + WRITE_COMMAND32 (GP3_BLT_BASE_OFFSET, base); + + /* PROGRAM PARAMETERS FOR COLOR SOURCE DATA */ + + WRITE_COMMAND32 (GP3_BLT_CH3_OFFSET, srcoffset & 0x3FFFFF); + WRITE_COMMAND32 (GP3_BLT_CH3_MODE_STR, + GP3_CH3_C3EN | + gp3_ch3_bpp | + gp3_src_stride | + ((gp3_blt_flags & CIMGP_BLTFLAGS_PRES_LUT) << 20)); + WRITE_COMMAND32 (GP3_BLT_MODE, gp3_blt_mode | GP3_BM_SRC_MONO | GP3_BM_SRC_FB); + + /* START THE BLT */ + + WRITE_COMMAND32 (GP3_BLT_CMD_HEADER, gp3_cmd_header); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; +} + +/*--------------------------------------------------------------------------- + * gp_bresenham_line + * + * This routine draws a vector using the specified Bresenham parameters. + * Currently this file does not support a routine that accepts the two + * endpoints of a vector and calculates the Bresenham parameters. If it + * ever does, this routine is still required for vectors that have been + * clipped. + *-------------------------------------------------------------------------*/ + +void gp_bresenham_line (unsigned long dstoffset, unsigned short length, + unsigned short initerr, unsigned short axialerr, unsigned short diagerr, + unsigned long flags) +{ + unsigned long base; + long offset; + + /* HANDLE NEGATIVE VECTORS */ + /* We have to be very careful with vectors that increment negatively */ + /* Our framebuffer scheme tries to align the destination of every */ + /* BLT or vector to the nearest 4MB-aligned boundary. This is */ + /* necessary because the GP only supports offsets up to 16MB, but the */ + /* framebuffer can be over 128MB. To solve this problem, the GP */ + /* base address registers are alignable to 4MB regions. However, we */ + /* cannot simply align the dest offset when the vector goes negative. */ + /* The vector offset could underflow, causing the offset to jump from */ + /* near 0 to 16MB. As we cannot accurately determine the last address */ + /* that will be written in a vector short of walking the algorithm in */ + /* software, we do a worst case approximation. */ + + offset = dstoffset; + if (!(flags & CIMGP_POSMAJOR)) + { + if (flags & CIMGP_YMAJOR) + offset -= length * gp3_dst_stride; + else + offset -= (length << gp3_pix_shift); + + if (offset < 0) + offset = 0; + } + if (!(flags & CIMGP_POSMINOR)) + { + if (flags & CIMGP_YMAJOR) + offset -= (length << gp3_pix_shift); + else + offset -= length * gp3_dst_stride; + + if (offset < 0) + offset = 0; + } + + offset &= 0xFFC00000; + dstoffset -= offset; + + base = ((gp3_fb_base << 24) + offset) | + (gp3_base_register & ~GP3_BASE_OFFSET_DSTMASK); + + /* ENABLE RELEVANT REGISTERS */ + /* Note that we always enable and write the channel 3 mode, if only */ + /* to turn it off. Cimarron also always writes the base offset */ + /* register to allow operation with frame buffers larger than 16MB. */ + + gp3_cmd_header |= GP3_VEC_HDR_DST_OFF_ENABLE | + GP3_VEC_HDR_VEC_ERR_ENABLE | + GP3_VEC_HDR_VEC_LEN_ENABLE | + GP3_VEC_HDR_BASE_OFFSET_ENABLE | + GP3_VEC_HDR_CH3_STR_ENABLE | + GP3_VEC_HDR_VEC_MODE_ENABLE; + + /* WRITE THE REGISTERS COMMON TO ALL PATTERN TYPES */ + /* The destination base is the frame buffer base plus whatever */ + /* 4MB segment we happen to be drawing to. */ + + WRITE_COMMAND32 (GP3_VECTOR_VEC_ERR, + (((unsigned long)axialerr << 16) | (unsigned long)diagerr)); + WRITE_COMMAND32 (GP3_VECTOR_VEC_LEN, + (((unsigned long)length << 16) | (unsigned long)initerr)); + WRITE_COMMAND32 (GP3_VECTOR_BASE_OFFSET, base); + + /* CHECK VECTOR PATTERN CASE */ + + if (gp3_ch3_pat) + { + /* SET THE SOLID COLOR */ + /* The color for vector patterns from channel 3 comes from */ + /* the regular pattern registers. */ + + gp3_cmd_header |= GP3_VEC_HDR_PAT_CLR0_ENABLE; + + WRITE_COMMAND32 (GP3_VECTOR_PAT_COLOR_0, gp3_vector_pattern_color); + + /* INITIALIZE CHANNEL 3 PARAMETERS */ + /* We route the channel 3 output to the old source channel. If the user */ + /* sets a ROP that involves source, they will get unexpected results. */ + + WRITE_COMMAND32 (GP3_VECTOR_DST_OFFSET, dstoffset); + WRITE_COMMAND32 (GP3_VECTOR_CH3_MODE_STR, + GP3_CH3_C3EN | GP3_CH3_REPLACE_SOURCE | GP3_CH3_COLOR_PAT_ENABLE | GP3_CH3_SRC_8_8_8_8); + } + else + { + /* DISABLE CHANNEL 3 AND USE NORMAL PATTERN ORIGINS */ + + WRITE_COMMAND32 (GP3_VECTOR_CH3_MODE_STR, 0); + WRITE_COMMAND32 (GP3_VECTOR_DST_OFFSET, (dstoffset | gp3_pat_origin)); + } + + /* START THE VECTOR */ + + WRITE_COMMAND32 (GP3_VEC_CMD_HEADER, gp3_cmd_header); + WRITE_COMMAND32 (GP3_VECTOR_MODE, (gp3_vec_mode | flags)); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + + gp3_cmd_current = gp3_cmd_next; + + /* ADD A SECOND VECTOR TO CLEAR THE BYTE ENABLES */ + /* We set a transparent pattern to clear the byte enables. */ + /* We then restore the previous pattern. (SiBZ #4001) */ + + if (gp3_ch3_pat) + { + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + WRITE_COMMAND32 (0, GP3_LUT_HDR_TYPE | GP3_LUT_HDR_DATA_ENABLE); + WRITE_COMMAND32 (4, 0x100); + WRITE_COMMAND32 (8, (1 | GP3_LUT_DATA_TYPE)); + WRITE_COMMAND32 (12, 0); + + /* DUMMY VECTOR */ + /* We shouldn't need to write anything but vector mode and the length. */ + + WRITE_COMMAND32 (16, GP3_VEC_HDR_TYPE | GP3_VEC_HDR_VEC_MODE_ENABLE | + GP3_VEC_HDR_VEC_LEN_ENABLE); + WRITE_COMMAND32 (16 + GP3_VECTOR_MODE, (gp3_vec_mode | flags)); + WRITE_COMMAND32 (16 + GP3_VECTOR_VEC_LEN, (1 << 16) | (unsigned long)initerr); + + WRITE_COMMAND32 (16 + GP3_VECTOR_COMMAND_SIZE, GP3_LUT_HDR_TYPE | GP3_LUT_HDR_DATA_ENABLE); + WRITE_COMMAND32 (20 + GP3_VECTOR_COMMAND_SIZE, 0x100); + WRITE_COMMAND32 (24 + GP3_VECTOR_COMMAND_SIZE, (1 | GP3_LUT_DATA_TYPE)); + WRITE_COMMAND32 (28 + GP3_VECTOR_COMMAND_SIZE, gp3_vec_pat); + + gp3_cmd_current += 32 + GP3_VECTOR_COMMAND_SIZE; + } +} + +/*--------------------------------------------------------------------------- + * gp_line_from_endpoints + * + * This routine draws a vector from a set of rectangular coordinates. The + * rectangle is assumed to use the currently specified destination stride. + *-------------------------------------------------------------------------*/ + +void gp_line_from_endpoints (unsigned long dstoffset, unsigned long x0, + unsigned long y0, unsigned long x1, unsigned long y1, int inclusive) +{ + unsigned long base; + unsigned long length; + unsigned long flags; + unsigned short initerr, axialerr, diagerr; + long dx, dy, dmaj, dmin; + long offset; + + /* ADJUST DESTINATION OFFSET BASED ON STARTING COORDINATE */ + + dstoffset += (x0 << gp3_pix_shift) + (y0 * gp3_dst_stride); + + /* CALCULATE BRESENHAM TERMS */ + + dx = (long)x1 - (long)x0; + dy = (long)y1 - (long)y0; + if (dx < 0) dx = -dx; + if (dy < 0) dy = -dy; + + if (dx >= dy) + { + dmaj = dx; + dmin = dy; + flags = 0; + if (x1 > x0) flags |= CIMGP_POSMAJOR; + if (y1 > y0) flags |= CIMGP_POSMINOR; + } + else + { + dmaj = dy; + dmin = dx; + flags = CIMGP_YMAJOR; + if (x1 > x0) flags |= CIMGP_POSMINOR; + if (y1 > y0) flags |= CIMGP_POSMAJOR; + } + + axialerr = (unsigned short)(dmin << 1); + diagerr = (unsigned short)((dmin-dmaj) << 1); + initerr = (unsigned short)((dmin << 1) - dmaj); + if (!(flags & CIMGP_POSMINOR)) initerr--; + + /* CHECK FOR NO WORK */ + + if (!dmaj) + return; + + /* CHECK INCLUSIVE OR EXCLUSIVE */ + /* An inclusive line can be accomplished by simply adding 1 to the */ + /* line length. */ + + length = dmaj; + if (inclusive) + length++; + + /* HANDLE NEGATIVE VECTORS */ + + offset = dstoffset; + if (!(flags & CIMGP_POSMAJOR)) + { + if (flags & CIMGP_YMAJOR) + offset -= length * gp3_dst_stride; + else + offset -= (length << gp3_pix_shift); + + if (offset < 0) + offset = 0; + } + if (!(flags & CIMGP_POSMINOR)) + { + if (flags & CIMGP_YMAJOR) + offset -= (length << gp3_pix_shift); + else + offset -= length * gp3_dst_stride; + + if (offset < 0) + offset = 0; + } + + offset &= 0xFFC00000; + dstoffset -= offset; + + base = ((gp3_fb_base << 24) + offset) | + (gp3_base_register & ~GP3_BASE_OFFSET_DSTMASK); + + /* ENABLE RELEVANT REGISTERS */ + /* Note that we always enable and write the channel 3 mode, if only */ + /* to turn it off. Cimarron also always writes the base offset */ + /* register to allow operation with frame buffers larger than 16MB. */ + + gp3_cmd_header |= GP3_VEC_HDR_DST_OFF_ENABLE | + GP3_VEC_HDR_VEC_ERR_ENABLE | + GP3_VEC_HDR_VEC_LEN_ENABLE | + GP3_VEC_HDR_BASE_OFFSET_ENABLE | + GP3_VEC_HDR_CH3_STR_ENABLE | + GP3_VEC_HDR_VEC_MODE_ENABLE; + + /* WRITE THE REGISTERS COMMON TO ALL PATTERN TYPES */ + /* The destination base is the frame buffer base plus whatever */ + /* 4MB segment we happen to be drawing to. */ + + WRITE_COMMAND32 (GP3_VECTOR_VEC_ERR, + (((unsigned long)axialerr << 16) | (unsigned long)diagerr)); + WRITE_COMMAND32 (GP3_VECTOR_VEC_LEN, + (((unsigned long)length << 16) | (unsigned long)initerr)); + WRITE_COMMAND32 (GP3_VECTOR_BASE_OFFSET, base); + + /* CHECK VECTOR PATTERN CASE */ + + if (gp3_ch3_pat) + { + /* SET THE SOLID COLOR */ + /* The color for vector patterns from channel 3 comes from */ + /* the regular pattern registers. */ + + gp3_cmd_header |= GP3_VEC_HDR_PAT_CLR0_ENABLE; + + WRITE_COMMAND32 (GP3_VECTOR_PAT_COLOR_0, gp3_vector_pattern_color); + + /* INITIALIZE CHANNEL 3 PARAMETERS */ + /* We route the channel 3 output to the old source channel. If the user */ + /* sets a ROP that involves source, they will get unexpected results. */ + + WRITE_COMMAND32 (GP3_VECTOR_DST_OFFSET, dstoffset); + WRITE_COMMAND32 (GP3_VECTOR_CH3_MODE_STR, + GP3_CH3_C3EN | GP3_CH3_REPLACE_SOURCE | GP3_CH3_COLOR_PAT_ENABLE | GP3_CH3_SRC_8_8_8_8); + } + else + { + /* DISABLE CHANNEL 3 AND USE NORMAL PATTERN ORIGINS */ + + WRITE_COMMAND32 (GP3_VECTOR_CH3_MODE_STR, 0); + WRITE_COMMAND32 (GP3_VECTOR_DST_OFFSET, (dstoffset | gp3_pat_origin)); + } + + /* START THE VECTOR */ + + WRITE_COMMAND32 (GP3_VEC_CMD_HEADER, gp3_cmd_header); + WRITE_COMMAND32 (GP3_VECTOR_MODE, (gp3_vec_mode | flags)); + WRITE_GP32 (GP3_CMD_WRITE, gp3_cmd_next); + gp3_cmd_current = gp3_cmd_next; + + /* ADD A SECOND VECTOR TO CLEAR THE BYTE ENABLES */ + /* We set a transparent pattern to clear the byte enables. */ + /* We then restore the previous pattern. (SiBZ #4001) */ + + if (gp3_ch3_pat) + { + cim_cmd_ptr = cim_cmd_base_ptr + gp3_cmd_current; + + WRITE_COMMAND32 (0, GP3_LUT_HDR_TYPE | GP3_LUT_HDR_DATA_ENABLE); + WRITE_COMMAND32 (4, 0x100); + WRITE_COMMAND32 (8, (1 | GP3_LUT_DATA_TYPE)); + WRITE_COMMAND32 (12, 0); + + /* DUMMY VECTOR */ + /* We shouldn't need to write anything but vector mode and the length. */ + + WRITE_COMMAND32 (16, GP3_VEC_HDR_TYPE | GP3_VEC_HDR_VEC_MODE_ENABLE | + GP3_VEC_HDR_VEC_LEN_ENABLE); + WRITE_COMMAND32 (16 + GP3_VECTOR_MODE, (gp3_vec_mode | flags)); + WRITE_COMMAND32 (16 + GP3_VECTOR_VEC_LEN, (1 << 16) | (unsigned long)initerr); + + WRITE_COMMAND32 (16 + GP3_VECTOR_COMMAND_SIZE, GP3_LUT_HDR_TYPE | GP3_LUT_HDR_DATA_ENABLE); + WRITE_COMMAND32 (20 + GP3_VECTOR_COMMAND_SIZE, 0x100); + WRITE_COMMAND32 (24 + GP3_VECTOR_COMMAND_SIZE, (1 | GP3_LUT_DATA_TYPE)); + WRITE_COMMAND32 (28 + GP3_VECTOR_COMMAND_SIZE, gp3_vec_pat); + + gp3_cmd_current += 32 + GP3_VECTOR_COMMAND_SIZE; + } +} + +/*--------------------------------------------------------------------------- + * gp_wait_until_idle + * + * This routine stalls execution until the GP is no longer actively rendering. + *-------------------------------------------------------------------------*/ + +void gp_wait_until_idle (void) +{ + unsigned long temp; + while (((temp = READ_GP32 (GP3_BLT_STATUS)) & GP3_BS_BLT_BUSY) || + !(temp & GP3_BS_CB_EMPTY)) + { + ; + } +} + +/*--------------------------------------------------------------------------- + * gp_test_blt_busy + *-------------------------------------------------------------------------*/ + +int gp_test_blt_busy (void) +{ + unsigned long temp; + + if (((temp = READ_GP32 (GP3_BLT_STATUS)) & GP3_BS_BLT_BUSY) || + !(temp & GP3_BS_CB_EMPTY)) + return 1; + + return 0; +} + +/*--------------------------------------------------------------------------- + * gp_test_blt_pending + *-------------------------------------------------------------------------*/ + +int gp_test_blt_pending (void) +{ + if ((READ_GP32 (GP3_BLT_STATUS)) & GP3_BS_BLT_PENDING) + return 1; + + return 0; +} + +/*--------------------------------------------------------------------------- + * gp_wait_blt_pending + *-------------------------------------------------------------------------*/ + +void gp_wait_blt_pending (void) +{ + while ((READ_GP32 (GP3_BLT_STATUS)) & GP3_BS_BLT_PENDING) + ; +} + +/*--------------------------------------------------------------------------- + * gp_save_state + * + * This routine saves all persistent GP information. + *-------------------------------------------------------------------------*/ + +void gp_save_state (GP_SAVE_RESTORE *gp_state) +{ + Q_WORD msr_value; + + gp_wait_until_idle(); + + msr_read64 (MSR_DEVICE_GEODELX_GP, MSR_GEODELINK_CONFIG, &msr_value); + gp_state->cmd_bottom = READ_GP32 (GP3_CMD_BOT) & 0xFFFFFF; + gp_state->cmd_top = READ_GP32 (GP3_CMD_TOP) & 0xFFFFFF; + gp_state->cmd_base = (msr_value.low << 4) & 0xFFF00000; + gp_state->base_offset = READ_GP32 (GP3_BASE_OFFSET); + + /* RESET THE READ POINTER */ + + gp_set_command_buffer_base (gp_state->cmd_base, gp_state->cmd_top, gp_state->cmd_bottom); +} + +/*--------------------------------------------------------------------------- + * gp_restore_state + * + * This routine restores all persistent GP information. + *-------------------------------------------------------------------------*/ + +void gp_restore_state (GP_SAVE_RESTORE *gp_state) +{ + gp_wait_until_idle(); + + WRITE_GP32 (GP3_BASE_OFFSET, gp_state->base_offset); + + gp_set_command_buffer_base (gp_state->cmd_base, gp_state->cmd_top, gp_state->cmd_bottom); +} --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_vg.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_vg.c 2005-12-14 11:38:10.000000000 -0700 @@ -0,0 +1,3616 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron display controller routines. These routines program the display + * mode and configure the hardware cursor and video buffers. + * */ + +/*---------------------*/ +/* CIMARRON VG GLOBALS */ +/*---------------------*/ + +CIMARRON_STATIC unsigned long vg3_x_hotspot = 0; +CIMARRON_STATIC unsigned long vg3_y_hotspot = 0; +CIMARRON_STATIC unsigned long vg3_cursor_offset = 0; +CIMARRON_STATIC unsigned long vg3_mode_width = 0; +CIMARRON_STATIC unsigned long vg3_mode_height = 0; +CIMARRON_STATIC unsigned long vg3_panel_width = 0; +CIMARRON_STATIC unsigned long vg3_panel_height = 0; +CIMARRON_STATIC unsigned long vg3_delta_x = 0; +CIMARRON_STATIC unsigned long vg3_delta_y = 0; +CIMARRON_STATIC unsigned long vg3_bpp = 0; + +CIMARRON_STATIC unsigned long vg3_color_cursor = 0; +CIMARRON_STATIC unsigned long vg3_panel_enable = 0; + +/*--------------------------------------------------------------------------- + * vg_delay_milliseconds + * + * This routine delays for a number of milliseconds based on a crude + * delay loop. + *---------------------------------------------------------------------------*/ + +int vg_delay_milliseconds (unsigned long ms) +{ + /* ASSUME 500 MHZ 20 CLOCKS PER READ */ + + unsigned long loop = ms * 25000; + while (loop-- > 0) + { + READ_REG32 (DC3_UNLOCK); + } + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_display_mode + * + * This routine sets a CRT display mode using predefined Cimarron timings. The + * source width and height are specified to allow scaling. + *---------------------------------------------------------------------------*/ + +int vg_set_display_mode (unsigned long src_width, unsigned long src_height, + unsigned long dst_width, unsigned long dst_height, int bpp, int hz, + unsigned long flags) +{ + VG_QUERY_MODE crt_query; + VG_DISPLAY_MODE crt_mode; + int mode; + + crt_query.active_width = dst_width; + crt_query.active_height = dst_height; + crt_query.bpp = bpp; + crt_query.hz = hz; + crt_query.query_flags = VG_QUERYFLAG_ACTIVEWIDTH | + VG_QUERYFLAG_ACTIVEHEIGHT | + VG_QUERYFLAG_BPP | + VG_QUERYFLAG_REFRESH; + + mode = vg_get_display_mode_index (&crt_query); + if (mode >= 0) + { + crt_mode = CimarronDisplayModes[mode]; + crt_mode.src_width = src_width; + crt_mode.src_height = src_height; + + /* ADD USER-REQUESTED FLAGS */ + + crt_mode.flags |= (flags & VG_MODEFLAG_VALIDUSERFLAGS); + + if (flags & VG_MODEFLAG_OVERRIDE_BAND) + { + crt_mode.flags &= ~VG_MODEFLAG_BANDWIDTHMASK; + crt_mode.flags |= (flags & VG_MODEFLAG_BANDWIDTHMASK); + } + if (flags & VG_MODEFLAG_INT_OVERRIDE) + { + crt_mode.flags &= ~VG_MODEFLAG_INT_MASK; + crt_mode.flags |= (flags & VG_MODEFLAG_INT_MASK); + } + + return vg_set_custom_mode (&crt_mode, bpp); + } + return CIM_STATUS_ERROR; +} + +/*--------------------------------------------------------------------------- + * vg_set_panel_mode + * + * This routine sets a panel mode using predefined Cimarron fixed timings. The + * source width and height specify the width and height of the data in the frame + * buffer. The destination width and height specify the width and height of + * the active data to be displayed. The panel width and height specify the + * dimensions of the panel. This interface allows the user to scale or center + * graphics data or both. To perform scaling, the src width or height should + * be different than the destination width or height. To perform centering or + * panning, the destination width and height should be different than the panel + * resolution. + *---------------------------------------------------------------------------*/ + +int vg_set_panel_mode (unsigned long src_width, unsigned long src_height, + unsigned long dst_width, unsigned long dst_height, + unsigned long panel_width, unsigned long panel_height, + int bpp, unsigned long flags) +{ + unsigned long sync_width; + unsigned long sync_offset; + VG_QUERY_MODE panel_query; + VG_DISPLAY_MODE panel_mode; + int mode; + + /* SEARCH CIMARRON'S TABLE OF PREDEFINED PANEL MODES */ + /* If the destination resolution is larger than the panel resolution, */ + /* panning will be performed. However, the timings for a panned mode */ + /* are identical to the timings without panning. To save space in the */ + /* mode tables, there are no additional table entries for modes with */ + /* panning. Instead, we read the timings for a mode without panning */ + /* and override the structure entries that specify the width and */ + /* height of the mode. We perform a similar procedure for centered */ + /* modes, except that certain timing parameters are dynamically */ + /* calculated. */ + + panel_query.active_width = panel_width; + panel_query.active_height = panel_height; + panel_query.panel_width = panel_width; + panel_query.panel_height = panel_height; + panel_query.bpp = bpp; + panel_query.query_flags = VG_QUERYFLAG_ACTIVEWIDTH | + VG_QUERYFLAG_ACTIVEHEIGHT | + VG_QUERYFLAG_PANELWIDTH | + VG_QUERYFLAG_PANELHEIGHT | + VG_QUERYFLAG_PANEL | + VG_QUERYFLAG_BPP; + + mode = vg_get_display_mode_index (&panel_query); + + /* COPY THE DATA FROM THE MODE TABLE TO A TEMPORARY STRUCTURE */ + + if (mode >= 0) + { + panel_mode = CimarronDisplayModes[mode]; + panel_mode.mode_width = dst_width; + panel_mode.mode_height = dst_height; + panel_mode.src_width = src_width; + panel_mode.src_height = src_height; + + /* ADD USER-REQUESTED FLAGS */ + + panel_mode.flags |= (flags & VG_MODEFLAG_VALIDUSERFLAGS); + + if (flags & VG_MODEFLAG_OVERRIDE_BAND) + { + panel_mode.flags &= ~VG_MODEFLAG_BANDWIDTHMASK; + panel_mode.flags |= (flags & VG_MODEFLAG_BANDWIDTHMASK); + } + if (flags & VG_MODEFLAG_INT_OVERRIDE) + { + panel_mode.flags &= ~VG_MODEFLAG_INT_MASK; + panel_mode.flags |= (flags & VG_MODEFLAG_INT_MASK); + } + + /* DYNAMICALLY CALCULATE CENTERED TIMINGS */ + /* For centered timings the blank start and blank end are set to */ + /* half the difference between the mode dimension and the panel */ + /* dimension. The sync pulse preserves the width and offset from */ + /* blanking whenever possible. */ + + if (dst_width < panel_width) + { + sync_width = panel_mode.hsyncend - panel_mode.hsyncstart; + sync_offset = panel_mode.hsyncstart - panel_mode.hblankstart; + + panel_mode.hactive = dst_width; + panel_mode.hblankstart = panel_mode.hactive + ((panel_width - dst_width) >> 1); + panel_mode.hblankend = panel_mode.htotal - ((panel_width - dst_width) >> 1); + panel_mode.hsyncstart = panel_mode.hblankstart + sync_offset; + panel_mode.hsyncend = panel_mode.hsyncstart + sync_width; + + panel_mode.flags |= VG_MODEFLAG_CENTERED; + } + if (dst_height < panel_height) + { + sync_width = panel_mode.vsyncend - panel_mode.vsyncstart; + sync_offset = panel_mode.vsyncstart - panel_mode.vblankstart; + + panel_mode.vactive = dst_height; + panel_mode.vblankstart = panel_mode.vactive + ((panel_height - dst_height) >> 1); + panel_mode.vblankend = panel_mode.vtotal - ((panel_height - dst_height) >> 1); + panel_mode.vsyncstart = panel_mode.vblankstart + sync_offset; + panel_mode.vsyncend = panel_mode.vsyncstart + sync_width; + + panel_mode.flags |= VG_MODEFLAG_CENTERED; + } + return vg_set_custom_mode (&panel_mode, bpp); + } + return CIM_STATUS_ERROR; +} + +/*--------------------------------------------------------------------------- + * vg_set_tv_mode + * + * This routine sets a TV display mode using predefined Cimarron timings. The + * source width and height are specified to allow scaling. + *---------------------------------------------------------------------------*/ + +int vg_set_tv_mode (unsigned long *src_width, unsigned long *src_height, + unsigned long encoder, unsigned long tvres, int bpp, unsigned long flags, + unsigned long h_overscan, unsigned long v_overscan) +{ + unsigned long sync_width; + unsigned long sync_offset; + VG_QUERY_MODE tv_query; + VG_DISPLAY_MODE tv_mode; + int mode; + + if (!src_width || !src_height) + return CIM_STATUS_INVALIDPARAMS; + + tv_query.bpp = bpp; + tv_query.encoder = encoder; + tv_query.tvmode = tvres; + tv_query.query_flags = VG_QUERYFLAG_BPP | + VG_QUERYFLAG_TVOUT | + VG_QUERYFLAG_ENCODER | + VG_QUERYFLAG_TVMODE; + + mode = vg_get_display_mode_index (&tv_query); + if (mode >= 0) + { + /* RETRIEVE THE UNSCALED RESOLUTION */ + /* As we are indexing here simply by a mode and encoder, the actual */ + /* timings may vary. A 0 value for source or height will thus query the */ + /* unscaled resolution. */ + + if (!(*src_width) || !(*src_height)) + { + *src_width = CimarronDisplayModes[mode].hactive - (h_overscan << 1); + *src_height = CimarronDisplayModes[mode].vactive; + + if (CimarronDisplayModes[mode].flags & VG_MODEFLAG_INTERLACED) + { + if (((flags & VG_MODEFLAG_INT_OVERRIDE) && + (flags & VG_MODEFLAG_INT_MASK) == VG_MODEFLAG_INT_LINEDOUBLE) || + (!(flags & VG_MODEFLAG_INT_OVERRIDE) && + (CimarronDisplayModes[mode].flags & VG_MODEFLAG_INT_MASK) == VG_MODEFLAG_INT_LINEDOUBLE)) + { + if (CimarronDisplayModes[mode].vactive_even > CimarronDisplayModes[mode].vactive) + *src_height = CimarronDisplayModes[mode].vactive_even; + + /* ONLY 1/2 THE OVERSCAN FOR LINE DOUBLED MODES */ + + *src_height -= v_overscan; + } + else + { + *src_height += CimarronDisplayModes[mode].vactive_even; + *src_height -= v_overscan << 1; + } + } + else + { + *src_height -= v_overscan << 1; + } + + return CIM_STATUS_OK; + } + + tv_mode = CimarronDisplayModes[mode]; + tv_mode.src_width = *src_width; + tv_mode.src_height = *src_height; + + /* ADD USER-REQUESTED FLAGS */ + + tv_mode.flags |= (flags & VG_MODEFLAG_VALIDUSERFLAGS); + + if (flags & VG_MODEFLAG_OVERRIDE_BAND) + { + tv_mode.flags &= ~VG_MODEFLAG_BANDWIDTHMASK; + tv_mode.flags |= (flags & VG_MODEFLAG_BANDWIDTHMASK); + } + if (flags & VG_MODEFLAG_INT_OVERRIDE) + { + tv_mode.flags &= ~VG_MODEFLAG_INT_MASK; + tv_mode.flags |= (flags & VG_MODEFLAG_INT_MASK); + } + + /* ADJUST FOR OVERSCAN */ + + if (h_overscan) + { + sync_width = tv_mode.hsyncend - tv_mode.hsyncstart; + sync_offset = tv_mode.hsyncstart - tv_mode.hblankstart; + + tv_mode.hactive -= h_overscan << 1; + tv_mode.hblankstart = tv_mode.hactive + h_overscan; + tv_mode.hblankend = tv_mode.htotal - h_overscan; + tv_mode.hsyncstart = tv_mode.hblankstart + sync_offset; + tv_mode.hsyncend = tv_mode.hsyncstart + sync_width; + + tv_mode.flags |= VG_MODEFLAG_CENTERED; + } + if (v_overscan) + { + sync_width = tv_mode.vsyncend - tv_mode.vsyncstart; + sync_offset = tv_mode.vsyncstart - tv_mode.vblankstart; + + if (tv_mode.flags & VG_MODEFLAG_INTERLACED) + { + tv_mode.vactive -= v_overscan; + tv_mode.vblankstart = tv_mode.vactive + (v_overscan >> 1); + tv_mode.vblankend = tv_mode.vtotal - (v_overscan >> 1); + tv_mode.vsyncstart = tv_mode.vblankstart + sync_offset; + tv_mode.vsyncend = tv_mode.vsyncstart + sync_width; + + sync_width = tv_mode.vsyncend_even - tv_mode.vsyncstart_even; + sync_offset = tv_mode.vsyncstart_even - tv_mode.vblankstart_even; + + tv_mode.vactive_even -= v_overscan; + tv_mode.vblankstart_even = tv_mode.vactive_even + (v_overscan >> 1); + tv_mode.vblankend_even = tv_mode.vtotal_even - (v_overscan >> 1); + tv_mode.vsyncstart_even = tv_mode.vblankstart_even + sync_offset; + tv_mode.vsyncend_even = tv_mode.vsyncstart_even + sync_width; + } + else + { + tv_mode.vactive -= v_overscan << 1; + tv_mode.vblankstart = tv_mode.vactive + v_overscan; + tv_mode.vblankend = tv_mode.vtotal - v_overscan; + tv_mode.vsyncstart = tv_mode.vblankstart + sync_offset; + tv_mode.vsyncend = tv_mode.vsyncstart + sync_width; + } + + tv_mode.flags |= VG_MODEFLAG_CENTERED; + } + + /* TV MODES WILL NEVER ALLOW PANNING */ + + tv_mode.panel_width = tv_mode.hactive; + tv_mode.panel_height = tv_mode.vactive; + tv_mode.mode_width = tv_mode.hactive; + tv_mode.mode_height = tv_mode.vactive; + + return vg_set_custom_mode (&tv_mode, bpp); + } + return CIM_STATUS_ERROR; +} + +/*--------------------------------------------------------------------------- + * vg_set_custom_mode + * + * This routine sets a display mode. The API is structured such that this routine + * can be called from four sources: + * - vg_set_display_mode + * - vg_set_panel_mode + * - vg_set_tv_mode + * - directly by the user for a custom mode. + *---------------------------------------------------------------------------*/ + +int vg_set_custom_mode (VG_DISPLAY_MODE *mode_params, int bpp) +{ + unsigned long config, misc, temp; + unsigned long irq_ctl, genlk_ctl; + unsigned long unlock, flags; + unsigned long acfg, gcfg, dcfg; + unsigned long size, line_size, pitch; + unsigned long bpp_mask, dv_size; + unsigned long hscale, vscale, starting_width; + unsigned long starting_height, output_height; + Q_WORD msr_value; + + /* DETERMINE DIMENSIONS FOR SCALING */ + /* Scaling is performed before flicker filtering and interlacing */ + + output_height = mode_params->vactive; + + if (mode_params->flags & VG_MODEFLAG_INTERLACED) + { + /* EVEN AND ODD FIELDS ARE SEPARATE */ + /* The composite image height is the sum of the height of both fields */ + + if ((mode_params->flags & VG_MODEFLAG_INT_MASK) == VG_MODEFLAG_INT_FLICKER || + (mode_params->flags & VG_MODEFLAG_INT_MASK) == VG_MODEFLAG_INT_ADDRESS) + { + output_height += mode_params->vactive_even; + } + + /* LINE DOUBLING */ + /* The composite image height is the greater of the two field heights. */ + + else if (mode_params->vactive_even > output_height) + output_height = mode_params->vactive_even; + } + + /* CHECK FOR VALID SCALING FACTOR */ + /* GeodeLX supports only 2:1 vertical downscale (before interlacing) and */ + /* 2:1 horizontal downscale. The source width when scaling must be */ + /* less than or equal to 1024 pixels. The destination can be any size, */ + /* except when flicker filtering is enabled. */ + + irq_ctl = 0; + if (mode_params->flags & VG_MODEFLAG_PANELOUT) + { + if (mode_params->src_width != mode_params->mode_width) + { + starting_width = (mode_params->hactive * mode_params->src_width) / mode_params->mode_width; + hscale = (mode_params->src_width << 14) / (mode_params->mode_width - 1); + irq_ctl |= (DC3_IRQFILT_ALPHA_FILT_EN | DC3_IRQFILT_GFX_FILT_EN); + } + else + { + starting_width = mode_params->hactive; + hscale = 0x4000; + } + if (mode_params->src_height != mode_params->mode_height) + { + starting_height = (output_height * mode_params->src_height) / mode_params->mode_height; + vscale = (mode_params->src_height << 14) / (mode_params->mode_height - 1); + irq_ctl |= (DC3_IRQFILT_ALPHA_FILT_EN | DC3_IRQFILT_GFX_FILT_EN); + } + else + { + starting_height = output_height; + vscale = 0x4000; + } + } + else + { + starting_width = mode_params->src_width; + starting_height = mode_params->src_height; + if (mode_params->src_width != mode_params->hactive) + { + hscale = (mode_params->src_width << 14) / (mode_params->hactive - 1); + irq_ctl |= (DC3_IRQFILT_ALPHA_FILT_EN | DC3_IRQFILT_GFX_FILT_EN); + } + else + { + hscale = 0x4000; + } + if (mode_params->src_height != output_height) + { + vscale = (mode_params->src_height << 14) / (output_height - 1); + irq_ctl |= (DC3_IRQFILT_ALPHA_FILT_EN | DC3_IRQFILT_GFX_FILT_EN); + } + else + { + vscale = 0x4000; + } + } + + starting_width = (starting_width + 7) & 0xFFFF8; + + if (mode_params->hactive < (starting_width >> 1) || + output_height < (starting_height >> 1) || + (irq_ctl && (starting_width > 1024))) + { + return CIM_STATUS_INVALIDSCALE; + } + + /* VERIFY INTERLACED SCALING */ + /* The output width must be less than or equal to 1024 pixels when the */ + /* flicker filter is enabled. Also, scaling should be disabled when */ + /* the interlacing mode is set to interlaced addressing. */ + + if (mode_params->flags & VG_MODEFLAG_INTERLACED) + { + if ((((mode_params->flags & VG_MODEFLAG_INT_MASK) == VG_MODEFLAG_INT_FLICKER) && + (mode_params->hactive > 1024)) || + (((mode_params->flags & VG_MODEFLAG_INT_MASK) == VG_MODEFLAG_INT_ADDRESS) && irq_ctl)) + { + return CIM_STATUS_INVALIDSCALE; + } + } + + /* CHECK FOR VALID BPP */ + + switch (bpp) + { + case 8: bpp_mask = DC3_DCFG_DISP_MODE_8BPP; break; + case 24: bpp_mask = DC3_DCFG_DISP_MODE_24BPP; break; + case 32: bpp_mask = DC3_DCFG_DISP_MODE_32BPP; break; + case 12: bpp_mask = DC3_DCFG_DISP_MODE_16BPP | DC3_DCFG_12BPP; break; + case 15: bpp_mask = DC3_DCFG_DISP_MODE_16BPP | DC3_DCFG_15BPP; break; + case 16: bpp_mask = DC3_DCFG_DISP_MODE_16BPP | DC3_DCFG_16BPP; break; + default: return CIM_STATUS_INVALIDPARAMS; + } + + vg3_bpp = bpp; + + /* CLEAR PANNING OFFSETS */ + + vg3_delta_x = 0; + vg3_delta_y = 0; + + /* SAVE PANEL PARAMETERS */ + + if (mode_params->flags & VG_MODEFLAG_PANELOUT) + { + vg3_panel_enable = 1; + vg3_panel_width = mode_params->panel_width; + vg3_panel_height = mode_params->panel_height; + vg3_mode_width = mode_params->mode_width; + vg3_mode_height = mode_params->mode_height; + + /* INVERT THE SHIFT CLOCK IF REQUESTED */ + /* Note that we avoid writing the power management register if */ + /* we can help it. */ + + temp = READ_VID32 (DF_POWER_MANAGEMENT); + if ((mode_params->flags & VG_MODEFLAG_INVERT_SHFCLK) && + !(temp & DF_PM_INVERT_SHFCLK)) + { + WRITE_VID32 (DF_POWER_MANAGEMENT, (temp | DF_PM_INVERT_SHFCLK)); + } + else if (!(mode_params->flags & VG_MODEFLAG_INVERT_SHFCLK) && + (temp & DF_PM_INVERT_SHFCLK)) + { + WRITE_VID32 (DF_POWER_MANAGEMENT, (temp & ~DF_PM_INVERT_SHFCLK)); + } + + /* SET PANEL TIMING VALUES */ + + if (!(mode_params->flags & VG_MODEFLAG_NOPANELTIMINGS)) + { + unsigned long pmtim1, pmtim2, dith_ctl; + + if (mode_params->flags & VG_MODEFLAG_XVGA_TFT) + { + pmtim1 = DF_DEFAULT_XVGA_PMTIM1; + pmtim2 = DF_DEFAULT_XVGA_PMTIM2; + dith_ctl = DF_DEFAULT_DITHCTL; + msr_value.low = DF_DEFAULT_XVGA_PAD_SEL_LOW; + msr_value.high = DF_DEFAULT_XVGA_PAD_SEL_HIGH; + } + else if (mode_params->flags & VG_MODEFLAG_CUSTOM_PANEL) + { + pmtim1 = mode_params->panel_tim1; + pmtim2 = mode_params->panel_tim2; + dith_ctl = mode_params->panel_dither_ctl; + msr_value.low = mode_params->panel_pad_sel_low; + msr_value.high = mode_params->panel_pad_sel_high; + } + else + { + pmtim1 = DF_DEFAULT_TFT_PMTIM1; + pmtim2 = DF_DEFAULT_TFT_PMTIM2; + dith_ctl = DF_DEFAULT_DITHCTL; + msr_value.low = DF_DEFAULT_TFT_PAD_SEL_LOW; + msr_value.high = DF_DEFAULT_TFT_PAD_SEL_HIGH; + + } + WRITE_VID32 (DF_VIDEO_PANEL_TIM1, pmtim1); + WRITE_VID32 (DF_VIDEO_PANEL_TIM2, pmtim2); + WRITE_VID32 (DF_DITHER_CONTROL, dith_ctl); + msr_write64 (MSR_DEVICE_GEODELX_DF, DF_MSR_PAD_SEL, &msr_value); + } + + /* SET APPROPRIATE PANEL OUTPUT MODE */ + + msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &msr_value); + + msr_value.low &= ~DF_CONFIG_OUTPUT_MASK; + msr_value.low |= DF_OUTPUT_PANEL; + if (mode_params->flags & VG_MODEFLAG_CRT_AND_FP) + msr_value.low |= DF_SIMULTANEOUS_CRT_FP; + else + msr_value.low &= ~DF_SIMULTANEOUS_CRT_FP; + + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &msr_value); + + } + else if (mode_params->flags & VG_MODEFLAG_TVOUT) + { + vg3_panel_enable = 0; + + /* SET APPROPRIATE TV OUTPUT MODE */ + + msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &msr_value); + + msr_value.low &= ~DF_CONFIG_OUTPUT_MASK; + msr_value.low |= DF_OUTPUT_PANEL; + if (mode_params->flags & VG_MODEFLAG_CRT_AND_FP) + msr_value.low |= DF_SIMULTANEOUS_CRT_FP; + else + msr_value.low &= ~DF_SIMULTANEOUS_CRT_FP; + + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &msr_value); + + /* CONFIGURE PADS FOR VOP OUTPUT */ + /* Note that the VOP clock is currently always inverted. */ + + msr_value.low = DF_DEFAULT_TV_PAD_SEL_LOW; + msr_value.high = DF_DEFAULT_TV_PAD_SEL_HIGH; + msr_write64 (MSR_DEVICE_GEODELX_DF, DF_MSR_PAD_SEL, &msr_value); + } + else + { + vg3_panel_enable = 0; + + /* SET OUTPUT TO CRT ONLY */ + + msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &msr_value); + msr_value.low &= ~DF_CONFIG_OUTPUT_MASK; + msr_value.low |= DF_OUTPUT_CRT; + msr_write64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &msr_value); + } + + /* SET UNLOCK VALUE */ + + unlock = READ_REG32 (DC3_UNLOCK); + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + + /*-------------------------------------------------------------------*/ + /* MAKE THE SYSTEM "SAFE" */ + /* Before setting a mode, we first ensure that the system is in a */ + /* benign quiescent state. This involves disabling compression and */ + /* all interrupt sources. It also involves terminating all accesses */ + /* to memory, including video, FIFO load, VIP and the GP. */ + /*-------------------------------------------------------------------*/ + + /* DISABLE VGA */ + /* VGA *MUST* be turned off before TGEN is enabled. If not, a condition */ + /* will result where VGA Enable is waiting for a VSync to be latched but */ + /* a VSync will not be generated until VGA is disabled. */ + + temp = READ_REG32 (DC3_GENERAL_CFG) & ~DC3_GCFG_VGAE; + + /* DISABLE VIDEO (INCLUDING ALPHA WINDOWS) */ + + WRITE_VID32 (DF_ALPHA_CONTROL_1, 0); + WRITE_VID32 (DF_ALPHA_CONTROL_1 + 32, 0); + WRITE_VID32 (DF_ALPHA_CONTROL_1 + 64, 0); + + WRITE_REG32 (DC3_GENERAL_CFG, (temp & ~DC3_GCFG_VIDE)); + temp = READ_VID32 (DF_VIDEO_CONFIG); + WRITE_VID32 (DF_VIDEO_CONFIG, (temp & ~DF_VCFG_VID_EN)); + + /* DISABLE VG INTERRUPTS */ + + WRITE_REG32 (DC3_IRQ, DC3_IRQ_MASK | DC3_VSYNC_IRQ_MASK | + DC3_IRQ_STATUS | DC3_VSYNC_IRQ_STATUS); + + /* DISABLE GENLOCK */ + + genlk_ctl = READ_REG32 (DC3_GENLK_CTL); + WRITE_REG32 (DC3_GENLK_CTL, (genlk_ctl & ~DC3_GC_GENLOCK_ENABLE)); + + /* DISABLE VIP CAPTURE AND VIP INTERRUPTS */ + + WRITE_VIP32 (VIP_CONTROL1, 0); + WRITE_VIP32 (VIP_CONTROL2, 0); + WRITE_VIP32 (VIP_INTERRUPT, VIP_ALL_INTERRUPTS | (VIP_ALL_INTERRUPTS >> 16)); + + /* DISABLE COLOR KEYING */ + /* The color key mechanism should be disabled whenever a mode switch occurs. */ + + temp = READ_REG32 (DC3_COLOR_KEY); + WRITE_REG32 (DC3_COLOR_KEY, (temp & ~DC3_CLR_KEY_ENABLE)); + + /* BLANK THE DISPLAY */ + /* Note that we never blank the panel. Most flat panels have very long */ + /* latency requirements when setting their power low. Some panels require */ + /* upwards of 500ms before VDD goes high again. Needless to say, we are not */ + /* planning to take over one half a second inside this routine. */ + + misc = READ_VID32 (DF_VID_MISC); + config = READ_VID32 (DF_DISPLAY_CONFIG); + + WRITE_VID32 (DF_VID_MISC, (misc | DF_DAC_POWER_DOWN)); + WRITE_VID32 (DF_DISPLAY_CONFIG, (config & ~(DF_DCFG_DIS_EN | DF_DCFG_HSYNC_EN | + DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN))); + + /* DISABLE COMPRESSION */ + + gcfg = READ_REG32 (DC3_GENERAL_CFG); + gcfg &= ~(DC3_GCFG_CMPE | DC3_GCFG_DECE); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + + /* DISABLE THE TIMING GENERATOR */ + + dcfg = READ_REG32 (DC3_DISPLAY_CFG); + dcfg &= ~DC3_DCFG_TGEN; + WRITE_REG32 (DC3_DISPLAY_CFG, dcfg); + + /* WAIT FOR PENDING MEMORY REQUESTS */ + + vg_delay_milliseconds(1); + + /* DISABLE DISPLAY FIFO LOAD */ + + gcfg &= ~DC3_GCFG_DFLE; + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + gcfg = 0; + dcfg = 0; + + /* WAIT FOR THE GP TO BE IDLE (JUST IN CASE) */ + + while (((temp = READ_GP32 (GP3_BLT_STATUS)) & GP3_BS_BLT_BUSY) || + !(temp & GP3_BS_CB_EMPTY)) + { + ; + } + + /* SET THE DOT CLOCK FREQUENCY */ + + if (!(mode_params->flags & VG_MODEFLAG_EXCLUDEPLL)) + { + if (mode_params->flags & VG_MODEFLAG_HALFCLOCK) + flags = VG_PLL_DIVIDE_BY_2; + else if (mode_params->flags & VG_MODEFLAG_QVGA) + flags = VG_PLL_DIVIDE_BY_4; + else + flags = 0; + + /* ALLOW DOTREF TO BE USED AS THE PLL */ + /* This is useful for some external TV encoders. */ + + if (mode_params->flags & VG_MODEFLAG_PLL_BYPASS) + flags |= VG_PLL_BYPASS; + + /* ALLOW THE USER TO MANUALLY ENTER THE MSR VALUE */ + + if (mode_params->flags & VG_MODEFLAG_MANUAL_FREQUENCY) + flags |= VG_PLL_MANUAL; + if (mode_params->flags & VG_MODEFLAG_VIP_TO_DOT_CLOCK) + flags |= VG_PLL_VIP_CLOCK; + + vg_set_clock_frequency (mode_params->frequency, flags); + } + + /* CLEAR ALL BUFFER OFFSETS */ + + WRITE_REG32 (DC3_FB_ST_OFFSET, 0); + WRITE_REG32 (DC3_CB_ST_OFFSET, 0); + WRITE_REG32 (DC3_CURS_ST_OFFSET, 0); + + genlk_ctl = READ_REG32 (DC3_GENLK_CTL) & ~(DC3_GC_ALPHA_FLICK_ENABLE | + DC3_GC_FLICKER_FILTER_ENABLE | DC3_GC_FLICKER_FILTER_MASK); + + /* ENABLE INTERLACING */ + + if (mode_params->flags & VG_MODEFLAG_INTERLACED) + { + irq_ctl |= DC3_IRQFILT_INTL_EN; + + if ((mode_params->flags & VG_MODEFLAG_INT_MASK) == VG_MODEFLAG_INT_ADDRESS) + irq_ctl |= DC3_IRQFILT_INTL_ADDR; + else if ((mode_params->flags & VG_MODEFLAG_INT_MASK) == VG_MODEFLAG_INT_FLICKER) + { + genlk_ctl |= DC3_GC_FLICKER_FILTER_1_8 | DC3_GC_FLICKER_FILTER_ENABLE | + DC3_GC_ALPHA_FLICK_ENABLE; + } + } + + WRITE_REG32 (DC3_GFX_SCALE, (vscale << 16) | (hscale & 0xFFFF)); + WRITE_REG32 (DC3_IRQ_FILT_CTL, irq_ctl); + WRITE_REG32 (DC3_GENLK_CTL, genlk_ctl); + + /* SET LINE SIZE AND PITCH */ + /* The line size and pitch are calculated from the src_width parameter */ + /* passed in to this routine. All other parameters are ignored. */ + /* The pitch is set either to a power of 2 to allow efficient */ + /* compression or to a linear value to allow efficient memory management. */ + + switch (bpp) + { + case 8: + size = mode_params->src_width; + line_size = starting_width; + break; + + case 12: + case 15: + case 16: + + size = mode_params->src_width << 1; + line_size = starting_width << 1; + break; + + case 24: + case 32: + default: + + size = mode_params->src_width << 2; + line_size = starting_width << 2; break; + } + + /* CALCULATE DV RAM SETTINGS AND POWER OF 2 PITCH */ + + pitch = 1024; + dv_size = DC3_DV_LINE_SIZE_1024; + + if (size > 1024) { pitch = 2048; dv_size = DC3_DV_LINE_SIZE_2048; } + if (size > 2048) { pitch = 4096; dv_size = DC3_DV_LINE_SIZE_4096; } + if (size > 4096) { pitch = 8192; dv_size = DC3_DV_LINE_SIZE_8192; } + + /* OVERRIDE SETTINGS FOR LINEAR PITCH */ + + if (mode_params->flags & VG_MODEFLAG_LINEARPITCH) + { + unsigned long max; + if (pitch != size) + { + /* CALCULATE MAXIMUM ADDRESS (1K ALIGNED) */ + + max = size * output_height; + max = (max + 0x3FF) & 0xFFFFFC00; + WRITE_REG32 (DC3_DV_TOP, max | DC3_DVTOP_ENABLE); + + gcfg |= DC3_GCFG_FDTY; + pitch = size; + } + else + { + WRITE_REG32 (DC3_DV_TOP, 0); + } + } + + /* WRITE PITCH AND DV RAM SETTINGS */ + /* The DV RAM line length is programmed at a power of 2 boundary */ + /* in case the user wants to toggle back to a power of 2 pitch */ + /* later. It could happen... */ + + temp = READ_REG32 (DC3_DV_CTL); + WRITE_REG32 (DC3_GFX_PITCH, pitch >> 3); + WRITE_REG32 (DC3_DV_CTL, (temp & ~DC3_DV_LINE_SIZE_MASK) | dv_size); + + /* SET THE LINE SIZE */ + + WRITE_REG32 (DC3_LINE_SIZE, (line_size + 7) >> 3); + + /* ALWAYS ENABLE VIDEO AND GRAPHICS DATA */ + /* These bits are relics from a previous design and */ + /* should always be enabled. */ + + dcfg |= (DC3_DCFG_VDEN | DC3_DCFG_GDEN); + + /* SET PIXEL FORMAT */ + + dcfg |= bpp_mask; + + /* ENABLE TIMING GENERATOR, TIM. REG. UPDATES, PALETTE BYPASS */ + /* AND VERT. INT. SELECT */ + + dcfg |= (unsigned long)(DC3_DCFG_TGEN | DC3_DCFG_TRUP | DC3_DCFG_PALB | DC3_DCFG_VISL); + + /* SET FIFO PRIORITIES AND DISPLAY FIFO LOAD ENABLE */ + /* Note that the bandwidth setting gets upgraded when scaling or flicker */ + /* filtering are enabled, as they require more data throughput. */ + + msr_read64 (MSR_DEVICE_GEODELX_VG, DC3_SPARE_MSR, &msr_value); + msr_value.low &= ~(DC3_SPARE_DISABLE_CFIFO_HGO | DC3_SPARE_VFIFO_ARB_SELECT | + DC3_SPARE_LOAD_WM_LPEN_MASK | DC3_SPARE_WM_LPEN_OVRD | + DC3_SPARE_DISABLE_INIT_VID_PRI | DC3_SPARE_DISABLE_VFIFO_WM); + + if ((mode_params->flags & VG_MODEFLAG_BANDWIDTHMASK) == VG_MODEFLAG_HIGH_BAND || + ((mode_params->flags & VG_MODEFLAG_INTERLACED) && + (mode_params->flags & VG_MODEFLAG_INT_MASK) == VG_MODEFLAG_INT_FLICKER) || + (irq_ctl & DC3_IRQFILT_GFX_FILT_EN)) + { + /* HIGH BANDWIDTH */ + /* Set agressive watermarks and disallow forced low priority */ + + gcfg |= 0x0000BA01; + dcfg |= 0x000EA000; + acfg = 0x001A0201; + + msr_value.low |= DC3_SPARE_DISABLE_CFIFO_HGO | DC3_SPARE_VFIFO_ARB_SELECT | + DC3_SPARE_WM_LPEN_OVRD; + } + else if ((mode_params->flags & VG_MODEFLAG_BANDWIDTHMASK) == VG_MODEFLAG_AVG_BAND) + { + /* AVERAGE BANDWIDTH */ + /* Set average watermarks and allow small regions of forced low priority. */ + + gcfg |= 0x0000B601; + dcfg |= 0x00009000; + acfg = 0x00160001; + + msr_value.low |= DC3_SPARE_DISABLE_CFIFO_HGO | DC3_SPARE_VFIFO_ARB_SELECT | + DC3_SPARE_WM_LPEN_OVRD; + + /* SET THE NUMBER OF LOW PRIORITY LINES TO 1/2 THE TOTAL AVAILABLE */ + + temp = ((READ_REG32 (DC3_V_ACTIVE_TIMING) >> 16) & 0x7FF) + 1; + temp -= (READ_REG32 (DC3_V_SYNC_TIMING) & 0x7FF) + 1; + temp >>= 1; + if (temp > 127) + temp = 127; + + acfg |= temp << 9; + } + else if ((mode_params->flags & VG_MODEFLAG_BANDWIDTHMASK) == VG_MODEFLAG_LOW_BAND) + { + /* LOW BANDWIDTH */ + /* Set low watermarks and allow larger regions of forced low priority. */ + + gcfg |= 0x00009501; + dcfg |= 0x00008000; + acfg = 0x00150001; + + msr_value.low |= DC3_SPARE_DISABLE_CFIFO_HGO | DC3_SPARE_VFIFO_ARB_SELECT | + DC3_SPARE_WM_LPEN_OVRD; + + /* SET THE NUMBER OF LOW PRIORITY LINES TO 3/4 THE TOTAL AVAILABLE */ + + temp = ((READ_REG32 (DC3_V_ACTIVE_TIMING) >> 16) & 0x7FF) + 1; + temp -= (READ_REG32 (DC3_V_SYNC_TIMING) & 0x7FF) + 1; + temp = (temp * 3) >> 2; + if (temp > 127) + temp = 127; + + acfg |= temp << 9; + } + else + { + /* LEGACY CHARACTERISTICS */ + /* Arbitration from a single set of watermarks. */ + + gcfg |= 0x0000B601; + msr_value.low |= DC3_SPARE_DISABLE_VFIFO_WM | DC3_SPARE_DISABLE_INIT_VID_PRI; + acfg = 0; + } + + msr_write64 (MSR_DEVICE_GEODELX_VG, DC3_SPARE_MSR, &msr_value); + + /* ENABLE FLAT PANEL CENTERING */ + /* For panel modes having a resolution smaller than the */ + /* panel resolution, turn on data centering. */ + + if (mode_params->flags & VG_MODEFLAG_CENTERED) + dcfg |= DC3_DCFG_DCEN; + + /* COMBINE AND SET TIMING VALUES */ + + temp = (mode_params->hactive - 1) | ((mode_params->htotal - 1) << 16); + WRITE_REG32(DC3_H_ACTIVE_TIMING, temp); + temp = (mode_params->hblankstart - 1) | ((mode_params->hblankend - 1) << 16); + WRITE_REG32(DC3_H_BLANK_TIMING, temp); + temp = (mode_params->hsyncstart - 1) | ((mode_params->hsyncend - 1) << 16); + WRITE_REG32(DC3_H_SYNC_TIMING, temp); + temp = (mode_params->vactive - 1) | ((mode_params->vtotal - 1) << 16); + WRITE_REG32(DC3_V_ACTIVE_TIMING, temp); + temp = (mode_params->vblankstart - 1) | ((mode_params->vblankend - 1) << 16); + WRITE_REG32(DC3_V_BLANK_TIMING, temp); + temp = (mode_params->vsyncstart - 1) | ((mode_params->vsyncend - 1) << 16); + WRITE_REG32(DC3_V_SYNC_TIMING, temp); + temp = (mode_params->vactive_even - 1) | ((mode_params->vtotal_even - 1) << 16); + WRITE_REG32(DC3_V_ACTIVE_EVEN, temp); + temp = (mode_params->vblankstart_even - 1) | ((mode_params->vblankend_even - 1) << 16); + WRITE_REG32(DC3_V_BLANK_EVEN, temp); + temp = (mode_params->vsyncstart_even - 1) | ((mode_params->vsyncend_even - 1) << 16); + WRITE_REG32(DC3_V_SYNC_EVEN, temp); + + /* SET THE VIDEO REQUEST REGISTER */ + + WRITE_VID32 (DF_VIDEO_REQUEST, 0); + + /* SET SOURCE DIMENSIONS */ + + WRITE_REG32 (DC3_FB_ACTIVE, ((starting_width - 1) << 16) | + (starting_height - 1)); + + /* SET SYNC POLARITIES */ + + temp = READ_VID32 (DF_DISPLAY_CONFIG); + + temp &= ~(DF_DCFG_CRT_SYNC_SKW_MASK | DF_DCFG_PWR_SEQ_DLY_MASK | + DF_DCFG_CRT_HSYNC_POL | DF_DCFG_CRT_VSYNC_POL); + + temp |= (DF_DCFG_CRT_SYNC_SKW_INIT | + DF_DCFG_PWR_SEQ_DLY_INIT | + DF_DCFG_GV_PAL_BYP); + + if (mode_params->flags & VG_MODEFLAG_NEG_HSYNC) + temp |= DF_DCFG_CRT_HSYNC_POL; + if (mode_params->flags & VG_MODEFLAG_NEG_VSYNC) + temp |= DF_DCFG_CRT_VSYNC_POL; + + WRITE_VID32 (DF_DISPLAY_CONFIG, temp); + + WRITE_REG32 (DC3_DISPLAY_CFG, dcfg); + WRITE_REG32 (DC3_ARB_CFG, acfg); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + + /* RESTORE VALUE OF DC3_UNLOCK */ + + WRITE_REG32(DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_bpp + * + * This routine changes the display BPP on the fly. It is intended only to + * switch between pixel depths of the same pixel size 24<->32 or 15<->16, NOT + * between pixel depths of differing sizes 16<->32 + *---------------------------------------------------------------------------*/ + +int vg_set_display_bpp (int bpp) +{ + unsigned long unlock, dcfg, bpp_mask; + + switch (bpp) + { + case 8: bpp_mask = DC3_DCFG_DISP_MODE_8BPP; break; + case 24: bpp_mask = DC3_DCFG_DISP_MODE_24BPP; break; + case 32: bpp_mask = DC3_DCFG_DISP_MODE_32BPP; break; + case 12: bpp_mask = DC3_DCFG_DISP_MODE_16BPP | DC3_DCFG_12BPP; break; + case 15: bpp_mask = DC3_DCFG_DISP_MODE_16BPP | DC3_DCFG_15BPP; break; + case 16: bpp_mask = DC3_DCFG_DISP_MODE_16BPP | DC3_DCFG_16BPP; break; + default: return CIM_STATUS_INVALIDPARAMS; + } + + unlock = READ_REG32 (DC3_UNLOCK); + dcfg = READ_REG32 (DC3_DISPLAY_CFG) & ~(DC3_DCFG_DISP_MODE_MASK | DC3_DCFG_16BPP_MODE_MASK); + dcfg |= bpp_mask; + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_DISPLAY_CFG, dcfg); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_get_display_mode_index + * + * This routine searches the Cimarron mode table for a mode that matches the + * input parameters. If a match is found, the return value is the index into + * the mode table. If no match is found, the return value is -1. + *---------------------------------------------------------------------------*/ + +int vg_get_display_mode_index (VG_QUERY_MODE *query) +{ + unsigned int mode; + unsigned long hz_flag = 0xFFFFFFFF; + unsigned long bpp_flag = 0xFFFFFFFF; + unsigned long enc_flag = 0xFFFFFFFF; + unsigned long tv_flag = 0; + unsigned long interlaced = 0; + unsigned long halfclock = 0; + long minimum = 0x7FFFFFFF; + long diff; + int match = -1; + + if (!query || !query->query_flags) + return -1; + + if (query->query_flags & VG_QUERYFLAG_REFRESH) + { + /* SET FLAGS TO MATCH REFRESH RATE */ + + if (query->hz == 56) hz_flag = VG_SUPPORTFLAG_56HZ; + else if (query->hz == 60) hz_flag = VG_SUPPORTFLAG_60HZ; + else if (query->hz == 70) hz_flag = VG_SUPPORTFLAG_70HZ; + else if (query->hz == 72) hz_flag = VG_SUPPORTFLAG_72HZ; + else if (query->hz == 75) hz_flag = VG_SUPPORTFLAG_75HZ; + else if (query->hz == 85) hz_flag = VG_SUPPORTFLAG_85HZ; + else if (query->hz == 90) hz_flag = VG_SUPPORTFLAG_90HZ; + else if (query->hz == 100) hz_flag = VG_SUPPORTFLAG_100HZ; + else hz_flag = 0; + } + + if (query->query_flags & VG_QUERYFLAG_BPP) + { + /* SET BPP FLAGS TO LIMIT MODE SELECTION */ + + if (query->bpp == 8) bpp_flag = VG_SUPPORTFLAG_8BPP; + else if (query->bpp == 12) bpp_flag = VG_SUPPORTFLAG_12BPP; + else if (query->bpp == 15) bpp_flag = VG_SUPPORTFLAG_15BPP; + else if (query->bpp == 16) bpp_flag = VG_SUPPORTFLAG_16BPP; + else if (query->bpp == 24) bpp_flag = VG_SUPPORTFLAG_24BPP; + else if (query->bpp == 32) bpp_flag = VG_SUPPORTFLAG_32BPP; + else bpp_flag = 0; + } + + if (query->query_flags & VG_QUERYFLAG_ENCODER) + { + /* SET ENCODER FLAGS TO LIMIT MODE SELECTION */ + + if (query->encoder == VG_ENCODER_ADV7171) enc_flag = VG_SUPPORTFLAG_ADV7171; + else if (query->encoder == VG_ENCODER_SAA7127) enc_flag = VG_SUPPORTFLAG_SAA7127; + else if (query->encoder == VG_ENCODER_FS454) enc_flag = VG_SUPPORTFLAG_FS454; + else if (query->encoder == VG_ENCODER_ADV7300) enc_flag = VG_SUPPORTFLAG_ADV7300; + else enc_flag = 0; + } + + if (query->query_flags & VG_QUERYFLAG_TVMODE) + { + /* SET ENCODER FLAGS TO LIMIT MODE SELECTION */ + + if (query->tvmode == VG_TVMODE_NTSC) tv_flag = VG_SUPPORTFLAG_NTSC; + else if (query->tvmode == VG_TVMODE_PAL) tv_flag = VG_SUPPORTFLAG_PAL; + else if (query->tvmode == VG_TVMODE_480P) tv_flag = VG_SUPPORTFLAG_480P; + else if (query->tvmode == VG_TVMODE_720P) tv_flag = VG_SUPPORTFLAG_720P; + else if (query->tvmode == VG_TVMODE_1080I) tv_flag = VG_SUPPORTFLAG_1080I; + else if (query->tvmode == VG_TVMODE_6X4_NTSC) tv_flag = VG_SUPPORTFLAG_6X4_NTSC; + else if (query->tvmode == VG_TVMODE_8X6_NTSC) tv_flag = VG_SUPPORTFLAG_8X6_NTSC; + else if (query->tvmode == VG_TVMODE_10X7_NTSC) tv_flag = VG_SUPPORTFLAG_10X7_NTSC; + else if (query->tvmode == VG_TVMODE_6X4_PAL) tv_flag = VG_SUPPORTFLAG_6X4_PAL; + else if (query->tvmode == VG_TVMODE_8X6_PAL) tv_flag = VG_SUPPORTFLAG_8X6_PAL; + else if (query->tvmode == VG_TVMODE_10X7_PAL) tv_flag = VG_SUPPORTFLAG_10X7_PAL; + else tv_flag = 0xFFFFFFFF; + } + + /* SET APPROPRIATE TV AND VOP FLAGS */ + + if (query->query_flags & VG_QUERYFLAG_INTERLACED) + interlaced = query->interlaced ? VG_MODEFLAG_INTERLACED : 0; + if (query->query_flags & VG_QUERYFLAG_HALFCLOCK) + halfclock = query->halfclock ? VG_MODEFLAG_HALFCLOCK : 0; + + /* CHECK FOR INVALID REQUEST */ + + if (!hz_flag || !bpp_flag || !enc_flag || tv_flag == 0xFFFFFFFF) + return -1; + + /* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */ + + for (mode = 0; mode < NUM_CIMARRON_DISPLAY_MODES; mode++) + { + if ( (!(query->query_flags & VG_QUERYFLAG_PANEL) || + (CimarronDisplayModes[mode].internal_flags & VG_SUPPORTFLAG_PANEL)) && + (!(query->query_flags & VG_QUERYFLAG_TVOUT) || + (CimarronDisplayModes[mode].internal_flags & VG_SUPPORTFLAG_TVOUT)) && + (!(query->query_flags & VG_QUERYFLAG_INTERLACED) || + (CimarronDisplayModes[mode].flags & VG_MODEFLAG_INTERLACED) == interlaced) && + (!(query->query_flags & VG_QUERYFLAG_HALFCLOCK) || + (CimarronDisplayModes[mode].flags & VG_MODEFLAG_HALFCLOCK) == halfclock) && + (!(query->query_flags & VG_QUERYFLAG_PANELWIDTH) || + (CimarronDisplayModes[mode].panel_width == query->panel_width)) && + (!(query->query_flags & VG_QUERYFLAG_PANELHEIGHT) || + (CimarronDisplayModes[mode].panel_height == query->panel_height)) && + (!(query->query_flags & VG_QUERYFLAG_ACTIVEWIDTH) || + (CimarronDisplayModes[mode].hactive == query->active_width)) && + (!(query->query_flags & VG_QUERYFLAG_ACTIVEHEIGHT) || + (CimarronDisplayModes[mode].vactive == query->active_height)) && + (!(query->query_flags & VG_QUERYFLAG_TOTALWIDTH) || + (CimarronDisplayModes[mode].htotal == query->total_width)) && + (!(query->query_flags & VG_QUERYFLAG_TOTALHEIGHT) || + (CimarronDisplayModes[mode].vtotal == query->total_height)) && + (!(query->query_flags & VG_QUERYFLAG_BPP) || + (CimarronDisplayModes[mode].internal_flags & bpp_flag)) && + (!(query->query_flags & VG_QUERYFLAG_REFRESH) || + (CimarronDisplayModes[mode].internal_flags & hz_flag)) && + (!(query->query_flags & VG_QUERYFLAG_ENCODER) || + (CimarronDisplayModes[mode].internal_flags & enc_flag)) && + (!(query->query_flags & VG_QUERYFLAG_TVMODE) || + ((CimarronDisplayModes[mode].internal_flags & VG_SUPPORTFLAG_TVMODEMASK) == tv_flag)) && + (!(query->query_flags & VG_QUERYFLAG_PIXELCLOCK) || + (CimarronDisplayModes[mode].frequency == query->frequency))) + { + /* ALLOW SEARCHING BASED ON AN APPROXIMATE PIXEL CLOCK */ + + if (query->query_flags & VG_QUERYFLAG_PIXELCLOCK_APPROX) + { + diff = query->frequency - CimarronDisplayModes[mode].frequency; + if (diff < 0) + diff = -diff; + + if (diff < minimum) + { + minimum = diff; + match = mode; + } + } + else + { + match = mode; + break; + } + } + } + + /* RETURN DISPLAY MODE INDEX */ + + return match; +} + +/*--------------------------------------------------------------------------- + * vg_get_display_mode_information + * + * This routine retrieves all information for a display mode contained + * within Cimarron's mode tables. + *---------------------------------------------------------------------------*/ + +int vg_get_display_mode_information (unsigned int index, VG_DISPLAY_MODE *vg_mode) +{ + if (index > NUM_CIMARRON_DISPLAY_MODES) + return CIM_STATUS_INVALIDPARAMS; + + *vg_mode = CimarronDisplayModes[index]; + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_get_display_mode_count + * + * This routine retrieves the count of all predefined Cimarron modes. + *---------------------------------------------------------------------------*/ + +int vg_get_display_mode_count (void) +{ + return NUM_CIMARRON_DISPLAY_MODES; +} + +/*--------------------------------------------------------------------------- + * vg_get_current_display_mode + * + * This routine retrieves the settings for the current display. This includes + * any panel settings. + *---------------------------------------------------------------------------*/ + +int vg_get_current_display_mode (VG_DISPLAY_MODE *current_display, int *bpp) +{ + Q_WORD msr_value; + unsigned long active, blank, sync; + unsigned long i, m, n, p; + unsigned long genlk, irq, temp; + unsigned long flags = 0; + unsigned long iflags = 0; + + /* READ THE CURRENT HORIZONTAL DISPLAY TIMINGS */ + + active = READ_REG32 (DC3_H_ACTIVE_TIMING); + blank = READ_REG32 (DC3_H_BLANK_TIMING); + sync = READ_REG32 (DC3_H_SYNC_TIMING); + + current_display->hactive = (active & 0xFFF) + 1; + current_display->hblankstart = (blank & 0xFFF) + 1; + current_display->hsyncstart = (sync & 0xFFF) + 1; + + current_display->htotal = ((active >> 16) & 0xFFF) + 1; + current_display->hblankend = ((blank >> 16) & 0xFFF) + 1; + current_display->hsyncend = ((sync >> 16) & 0xFFF) + 1; + + /* READ THE CURRENT VERTICAL DISPLAY TIMINGS */ + + active = READ_REG32 (DC3_V_ACTIVE_TIMING); + blank = READ_REG32 (DC3_V_BLANK_TIMING); + sync = READ_REG32 (DC3_V_SYNC_TIMING); + + current_display->vactive = (active & 0x7FF) + 1; + current_display->vblankstart = (blank & 0x7FF) + 1; + current_display->vsyncstart = (sync & 0x7FF) + 1; + + current_display->vtotal = ((active >> 16) & 0x7FF) + 1; + current_display->vblankend = ((blank >> 16) & 0x7FF) + 1; + current_display->vsyncend = ((sync >> 16) & 0x7FF) + 1; + + /* READ THE CURRENT EVEN FIELD VERTICAL DISPLAY TIMINGS */ + + active = READ_REG32 (DC3_V_ACTIVE_EVEN); + blank = READ_REG32 (DC3_V_BLANK_EVEN); + sync = READ_REG32 (DC3_V_SYNC_EVEN); + + current_display->vactive_even = (active & 0x7FF) + 1; + current_display->vblankstart_even = (blank & 0x7FF) + 1; + current_display->vsyncstart_even = (sync & 0x7FF) + 1; + + current_display->vtotal_even = ((active >> 16) & 0x7FF) + 1; + current_display->vblankend_even = ((blank >> 16) & 0x7FF) + 1; + current_display->vsyncend_even = ((sync >> 16) & 0x7FF) + 1; + + /* READ THE CURRENT SOURCE DIMENSIONS */ + /* The DC3_FB_ACTIVE register is only used when scaling is enabled. */ + /* As the goal of this routine is to return a structure that can be */ + /* passed to vg_set_custom_mode to exactly recreate the current mode, */ + /* we must check the status of the scaler/filter. */ + + genlk = READ_REG32 (DC3_GENLK_CTL); + irq = READ_REG32 (DC3_IRQ_FILT_CTL); + temp = READ_REG32 (DC3_FB_ACTIVE); + + current_display->src_height = (temp & 0xFFFF) + 1; + current_display->src_width = ((temp >> 16) & 0xFFF8) + 8; + + /* READ THE CURRENT PANEL CONFIGURATION */ + /* We can only infer some of the panel settings based on hardware */ + /* (like when panning). We will instead assume that the current */ + /* mode was set using Cimarron and use the panel variables inside */ + /* Cimarron when returning the current mode information. */ + + if (vg3_panel_enable) + { + Q_WORD msr_value; + + flags |= VG_MODEFLAG_PANELOUT; + + current_display->panel_width = vg3_panel_width; + current_display->panel_height = vg3_panel_height; + current_display->mode_width = vg3_mode_width; + current_display->mode_height = vg3_mode_height; + + if (READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_DCEN) + flags |= VG_MODEFLAG_CENTERED; + + msr_read64 (MSR_DEVICE_GEODELX_DF, DF_MSR_PAD_SEL, &msr_value); + current_display->panel_tim1 = READ_VID32 (DF_VIDEO_PANEL_TIM1); + current_display->panel_tim2 = READ_VID32 (DF_VIDEO_PANEL_TIM2); + current_display->panel_dither_ctl = READ_VID32 (DF_DITHER_CONTROL); + current_display->panel_pad_sel_low = msr_value.low; + current_display->panel_pad_sel_high = msr_value.high; + } + + /* SET MISCELLANEOUS MODE FLAGS */ + + /* INTERLACED */ + + if (irq & DC3_IRQFILT_INTL_EN) + { + flags |= VG_MODEFLAG_INTERLACED; + if (irq & DC3_IRQFILT_INTL_ADDR) + flags |= VG_MODEFLAG_INT_ADDRESS; + else if (genlk & DC3_GC_FLICKER_FILTER_ENABLE) + flags |= VG_MODEFLAG_INT_FLICKER; + else + flags |= VG_MODEFLAG_INT_LINEDOUBLE; + } + + /* POLARITIES */ + + temp = READ_VID32 (DF_DISPLAY_CONFIG); + if (temp & DF_DCFG_CRT_HSYNC_POL) + flags |= VG_MODEFLAG_NEG_HSYNC; + if (temp & DF_DCFG_CRT_VSYNC_POL) + flags |= VG_MODEFLAG_NEG_VSYNC; + + /* BPP */ + + temp = READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_DISP_MODE_MASK; + if (temp == DC3_DCFG_DISP_MODE_8BPP) + { + iflags |= VG_SUPPORTFLAG_8BPP; + *bpp = 8; + } + else if (temp == DC3_DCFG_DISP_MODE_24BPP) + { + iflags |= VG_SUPPORTFLAG_24BPP; + *bpp = 24; + } + else if (temp == DC3_DCFG_DISP_MODE_32BPP) + { + iflags |= VG_SUPPORTFLAG_32BPP; + *bpp = 32; + } + else if (temp == DC3_DCFG_DISP_MODE_16BPP) + { + temp = READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_16BPP_MODE_MASK; + if (temp == DC3_DCFG_16BPP) + { + iflags |= VG_SUPPORTFLAG_16BPP; + *bpp = 16; + } + else if (temp == DC3_DCFG_15BPP) + { + iflags |= VG_SUPPORTFLAG_15BPP; + *bpp = 15; + } + else if (temp == DC3_DCFG_12BPP) + { + iflags |= VG_SUPPORTFLAG_12BPP; + *bpp = 12; + } + } + + /* TV RELATED FLAGS */ + + msr_read64 (MSR_DEVICE_GEODELX_DF, DF_MSR_PAD_SEL, &msr_value); + if (msr_value.high & DF_INVERT_VOP_CLOCK) + flags |= VG_MODEFLAG_TVOUT; + + /* LINEAR PITCH */ + + temp = (READ_REG32 (DC3_GFX_PITCH) & 0x0000FFFF) << 3; + if (temp != 1024 && temp != 2048 && temp != 4096 && temp != 8192) + flags |= VG_MODEFLAG_LINEARPITCH; + + /* SIMULTANEOUS CRT/FP */ + + msr_read64 (MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &msr_value); + if (msr_value.low & DF_SIMULTANEOUS_CRT_FP) + flags |= VG_MODEFLAG_CRT_AND_FP; + + /* SET PLL-RELATED FLAGS */ + + msr_read64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DOTPLL, &msr_value); + if (msr_value.high & GLCP_DOTPLL_DIV4) + flags |= VG_MODEFLAG_QVGA; + if (msr_value.low & GLCP_DOTPLL_HALFPIX) + flags |= VG_MODEFLAG_HALFCLOCK; + + /* SAVE THE FLAGS IN THE MODE STRUCTURE */ + + current_display->internal_flags = iflags; + current_display->flags = flags; + + /* READ PIXEL CLOCK FREQUENCY */ + /* We first search for an exact match. If none is found, we try */ + /* a fixed point calculation and return CIM_STATUS_INEXACTMATCH. */ + + for (i = 0; i < NUM_CIMARRON_PLL_FREQUENCIES; i++) + { + if (CimarronPLLFrequencies[i].pll_value == msr_value.high) + break; + } + + if (i == NUM_CIMARRON_PLL_FREQUENCIES) + { + /* ATTEMPT 16.16 CALCULATION */ + /* We assume the input frequency is 48 MHz, which is represented */ + /* in 16.16 fixed point as 0x300000. The PLL calculation is: */ + /* n + 1 */ + /* Fout = 48.000 * -------------- */ + /* m + 1 * p + 1 */ + + p = msr_value.high & 0xF; + n = (msr_value.high >> 4) & 0xFF; + m = (msr_value.high >> 12) & 0x7; + current_display->frequency = (0x300000 * (n + 1)) / ((p + 1) * (m + 1)); + + return CIM_STATUS_INEXACTMATCH; + } + + current_display->frequency = CimarronPLLFrequencies[i].frequency; + + /* NOW SEARCH FOR AN IDENTICAL MODE */ + /* This is just to inform the user that an exact match was found. */ + /* With an exact match, the user can use the refresh rate flag that */ + /* is returned in the VG_DISPLAY_MODE structure. */ + + for (i = 0; i < NUM_CIMARRON_DISPLAY_MODES; i++) + { + if ((CimarronDisplayModes[i].flags & current_display->flags) && + CimarronDisplayModes[i].frequency == current_display->frequency && + CimarronDisplayModes[i].hactive == current_display->hactive && + CimarronDisplayModes[i].hblankstart == current_display->hblankstart && + CimarronDisplayModes[i].hsyncstart == current_display->hsyncstart && + CimarronDisplayModes[i].hsyncend == current_display->hsyncend && + CimarronDisplayModes[i].hblankend == current_display->hblankend && + CimarronDisplayModes[i].htotal == current_display->htotal && + CimarronDisplayModes[i].vactive == current_display->vactive && + CimarronDisplayModes[i].vblankstart == current_display->vblankstart && + CimarronDisplayModes[i].vsyncstart == current_display->vsyncstart && + CimarronDisplayModes[i].vsyncend == current_display->vsyncend && + CimarronDisplayModes[i].vblankend == current_display->vblankend && + CimarronDisplayModes[i].vtotal == current_display->vtotal) + { + break; + } + } + + if (i == NUM_CIMARRON_DISPLAY_MODES) + return CIM_STATUS_INEXACTMATCH; + + current_display->internal_flags |= (CimarronDisplayModes[i].internal_flags & VG_SUPPORTFLAG_HZMASK); + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_scaler_filter_coefficients + * + * This routine sets the vertical and horizontal filter coefficients for + * graphics scaling. If either of the input arrays is specified as NULL, a + * set of default coeffecients will be used. + *---------------------------------------------------------------------------*/ + +int vg_set_scaler_filter_coefficients (long h_taps[][5], long v_taps[][3]) +{ + unsigned long irqfilt, i; + unsigned long temp0, temp1; + unsigned long lock; + + /* ENABLE ACCESS TO THE HORIZONTAL COEFFICIENTS */ + + irqfilt = READ_REG32 (DC3_IRQ_FILT_CTL); + irqfilt |= DC3_IRQFILT_H_FILT_SEL; + + /* UNLOCK THE COEFFICIENT REGISTERS */ + + lock = READ_REG32 (DC3_UNLOCK); + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + + /* WRITE COEFFICIENTS */ + /* Coefficient indexes do not auto-increment, so we must */ + /* write the address for every phase */ + + for (i = 0; i < 256; i++) + { + WRITE_REG32 (DC3_IRQ_FILT_CTL, ((irqfilt & 0xFFFFFF00L) | i)); + + if (!h_taps) + { + temp0 = CimarronHorizontalGraphicsFilter[i][0]; + temp1 = CimarronHorizontalGraphicsFilter[i][1]; + } + else + { + temp0 = ((unsigned long)h_taps[i][0] & 0x3FF) | + (((unsigned long)h_taps[i][1] & 0x3FF) << 10) | + (((unsigned long)h_taps[i][2] & 0x3FF) << 20); + + temp1 = ((unsigned long)h_taps[i][3] & 0x3FF) | + (((unsigned long)h_taps[i][4] & 0x3FF) << 10); + } + WRITE_REG32 (DC3_FILT_COEFF1, temp0); + WRITE_REG32 (DC3_FILT_COEFF2, temp1); + } + + /* ENABLE ACCESS TO THE VERTICAL COEFFICIENTS */ + + irqfilt &= ~DC3_IRQFILT_H_FILT_SEL; + + /* WRITE COEFFICIENTS */ + + for (i = 0; i < 256; i++) + { + WRITE_REG32 (DC3_IRQ_FILT_CTL, ((irqfilt & 0xFFFFFF00L) | i)); + + if (!v_taps) + { + temp0 = CimarronVerticalGraphicsFilter[i]; + } + else + { + temp0 = ((unsigned long)v_taps[i][0] & 0x3FF) | + (((unsigned long)v_taps[i][1] & 0x3FF) << 10) | + (((unsigned long)v_taps[i][2] & 0x3FF) << 20); + } + + WRITE_REG32 (DC3_FILT_COEFF1, temp0); + } + + WRITE_REG32 (DC3_UNLOCK, lock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_configure_flicker_filter + * + * This routine updates the VG flicker filter settings when in an interlaced + * mode. Note that flicker filtering is enabled inside a mode set. This routine + * is provided to change from the default flicker filter setting of + * 1/4, 1/2, 1/4. + *---------------------------------------------------------------------------*/ + +int vg_configure_flicker_filter (unsigned long flicker_strength, int flicker_alpha) +{ + unsigned long unlock; + unsigned long genlk_ctl; + + /* CHECK FOR VALID FLICKER SETTING */ + + if (flicker_strength != VG_FLICKER_FILTER_NONE && + flicker_strength != VG_FLICKER_FILTER_1_16 && + flicker_strength != VG_FLICKER_FILTER_1_8 && + flicker_strength != VG_FLICKER_FILTER_1_4 && + flicker_strength != VG_FLICKER_FILTER_5_16) + { + return CIM_STATUS_INVALIDPARAMS; + } + + unlock = READ_REG32 (DC3_UNLOCK); + genlk_ctl = READ_REG32 (DC3_GENLK_CTL) & ~(DC3_GC_FLICKER_FILTER_MASK | DC3_GC_ALPHA_FLICK_ENABLE); + genlk_ctl |= flicker_strength; + if (flicker_alpha) + genlk_ctl |= DC3_GC_ALPHA_FLICK_ENABLE; + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_GENLK_CTL, genlk_ctl); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_clock_frequency + * + * This routine sets the frequency of the dot clock. The input to this routine + * is a 16.16 fraction. If an exact match is not found, this routine will program + * the closest available frequency and return CIM_STATUS_INEXACTMATCH. + *---------------------------------------------------------------------------*/ + +int vg_set_clock_frequency (unsigned long frequency, unsigned long pll_flags) +{ + Q_WORD msr_value; + unsigned long timeout; + unsigned long index = 0; + unsigned long unlock, i; + unsigned long pll_high, pll_low; + long diff, min = 0; + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + /* This search is skipped if the user is manually specifying */ + /* the MSR value. */ + + pll_low = 0; + if (!(pll_flags & VG_PLL_MANUAL)) + { + min = (long)CimarronPLLFrequencies[0].frequency - (long)frequency; + if (min < 0L) + min = -min; + + for (i = 1; i < NUM_CIMARRON_PLL_FREQUENCIES; i++) + { + diff = (long)CimarronPLLFrequencies[i].frequency - (long)frequency; + if (diff < 0L) + diff = -diff; + + if (diff < min) + { + min = diff; + index = i; + } + } + + pll_high = CimarronPLLFrequencies[index].pll_value & 0x00007FFF; + } + else + { + pll_high = frequency; + } + + if (pll_flags & VG_PLL_DIVIDE_BY_2) + pll_low |= GLCP_DOTPLL_HALFPIX; + if (pll_flags & VG_PLL_DIVIDE_BY_4) + pll_high |= GLCP_DOTPLL_DIV4; + if (pll_flags & VG_PLL_BYPASS) + pll_low |= GLCP_DOTPLL_BYPASS; + if (pll_flags & VG_PLL_VIP_CLOCK) + pll_high |= GLCP_DOTPLL_VIPCLK; + + /* VERIFY THAT WE ARE NOT WRITING WHAT IS ALREADY IN THE REGISTERS */ + /* The Dot PLL reset bit is tied to VDD for flat panels. This can */ + /* cause a brief drop in flat panel power, which can cause serious */ + /* glitches on some panels. */ + + msr_read64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DOTPLL, &msr_value); + + if ((msr_value.low & GLCP_DOTPLL_LOCK) && + ((msr_value.low & (GLCP_DOTPLL_HALFPIX | GLCP_DOTPLL_BYPASS)) == pll_low) && + (msr_value.high == pll_high)) + { + return CIM_STATUS_OK; + } + + /* PROGRAM THE SETTINGS WITH THE RESET BIT SET */ + /* Clear the bypass bit to ensure that the programmed */ + /* M, N and P values are being used. */ + + msr_value.high = pll_high; + msr_value.low &= ~(GLCP_DOTPLL_BYPASS | GLCP_DOTPLL_HALFPIX); + msr_value.low |= (pll_low | 0x00000001); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DOTPLL, &msr_value); + + /* WAIT FOR THE LOCK BIT */ + /* The PLL spec states that the PLL may take up to 100 us to */ + /* properly lock. Furthermore, the lock signal is not 100% */ + /* reliable. To address this, we add a hefty delay followed */ + /* by a polling loop that times out after a 1000 reads. */ + + unlock = READ_REG32 (DC3_UNLOCK); + for (timeout = 0; timeout < 1280; timeout++) + WRITE_REG32 (DC3_UNLOCK, unlock); + + for (timeout = 0; timeout < 1000; timeout++) + { + msr_read64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DOTPLL, &msr_value); + if (msr_value.low & GLCP_DOTPLL_LOCK) + break; + } + + /* CLEAR THE RESET BIT */ + + msr_value.low &= 0xFFFFFFFE; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DOTPLL, &msr_value); + + /* DID THE PLL SUCCESSFULLY LOCK? */ + + if (!(msr_value.low & GLCP_DOTPLL_LOCK)) + return CIM_STATUS_NOLOCK; + + /* RETURN THE APPROPRIATE CODE */ + + if (min == 0) + return CIM_STATUS_OK; + else + return CIM_STATUS_INEXACTMATCH; +} + +/*--------------------------------------------------------------------------- + * vg_set_border_color + * + * This routine sets the color used as the border in centered panel modes. + *---------------------------------------------------------------------------*/ + +int vg_set_border_color (unsigned long border_color) +{ + unsigned long lock = READ_REG32 (DC3_UNLOCK); + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_PAL_ADDRESS, 0x104); + WRITE_REG32 (DC3_PAL_DATA, border_color); + WRITE_REG32 (DC3_UNLOCK, lock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_cursor_enable + * + * This routine enables or disables the hardware cursor. This routine should + * only be called after the hardware cursor has been completely configured. + *---------------------------------------------------------------------------*/ + +int vg_set_cursor_enable(int enable) +{ + unsigned long unlock, gcfg; + + /* SET OR CLEAR CURSOR ENABLE BIT */ + + unlock = READ_REG32(DC3_UNLOCK); + gcfg = READ_REG32(DC3_GENERAL_CFG); + if (enable) gcfg |= DC3_GCFG_CURE; + else gcfg &= ~(DC3_GCFG_CURE); + + /* WRITE NEW REGISTER VALUE */ + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_mono_cursor_colors + * + * This routine sets the colors of the hardware monochrome cursor. + *---------------------------------------------------------------------------*/ + +int vg_set_mono_cursor_colors (unsigned long bkcolor, unsigned long fgcolor) +{ + unsigned long lock = READ_REG32 (DC3_UNLOCK); + + /* SET CURSOR COLORS */ + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_PAL_ADDRESS, 0x100); + WRITE_REG32 (DC3_PAL_DATA, bkcolor); + WRITE_REG32 (DC3_PAL_DATA, fgcolor); + WRITE_REG32 (DC3_UNLOCK, lock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_cursor_position + * + * This routine sets the position of the hardware cursor. The cursor hotspots + * and memory offset must have been specified in an earlier call to + * a vg_set_cursor_shape_XX routine. The coordinates passed to this routine + * generally specify the focal point of the cursor, NOT the upper left coordinate of + * the cursor pattern. However, for operating systems that do not include a hotspot + * the input parameters may be negative. + *---------------------------------------------------------------------------*/ + +int vg_set_cursor_position (long xpos, long ypos, VG_PANNING_COORDINATES *panning) +{ + unsigned long unlock, memoffset; + unsigned long gcfg; + long x, xoffset; + long y, yoffset; + + memoffset = vg3_cursor_offset; + x = xpos - (long) vg3_x_hotspot; + y = ypos - (long) vg3_y_hotspot; + + /* HANDLE NEGATIVE COORDINATES */ + /* This routine supports operating systems that use negative */ + /* coordinates, instead of positive coordinates with an appropriate */ + /* hotspot. */ + + if (xpos < 0) xpos = 0; + if (ypos < 0) ypos = 0; + + if (x < -63) return CIM_STATUS_INVALIDPARAMS; + if (y < -63) return CIM_STATUS_INVALIDPARAMS; + + if (vg3_panel_enable) + { + if ((vg3_mode_width > vg3_panel_width) || (vg3_mode_height > vg3_panel_height)) + { + vg_pan_desktop (xpos, ypos, panning); + x = x - (unsigned short)vg3_delta_x; + y = y - (unsigned short)vg3_delta_y; + } + else + { + panning->start_x = 0; + panning->start_y = 0; + panning->start_updated = 0; + } + } + + /* ADJUST OFFSETS */ + /* Cursor movement and panning work as follows: The cursor position */ + /* refers to where the hotspot of the cursor is located. However, for */ + /* non-zero hotspots, the cursor buffer actually begins before the */ + /* specified position. */ + + if (x < 0) { xoffset = -x; x = 0; } + else { xoffset = 0; } + if (y < 0) { yoffset = -y; y = 0; } + else { yoffset = 0; } + + if (vg3_color_cursor) memoffset += (unsigned long) yoffset * 192; + else memoffset += (unsigned long) yoffset << 4; + + /* SET COLOR CURSOR BIT */ + + gcfg = READ_REG32(DC3_GENERAL_CFG); + if (vg3_color_cursor) + gcfg |= DC3_GCFG_CLR_CUR; + else + gcfg &= ~DC3_GCFG_CLR_CUR; + + /* SET CURSOR POSITION */ + + unlock = READ_REG32(DC3_UNLOCK); + WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_CURS_ST_OFFSET, memoffset); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + WRITE_REG32 (DC3_CURSOR_X, (unsigned long) x | + (((unsigned long) xoffset) << 11)); + WRITE_REG32 (DC3_CURSOR_Y, (unsigned long) y | + (((unsigned long) yoffset) << 11)); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_mono_cursor_shape32 + * + * This routine loads 32x32 cursor data into the cursor buffer in graphics memory. + * The outside of the GeodeLX cursor buffer is padded with transparency. + *---------------------------------------------------------------------------*/ + +int vg_set_mono_cursor_shape32 (unsigned long memoffset, unsigned long *andmask, + unsigned long *xormask, unsigned long x_hotspot, unsigned long y_hotspot) +{ + int i; + + /* SAVE THE CURSOR OFFSET AND HOTSPOTS */ + /* These are reused later when updating the cursor position, panning */ + /* and clipping the cursor pointer. */ + + vg3_x_hotspot = x_hotspot; + vg3_y_hotspot = y_hotspot; + vg3_cursor_offset = memoffset; + vg3_color_cursor = 0; + + for (i = 0; i < 32; i++) + { + /* EVEN QWORDS CONTAIN THE AND MASK */ + + WRITE_FB32 (memoffset, 0xFFFFFFFF); + WRITE_FB32 (memoffset + 4, andmask[i]); + + /* ODD QWORDS CONTAIN THE XOR MASK */ + + WRITE_FB32 (memoffset + 8, 0x00000000); + WRITE_FB32 (memoffset + 12, xormask[i]); + + memoffset += 16; + } + + /* FILL THE LOWER HALF OF THE BUFFER WITH TRANSPARENT PIXELS */ + + for (i = 0; i < 32; i++) + { + WRITE_FB32 (memoffset, 0xFFFFFFFF); + WRITE_FB32 (memoffset + 4, 0xFFFFFFFF); + WRITE_FB32 (memoffset + 8, 0x00000000); + WRITE_FB32 (memoffset + 12, 0x00000000); + + memoffset += 16; + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_mono_cursor_shape64 + * + * This routine loads 64x64 cursor data into the cursor buffer in graphics memory. + *---------------------------------------------------------------------------*/ + +int vg_set_mono_cursor_shape64 (unsigned long memoffset, unsigned long *andmask, + unsigned long *xormask, unsigned long x_hotspot, unsigned long y_hotspot) +{ + int i; + + /* SAVE THE CURSOR OFFSET AND HOTSPOTS */ + /* These are reused later when updating the cursor position, panning */ + /* and clipping the cursor pointer. */ + + vg3_x_hotspot = x_hotspot; + vg3_y_hotspot = y_hotspot; + vg3_cursor_offset = memoffset; + vg3_color_cursor = 0; + + for (i = 0; i < 128; i += 2) + { + /* EVEN QWORDS CONTAIN THE AND MASK */ + /* We invert the dwords to prevent the calling */ + /* application from having to think in terms of Qwords. */ + /* The hardware data order is actually 63:0, or 31:0 of */ + /* the second dword followed by 31:0 of the first dword. */ + + WRITE_FB32 (memoffset, andmask[i + 1]); + WRITE_FB32 (memoffset + 4, andmask[i]); + + /* ODD QWORDS CONTAIN THE XOR MASK */ + + WRITE_FB32 (memoffset + 8, xormask[i + 1]); + WRITE_FB32 (memoffset + 12, xormask[i]); + + memoffset += 16; + } + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_color_cursor_shape + * + * This routine loads 8:8:8:8 cursor data into the color cursor buffer. + *---------------------------------------------------------------------------*/ + +int vg_set_color_cursor_shape (unsigned long memoffset, unsigned char *data, + unsigned long width, unsigned long height, long pitch, + unsigned long x_hotspot, unsigned long y_hotspot) +{ + unsigned long y; + + /* SAVE THE CURSOR OFFSET AND HOTSPOTS */ + /* These are reused later when updating the cursor position, panning */ + /* and clipping the cursor pointer. */ + + vg3_x_hotspot = x_hotspot; + vg3_y_hotspot = y_hotspot; + vg3_cursor_offset = memoffset; + vg3_color_cursor = 1; + + /* WRITE THE CURSOR DATA */ + /* The outside edges of the color cursor are filled with transparency */ + /* The cursor buffer dimensions are 48x64. */ + + for (y = 0; y < height; y++) + { + /* WRITE THE ACTIVE AND TRANSPARENT DATA */ + /* We implement this as a macro in our dedication to squeaking */ + /* every ounce of performance out of our code... */ + + WRITE_FB_STRING32 (memoffset, data, width); + WRITE_FB_CONSTANT ((memoffset + (width << 2)), 0, (48 - width)); + + /* INCREMENT PAST THE LINE */ + + memoffset += 192; + data += pitch; + } + + /* WRITE THE EXTRA TRANSPARENT LINES */ + /* Write the lines in one big bulk setting. */ + + WRITE_FB_CONSTANT (memoffset, 0, ((64 - height) * 48)); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_pan_desktop + * + * This routine sets the correct display offset based on the current cursor + * position. + *---------------------------------------------------------------------------*/ + +int vg_pan_desktop (unsigned long x, unsigned long y, VG_PANNING_COORDINATES *panning) +{ + unsigned long modeShiftPerPixel; + unsigned long modeBytesPerScanline; + unsigned long startAddress; + + /* TEST FOR NO-WORK */ + + if (x >= vg3_delta_x && x < (vg3_panel_width + vg3_delta_x) && + y >= vg3_delta_y && y < (vg3_panel_height + vg3_delta_y)) + { + panning->start_x = vg3_delta_x; + panning->start_y = vg3_delta_y; + panning->start_updated = 0; + return CIM_STATUS_OK; + } + + if (vg3_bpp == 24) modeShiftPerPixel = 2; + else modeShiftPerPixel = (vg3_bpp + 7) >> 4; + + modeBytesPerScanline = (READ_REG32 (DC3_GFX_PITCH) & 0x0000FFFF) << 3; + + /* ADJUST PANNING VARIABLES WHEN CURSOR EXCEEDS BOUNDARY */ + /* Test the boundary conditions for each coordinate and update */ + /* all variables and the starting offset accordingly. */ + + if (x < vg3_delta_x) + vg3_delta_x = x; + + else if (x >= (vg3_delta_x + vg3_panel_width)) + vg3_delta_x = x - vg3_panel_width + 1; + + if (y < vg3_delta_y) + vg3_delta_y = y; + + else if (y >= (vg3_delta_y + vg3_panel_height)) + vg3_delta_y = y - vg3_panel_height + 1; + + /* CALCULATE THE START OFFSET */ + + startAddress = (vg3_delta_x << modeShiftPerPixel) + (vg3_delta_y * modeBytesPerScanline); + + vg_set_display_offset (startAddress); + + panning->start_updated = 1; + panning->start_x = vg3_delta_x; + panning->start_y = vg3_delta_y; + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_display_offset + * + * This routine sets the start address of the frame buffer. It is + * typically used to pan across a virtual desktop (frame buffer larger than + * the displayed screen) or to flip the display between multiple buffers. + *---------------------------------------------------------------------------*/ + +int vg_set_display_offset (unsigned long address) +{ + unsigned long lock, gcfg; + + lock = READ_REG32 (DC3_UNLOCK); + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + + /* DISABLE COMPRESSION */ + /* When setting a non-zero display offset, we must disable display */ + /* compression. We could maintain a variable and re-enable */ + /* compression when the offset returns to zero. However, that */ + /* creates additional complexity for applications that perform */ + /* graphics animation. Re-enabling compression each time would */ + /* be tedious and slow for such applications, implying that they */ + /* would have to disable compression before starting the animation. */ + /* We will instead disable compression and force the user to */ + /* re-enable compression when they are ready. */ + + if (address != 0) + { + if (READ_REG32 (DC3_GENERAL_CFG) & DC3_GCFG_CMPE) + { + gcfg = READ_REG32 (DC3_GENERAL_CFG); + WRITE_REG32 (DC3_GENERAL_CFG, (gcfg & ~(DC3_GCFG_CMPE | DC3_GCFG_DECE))); + } + } + + WRITE_REG32 (DC3_FB_ST_OFFSET, address); + WRITE_REG32 (DC3_UNLOCK, lock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_display_pitch + * + * This routine sets the stride between successive lines of data in the frame + * buffer. + *---------------------------------------------------------------------------*/ + +int vg_set_display_pitch (unsigned long pitch) +{ + unsigned long temp, dvsize, dvtop, value; + unsigned long lock = READ_REG32(DC3_UNLOCK); + + value = READ_REG32(DC3_GFX_PITCH) & 0xFFFF0000; + value |= (pitch >> 3); + + /* PROGRAM THE DISPLAY PITCH */ + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_GFX_PITCH, value); + + /* SET THE COMPRESSION BEHAVIOR BASED ON THE PITCH */ + /* Strides that are not a power of two will not work with line */ + /* by line compression. For these cases, we enable full-screen */ + /* compression. In this mode, any write to the frame buffer */ + /* region marks the entire frame as dirty. Also, the DV line */ + /* size must be updated when the pitch is programmed outside of */ + /* the power of 2 range specified in a mode set. */ + + if (pitch > 4096) { dvsize = DC3_DV_LINE_SIZE_8192; } + else if (pitch > 2048) { dvsize = DC3_DV_LINE_SIZE_4096; } + else if (pitch > 1024) { dvsize = DC3_DV_LINE_SIZE_2048; } + else { dvsize = DC3_DV_LINE_SIZE_1024; } + + temp = READ_REG32 (DC3_DV_CTL); + WRITE_REG32 (DC3_DV_CTL, (temp & ~DC3_DV_LINE_SIZE_MASK) | dvsize | 0x00000001); + + value = READ_REG32 (DC3_GENERAL_CFG); + + if (pitch == 1024 || pitch == 2048 || pitch == 4096 || pitch == 8192) + { + value &= ~DC3_GCFG_FDTY; + dvtop = 0; + } + else + { + value |= DC3_GCFG_FDTY; + + dvtop = (READ_REG32 (DC3_FB_ACTIVE) & 0xFFF) + 1; + dvtop = ((dvtop * pitch) + 0x3FF) & 0xFFFFFC00; + dvtop |= DC3_DVTOP_ENABLE; + } + + WRITE_REG32 (DC3_GENERAL_CFG, value); + WRITE_REG32 (DC3_DV_TOP, dvtop); + WRITE_REG32 (DC3_UNLOCK, lock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_display_palette_entry + * + * This routine sets a single 8BPP palette entry in the display controller. + *---------------------------------------------------------------------------*/ + +int vg_set_display_palette_entry (unsigned long index, unsigned long palette) +{ + unsigned long dcfg, unlock; + + if (index > 0xFF) + return CIM_STATUS_INVALIDPARAMS; + + unlock = READ_REG32 (DC3_UNLOCK); + dcfg = READ_REG32 (DC3_DISPLAY_CFG); + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_DISPLAY_CFG, dcfg & ~DC3_DCFG_PALB); + WRITE_REG32 (DC3_UNLOCK, unlock); + + WRITE_REG32 (DC3_PAL_ADDRESS, index); + WRITE_REG32 (DC3_PAL_DATA, palette); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_set_display_palette + * + * This routine sets the entire palette in the display controller. + * A pointer is provided to a 256 entry table of 32-bit X:R:G:B values. + *---------------------------------------------------------------------------*/ + +int vg_set_display_palette (unsigned long *palette) +{ + unsigned long unlock, dcfg, i; + WRITE_REG32 (DC3_PAL_ADDRESS, 0); + + if (palette) + { + unlock = READ_REG32 (DC3_UNLOCK); + dcfg = READ_REG32 (DC3_DISPLAY_CFG); + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_DISPLAY_CFG, dcfg & ~DC3_DCFG_PALB); + WRITE_REG32 (DC3_UNLOCK, unlock); + + for (i = 0; i < 256; i++) + WRITE_REG32 (DC3_PAL_DATA, palette[i]); + + return CIM_STATUS_OK; + } + return CIM_STATUS_INVALIDPARAMS; +} + +/*--------------------------------------------------------------------------- + * vg_set_compression_enable + * + * This routine enables or disables display compression. + *---------------------------------------------------------------------------*/ + +int vg_set_compression_enable (int enable) +{ + Q_WORD msr_value; + unsigned long unlock, gcfg; + unsigned long temp; + + unlock = READ_REG32 (DC3_UNLOCK); + gcfg = READ_REG32 (DC3_GENERAL_CFG); + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + + if (enable) + { + /* DO NOT ENABLE IF THE DISPLAY OFFSET IS NOT ZERO */ + + if (READ_REG32 (DC3_FB_ST_OFFSET) & 0x0FFFFFFF) + return CIM_STATUS_ERROR; + + /* ENABLE BIT 1 IN THE VG SPARE MSR */ + /* The bus can hang when the VG attempts to merge compression writes. */ + /* No performance is lost due to the GeodeLink QUACK features in */ + /* GeodeLX. We also enable the command word check for a valid */ + /* compression header. */ + + msr_read64 (MSR_DEVICE_GEODELX_VG, DC3_SPARE_MSR, &msr_value); + msr_value.low |= DC3_SPARE_FIRST_REQ_MASK; + msr_value.low &= ~DC3_SPARE_DISABLE_CWD_CHECK; + msr_write64 (MSR_DEVICE_GEODELX_VG, DC3_SPARE_MSR, &msr_value); + + /* CLEAR DIRTY/VALID BITS IN MEMORY CONTROLLER */ + /* We don't want the controller to think that old lines are still */ + /* valid. Writing a 1 to bit 0 of the DV Control register will force */ + /* the hardware to clear all the valid bits. */ + + temp = READ_REG32 (DC3_DV_CTL); + WRITE_REG32 (DC3_DV_CTL, temp | 0x00000001); + + /* ENABLE COMPRESSION BITS */ + + gcfg |= DC3_GCFG_CMPE | DC3_GCFG_DECE; + } + else + { + gcfg &= ~(DC3_GCFG_CMPE | DC3_GCFG_DECE); + } + + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_configure_compression + * + * This routine configures all aspects of display compression, including pitch, + * size and the offset of the compression buffer. + *---------------------------------------------------------------------------*/ + +int vg_configure_compression (VG_COMPRESSION_DATA *comp_data) +{ + unsigned long delta, size; + unsigned long comp_size, unlock; + + /* CHECK FOR VALID PARAMETERS */ + /* The maximum size for the compression buffer is 544 bytes (with */ + /* the header) Also, the pitch cannot be less than the line size */ + /* and the compression buffer offset must be 16-byte aligned. */ + + if (comp_data->size > 544 || comp_data->pitch < comp_data->size || + comp_data->compression_offset & 0x0F) + { + return CIM_STATUS_INVALIDPARAMS; + } + + /* SUBTRACT 32 FROM SIZE */ + /* The display controller will actually write 4 extra QWords. So, */ + /* if we assume that "size" refers to the allocated size, we must */ + /* subtract 32 bytes. */ + + comp_size = comp_data->size - 32; + + /* CALCULATE REGISTER VALUES */ + + unlock = READ_REG32 (DC3_UNLOCK); + size = READ_REG32 (DC3_LINE_SIZE) & ~DC3_LINE_SIZE_CBLS_MASK; + delta = READ_REG32 (DC3_GFX_PITCH) & ~DC3_GFX_PITCH_CBP_MASK; + + size |= ((comp_size >> 3) + 1) << DC3_LINE_SIZE_CB_SHIFT; + delta |= ((comp_data->pitch >> 3) << 16); + + /* WRITE COMPRESSION PARAMETERS */ + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_CB_ST_OFFSET, comp_data->compression_offset); + WRITE_REG32 (DC3_LINE_SIZE, size); + WRITE_REG32 (DC3_GFX_PITCH, delta); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_test_timing_active + * + * This routine checks the status of the display timing generator. + *---------------------------------------------------------------------------*/ + +int vg_test_timing_active (void) +{ + if (READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_TGEN) + return 1; + + return 0; +} + +/*--------------------------------------------------------------------------- + * vg_test_vertical_active + * + * This routine checks if the display is currently in the middle of a frame + * (not in the VBlank interval) + *---------------------------------------------------------------------------*/ + +int vg_test_vertical_active (void) +{ + if (READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VNA) + return 0; + + return 1; +} + +/*--------------------------------------------------------------------------- + * vg_wait_vertical_blank + * + * This routine waits until the beginning of the vertical blank interval. + * When the display is already in vertical blank, this routine will wait until + * the beginning of the next vertical blank. + *---------------------------------------------------------------------------*/ + +int vg_wait_vertical_blank(void) +{ + if (vg_test_timing_active()) + { + while (!vg_test_vertical_active()); + while (vg_test_vertical_active()); + } + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_test_even_field + * + * This routine tests the odd/even status of the current VG output field. + *---------------------------------------------------------------------------*/ + +int vg_test_even_field(void) +{ + if (READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_EVEN_FIELD) + return 1; + + return 0; +} + +/*--------------------------------------------------------------------------- + * vg_configure_line_interrupt + * + * This routine configures the display controller's line count interrupt. This + * interrupt can be used to interrupt mid-frame or to interrupt at the beginning + * of vertical blank. + *---------------------------------------------------------------------------*/ + +int vg_configure_line_interrupt (VG_INTERRUPT_PARAMS *interrupt_info) +{ + unsigned long irq_line, irq_enable; + unsigned long lock; + + irq_line = READ_REG32 (DC3_IRQ_FILT_CTL); + irq_enable = READ_REG32 (DC3_IRQ); + lock = READ_REG32 (DC3_UNLOCK); + + irq_line = (irq_line & ~DC3_IRQFILT_LINE_MASK) | ((interrupt_info->line << 16) & DC3_IRQFILT_LINE_MASK); + + /* ENABLE OR DISABLE THE INTERRUPT */ + /* The line count is set before enabling and after disabling to */ + /* minimize spurious interrupts. The line count is set even */ + /* when interrupts are disabled to allow polling-based or debug */ + /* applications. */ + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + if (interrupt_info->enable) + { + WRITE_REG32 (DC3_IRQ_FILT_CTL, irq_line); + WRITE_REG32 (DC3_IRQ, ((irq_enable & ~DC3_IRQ_MASK) | DC3_IRQ_STATUS)); + } + else + { + WRITE_REG32 (DC3_IRQ, (irq_enable | DC3_IRQ_MASK)); + WRITE_REG32 (DC3_IRQ_FILT_CTL, irq_line); + } + WRITE_REG32 (DC3_UNLOCK, lock); + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_test_and_clear_interrupt + * + * This routine resets any pending interrupt in the video generator. The return + * value indicates the interrupt status prior to the reset. + *---------------------------------------------------------------------------*/ + +unsigned long vg_test_and_clear_interrupt (void) +{ + unsigned long irq_enable; + unsigned long lock; + + irq_enable = READ_REG32 (DC3_IRQ); + lock = READ_REG32 (DC3_UNLOCK); + + /* NO ACTION IF INTERRUPTS ARE MASKED */ + /* We are assuming that a driver or application will not want to receive */ + /* the status of the interrupt when it is masked. */ + + if ((irq_enable & (DC3_IRQ_MASK | DC3_VSYNC_IRQ_MASK)) == (DC3_IRQ_MASK | DC3_VSYNC_IRQ_MASK)) + return 0; + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_IRQ, irq_enable); + WRITE_REG32 (DC3_UNLOCK, lock); + + return (irq_enable & (DC3_IRQ_STATUS | DC3_VSYNC_IRQ_STATUS)); +} + +/*--------------------------------------------------------------------------- + * vg_test_flip_status + * + * This routine tests if a new display offset has been latched. + *---------------------------------------------------------------------------*/ + +unsigned long vg_test_flip_status (void) +{ + return (READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_FLIP); +} + +/*--------------------------------------------------------------------------- + * vg_save_state + * + * This routine saves all persistent VG state information. + *---------------------------------------------------------------------------*/ + +int vg_save_state (VG_SAVE_RESTORE *vg_state) +{ + Q_WORD msr_value; + unsigned long irqfilt; + unsigned long offset, i; + unsigned long lock; + + /* READ ALL CURRENT REGISTER SETTINGS */ + + vg_state->unlock = READ_REG32 (DC3_UNLOCK); + vg_state->gcfg = READ_REG32 (DC3_GENERAL_CFG); + vg_state->dcfg = READ_REG32 (DC3_DISPLAY_CFG); + vg_state->arb_cfg = READ_REG32 (DC3_ARB_CFG); + vg_state->fb_offset = READ_REG32 (DC3_FB_ST_OFFSET); + vg_state->cb_offset = READ_REG32 (DC3_CB_ST_OFFSET); + vg_state->cursor_offset = READ_REG32 (DC3_CURS_ST_OFFSET); + vg_state->video_y_offset = READ_REG32 (DC3_VID_Y_ST_OFFSET); + vg_state->video_u_offset = READ_REG32 (DC3_VID_U_ST_OFFSET); + vg_state->video_v_offset = READ_REG32 (DC3_VID_V_ST_OFFSET); + vg_state->dv_top = READ_REG32 (DC3_DV_TOP); + vg_state->line_size = READ_REG32 (DC3_LINE_SIZE); + vg_state->gfx_pitch = READ_REG32 (DC3_GFX_PITCH); + vg_state->video_yuv_pitch = READ_REG32 (DC3_VID_YUV_PITCH); + vg_state->h_active = READ_REG32 (DC3_H_ACTIVE_TIMING); + vg_state->h_blank = READ_REG32 (DC3_H_BLANK_TIMING); + vg_state->h_sync = READ_REG32 (DC3_H_SYNC_TIMING); + vg_state->v_active = READ_REG32 (DC3_V_ACTIVE_TIMING); + vg_state->v_blank = READ_REG32 (DC3_V_BLANK_TIMING); + vg_state->v_sync = READ_REG32 (DC3_V_SYNC_TIMING); + vg_state->fb_active = READ_REG32 (DC3_FB_ACTIVE); + vg_state->cursor_x = READ_REG32 (DC3_CURSOR_X); + vg_state->cursor_y = READ_REG32 (DC3_CURSOR_Y); + vg_state->vid_ds_delta = READ_REG32 (DC3_VID_DS_DELTA); + vg_state->fb_base = READ_REG32 (DC3_PHY_MEM_OFFSET); + vg_state->dv_ctl = READ_REG32 (DC3_DV_CTL); + vg_state->gfx_scale = READ_REG32 (DC3_GFX_SCALE); + vg_state->irq_ctl = READ_REG32 (DC3_IRQ_FILT_CTL); + vg_state->vbi_even_ctl = READ_REG32 (DC3_VBI_EVEN_CTL); + vg_state->vbi_odd_ctl = READ_REG32 (DC3_VBI_ODD_CTL); + vg_state->vbi_hor_ctl = READ_REG32 (DC3_VBI_HOR); + vg_state->vbi_odd_line_enable = READ_REG32 (DC3_VBI_LN_ODD); + vg_state->vbi_even_line_enable = READ_REG32 (DC3_VBI_LN_EVEN); + vg_state->vbi_pitch = READ_REG32 (DC3_VBI_PITCH); + vg_state->color_key = READ_REG32 (DC3_COLOR_KEY); + vg_state->color_key_mask = READ_REG32 (DC3_COLOR_MASK); + vg_state->color_key_x = READ_REG32 (DC3_CLR_KEY_X); + vg_state->color_key_y = READ_REG32 (DC3_CLR_KEY_Y); + vg_state->irq = READ_REG32 (DC3_IRQ); + vg_state->genlk_ctl = READ_REG32 (DC3_GENLK_CTL); + vg_state->vid_y_even_offset = READ_REG32 (DC3_VID_EVEN_Y_ST_OFFSET); + vg_state->vid_u_even_offset = READ_REG32 (DC3_VID_EVEN_U_ST_OFFSET); + vg_state->vid_v_even_offset = READ_REG32 (DC3_VID_EVEN_V_ST_OFFSET); + vg_state->vactive_even = READ_REG32 (DC3_V_ACTIVE_EVEN); + vg_state->vblank_even = READ_REG32 (DC3_V_BLANK_EVEN); + vg_state->vsync_even = READ_REG32 (DC3_V_SYNC_EVEN); + + /* READ THE CURRENT PALETTE */ + + lock = READ_REG32 (DC3_UNLOCK); + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_PAL_ADDRESS, 0); + for (i = 0; i < 261; i++) + vg_state->palette[i] = READ_REG32 (DC3_PAL_DATA); + + /* READ THE CURRENT FILTER COEFFICIENTS */ + + /* ENABLE ACCESS TO THE HORIZONTAL COEFFICIENTS */ + + irqfilt = READ_REG32 (DC3_IRQ_FILT_CTL); + irqfilt |= DC3_IRQFILT_H_FILT_SEL; + + /* READ HORIZONTAL COEFFICIENTS */ + + for (i = 0; i < 256; i++) + { + WRITE_REG32 (DC3_IRQ_FILT_CTL, ((irqfilt & 0xFFFFFF00L) | i)); + + vg_state->h_coeff[(i << 1)] = READ_REG32 (DC3_FILT_COEFF1); + vg_state->h_coeff[(i << 1) + 1] = READ_REG32 (DC3_FILT_COEFF2); + } + + /* ENABLE ACCESS TO THE VERTICAL COEFFICIENTS */ + + irqfilt &= ~DC3_IRQFILT_H_FILT_SEL; + + /* READ COEFFICIENTS */ + + for (i = 0; i < 256; i++) + { + WRITE_REG32 (DC3_IRQ_FILT_CTL, ((irqfilt & 0xFFFFFF00L) | i)); + + vg_state->v_coeff[i] = READ_REG32 (DC3_FILT_COEFF1); + } + + /* READ THE CURSOR DATA */ + + offset = READ_REG32 (DC3_CURS_ST_OFFSET) & 0x0FFFFFFF; + for (i = 0; i < 3072; i++) + vg_state->cursor_data[i] = READ_FB32 (offset + (i << 2)); + + /* READ THE CURRENT PLL */ + + msr_read64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DOTPLL, &msr_value); + + vg_state->pll_flags = 0; + for (i = 0; i < NUM_CIMARRON_PLL_FREQUENCIES; i++) + { + if (CimarronPLLFrequencies[i].pll_value == (msr_value.high & 0x7FFF)) + { + vg_state->dot_pll = CimarronPLLFrequencies[i].frequency; + break; + } + } + + if (i == NUM_CIMARRON_PLL_FREQUENCIES) + { + /* NO MATCH */ + /* Enter the frequency as a manual frequency. */ + + vg_state->dot_pll = msr_value.high; + vg_state->pll_flags |= VG_PLL_MANUAL; + } + if (msr_value.low & GLCP_DOTPLL_HALFPIX) + vg_state->pll_flags |= VG_PLL_DIVIDE_BY_2; + if (msr_value.low & GLCP_DOTPLL_BYPASS) + vg_state->pll_flags |= VG_PLL_BYPASS; + if (msr_value.high & GLCP_DOTPLL_DIV4) + vg_state->pll_flags |= VG_PLL_DIVIDE_BY_4; + if (msr_value.high & GLCP_DOTPLL_VIPCLK) + vg_state->pll_flags |= VG_PLL_VIP_CLOCK; + + /* READ ALL VG MSRS */ + + msr_read64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_CAP, &(vg_state->msr_cap)); + msr_read64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_CONFIG, &(vg_state->msr_config)); + msr_read64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_SMI, &(vg_state->msr_smi)); + msr_read64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_ERROR, &(vg_state->msr_error)); + msr_read64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_PM, &(vg_state->msr_pm)); + msr_read64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_DIAG, &(vg_state->msr_diag)); + msr_read64 (MSR_DEVICE_GEODELX_VG, DC3_SPARE_MSR, &(vg_state->msr_spare)); + msr_read64 (MSR_DEVICE_GEODELX_VG, DC3_RAM_CTL, &(vg_state->msr_ram_ctl)); + + WRITE_REG32 (DC3_UNLOCK, lock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_restore_state + * + * This routine restores all persistent VG state information. + *---------------------------------------------------------------------------*/ + +int vg_restore_state (VG_SAVE_RESTORE *vg_state) +{ + unsigned long irqfilt, i; + unsigned long memoffset; + + /* TEMPORARILY UNLOCK ALL REGISTERS */ + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + + /* RESTORE THE FRAME BUFFER OFFSET */ + + WRITE_REG32 (DC3_PHY_MEM_OFFSET, vg_state->fb_base); + + /* BLANK GCFG AND DCFG */ + + WRITE_REG32 (DC3_GENERAL_CFG, 0); + WRITE_REG32 (DC3_DISPLAY_CFG, 0); + + /* RESTORE ALL REGISTERS */ + + WRITE_REG32 (DC3_ARB_CFG, vg_state->arb_cfg); + WRITE_REG32 (DC3_FB_ST_OFFSET, vg_state->fb_offset); + WRITE_REG32 (DC3_CB_ST_OFFSET, vg_state->cb_offset); + WRITE_REG32 (DC3_CURS_ST_OFFSET, vg_state->cursor_offset); + WRITE_REG32 (DC3_VID_Y_ST_OFFSET, vg_state->video_y_offset); + WRITE_REG32 (DC3_VID_U_ST_OFFSET, vg_state->video_u_offset); + WRITE_REG32 (DC3_VID_V_ST_OFFSET, vg_state->video_v_offset); + WRITE_REG32 (DC3_DV_TOP, vg_state->dv_top); + WRITE_REG32 (DC3_LINE_SIZE, vg_state->line_size); + WRITE_REG32 (DC3_GFX_PITCH, vg_state->gfx_pitch); + WRITE_REG32 (DC3_VID_YUV_PITCH, vg_state->video_yuv_pitch); + WRITE_REG32 (DC3_H_ACTIVE_TIMING, vg_state->h_active); + WRITE_REG32 (DC3_H_BLANK_TIMING, vg_state->h_blank); + WRITE_REG32 (DC3_H_SYNC_TIMING, vg_state->h_sync); + WRITE_REG32 (DC3_V_ACTIVE_TIMING, vg_state->v_active); + WRITE_REG32 (DC3_V_BLANK_TIMING, vg_state->v_blank); + WRITE_REG32 (DC3_V_SYNC_TIMING, vg_state->v_sync); + WRITE_REG32 (DC3_FB_ACTIVE, vg_state->fb_active); + WRITE_REG32 (DC3_CURSOR_X, vg_state->cursor_x); + WRITE_REG32 (DC3_CURSOR_Y, vg_state->cursor_y); + WRITE_REG32 (DC3_VID_DS_DELTA, vg_state->vid_ds_delta); + WRITE_REG32 (DC3_PHY_MEM_OFFSET, vg_state->fb_base); + WRITE_REG32 (DC3_DV_CTL, vg_state->dv_ctl | 0x00000001); + WRITE_REG32 (DC3_GFX_SCALE, vg_state->gfx_scale); + WRITE_REG32 (DC3_IRQ_FILT_CTL, vg_state->irq_ctl); + WRITE_REG32 (DC3_VBI_EVEN_CTL, vg_state->vbi_even_ctl); + WRITE_REG32 (DC3_VBI_ODD_CTL, vg_state->vbi_odd_ctl); + WRITE_REG32 (DC3_VBI_HOR, vg_state->vbi_hor_ctl); + WRITE_REG32 (DC3_VBI_LN_ODD, vg_state->vbi_odd_line_enable); + WRITE_REG32 (DC3_VBI_LN_EVEN, vg_state->vbi_even_line_enable); + WRITE_REG32 (DC3_VBI_PITCH, vg_state->vbi_pitch); + WRITE_REG32 (DC3_COLOR_KEY, vg_state->color_key); + WRITE_REG32 (DC3_COLOR_MASK, vg_state->color_key_mask); + WRITE_REG32 (DC3_CLR_KEY_X, vg_state->color_key_x); + WRITE_REG32 (DC3_CLR_KEY_Y, vg_state->color_key_y); + WRITE_REG32 (DC3_IRQ, vg_state->irq); + WRITE_REG32 (DC3_GENLK_CTL, vg_state->genlk_ctl); + WRITE_REG32 (DC3_VID_EVEN_Y_ST_OFFSET, vg_state->vid_y_even_offset); + WRITE_REG32 (DC3_VID_EVEN_U_ST_OFFSET, vg_state->vid_u_even_offset); + WRITE_REG32 (DC3_VID_EVEN_V_ST_OFFSET, vg_state->vid_v_even_offset); + WRITE_REG32 (DC3_V_ACTIVE_EVEN, vg_state->vactive_even); + WRITE_REG32 (DC3_V_BLANK_EVEN, vg_state->vblank_even); + WRITE_REG32 (DC3_V_SYNC_EVEN, vg_state->vsync_even); + + /* RESTORE THE PALETTE */ + + WRITE_REG32 (DC3_PAL_ADDRESS, 0); + for (i = 0; i < 261; i++) + WRITE_REG32 (DC3_PAL_DATA, vg_state->palette[i]); + + /* RESTORE THE HORIZONTAL FILTER COEFFICIENTS */ + + irqfilt = READ_REG32 (DC3_IRQ_FILT_CTL); + irqfilt |= DC3_IRQFILT_H_FILT_SEL; + + for (i = 0; i < 256; i++) + { + WRITE_REG32 (DC3_IRQ_FILT_CTL, ((irqfilt & 0xFFFFFF00L) | i)); + WRITE_REG32 (DC3_FILT_COEFF1, vg_state->h_coeff[(i << 1)]); + WRITE_REG32 (DC3_FILT_COEFF2, vg_state->h_coeff[(i << 1) + 1]); + } + + /* RESTORE VERTICAL COEFFICIENTS */ + + irqfilt &= ~DC3_IRQFILT_H_FILT_SEL; + + for (i = 0; i < 256; i++) + { + WRITE_REG32 (DC3_IRQ_FILT_CTL, ((irqfilt & 0xFFFFFF00L) | i)); + WRITE_REG32 (DC3_FILT_COEFF1, vg_state->v_coeff[i]); + } + + /* RESTORE THE CURSOR DATA */ + + memoffset = READ_REG32 (DC3_CURS_ST_OFFSET) & 0x0FFFFFFF; + WRITE_FB_STRING32 (memoffset, (unsigned char *)&(vg_state->cursor_data[0]), 3072); + + /* RESTORE THE PLL */ + /* Use a common routine to use common code to poll for lock bit */ + + vg_set_clock_frequency (vg_state->dot_pll, vg_state->pll_flags); + + /* RESTORE ALL VG MSRS */ + + msr_write64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_CAP, &(vg_state->msr_cap)); + msr_write64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_CONFIG, &(vg_state->msr_config)); + msr_write64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_SMI, &(vg_state->msr_smi)); + msr_write64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_ERROR, &(vg_state->msr_error)); + msr_write64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_PM, &(vg_state->msr_pm)); + msr_write64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_DIAG, &(vg_state->msr_diag)); + msr_write64 (MSR_DEVICE_GEODELX_VG, DC3_SPARE_MSR, &(vg_state->msr_spare)); + msr_write64 (MSR_DEVICE_GEODELX_VG, DC3_RAM_CTL, &(vg_state->msr_ram_ctl)); + + /* NOW RESTORE GCFG AND DCFG */ + + WRITE_REG32 (DC3_DISPLAY_CFG, vg_state->dcfg); + WRITE_REG32 (DC3_GENERAL_CFG, vg_state->gcfg); + + /* FINALLY RESTORE UNLOCK */ + + WRITE_REG32 (DC3_UNLOCK, vg_state->unlock); + + return CIM_STATUS_OK; +} + +/*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * CIMARRON VG READ ROUTINES + * These routines are included for use in diagnostics or when debugging. They + * can be optionally excluded from a project. + *+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ + +#if CIMARRON_INCLUDE_VG_READ_ROUTINES + +/*--------------------------------------------------------------------------- + * vg_read_graphics_crc + * + * This routine reads the Cyclic Redundancy Check (CRC) value for the graphics + * frame. + *---------------------------------------------------------------------------*/ + +unsigned long vg_read_graphics_crc (int crc_source) +{ + unsigned long gcfg, unlock; + unsigned long crc, vbi_even; + unsigned long interlaced; + unsigned long line, field; + + if (!(READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_TGEN)) + return 0xFFFFFFFF; + + unlock = READ_REG32 (DC3_UNLOCK); + gcfg = READ_REG32 (DC3_GENERAL_CFG); + vbi_even = READ_REG32 (DC3_VBI_EVEN_CTL); + + vbi_even &= ~DC3_VBI_EVEN_ENABLE_CRC; + + gcfg |= DC3_GCFG_SGRE | DC3_GCFG_CRC_MODE; + gcfg &= ~(DC3_GCFG_SGFR | DC3_GCFG_SIG_SEL | DC3_GCFG_FILT_SIG_SEL); + + switch (crc_source) + { + case VG_CRC_SOURCE_PREFILTER_EVEN: + case VG_CRC_SOURCE_PREFILTER: gcfg |= DC3_GCFG_SIG_SEL; break; + case VG_CRC_SOURCE_PREFLICKER: + case VG_CRC_SOURCE_PREFLICKER_EVEN: gcfg |= DC3_GCFG_FILT_SIG_SEL; break; + case VG_CRC_SOURCE_POSTFLICKER: + case VG_CRC_SOURCE_POSTFLICKER_EVEN: /* NO WORK */ break; + + default: + return 0xFFFFFFFF; + } + + if (crc_source & VG_CRC_SOURCE_EVEN) field = 0; + else field = DC3_LNCNT_EVEN_FIELD; + + if ((interlaced = (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN))) + { + /* WAIT FOR THE BEGINNING OF THE FIELD (LINE 1-5) */ + /* Note that we wait for the field to be odd when CRCing the even */ + /* field and vice versa. This is because the CRC will not begin */ + /* until the following field. */ + + do + { + line = READ_REG32 (DC3_LINE_CNT_STATUS); + } while ((line & DC3_LNCNT_EVEN_FIELD) != field || + ((line & DC3_LNCNT_V_LINE_CNT) >> 16) < 10 || + ((line & DC3_LNCNT_V_LINE_CNT) >> 16) > 15); + } + else + { + /* NON-INTERLACED - EVEN FIELD CRCS ARE INVALID */ + + if (crc_source & VG_CRC_SOURCE_EVEN) + return 0xFFFFFFFF; + } + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_VBI_EVEN_CTL, vbi_even); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg & ~DC3_GCFG_SIGE); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg | DC3_GCFG_SIGE); + + /* WAIT FOR THE CRC TO BE COMPLETED */ + + while (!(READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_SIGC)) + ; + + /* READ THE COMPLETED CRC */ + + crc = READ_REG32 (DC3_PAL_DATA); + + /* RESTORE THE PALETTE SETTINGS */ + + gcfg &= ~DC3_GCFG_SGRE; + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return crc; +} + +/*--------------------------------------------------------------------------- + * vg_read_window_crc + * + * This routine reads the Cyclic Redundancy Check (CRC) value for a sub-section + * of the frame. + *---------------------------------------------------------------------------*/ + +unsigned long vg_read_window_crc (int crc_source, unsigned long x, unsigned long y, + unsigned long width, unsigned long height) +{ + Q_WORD msr_value; + unsigned long crc = 0; + unsigned long hactive, hblankstart; + unsigned long htotal, hblankend; + unsigned long line, field; + unsigned long diag; + + hactive = ((READ_REG32 (DC3_H_ACTIVE_TIMING)) & 0xFFF) + 1; + hblankstart = ((READ_REG32 (DC3_H_BLANK_TIMING)) & 0xFFF) + 1; + htotal = ((READ_REG32 (DC3_H_ACTIVE_TIMING) >> 16) & 0xFFF) + 1; + hblankend = ((READ_REG32 (DC3_H_BLANK_TIMING) >> 16) & 0xFFF) + 1; + + /* TIMINGS MUST BE ACTIVE */ + + if (!(READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_TGEN)) + return 0xFFFFFFFF; + + /* DISABLE GLCP ACTIONS */ + + msr_value.low = 0; + msr_value.high = 0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DIAGCTL, &msr_value); + + if ((x == 0 && width == 1) || x == 1) + { + /* SPECIAL CASE FOR X == 0 */ + /* The comparator output is a clock late in the MCP, so we cannot */ + /* easily catch the first pixel. If the first pixel is desired, */ + /* we will insert a special state machine to CRC just the first */ + /* pixel. */ + + /* N2 - DISPE HIGH AND Y == 1 */ + /* Goto state YState = 2 */ + + msr_value.high = 0x00000002; + msr_value.low = 0x00000C00; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL + 2, &msr_value); + + /* M3 - DISPE HIGH AND Y == 0 */ + /* Goto YState = 1 */ + + msr_value.high = 0x00000002; + msr_value.low = 0x00000A00; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETM0CTL + 3, &msr_value); + + /* N3 - DISPE LOW */ + /* Goto YState = 0 */ + + msr_value.high = 0x00080000; + msr_value.low = 0x00000000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL + 3, &msr_value); + + /* Y0 -> Y1 (SET M3) */ + + msr_value.high = 0x00000000; + msr_value.low = 0x0000C000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 18, &msr_value); + + /* Y1 -> Y0 (SET N3) */ + + msr_value.low = 0x0000A000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 17, &msr_value); + + /* Y1 -> Y2 (SET N2) */ + + msr_value.low = 0x00000A00; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 19, &msr_value); + + /* N5 (XSTATE = 10 && CMP2 <= V. COUNTER <= CMP3) && DISPE && Y == 0 */ + /* CRC into REGB */ + + msr_value.high = 0x00000002; + msr_value.low = 0x10800B20; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL + 5, &msr_value); + + /* N6 (XSTATE = 10 && CMP2 <= V. COUNTER <= CMP3) && DISPE && Y == 1 */ + /* CRC into REGB */ + + msr_value.high = 0x00000002; + msr_value.low = 0x10800D20; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL + 6, &msr_value); + } + + /* M4 (XSTATE = 00 AND VSYNC HIGH) */ + /* Goto state 01 */ + /* Note: VSync = H3A */ + + msr_value.high = 0x00000001; + msr_value.low = 0x000000A0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETM0CTL + 4, &msr_value); + + /* N0 (XSTATE = 01 AND VSYNC LOW) */ + /* Goto state 02 */ + /* Note: VSync low = H3B */ + + msr_value.high = 0x00040000; + msr_value.low = 0x000000C0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL, &msr_value); + + /* M5 (XSTATE = 10 AND VSYNC HIGH) */ + /* Goto state 11 */ + + msr_value.high = 0x00000001; + msr_value.low = 0x00000120; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETM0CTL + 5, &msr_value); + + /* N1 (XSTATE = 10 and DISPE HIGH) */ + /* Increment H. Counter */ + /* Note: DispE = H4 */ + + msr_value.high = 0x00000002; + msr_value.low = 0x00000120; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL + 1, &msr_value); + + /* M0 (XSTATE = 10 and H. COUNTER == LIMIT) */ + /* Clear H. Counter and increment V. Counter */ + + msr_value.high = 0x00000000; + msr_value.low = 0x00000122; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETM0CTL, &msr_value); + + /* N4 (XSTATE = 10 && CMP0 <= H. COUNTER <= CMP1 && CMP2 <= V. COUNTER <= CMP3) && DISPE */ + /* CRC into REGB */ + + msr_value.high = 0x00000002; + msr_value.low = 0x10C20120; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_SETN0CTL + 4, &msr_value); + + /* COMPARATOR 0 VALUE */ + /* We subtract 1 to account for a pipeline delay in the GLCP. */ + /* When the x coordinate is 0, we must play a special game. */ + /* If the width is exactly 1, we will set up a state machine */ + /* to only CRC the first pixel. Otherwise, we will set it */ + /* as an OR combination of a state that CRCs the first pixel */ + /* and a state that CRCs 1 clock delayed width (width - 1) */ + + msr_value.high = 0; + if (x > 1) msr_value.low = (x - 1) & 0xFFFF; + else msr_value.low = x; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPVAL0, &msr_value); + + /* COMPARATOR 1 VALUE */ + + if ((x == 0 || x == 1) && width > 1) msr_value.low += width - 2; + else msr_value.low += width - 1; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPVAL0 + 2, &msr_value); + + /* COMPARATOR 2 VALUE */ + + msr_value.low = y << 16; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPVAL0 + 4, &msr_value); + + /* COMPARATOR 3 VALUE */ + + msr_value.low += (height - 1) << 16; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPVAL0 + 6, &msr_value); + + /* COMPARATOR MASKS */ + /* Comparators 0 and 1 refer to lower 16 bits of RegB */ + + msr_value.low = 0x0000FFFF; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPMASK0, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPMASK0 + 2, &msr_value); + + /* Comparators 2 and 3 refer to upper 16 bits of RegB */ + + msr_value.low = 0xFFFF0000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPMASK0 + 4, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_CMPMASK0 + 6, &msr_value); + + /* SET REGB MASK */ + /* We set the mask such that all all 32 bits of data are CRCed */ + + msr_value.low = 0xFFFFFFFF; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_REGBMASK, &msr_value); + + /* ACTIONS */ + + /* STATE 00->01 (SET 4M) */ + + msr_value.low = 0x000C0000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 14, &msr_value); + + /* STATE 01->10 (SET 0N) */ + + msr_value.low = 0x0000000A; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 15, &msr_value); + + /* STATE 10->11 (SET 5M) */ + + msr_value.low = 0x00C00000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 16, &msr_value); + + /* CLEAR REGA WHEN TRANSITIONING TO STATE 10 */ + /* Do not clear RegB as the initial value must be 0x00000001 */ + + msr_value.low = 0x0000000A; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0, &msr_value); + + /* REGISTER ACTION 1 */ + /* CRC into RegB if cmp0 <= h.counter <= cmp1 && cmp2 <= v. counter < cmp3 && 7 xstate = 10 */ + /* Increment h.counter if xstate = 10 and HSync is low. */ + + msr_value.low = 0x000A00A0; + if (x == 0 && width == 1) + msr_value.low = 0x00A000A0; + else if (x == 1 && width == 1) + msr_value.low = 0x0A0000A0; + else if (x == 1 && width > 1) + msr_value.low |= 0x0A000000; + + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 1, &msr_value); + + /* REGISTER ACTION 2 */ + /* Increment V. Counter in REGA */ + + msr_value.low = 0x0000000C; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 2, &msr_value); + + /* SET REGB TO 0x00000001 */ + + msr_value.low = 0x00000001; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_REGB, &msr_value); + + /* SET XSTATE TO 0 */ + + msr_value.low = 0x00000000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_XSTATE, &msr_value); + + /* SET YSTATE TO 0 */ + + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_YSTATE, &msr_value); + + /* CLEAR ALL OTHER ACTIONS */ + /* This prevents side-effects from previous accesses to the GLCP */ + /* debug logic. */ + + msr_value.low = 0x00000000; + msr_value.high = 0x00000000; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 3, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 4, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 5, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 6, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 7, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 8, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 9, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 10, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 11, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 12, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 13, &msr_value); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_ACTION0 + 20, &msr_value); + + /* SET DIAG SETTINGS BASED ON DESIRED CRC */ + + if (crc_source == VG_CRC_SOURCE_POSTFLICKER || crc_source == VG_CRC_SOURCE_POSTFLICKER_EVEN) + { + diag = 0x80808086; + + /* ENABLE HW CLOCK GATING AND SET GLCP CLOCK TO DOT CLOCK */ + + msr_value.high = 0; + msr_value.low = 5; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, MSR_GEODELINK_PM, &msr_value); + msr_value.low = 0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DBGCLKCTL, &msr_value); + msr_value.low = 3; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DBGCLKCTL, &msr_value); + + /* SET REGA LIMITS */ + /* Lower counter uses pixels/line */ + /* Upper counter is 0xFFFF to prevent rollover. */ + + msr_value.low = 0xFFFF0000 | (hactive - 1); + if (READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_DCEN) + { + msr_value.low += hblankstart - hactive; + msr_value.low += htotal - hblankend; + } + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_REGAVAL, &msr_value); + + /* USE H4 FUNCTION A FOR DISPE AND H4 FUNCTION B FOR NOT DISPE */ + /* DISPE is bit 34 */ + + msr_value.high = 0x00000002; + msr_value.low = 0x20000FF0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_H0CTL + 4, &msr_value); + + /* USE H3 FUNCTION A FOR VSYNC AND H3 FUNCTION B FOR NOT VSYNC */ + /* VSYNC is bit 32. */ + + msr_value.high = 0x00000000; + msr_value.low = 0x002055AA; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_H0CTL + 3, &msr_value); + } + else if (crc_source == VG_CRC_SOURCE_PREFLICKER || crc_source == VG_CRC_SOURCE_PREFLICKER_EVEN) + { + diag = 0x801F8032; + + /* ENABLE HW CLOCK GATING AND SET GLCP CLOCK TO GEODELINK CLOCK */ + + msr_value.high = 0; + msr_value.low = 5; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, MSR_GEODELINK_PM, &msr_value); + msr_value.low = 0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DBGCLKCTL, &msr_value); + msr_value.low = 2; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DBGCLKCTL, &msr_value); + + /* SET REGA LIMITS */ + /* Lower counter uses pixels/line */ + /* Upper counter is 0xFFFF to prevent rollover. */ + + msr_value.low = 0xFFFF0000 | (hactive - 1); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_REGAVAL, &msr_value); + + /* USE H4 FUNCTION A FOR DISPE AND H4 FUNCTION B FOR NOT DISPE */ + /* DISPE is bit 47 */ + + msr_value.high = 0x00000002; + msr_value.low = 0xF0000FF0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_H0CTL + 4, &msr_value); + + /* USE H3 FUNCTION A FOR VSYNC AND H3 FUNCTION B FOR NOT VSYNC */ + /* VSYNC is bit 45. */ + + msr_value.high = 0x00000000; + msr_value.low = 0x002D55AA; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_H0CTL + 3, &msr_value); + } + else + { + /* PREFILTER CRC */ + + diag = 0x80138048; + msr_write64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_DIAG, &msr_value); + + /* ENABLE HW CLOCK GATING AND SET GLCP CLOCK TO GEODELINK CLOCK */ + + msr_value.high = 0; + msr_value.low = 5; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, MSR_GEODELINK_PM, &msr_value); + msr_value.low = 0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DBGCLKCTL, &msr_value); + msr_value.low = 2; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DBGCLKCTL, &msr_value); + + /* SET REGA LIMITS */ + /* Lower counter uses pixels/line */ + /* Upper counter is 0xFFFF to prevent rollover. */ + /* Note that we are assuming that the number of */ + /* source pixels is specified in the FB_ACTIVE register */ + + msr_value.low = 0xFFFF0000 | ((READ_REG32 (DC3_FB_ACTIVE) >> 16) & 0xFFF); + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_REGAVAL, &msr_value); + + /* USE H4 FUNCTION A FOR DISPE AND H4 FUNCTION B FOR NOT DISPE */ + /* DISPE is bit 55 */ + + msr_value.high = 0x00000003; + msr_value.low = 0x70000FF0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_H0CTL + 4, &msr_value); + + /* USE H3 FUNCTION A FOR VSYNC AND H3 FUNCTION B FOR NOT VSYNC */ + /* VSYNC is bit 53. */ + + msr_value.high = 0x00000000; + msr_value.low = 0x003555AA; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_H0CTL + 3, &msr_value); + } + + /* WAIT FOR THE CORRECT FIELD */ + /* We use the VG line count and field indicator to determine when */ + /* to kick off a CRC. */ + + if (crc_source & VG_CRC_SOURCE_EVEN) field = 0; + else field = DC3_LNCNT_EVEN_FIELD; + + if (READ_REG32 (DC3_IRQ_FILT_CTL) & DC3_IRQFILT_INTL_EN) + { + /* WAIT FOR THE BEGINNING OF THE FIELD (LINE 1-5) */ + /* Note that we wait for the field to be odd when CRCing the even */ + /* field and vice versa. This is because the CRC will not begin */ + /* until the following field. */ + + do + { + line = READ_REG32 (DC3_LINE_CNT_STATUS); + } while ((line & DC3_LNCNT_EVEN_FIELD) != field || + ((line & DC3_LNCNT_V_LINE_CNT) >> 16) < 1 || + ((line & DC3_LNCNT_V_LINE_CNT) >> 16) > 5); + } + else + { + /* NON-INTERLACED - EVEN FIELD CRCS ARE INVALID */ + + if (crc_source & VG_CRC_SOURCE_EVEN) + return 0xFFFFFFFF; + } + + /* UPDATE VG DIAG OUTPUT */ + + msr_value.high = 0; + msr_value.low = diag; + msr_write64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_DIAG, &msr_value); + + /* CONFIGURE DIAG CONTROL */ + /* Set RegA action1 to increment lower 16 bits and clear at limit. (5) */ + /* Set RegA action2 to increment upper 16 bits. (6) */ + /* Set RegB action1 to CRC32 (1) */ + /* Set all comparators to REGA override (0,1 lower mbus, 2,3 upper mbus) */ + /* Enable all actions */ + + msr_value.low = 0x80EA20A0; + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DIAGCTL, &msr_value); + + /* DELAY TWO FRAMES */ + + while (READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VNA); + while (!(READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VNA)); + while (READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VNA); + while (!(READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VNA)); + while (READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VNA); + + /* VERIFY THAT XSTATE = 11 */ + + msr_read64 (MSR_DEVICE_GEODELX_GLCP, GLCP_XSTATE, &msr_value); + if ((msr_value.low & 3) == 3) + { + msr_read64 (MSR_DEVICE_GEODELX_GLCP, GLCP_REGB, &msr_value); + + crc = msr_value.low; + } + + /* DISABLE VG DIAG BUS OUTPUTS */ + + msr_value.low = 0x00000000; + msr_value.high = 0x00000000; + msr_write64 (MSR_DEVICE_GEODELX_VG, MSR_GEODELINK_DIAG, &msr_value); + + /* DISABLE GLCP ACTIONS */ + + msr_write64 (MSR_DEVICE_GEODELX_GLCP, GLCP_DIAGCTL, &msr_value); + + return crc; +} + +/*--------------------------------------------------------------------------- + * vg_get_scaler_filter_coefficients + * + * This routine gets the vertical and horizontal filter coefficients for + * graphics scaling. The coefficients are sign extended to 32-bit values. + *---------------------------------------------------------------------------*/ + +int vg_get_scaler_filter_coefficients (long h_taps[][5], long v_taps[][3]) +{ + unsigned long irqfilt, i; + unsigned long temp; + long coeff0, coeff1, coeff2; + unsigned long lock; + + /* ENABLE ACCESS TO THE HORIZONTAL COEFFICIENTS */ + + lock = READ_REG32 (DC3_UNLOCK); + irqfilt = READ_REG32 (DC3_IRQ_FILT_CTL); + irqfilt |= DC3_IRQFILT_H_FILT_SEL; + + /* WRITE COEFFICIENTS */ + /* Coefficient indexes do not auto-increment, so we must */ + /* write the address for every phase */ + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + + for (i = 0; i < 256; i++) + { + WRITE_REG32 (DC3_IRQ_FILT_CTL, ((irqfilt & 0xFFFFFF00L) | i)); + + temp = READ_REG32 (DC3_FILT_COEFF1); + coeff0 = (temp & 0x3FF); + coeff1 = (temp >> 10) & 0x3FF; + coeff2 = (temp >> 20) & 0x3FF; + + h_taps[i][0] = (coeff0 << 22) >> 22; + h_taps[i][1] = (coeff1 << 22) >> 22; + h_taps[i][2] = (coeff2 << 22) >> 22; + + temp = READ_REG32 (DC3_FILT_COEFF2); + coeff0 = (temp & 0x3FF); + coeff1 = (temp >> 10) & 0x3FF; + + h_taps[i][3] = (coeff0 << 22) >> 22; + h_taps[i][4] = (coeff1 << 22) >> 22; + } + + /* ENABLE ACCESS TO THE VERTICAL COEFFICIENTS */ + + irqfilt &= ~DC3_IRQFILT_H_FILT_SEL; + + /* WRITE COEFFICIENTS */ + + for (i = 0; i < 256; i++) + { + WRITE_REG32 (DC3_IRQ_FILT_CTL, ((irqfilt & 0xFFFFFF00L) | i)); + + temp = READ_REG32 (DC3_FILT_COEFF1); + coeff0 = (temp & 0x3FF); + coeff1 = (temp >> 10) & 0x3FF; + coeff2 = (temp >> 20) & 0x3FF; + + v_taps[i][0] = (coeff0 << 22) >> 22; + v_taps[i][1] = (coeff1 << 22) >> 22; + v_taps[i][2] = (coeff2 << 22) >> 22; + } + + WRITE_REG32 (DC3_UNLOCK, lock); + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_get_flicker_filter_configuration + * + * This routine returns the current VG flicker filter configuration. + *---------------------------------------------------------------------------*/ + +int vg_get_flicker_filter_configuration (unsigned long *strength, int *flicker_alpha) +{ + unsigned long genlk_ctl; + + if (!strength || !flicker_alpha) + return CIM_STATUS_INVALIDPARAMS; + + genlk_ctl = READ_REG32 (DC3_GENLK_CTL); + *strength = genlk_ctl & DC3_GC_FLICKER_FILTER_MASK; + if (genlk_ctl & DC3_GC_ALPHA_FLICK_ENABLE) + *flicker_alpha = 1; + else + *flicker_alpha = 0; + + return CIM_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * vg_get_display_pitch + * + * This routine returns the current stride between successive lines of frame + * buffer data. + *---------------------------------------------------------------------------*/ + +unsigned long vg_get_display_pitch (void) +{ + return ((READ_REG32 (DC3_GFX_PITCH) & 0x0000FFFF) << 3); +} + +/*--------------------------------------------------------------------------- + * vg_get_frame_buffer_line_size + * + * This routine returns the current size in bytes of one line of frame buffer + * data. + *---------------------------------------------------------------------------*/ + +unsigned long vg_get_frame_buffer_line_size (void) +{ + return ((READ_REG32 (DC3_LINE_SIZE) & 0x3FF) << 3); +} + +/*--------------------------------------------------------------------------- + * vg_get_current_vline + * + * This routine returns the number of the current line that is being displayed + * by the display controller. + *---------------------------------------------------------------------------*/ + +unsigned long vg_get_current_vline (void) +{ + unsigned long current_line; + + /* READ THE REGISTER TWICE TO ENSURE THAT THE VALUE IS NOT TRANSITIONING */ + + do + { + current_line = READ_REG32(DC3_LINE_CNT_STATUS) & DC3_LNCNT_V_LINE_CNT; + } + while (current_line != (READ_REG32(DC3_LINE_CNT_STATUS) & DC3_LNCNT_V_LINE_CNT)); + + return (current_line >> 16); +} + +/*--------------------------------------------------------------------------- + * vg_get_display_offset + * + * This routine returns the offset into the frame buffer for the first pixel + * of the display. + *---------------------------------------------------------------------------*/ + +unsigned long vg_get_display_offset (void) +{ + return (READ_REG32(DC3_FB_ST_OFFSET) & 0x0FFFFFFF); +} + +/*--------------------------------------------------------------------------- + * vg_get_cursor_info + * + * This routine returns the current settings for the hardware cursor. + *---------------------------------------------------------------------------*/ + +int vg_get_cursor_info (VG_CURSOR_DATA *cursor_data) +{ + unsigned long temp; + + /* CURSOR OFFSET */ + + cursor_data->cursor_offset = READ_REG32 (DC3_CURS_ST_OFFSET) & 0x0FFFFFFF; + + /* CURSOR X POSITION */ + + temp = READ_REG32 (DC3_CURSOR_X); + cursor_data->cursor_x = temp & 0x7FF; + cursor_data->clipx = (temp >> 11) & 0x3F; + + /* CURSOR Y POSITION */ + + temp = READ_REG32 (DC3_CURSOR_Y); + cursor_data->cursor_y = temp & 0x7FF; + cursor_data->clipy = (temp >> 11) & 0x3F; + + /* CURSOR COLORS */ + + WRITE_REG32 (DC3_PAL_ADDRESS, 0x100); + cursor_data->mono_color0 = READ_REG32 (DC3_PAL_DATA); + cursor_data->mono_color1 = READ_REG32 (DC3_PAL_DATA); + + /* CURSOR ENABLES */ + + temp = READ_REG32 (DC3_GENERAL_CFG); + if (temp & DC3_GCFG_CURE) cursor_data->enable = 1; + else cursor_data->enable = 0; + if (temp & DC3_GCFG_CLR_CUR) cursor_data->color_cursor = 1; + else cursor_data->color_cursor = 0; + + return CIM_STATUS_OK; +} + +/*----------------------------------------------------------------------------- + * vg_get_display_palette_entry + * + * This routine reads a single entry in the 8BPP display palette. + *----------------------------------------------------------------------------*/ + +int vg_get_display_palette_entry (unsigned long index, unsigned long *entry) +{ + if (index > 0xFF) + return CIM_STATUS_INVALIDPARAMS; + + WRITE_REG32 (DC3_PAL_ADDRESS, index); + *entry = READ_REG32 (DC3_PAL_DATA); + + return CIM_STATUS_OK; +} + +/*----------------------------------------------------------------------------- + * vg_get_border_color + * + * This routine reads the current border color for centered displays. + *----------------------------------------------------------------------------*/ + +unsigned long vg_get_border_color (void) +{ + WRITE_REG32 (DC3_PAL_ADDRESS, 0x104); + return READ_REG32 (DC3_PAL_DATA); +} + +/*----------------------------------------------------------------------------- + * vg_get_display_palette + * + * This routines reads the entire contents of the display palette into a buffer. + * The display palette consists of 256 X:R:G:B values. + *----------------------------------------------------------------------------*/ + +int vg_get_display_palette (unsigned long *palette) +{ + unsigned long i; + + if (palette) + { + WRITE_REG32 (DC3_PAL_ADDRESS, 0); + for (i = 0; i < 256; i++) + { + palette[i] = READ_REG32 (DC3_PAL_DATA); + } + return CIM_STATUS_OK; + } + return CIM_STATUS_INVALIDPARAMS; +} + +/*----------------------------------------------------------------------------- + * vg_get_compression_info + * + * This routines reads the current status of the display compression hardware. + *----------------------------------------------------------------------------*/ + +int vg_get_compression_info (VG_COMPRESSION_DATA *comp_data) +{ + comp_data->compression_offset = READ_REG32 (DC3_CB_ST_OFFSET) & 0x0FFFFFFF; + comp_data->pitch = (READ_REG32 (DC3_GFX_PITCH) >> 13) & 0x7FFF8; + comp_data->size = ((READ_REG32 (DC3_LINE_SIZE) >> (DC3_LINE_SIZE_CB_SHIFT - 3)) & 0x3F8) + 24; + + return CIM_STATUS_OK; +} + +/*----------------------------------------------------------------------------- + * vg_get_compression_enable + * + * This routines reads the current enable status of the display compression hardware. + *----------------------------------------------------------------------------*/ + +int vg_get_compression_enable (void) +{ + if (READ_REG32 (DC3_GENERAL_CFG) & DC3_GCFG_CMPE) + return 1; + + return 0; +} + +/*----------------------------------------------------------------------------- + * vg_get_valid_bit + *----------------------------------------------------------------------------*/ + +int vg_get_valid_bit (int line) +{ + unsigned long offset; + unsigned long valid; + unsigned long lock; + + lock = READ_REG32 (DC3_UNLOCK); + offset = READ_REG32 (DC3_PHY_MEM_OFFSET) & 0xFF000000; + offset |= line; + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_PHY_MEM_OFFSET, offset); + WRITE_REG32 (DC3_UNLOCK, lock); + valid = READ_REG32 (DC3_DV_ACC) & 2; + + if (valid) return 1; + return 0; +} + +#endif --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cimarron.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cimarron.c 2005-12-14 11:37:43.000000000 -0700 @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Base include file for the Cimarron library. This file should be modified + * and included in any Cimarron-based project. + * */ + +/*----------------------------------------------------------------------*/ +/* MODULE SETTINGS */ +/* The following #defines affect which modules are included in the */ +/* project. */ +/*----------------------------------------------------------------------*/ + +#define CIMARRON_INCLUDE_GP 1 +#define CIMARRON_INCLUDE_VG 1 +#define CIMARRON_INCLUDE_VIP 1 +#define CIMARRON_INCLUDE_VOP 1 +#define CIMARRON_INCLUDE_VIDEO 1 +#define CIMARRON_INCLUDE_INIT 1 + +#define CIMARRON_INCLUDE_VG_READ_ROUTINES 1 +#define CIMARRON_INCLUDE_DF_READ_ROUTINES 1 +#define CIMARRON_INCLUDE_VIP_READ_ROUTINES 1 +#define CIMARRON_INCLUDE_VOP_READ_ROUTINES 1 + +/*----------------------------------------------------------------------*/ +/* HARDWARE ACCESS SETTINGS */ +/* The following #defines affect how the Cimarron macros access the */ +/* hardware. The hardware access macros are broken up into groups. */ +/* Each group includes an enabling #define as well as several #define */ +/* options that modify the macro configuration that is included. */ +/* If the enabling define is deleted or all options are set to 0, the */ +/* corresponding macros must be implemented by the user. The */ +/* combinations are explained as follows: */ +/* must be manually defined by the user. This allows a user to use the */ +/* cim_defs.h file for only those macros that suit the needs of his/her */ +/* project. For example, a user may need custom implementations of the */ +/* I/O and MSR macros, but may still want to use the default macros to */ +/* read and write hardware registers. The combinations are explained as */ +/* follows: */ +/* */ +/* Register Group: */ +/* Disabling define: */ +/* CIMARRON_EXCLUDE_REGISTER_ACCESS_MACROS */ +/* Define this setting to exclude the register access macros. */ +/* This setting is the inverse of the other group settings in */ +/* that these macros are included by default. This allows the */ +/* cim_defs.h file to be included outside of cimarron.c for */ +/* basic operations. */ +/* */ +/* Memory Group: */ +/* Enabling define: */ +/* CIMARRON_INCLUDE_STRING_MACROS */ +/* Options: */ +/* CIMARRON_OPTIMIZE_ASSEMBLY */ +/* Set to 1 to allow the use of inline assembly when writing */ +/* large chunks of data to memory. Essentially, this allows */ +/* a rep movsd in place of a slower C for-loop. */ +/* CIMARRON_OPTIMIZE_FORLOOP */ +/* Define for C only data writes. */ +/* */ +/* MSR Group: */ +/* Enabling define: */ +/* CIMARRON_INCLUDE_MSR_MACROS */ +/* Options: */ +/* CIMARRON_MSR_DIRECT_ASM */ +/* Set to 1 to allow the use of the rdmsr and wrmsr opcodes in */ +/* inline assembly. */ +/* CIMARRON_MSR_VSA_IO */ +/* Set to 1 to access MSRs using a VSAII virtual register. */ +/* CIMARRON_MSR_KERNEL_ROUTINE */ +/* Set to 1 to access MSRs using a wrapper routine in the */ +/* Linux kernel. */ +/* */ +/* IO Group: */ +/* Enabling define: */ +/* CIMARRON_INCLUDE_IO_MACROS */ +/* Options: */ +/* CIMARRON_IO_DIRECT_ACCESS */ +/* Set to 1 to perform IO accesses using inline assembly. */ +/* CIMARRON_IO_ABSTRACTED_ASM */ +/* Set to 1 to perform IO using abstracted IO in Linux. */ +/* */ +/* Custom Group: */ +/* Disabling define: */ +/* CIMARRON_EXCLUDE_CUSTOM_MACROS */ +/* By default, the custom macros (the macros used by */ +/* gp_custom_convert_blt) are mapped to the normal command */ +/* string macros. Setting this to 1 allows the user to */ +/* create a custom implementation. */ +/*----------------------------------------------------------------------*/ + +/* UNCOMMENT THE FOLLOWING LINE TO EXCLUDE BASIC REGISTER ACCESS MACROS */ + +/* #define CIMARRON_EXCLUDE_REGISTER_ACCESS_MACROS */ + +#define CIMARRON_INCLUDE_STRING_MACROS +#define CIMARRON_OPTIMIZE_ASSEMBLY 1 +#define CIMARRON_OPTIMIZE_FORLOOP 0 +#define CIMARRON_OPTIMIZE_ABSTRACTED_ASM 0 + +#define CIMARRON_INCLUDE_MSR_MACROS +#define CIMARRON_MSR_DIRECT_ASM 0 +#define CIMARRON_MSR_VSA_IO 1 +#define CIMARRON_MSR_ABSTRACTED_ASM 0 +#define CIMARRON_MSR_KERNEL_ROUTINE 0 + +#define CIMARRON_INCLUDE_IO_MACROS +#define CIMARRON_IO_DIRECT_ACCESS 1 +#define CIMARRON_IO_ABSTRACTED_ASM 0 + +/* UNCOMMENT THE FOLLOWING LINE TO IMPLEMENT CUSTOM MACROS FOR GP_CUSTOM_CONVERT_BLT */ + +/* #define CIMARRON_EXCLUDE_CUSTOM_MACROS */ + +/*----------------------------------------------------------------------*/ +/* MODULE VARIABLES */ +/* The following #defines affect how global variables in each Cimarron */ +/* module are defined. These variables can be made static (to prevent */ +/* naming conflicts) or they can be defined without the static keyword */ +/* (to allow extern references). */ +/*----------------------------------------------------------------------*/ + +#if 1 +#define CIMARRON_STATIC static +#else +#define CIMARRON_STATIC +#endif + +/*----------------------------------------------------------------------*/ +/* CIMARRON GLOBAL VARIABLES */ +/* These globals are used by the hardware access macros. They must be */ +/* initialized by the application to point to the memory-mapped */ +/* registers of their respective blocks. */ +/*----------------------------------------------------------------------*/ + +unsigned char *cim_gp_ptr = (unsigned char *)0; +unsigned char *cim_fb_ptr = (unsigned char *)0; +unsigned char *cim_cmd_base_ptr = (unsigned char *)0; +unsigned char *cim_cmd_ptr = (unsigned char *)0; +unsigned char *cim_vid_ptr = (unsigned char *)0; +unsigned char *cim_vip_ptr = (unsigned char *)0; +unsigned char *cim_vg_ptr = (unsigned char *)0; + +/*----------------------------------------------------------------------*/ +/* INCLUDE RELEVANT CIMARRON HEADERS */ +/*----------------------------------------------------------------------*/ + +/* HARDWARE REGISTER DEFINITIONS */ + +#include "cim_regs.h" + +/* ROUTINE DEFINITIONS */ +/* All routines have a prototype, even those that are not included */ +/* via #ifdefs. This prevents the user from having to include the */ +/* correct #defines anywhere he/she wants to call a Cimarron routine. */ + +#include "cim_rtns.h" + +/* HARDWARE ACCESS MACROS */ + +#include "cim_defs.h" + +/*----------------------------------------------------------------------*/ +/* CIMARRON MODULES */ +/* Modules and sub-modules are included based on user settings. Note */ +/* that excluding one or more modules may result in functionality */ +/* holes. */ +/*----------------------------------------------------------------------*/ + +/* GRAPHICS PROCESSOR */ + +#if CIMARRON_INCLUDE_GP +#include "cim_gp.c" +#endif + +/* VIDEO GENERATOR */ + +#if CIMARRON_INCLUDE_VG +#include "cim_modes.c" +#include "cim_vg.c" +#endif + +/* DISPLAY FILTER */ + +#if CIMARRON_INCLUDE_VIDEO +#include "cim_filter.c" +#include "cim_df.c" +#endif + +/* INITIALIZATION AND DETECTION */ + +#if CIMARRON_INCLUDE_INIT +#include "cim_init.c" +#endif + +/* VIP SUPPORT */ + +#if CIMARRON_INCLUDE_VIP +#include "cim_vip.c" +#endif + +/* VOP SUPPORT */ + +#if CIMARRON_INCLUDE_VOP +#include "cim_vop.c" +#endif + +/* MSR ACCESS */ +/* This module is used to access machine-specific registers. */ +/* It cannot be excluded from a project. */ + +#include "cim_msr.c" + --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_filter.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_filter.c 2005-12-14 11:39:24.000000000 -0700 @@ -0,0 +1,550 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron default video coefficients. + * */ + +long CimarronVideoFilter256[][2] = +{ + { 0x10000000, 0x00000000 }, /* 0, 4096, 0, 0 */ + { 0x10008008, 0x00000008 }, /* -8, 4096, 8, 0 */ + { 0x10008010, 0x80010011 }, /* -16, 4096, 17, -1 */ + { 0x10008019, 0x8001001A }, /* -25, 4096, 26, -1 */ + { 0x10008021, 0x80020023 }, /* -33, 4096, 35, -2 */ + { 0x0FFF8029, 0x8003002D }, /* -41, 4095, 45, -3 */ + { 0x0FFE8031, 0x80030036 }, /* -49, 4094, 54, -3 */ + { 0x0FFC8038, 0x80040040 }, /* -56, 4092, 64, -4 */ + { 0x0FFB8040, 0x8005004A }, /* -64, 4091, 74, -5 */ + { 0x0FF88047, 0x80050054 }, /* -71, 4088, 84, -5 */ + { 0x0FF6804E, 0x8006005E }, /* -78, 4086, 94, -6 */ + { 0x0FF48055, 0x80070068 }, /* -85, 4084, 104, -7 */ + { 0x0FF0805C, 0x80070073 }, /* -92, 4080, 115, -7 */ + { 0x0FEE8063, 0x8008007D }, /* -99, 4078, 125, -8 */ + { 0x0FEA8069, 0x80090088 }, /* -105, 4074, 136, -9 */ + { 0x0FE78070, 0x800A0093 }, /* -112, 4071, 147, -10 */ + { 0x0FE28076, 0x800A009E }, /* -118, 4066, 158, -10 */ + { 0x0FDD807C, 0x800B00AA }, /* -124, 4061, 170, -11 */ + { 0x0FD98082, 0x800C00B5 }, /* -130, 4057, 181, -12 */ + { 0x0FD48088, 0x800D00C1 }, /* -136, 4052, 193, -13 */ + { 0x0FCE808E, 0x800D00CD }, /* -142, 4046, 205, -13 */ + { 0x0FC88093, 0x800E00D9 }, /* -147, 4040, 217, -14 */ + { 0x0FC38099, 0x800F00E5 }, /* -153, 4035, 229, -15 */ + { 0x0FBD809E, 0x801000F1 }, /* -158, 4029, 241, -16 */ + { 0x0FB680A3, 0x801000FD }, /* -163, 4022, 253, -16 */ + { 0x0FAF80A8, 0x8011010A }, /* -168, 4015, 266, -17 */ + { 0x0FA880AD, 0x80120117 }, /* -173, 4008, 279, -18 */ + { 0x0FA180B2, 0x80130124 }, /* -178, 4001, 292, -19 */ + { 0x0F9980B6, 0x80140131 }, /* -182, 3993, 305, -20 */ + { 0x0F9280BB, 0x8015013E }, /* -187, 3986, 318, -21 */ + { 0x0F8880BF, 0x8015014C }, /* -191, 3976, 332, -21 */ + { 0x0F8080C3, 0x80160159 }, /* -195, 3968, 345, -22 */ + { 0x0F7880C8, 0x80170167 }, /* -200, 3960, 359, -23 */ + { 0x0F6E80CB, 0x80180175 }, /* -203, 3950, 373, -24 */ + { 0x0F6580CF, 0x80190183 }, /* -207, 3941, 387, -25 */ + { 0x0F5C80D3, 0x801A0191 }, /* -211, 3932, 401, -26 */ + { 0x0F5280D7, 0x801B01A0 }, /* -215, 3922, 416, -27 */ + { 0x0F4880DA, 0x801C01AE }, /* -218, 3912, 430, -28 */ + { 0x0F3D80DD, 0x801D01BD }, /* -221, 3901, 445, -29 */ + { 0x0F3280E0, 0x801E01CC }, /* -224, 3890, 460, -30 */ + { 0x0F2880E4, 0x801F01DB }, /* -228, 3880, 475, -31 */ + { 0x0F1C80E6, 0x802001EA }, /* -230, 3868, 490, -32 */ + { 0x0F1180E9, 0x802101F9 }, /* -233, 3857, 505, -33 */ + { 0x0F0480EB, 0x80210208 }, /* -235, 3844, 520, -33 */ + { 0x0EFA80EF, 0x80230218 }, /* -239, 3834, 536, -35 */ + { 0x0EEC80F0, 0x80230227 }, /* -240, 3820, 551, -35 */ + { 0x0EE080F3, 0x80240237 }, /* -243, 3808, 567, -36 */ + { 0x0ED380F5, 0x80250247 }, /* -245, 3795, 583, -37 */ + { 0x0EC780F7, 0x80270257 }, /* -247, 3783, 599, -39 */ + { 0x0EB980F9, 0x80280268 }, /* -249, 3769, 616, -40 */ + { 0x0EAC80FB, 0x80290278 }, /* -251, 3756, 632, -41 */ + { 0x0E9E80FD, 0x802A0289 }, /* -253, 3742, 649, -42 */ + { 0x0E9080FE, 0x802B0299 }, /* -254, 3728, 665, -43 */ + { 0x0E838100, 0x802D02AA }, /* -256, 3715, 682, -45 */ + { 0x0E758102, 0x802E02BB }, /* -258, 3701, 699, -46 */ + { 0x0E668103, 0x802F02CC }, /* -259, 3686, 716, -47 */ + { 0x0E568104, 0x803002DE }, /* -260, 3670, 734, -48 */ + { 0x0E498106, 0x803202EF }, /* -262, 3657, 751, -50 */ + { 0x0E398107, 0x80330301 }, /* -263, 3641, 769, -51 */ + { 0x0E298108, 0x80340313 }, /* -264, 3625, 787, -52 */ + { 0x0E1A8109, 0x80360325 }, /* -265, 3610, 805, -54 */ + { 0x0E0B810A, 0x80370336 }, /* -266, 3595, 822, -55 */ + { 0x0DFA810A, 0x80380348 }, /* -266, 3578, 840, -56 */ + { 0x0DEA810B, 0x803A035B }, /* -267, 3562, 859, -58 */ + { 0x0DDA810C, 0x803B036D }, /* -268, 3546, 877, -59 */ + { 0x0DCA810C, 0x803D037F }, /* -268, 3530, 895, -61 */ + { 0x0DB7810B, 0x803E0392 }, /* -267, 3511, 914, -62 */ + { 0x0DA7810C, 0x804003A5 }, /* -268, 3495, 933, -64 */ + { 0x0D95810C, 0x804103B8 }, /* -268, 3477, 952, -65 */ + { 0x0D85810C, 0x804303CA }, /* -268, 3461, 970, -67 */ + { 0x0D73810C, 0x804403DD }, /* -268, 3443, 989, -68 */ + { 0x0D61810C, 0x804603F1 }, /* -268, 3425, 1009, -70 */ + { 0x0D50810C, 0x80480404 }, /* -268, 3408, 1028, -72 */ + { 0x0D3E810C, 0x80490417 }, /* -268, 3390, 1047, -73 */ + { 0x0D2C810C, 0x804B042B }, /* -268, 3372, 1067, -75 */ + { 0x0D1B810C, 0x804D043E }, /* -268, 3355, 1086, -77 */ + { 0x0D07810B, 0x804E0452 }, /* -267, 3335, 1106, -78 */ + { 0x0CF5810B, 0x80500466 }, /* -267, 3317, 1126, -80 */ + { 0x0CE2810A, 0x8052047A }, /* -266, 3298, 1146, -82 */ + { 0x0CCF810A, 0x8053048E }, /* -266, 3279, 1166, -83 */ + { 0x0CBC8109, 0x805504A2 }, /* -265, 3260, 1186, -85 */ + { 0x0CA98108, 0x805704B6 }, /* -264, 3241, 1206, -87 */ + { 0x0C968108, 0x805904CB }, /* -264, 3222, 1227, -89 */ + { 0x0C838107, 0x805B04DF }, /* -263, 3203, 1247, -91 */ + { 0x0C6F8106, 0x805C04F3 }, /* -262, 3183, 1267, -92 */ + { 0x0C5B8105, 0x805E0508 }, /* -261, 3163, 1288, -94 */ + { 0x0C478104, 0x8060051D }, /* -260, 3143, 1309, -96 */ + { 0x0C348103, 0x80620531 }, /* -259, 3124, 1329, -98 */ + { 0x0C1F8102, 0x80640547 }, /* -258, 3103, 1351, -100 */ + { 0x0C0C8101, 0x8066055B }, /* -257, 3084, 1371, -102 */ + { 0x0BF88100, 0x80680570 }, /* -256, 3064, 1392, -104 */ + { 0x0BE380FE, 0x806A0585 }, /* -254, 3043, 1413, -106 */ + { 0x0BCF80FD, 0x806C059A }, /* -253, 3023, 1434, -108 */ + { 0x0BBA80FC, 0x806E05B0 }, /* -252, 3002, 1456, -110 */ + { 0x0BA480F9, 0x807005C5 }, /* -249, 2980, 1477, -112 */ + { 0x0B8F80F8, 0x807205DB }, /* -248, 2959, 1499, -114 */ + { 0x0B7A80F6, 0x807405F0 }, /* -246, 2938, 1520, -116 */ + { 0x0B6580F5, 0x80760606 }, /* -245, 2917, 1542, -118 */ + { 0x0B4F80F3, 0x8077061B }, /* -243, 2895, 1563, -119 */ + { 0x0B3A80F2, 0x80790631 }, /* -242, 2874, 1585, -121 */ + { 0x0B2480F0, 0x807B0647 }, /* -240, 2852, 1607, -123 */ + { 0x0B0F80EE, 0x807D065C }, /* -238, 2831, 1628, -125 */ + { 0x0AF980ED, 0x807F0673 }, /* -237, 2809, 1651, -127 */ + { 0x0AE480EB, 0x80810688 }, /* -235, 2788, 1672, -129 */ + { 0x0ACE80E9, 0x8084069F }, /* -233, 2766, 1695, -132 */ + { 0x0AB980E7, 0x808606B4 }, /* -231, 2745, 1716, -134 */ + { 0x0AA380E6, 0x808806CB }, /* -230, 2723, 1739, -136 */ + { 0x0A8D80E4, 0x808A06E1 }, /* -228, 2701, 1761, -138 */ + { 0x0A7780E2, 0x808C06F7 }, /* -226, 2679, 1783, -140 */ + { 0x0A6180E0, 0x808E070D }, /* -224, 2657, 1805, -142 */ + { 0x0A4B80DE, 0x80910724 }, /* -222, 2635, 1828, -145 */ + { 0x0A3580DC, 0x8093073A }, /* -220, 2613, 1850, -147 */ + { 0x0A1F80DA, 0x80950750 }, /* -218, 2591, 1872, -149 */ + { 0x0A0880D8, 0x80970767 }, /* -216, 2568, 1895, -151 */ + { 0x09F280D6, 0x8099077D }, /* -214, 2546, 1917, -153 */ + { 0x09DD80D4, 0x809C0793 }, /* -212, 2525, 1939, -156 */ + { 0x09C680D2, 0x809E07AA }, /* -210, 2502, 1962, -158 */ + { 0x09B080D0, 0x80A007C0 }, /* -208, 2480, 1984, -160 */ + { 0x099980CE, 0x80A207D7 }, /* -206, 2457, 2007, -162 */ + { 0x098380CB, 0x80A507ED }, /* -203, 2435, 2029, -165 */ + { 0x096C80C9, 0x80A70804 }, /* -201, 2412, 2052, -167 */ + { 0x095680C7, 0x80A9081A }, /* -199, 2390, 2074, -169 */ + { 0x094080C5, 0x80AB0830 }, /* -197, 2368, 2096, -171 */ + { 0x092980C3, 0x80AE0848 }, /* -195, 2345, 2120, -174 */ + { 0x091380C1, 0x80B0085E }, /* -193, 2323, 2142, -176 */ + { 0x08FC80BE, 0x80B20874 }, /* -190, 2300, 2164, -178 */ + { 0x08E580BC, 0x80B4088B }, /* -188, 2277, 2187, -180 */ + { 0x08D080BB, 0x80B708A2 }, /* -187, 2256, 2210, -183 */ + { 0x08B980B9, 0x80B908B9 }, /* -185, 2233, 2233, -185 */ + { 0x08A380B7, 0x80BB08CF }, /* -183, 2211, 2255, -187 */ + { 0x088B80B4, 0x80BC08E5 }, /* -180, 2187, 2277, -188 */ + { 0x087480B2, 0x80BE08FC }, /* -178, 2164, 2300, -190 */ + { 0x085E80B0, 0x80C10913 }, /* -176, 2142, 2323, -193 */ + { 0x084880AE, 0x80C30929 }, /* -174, 2120, 2345, -195 */ + { 0x083080AB, 0x80C50940 }, /* -171, 2096, 2368, -197 */ + { 0x081A80A9, 0x80C70956 }, /* -169, 2074, 2390, -199 */ + { 0x080480A7, 0x80C9096C }, /* -167, 2052, 2412, -201 */ + { 0x07ED80A5, 0x80CB0983 }, /* -165, 2029, 2435, -203 */ + { 0x07D780A2, 0x80CE0999 }, /* -162, 2007, 2457, -206 */ + { 0x07C080A0, 0x80D009B0 }, /* -160, 1984, 2480, -208 */ + { 0x07AA809E, 0x80D209C6 }, /* -158, 1962, 2502, -210 */ + { 0x0793809C, 0x80D409DD }, /* -156, 1939, 2525, -212 */ + { 0x077D8099, 0x80D609F2 }, /* -153, 1917, 2546, -214 */ + { 0x07668097, 0x80D80A09 }, /* -151, 1894, 2569, -216 */ + { 0x074F8095, 0x80DA0A20 }, /* -149, 1871, 2592, -218 */ + { 0x073A8093, 0x80DC0A35 }, /* -147, 1850, 2613, -220 */ + { 0x07238091, 0x80DE0A4C }, /* -145, 1827, 2636, -222 */ + { 0x070C808E, 0x80E00A62 }, /* -142, 1804, 2658, -224 */ + { 0x06F7808C, 0x80E20A77 }, /* -140, 1783, 2679, -226 */ + { 0x06E0808A, 0x80E40A8E }, /* -138, 1760, 2702, -228 */ + { 0x06CA8088, 0x80E60AA4 }, /* -136, 1738, 2724, -230 */ + { 0x06B48086, 0x80E70AB9 }, /* -134, 1716, 2745, -231 */ + { 0x069E8084, 0x80E90ACF }, /* -132, 1694, 2767, -233 */ + { 0x06878081, 0x80EB0AE5 }, /* -129, 1671, 2789, -235 */ + { 0x0672807F, 0x80ED0AFA }, /* -127, 1650, 2810, -237 */ + { 0x065C807D, 0x80EE0B0F }, /* -125, 1628, 2831, -238 */ + { 0x0646807B, 0x80F00B25 }, /* -123, 1606, 2853, -240 */ + { 0x06308079, 0x80F20B3B }, /* -121, 1584, 2875, -242 */ + { 0x061A8077, 0x80F30B50 }, /* -119, 1562, 2896, -243 */ + { 0x06068076, 0x80F50B65 }, /* -118, 1542, 2917, -245 */ + { 0x05F08074, 0x80F60B7A }, /* -116, 1520, 2938, -246 */ + { 0x05DB8072, 0x80F80B8F }, /* -114, 1499, 2959, -248 */ + { 0x05C58070, 0x80F90BA4 }, /* -112, 1477, 2980, -249 */ + { 0x05B1806E, 0x80FC0BB9 }, /* -110, 1457, 3001, -252 */ + { 0x059B806C, 0x80FD0BCE }, /* -108, 1435, 3022, -253 */ + { 0x0586806A, 0x80FE0BE2 }, /* -106, 1414, 3042, -254 */ + { 0x05718068, 0x81000BF7 }, /* -104, 1393, 3063, -256 */ + { 0x055C8066, 0x81010C0B }, /* -102, 1372, 3083, -257 */ + { 0x05478064, 0x81020C1F }, /* -100, 1351, 3103, -258 */ + { 0x05328062, 0x81030C33 }, /* -98, 1330, 3123, -259 */ + { 0x051D8060, 0x81040C47 }, /* -96, 1309, 3143, -260 */ + { 0x0508805E, 0x81050C5B }, /* -94, 1288, 3163, -261 */ + { 0x04F3805C, 0x81060C6F }, /* -92, 1267, 3183, -262 */ + { 0x04E0805B, 0x81070C82 }, /* -91, 1248, 3202, -263 */ + { 0x04CB8059, 0x81080C96 }, /* -89, 1227, 3222, -264 */ + { 0x04B68057, 0x81080CA9 }, /* -87, 1206, 3241, -264 */ + { 0x04A28055, 0x81090CBC }, /* -85, 1186, 3260, -265 */ + { 0x048E8053, 0x810A0CCF }, /* -83, 1166, 3279, -266 */ + { 0x047A8052, 0x810A0CE2 }, /* -82, 1146, 3298, -266 */ + { 0x04668050, 0x810B0CF5 }, /* -80, 1126, 3317, -267 */ + { 0x0451804E, 0x810B0D08 }, /* -78, 1105, 3336, -267 */ + { 0x043E804D, 0x810C0D1B }, /* -77, 1086, 3355, -268 */ + { 0x042B804B, 0x810C0D2C }, /* -75, 1067, 3372, -268 */ + { 0x04178049, 0x810C0D3E }, /* -73, 1047, 3390, -268 */ + { 0x04038048, 0x810C0D51 }, /* -72, 1027, 3409, -268 */ + { 0x03F08046, 0x810C0D62 }, /* -70, 1008, 3426, -268 */ + { 0x03DD8044, 0x810C0D73 }, /* -68, 989, 3443, -268 */ + { 0x03CA8043, 0x810C0D85 }, /* -67, 970, 3461, -268 */ + { 0x03B78041, 0x810C0D96 }, /* -65, 951, 3478, -268 */ + { 0x03A48040, 0x810C0DA8 }, /* -64, 932, 3496, -268 */ + { 0x0391803E, 0x810B0DB8 }, /* -62, 913, 3512, -267 */ + { 0x0380803D, 0x810C0DC9 }, /* -61, 896, 3529, -268 */ + { 0x036D803B, 0x810C0DDA }, /* -59, 877, 3546, -268 */ + { 0x035B803A, 0x810B0DEA }, /* -58, 859, 3562, -267 */ + { 0x03488038, 0x810A0DFA }, /* -56, 840, 3578, -266 */ + { 0x03368037, 0x810A0E0B }, /* -55, 822, 3595, -266 */ + { 0x03248036, 0x81090E1B }, /* -54, 804, 3611, -265 */ + { 0x03128034, 0x81080E2A }, /* -52, 786, 3626, -264 */ + { 0x03018033, 0x81070E39 }, /* -51, 769, 3641, -263 */ + { 0x02EF8032, 0x81060E49 }, /* -50, 751, 3657, -262 */ + { 0x02DE8030, 0x81040E56 }, /* -48, 734, 3670, -260 */ + { 0x02CC802F, 0x81030E66 }, /* -47, 716, 3686, -259 */ + { 0x02BB802E, 0x81020E75 }, /* -46, 699, 3701, -258 */ + { 0x02AA802D, 0x81000E83 }, /* -45, 682, 3715, -256 */ + { 0x0299802B, 0x80FE0E90 }, /* -43, 665, 3728, -254 */ + { 0x0288802A, 0x80FD0E9F }, /* -42, 648, 3743, -253 */ + { 0x02778029, 0x80FB0EAD }, /* -41, 631, 3757, -251 */ + { 0x02678028, 0x80F90EBA }, /* -40, 615, 3770, -249 */ + { 0x02568027, 0x80F70EC8 }, /* -39, 598, 3784, -247 */ + { 0x02468025, 0x80F50ED4 }, /* -37, 582, 3796, -245 */ + { 0x02368024, 0x80F30EE1 }, /* -36, 566, 3809, -243 */ + { 0x02268023, 0x80F00EED }, /* -35, 550, 3821, -240 */ + { 0x02188023, 0x80EF0EFA }, /* -35, 536, 3834, -239 */ + { 0x02078021, 0x80EB0F05 }, /* -33, 519, 3845, -235 */ + { 0x01F98021, 0x80E90F11 }, /* -33, 505, 3857, -233 */ + { 0x01EA8020, 0x80E60F1C }, /* -32, 490, 3868, -230 */ + { 0x01DC801F, 0x80E40F27 }, /* -31, 476, 3879, -228 */ + { 0x01CD801E, 0x80E00F31 }, /* -30, 461, 3889, -224 */ + { 0x01BE801D, 0x80DD0F3C }, /* -29, 446, 3900, -221 */ + { 0x01AF801C, 0x80DA0F47 }, /* -28, 431, 3911, -218 */ + { 0x01A1801B, 0x80D70F51 }, /* -27, 417, 3921, -215 */ + { 0x0192801A, 0x80D30F5B }, /* -26, 402, 3931, -211 */ + { 0x01848019, 0x80CF0F64 }, /* -25, 388, 3940, -207 */ + { 0x01768018, 0x80CB0F6D }, /* -24, 374, 3949, -203 */ + { 0x01688017, 0x80C80F77 }, /* -23, 360, 3959, -200 */ + { 0x015A8016, 0x80C30F7F }, /* -22, 346, 3967, -195 */ + { 0x014D8015, 0x80BF0F87 }, /* -21, 333, 3975, -191 */ + { 0x013F8015, 0x80BB0F91 }, /* -21, 319, 3985, -187 */ + { 0x01328014, 0x80B60F98 }, /* -20, 306, 3992, -182 */ + { 0x01258013, 0x80B20FA0 }, /* -19, 293, 4000, -178 */ + { 0x01188012, 0x80AD0FA7 }, /* -18, 280, 4007, -173 */ + { 0x010B8011, 0x80A80FAE }, /* -17, 267, 4014, -168 */ + { 0x00FE8010, 0x80A30FB5 }, /* -16, 254, 4021, -163 */ + { 0x00F28010, 0x809E0FBC }, /* -16, 242, 4028, -158 */ + { 0x00E6800F, 0x80990FC2 }, /* -15, 230, 4034, -153 */ + { 0x00DA800E, 0x80930FC7 }, /* -14, 218, 4039, -147 */ + { 0x00CE800D, 0x808E0FCD }, /* -13, 206, 4045, -142 */ + { 0x00C2800D, 0x80880FD3 }, /* -13, 194, 4051, -136 */ + { 0x00B6800C, 0x80820FD8 }, /* -12, 182, 4056, -130 */ + { 0x00AB800B, 0x807C0FDC }, /* -11, 171, 4060, -124 */ + { 0x009F800A, 0x80760FE1 }, /* -10, 159, 4065, -118 */ + { 0x0094800A, 0x80700FE6 }, /* -10, 148, 4070, -112 */ + { 0x00898009, 0x80690FE9 }, /* -9, 137, 4073, -105 */ + { 0x007E8008, 0x80630FED }, /* -8, 126, 4077, -99 */ + { 0x00748007, 0x805C0FEF }, /* -7, 116, 4079, -92 */ + { 0x00698007, 0x80550FF3 }, /* -7, 105, 4083, -85 */ + { 0x005F8006, 0x804E0FF5 }, /* -6, 95, 4085, -78 */ + { 0x00558005, 0x80470FF7 }, /* -5, 85, 4087, -71 */ + { 0x004B8005, 0x80400FFA }, /* -5, 75, 4090, -64 */ + { 0x00418004, 0x80380FFB }, /* -4, 65, 4091, -56 */ + { 0x00378003, 0x80310FFD }, /* -3, 55, 4093, -49 */ + { 0x002E8003, 0x80290FFE }, /* -3, 46, 4094, -41 */ + { 0x00238002, 0x80211000 }, /* -2, 35, 4096, -33 */ + { 0x001A8001, 0x80191000 }, /* -1, 26, 4096, -25 */ + { 0x00118001, 0x80101000 }, /* -1, 17, 4096, -16 */ + { 0x00080000, 0x80081000 }, /* 0, 8, 4096, -8 */ +}; + +long CimarronVideoFilter128[][2] = +{ + { 0x10000000, 0x00000000 }, /* 0, 4096, 0, 0 */ + { 0x10018011, 0x80010011 }, /* -17, 4097, 17, -1 */ + { 0x10008021, 0x80020023 }, /* -33, 4096, 35, -2 */ + { 0x0FFE8031, 0x80030036 }, /* -49, 4094, 54, -3 */ + { 0x0FFB8040, 0x8005004A }, /* -64, 4091, 74, -5 */ + { 0x0FF6804E, 0x8006005E }, /* -78, 4086, 94, -6 */ + { 0x0FF0805C, 0x80070073 }, /* -92, 4080, 115, -7 */ + { 0x0FEB806A, 0x80090088 }, /* -106, 4075, 136, -9 */ + { 0x0FE18076, 0x800A009F }, /* -118, 4065, 159, -10 */ + { 0x0FD98082, 0x800C00B5 }, /* -130, 4057, 181, -12 */ + { 0x0FCE808E, 0x800D00CD }, /* -142, 4046, 205, -13 */ + { 0x0FC38099, 0x800F00E5 }, /* -153, 4035, 229, -15 */ + { 0x0FB680A4, 0x801000FE }, /* -164, 4022, 254, -16 */ + { 0x0FA880AD, 0x80120117 }, /* -173, 4008, 279, -18 */ + { 0x0F9A80B7, 0x80140131 }, /* -183, 3994, 305, -20 */ + { 0x0F8980C0, 0x8015014C }, /* -192, 3977, 332, -21 */ + { 0x0F7880C8, 0x80170167 }, /* -200, 3960, 359, -23 */ + { 0x0F6680D0, 0x80190183 }, /* -208, 3942, 387, -25 */ + { 0x0F5280D7, 0x801B01A0 }, /* -215, 3922, 416, -27 */ + { 0x0F3E80DE, 0x801D01BD }, /* -222, 3902, 445, -29 */ + { 0x0F2880E4, 0x801F01DB }, /* -228, 3880, 475, -31 */ + { 0x0F1180EA, 0x802101FA }, /* -234, 3857, 506, -33 */ + { 0x0EF880EE, 0x80220218 }, /* -238, 3832, 536, -34 */ + { 0x0EDF80F3, 0x80240238 }, /* -243, 3807, 568, -36 */ + { 0x0EC680F7, 0x80270258 }, /* -247, 3782, 600, -39 */ + { 0x0EAB80FB, 0x80290279 }, /* -251, 3755, 633, -41 */ + { 0x0E9080FF, 0x802B029A }, /* -255, 3728, 666, -43 */ + { 0x0E748102, 0x802E02BC }, /* -258, 3700, 700, -46 */ + { 0x0E588105, 0x803102DE }, /* -261, 3672, 734, -49 */ + { 0x0E388107, 0x80330302 }, /* -263, 3640, 770, -51 */ + { 0x0E1A8109, 0x80360325 }, /* -265, 3610, 805, -54 */ + { 0x0DFB810B, 0x80390349 }, /* -267, 3579, 841, -57 */ + { 0x0DDB810C, 0x803C036D }, /* -268, 3547, 877, -60 */ + { 0x0DBA810D, 0x803F0392 }, /* -269, 3514, 914, -63 */ + { 0x0D98810E, 0x804203B8 }, /* -270, 3480, 952, -66 */ + { 0x0D74810D, 0x804503DE }, /* -269, 3444, 990, -69 */ + { 0x0D50810D, 0x80480405 }, /* -269, 3408, 1029, -72 */ + { 0x0D2C810C, 0x804B042B }, /* -268, 3372, 1067, -75 */ + { 0x0D08810C, 0x804F0453 }, /* -268, 3336, 1107, -79 */ + { 0x0CE3810B, 0x8052047A }, /* -267, 3299, 1146, -82 */ + { 0x0CBD810A, 0x805604A3 }, /* -266, 3261, 1187, -86 */ + { 0x0C968108, 0x805904CB }, /* -264, 3222, 1227, -89 */ + { 0x0C708107, 0x805D04F4 }, /* -263, 3184, 1268, -93 */ + { 0x0C488105, 0x8061051E }, /* -261, 3144, 1310, -97 */ + { 0x0C208103, 0x80640547 }, /* -259, 3104, 1351, -100 */ + { 0x0BF78100, 0x80680571 }, /* -256, 3063, 1393, -104 */ + { 0x0BCF80FE, 0x806C059B }, /* -254, 3023, 1435, -108 */ + { 0x0BA480FA, 0x807005C6 }, /* -250, 2980, 1478, -112 */ + { 0x0B7A80F7, 0x807405F1 }, /* -247, 2938, 1521, -116 */ + { 0x0B4F80F4, 0x8077061C }, /* -244, 2895, 1564, -119 */ + { 0x0B2580F1, 0x807C0648 }, /* -241, 2853, 1608, -124 */ + { 0x0AFA80ED, 0x80800673 }, /* -237, 2810, 1651, -128 */ + { 0x0ACF80EA, 0x8084069F }, /* -234, 2767, 1695, -132 */ + { 0x0AA380E6, 0x808806CB }, /* -230, 2723, 1739, -136 */ + { 0x0A7880E2, 0x808D06F7 }, /* -226, 2680, 1783, -141 */ + { 0x0A4C80DF, 0x80910724 }, /* -223, 2636, 1828, -145 */ + { 0x0A2080DB, 0x80960751 }, /* -219, 2592, 1873, -150 */ + { 0x09F480D7, 0x809A077D }, /* -215, 2548, 1917, -154 */ + { 0x09C780D2, 0x809F07AA }, /* -210, 2503, 1962, -159 */ + { 0x099A80CE, 0x80A307D7 }, /* -206, 2458, 2007, -163 */ + { 0x096D80CA, 0x80A70804 }, /* -202, 2413, 2052, -167 */ + { 0x094180C6, 0x80AC0831 }, /* -198, 2369, 2097, -172 */ + { 0x091380C1, 0x80B0085E }, /* -193, 2323, 2142, -176 */ + { 0x08E780BE, 0x80B5088C }, /* -190, 2279, 2188, -181 */ + { 0x08B980B9, 0x80B908B9 }, /* -185, 2233, 2233, -185 */ + { 0x088C80B5, 0x80BE08E7 }, /* -181, 2188, 2279, -190 */ + { 0x085E80B0, 0x80C10913 }, /* -176, 2142, 2323, -193 */ + { 0x083180AC, 0x80C60941 }, /* -172, 2097, 2369, -198 */ + { 0x080480A7, 0x80CA096D }, /* -167, 2052, 2413, -202 */ + { 0x07D780A3, 0x80CE099A }, /* -163, 2007, 2458, -206 */ + { 0x07AA809F, 0x80D209C7 }, /* -159, 1962, 2503, -210 */ + { 0x077D809A, 0x80D709F4 }, /* -154, 1917, 2548, -215 */ + { 0x07518096, 0x80DB0A20 }, /* -150, 1873, 2592, -219 */ + { 0x07248091, 0x80DF0A4C }, /* -145, 1828, 2636, -223 */ + { 0x06F7808D, 0x80E20A78 }, /* -141, 1783, 2680, -226 */ + { 0x06CA8088, 0x80E60AA4 }, /* -136, 1738, 2724, -230 */ + { 0x069E8084, 0x80EA0AD0 }, /* -132, 1694, 2768, -234 */ + { 0x06738080, 0x80ED0AFA }, /* -128, 1651, 2810, -237 */ + { 0x0647807C, 0x80F10B26 }, /* -124, 1607, 2854, -241 */ + { 0x061B8077, 0x80F40B50 }, /* -119, 1563, 2896, -244 */ + { 0x05F18074, 0x80F70B7A }, /* -116, 1521, 2938, -247 */ + { 0x05C68070, 0x80FA0BA4 }, /* -112, 1478, 2980, -250 */ + { 0x059C806C, 0x80FE0BCE }, /* -108, 1436, 3022, -254 */ + { 0x05728068, 0x81000BF6 }, /* -104, 1394, 3062, -256 */ + { 0x05478064, 0x81030C20 }, /* -100, 1351, 3104, -259 */ + { 0x051E8061, 0x81050C48 }, /* -97, 1310, 3144, -261 */ + { 0x04F4805D, 0x81070C70 }, /* -93, 1268, 3184, -263 */ + { 0x04CB8059, 0x81080C96 }, /* -89, 1227, 3222, -264 */ + { 0x04A38056, 0x810A0CBD }, /* -86, 1187, 3261, -266 */ + { 0x047A8052, 0x810B0CE3 }, /* -82, 1146, 3299, -267 */ + { 0x0453804F, 0x810C0D08 }, /* -79, 1107, 3336, -268 */ + { 0x042B804B, 0x810C0D2C }, /* -75, 1067, 3372, -268 */ + { 0x04048048, 0x810D0D51 }, /* -72, 1028, 3409, -269 */ + { 0x03DE8045, 0x810D0D74 }, /* -69, 990, 3444, -269 */ + { 0x03B88042, 0x810E0D98 }, /* -66, 952, 3480, -270 */ + { 0x0393803F, 0x810D0DB9 }, /* -63, 915, 3513, -269 */ + { 0x036E803C, 0x810C0DDA }, /* -60, 878, 3546, -268 */ + { 0x03498039, 0x810B0DFB }, /* -57, 841, 3579, -267 */ + { 0x03258036, 0x81090E1A }, /* -54, 805, 3610, -265 */ + { 0x03018033, 0x81070E39 }, /* -51, 769, 3641, -263 */ + { 0x02DE8031, 0x81050E58 }, /* -49, 734, 3672, -261 */ + { 0x02BC802E, 0x81020E74 }, /* -46, 700, 3700, -258 */ + { 0x0299802B, 0x80FF0E91 }, /* -43, 665, 3729, -255 */ + { 0x02788029, 0x80FB0EAC }, /* -41, 632, 3756, -251 */ + { 0x02578027, 0x80F70EC7 }, /* -39, 599, 3783, -247 */ + { 0x02378024, 0x80F30EE0 }, /* -36, 567, 3808, -243 */ + { 0x02178022, 0x80EE0EF9 }, /* -34, 535, 3833, -238 */ + { 0x01FA8021, 0x80EA0F11 }, /* -33, 506, 3857, -234 */ + { 0x01DC801F, 0x80E40F27 }, /* -31, 476, 3879, -228 */ + { 0x01BE801D, 0x80DE0F3D }, /* -29, 446, 3901, -222 */ + { 0x01A1801B, 0x80D70F51 }, /* -27, 417, 3921, -215 */ + { 0x01848019, 0x80D00F65 }, /* -25, 388, 3941, -208 */ + { 0x01688017, 0x80C80F77 }, /* -23, 360, 3959, -200 */ + { 0x014D8015, 0x80C00F88 }, /* -21, 333, 3976, -192 */ + { 0x01328014, 0x80B70F99 }, /* -20, 306, 3993, -183 */ + { 0x01188012, 0x80AD0FA7 }, /* -18, 280, 4007, -173 */ + { 0x00FF8010, 0x80A40FB5 }, /* -16, 255, 4021, -164 */ + { 0x00E6800F, 0x80990FC2 }, /* -15, 230, 4034, -153 */ + { 0x00CE800D, 0x808E0FCD }, /* -13, 206, 4045, -142 */ + { 0x00B6800C, 0x80820FD8 }, /* -12, 182, 4056, -130 */ + { 0x00A0800A, 0x80760FE0 }, /* -10, 160, 4064, -118 */ + { 0x00898009, 0x806A0FEA }, /* -9, 137, 4074, -106 */ + { 0x00748007, 0x805C0FEF }, /* -7, 116, 4079, -92 */ + { 0x005F8006, 0x804E0FF5 }, /* -6, 95, 4085, -78 */ + { 0x004B8005, 0x80400FFA }, /* -5, 75, 4090, -64 */ + { 0x00378003, 0x80310FFD }, /* -3, 55, 4093, -49 */ + { 0x00238002, 0x80211000 }, /* -2, 35, 4096, -33 */ + { 0x00118001, 0x80111001 }, /* -1, 17, 4097, -17 */ + { 0x10000000, 0x00000000 }, /* 0, 4096, 0, 0 */ + { 0x10018011, 0x80010011 }, /* -17, 4097, 17, -1 */ + { 0x10008021, 0x80020023 }, /* -33, 4096, 35, -2 */ + { 0x0FFE8031, 0x80030036 }, /* -49, 4094, 54, -3 */ + { 0x0FFB8040, 0x8005004A }, /* -64, 4091, 74, -5 */ + { 0x0FF6804E, 0x8006005E }, /* -78, 4086, 94, -6 */ + { 0x0FF0805C, 0x80070073 }, /* -92, 4080, 115, -7 */ + { 0x0FEB806A, 0x80090088 }, /* -106, 4075, 136, -9 */ + { 0x0FE18076, 0x800A009F }, /* -118, 4065, 159, -10 */ + { 0x0FD98082, 0x800C00B5 }, /* -130, 4057, 181, -12 */ + { 0x0FCE808E, 0x800D00CD }, /* -142, 4046, 205, -13 */ + { 0x0FC38099, 0x800F00E5 }, /* -153, 4035, 229, -15 */ + { 0x0FB680A4, 0x801000FE }, /* -164, 4022, 254, -16 */ + { 0x0FA880AD, 0x80120117 }, /* -173, 4008, 279, -18 */ + { 0x0F9A80B7, 0x80140131 }, /* -183, 3994, 305, -20 */ + { 0x0F8980C0, 0x8015014C }, /* -192, 3977, 332, -21 */ + { 0x0F7880C8, 0x80170167 }, /* -200, 3960, 359, -23 */ + { 0x0F6680D0, 0x80190183 }, /* -208, 3942, 387, -25 */ + { 0x0F5280D7, 0x801B01A0 }, /* -215, 3922, 416, -27 */ + { 0x0F3E80DE, 0x801D01BD }, /* -222, 3902, 445, -29 */ + { 0x0F2880E4, 0x801F01DB }, /* -228, 3880, 475, -31 */ + { 0x0F1180EA, 0x802101FA }, /* -234, 3857, 506, -33 */ + { 0x0EF880EE, 0x80220218 }, /* -238, 3832, 536, -34 */ + { 0x0EDF80F3, 0x80240238 }, /* -243, 3807, 568, -36 */ + { 0x0EC680F7, 0x80270258 }, /* -247, 3782, 600, -39 */ + { 0x0EAB80FB, 0x80290279 }, /* -251, 3755, 633, -41 */ + { 0x0E9080FF, 0x802B029A }, /* -255, 3728, 666, -43 */ + { 0x0E748102, 0x802E02BC }, /* -258, 3700, 700, -46 */ + { 0x0E588105, 0x803102DE }, /* -261, 3672, 734, -49 */ + { 0x0E388107, 0x80330302 }, /* -263, 3640, 770, -51 */ + { 0x0E1A8109, 0x80360325 }, /* -265, 3610, 805, -54 */ + { 0x0DFB810B, 0x80390349 }, /* -267, 3579, 841, -57 */ + { 0x0DDB810C, 0x803C036D }, /* -268, 3547, 877, -60 */ + { 0x0DBA810D, 0x803F0392 }, /* -269, 3514, 914, -63 */ + { 0x0D98810E, 0x804203B8 }, /* -270, 3480, 952, -66 */ + { 0x0D74810D, 0x804503DE }, /* -269, 3444, 990, -69 */ + { 0x0D50810D, 0x80480405 }, /* -269, 3408, 1029, -72 */ + { 0x0D2C810C, 0x804B042B }, /* -268, 3372, 1067, -75 */ + { 0x0D08810C, 0x804F0453 }, /* -268, 3336, 1107, -79 */ + { 0x0CE3810B, 0x8052047A }, /* -267, 3299, 1146, -82 */ + { 0x0CBD810A, 0x805604A3 }, /* -266, 3261, 1187, -86 */ + { 0x0C968108, 0x805904CB }, /* -264, 3222, 1227, -89 */ + { 0x0C708107, 0x805D04F4 }, /* -263, 3184, 1268, -93 */ + { 0x0C488105, 0x8061051E }, /* -261, 3144, 1310, -97 */ + { 0x0C208103, 0x80640547 }, /* -259, 3104, 1351, -100 */ + { 0x0BF78100, 0x80680571 }, /* -256, 3063, 1393, -104 */ + { 0x0BCF80FE, 0x806C059B }, /* -254, 3023, 1435, -108 */ + { 0x0BA480FA, 0x807005C6 }, /* -250, 2980, 1478, -112 */ + { 0x0B7A80F7, 0x807405F1 }, /* -247, 2938, 1521, -116 */ + { 0x0B4F80F4, 0x8077061C }, /* -244, 2895, 1564, -119 */ + { 0x0B2580F1, 0x807C0648 }, /* -241, 2853, 1608, -124 */ + { 0x0AFA80ED, 0x80800673 }, /* -237, 2810, 1651, -128 */ + { 0x0ACF80EA, 0x8084069F }, /* -234, 2767, 1695, -132 */ + { 0x0AA380E6, 0x808806CB }, /* -230, 2723, 1739, -136 */ + { 0x0A7880E2, 0x808D06F7 }, /* -226, 2680, 1783, -141 */ + { 0x0A4C80DF, 0x80910724 }, /* -223, 2636, 1828, -145 */ + { 0x0A2080DB, 0x80960751 }, /* -219, 2592, 1873, -150 */ + { 0x09F480D7, 0x809A077D }, /* -215, 2548, 1917, -154 */ + { 0x09C780D2, 0x809F07AA }, /* -210, 2503, 1962, -159 */ + { 0x099A80CE, 0x80A307D7 }, /* -206, 2458, 2007, -163 */ + { 0x096D80CA, 0x80A70804 }, /* -202, 2413, 2052, -167 */ + { 0x094180C6, 0x80AC0831 }, /* -198, 2369, 2097, -172 */ + { 0x091380C1, 0x80B0085E }, /* -193, 2323, 2142, -176 */ + { 0x08E780BE, 0x80B5088C }, /* -190, 2279, 2188, -181 */ + { 0x08B980B9, 0x80B908B9 }, /* -185, 2233, 2233, -185 */ + { 0x088C80B5, 0x80BE08E7 }, /* -181, 2188, 2279, -190 */ + { 0x085E80B0, 0x80C10913 }, /* -176, 2142, 2323, -193 */ + { 0x083180AC, 0x80C60941 }, /* -172, 2097, 2369, -198 */ + { 0x080480A7, 0x80CA096D }, /* -167, 2052, 2413, -202 */ + { 0x07D780A3, 0x80CE099A }, /* -163, 2007, 2458, -206 */ + { 0x07AA809F, 0x80D209C7 }, /* -159, 1962, 2503, -210 */ + { 0x077D809A, 0x80D709F4 }, /* -154, 1917, 2548, -215 */ + { 0x07518096, 0x80DB0A20 }, /* -150, 1873, 2592, -219 */ + { 0x07248091, 0x80DF0A4C }, /* -145, 1828, 2636, -223 */ + { 0x06F7808D, 0x80E20A78 }, /* -141, 1783, 2680, -226 */ + { 0x06CA8088, 0x80E60AA4 }, /* -136, 1738, 2724, -230 */ + { 0x069E8084, 0x80EA0AD0 }, /* -132, 1694, 2768, -234 */ + { 0x06738080, 0x80ED0AFA }, /* -128, 1651, 2810, -237 */ + { 0x0647807C, 0x80F10B26 }, /* -124, 1607, 2854, -241 */ + { 0x061B8077, 0x80F40B50 }, /* -119, 1563, 2896, -244 */ + { 0x05F18074, 0x80F70B7A }, /* -116, 1521, 2938, -247 */ + { 0x05C68070, 0x80FA0BA4 }, /* -112, 1478, 2980, -250 */ + { 0x059C806C, 0x80FE0BCE }, /* -108, 1436, 3022, -254 */ + { 0x05728068, 0x81000BF6 }, /* -104, 1394, 3062, -256 */ + { 0x05478064, 0x81030C20 }, /* -100, 1351, 3104, -259 */ + { 0x051E8061, 0x81050C48 }, /* -97, 1310, 3144, -261 */ + { 0x04F4805D, 0x81070C70 }, /* -93, 1268, 3184, -263 */ + { 0x04CB8059, 0x81080C96 }, /* -89, 1227, 3222, -264 */ + { 0x04A38056, 0x810A0CBD }, /* -86, 1187, 3261, -266 */ + { 0x047A8052, 0x810B0CE3 }, /* -82, 1146, 3299, -267 */ + { 0x0453804F, 0x810C0D08 }, /* -79, 1107, 3336, -268 */ + { 0x042B804B, 0x810C0D2C }, /* -75, 1067, 3372, -268 */ + { 0x04048048, 0x810D0D51 }, /* -72, 1028, 3409, -269 */ + { 0x03DE8045, 0x810D0D74 }, /* -69, 990, 3444, -269 */ + { 0x03B88042, 0x810E0D98 }, /* -66, 952, 3480, -270 */ + { 0x0393803F, 0x810D0DB9 }, /* -63, 915, 3513, -269 */ + { 0x036E803C, 0x810C0DDA }, /* -60, 878, 3546, -268 */ + { 0x03498039, 0x810B0DFB }, /* -57, 841, 3579, -267 */ + { 0x03258036, 0x81090E1A }, /* -54, 805, 3610, -265 */ + { 0x03018033, 0x81070E39 }, /* -51, 769, 3641, -263 */ + { 0x02DE8031, 0x81050E58 }, /* -49, 734, 3672, -261 */ + { 0x02BC802E, 0x81020E74 }, /* -46, 700, 3700, -258 */ + { 0x0299802B, 0x80FF0E91 }, /* -43, 665, 3729, -255 */ + { 0x02788029, 0x80FB0EAC }, /* -41, 632, 3756, -251 */ + { 0x02578027, 0x80F70EC7 }, /* -39, 599, 3783, -247 */ + { 0x02378024, 0x80F30EE0 }, /* -36, 567, 3808, -243 */ + { 0x02178022, 0x80EE0EF9 }, /* -34, 535, 3833, -238 */ + { 0x01FA8021, 0x80EA0F11 }, /* -33, 506, 3857, -234 */ + { 0x01DC801F, 0x80E40F27 }, /* -31, 476, 3879, -228 */ + { 0x01BE801D, 0x80DE0F3D }, /* -29, 446, 3901, -222 */ + { 0x01A1801B, 0x80D70F51 }, /* -27, 417, 3921, -215 */ + { 0x01848019, 0x80D00F65 }, /* -25, 388, 3941, -208 */ + { 0x01688017, 0x80C80F77 }, /* -23, 360, 3959, -200 */ + { 0x014D8015, 0x80C00F88 }, /* -21, 333, 3976, -192 */ + { 0x01328014, 0x80B70F99 }, /* -20, 306, 3993, -183 */ + { 0x01188012, 0x80AD0FA7 }, /* -18, 280, 4007, -173 */ + { 0x00FF8010, 0x80A40FB5 }, /* -16, 255, 4021, -164 */ + { 0x00E6800F, 0x80990FC2 }, /* -15, 230, 4034, -153 */ + { 0x00CE800D, 0x808E0FCD }, /* -13, 206, 4045, -142 */ + { 0x00B6800C, 0x80820FD8 }, /* -12, 182, 4056, -130 */ + { 0x00A0800A, 0x80760FE0 }, /* -10, 160, 4064, -118 */ + { 0x00898009, 0x806A0FEA }, /* -9, 137, 4074, -106 */ + { 0x00748007, 0x805C0FEF }, /* -7, 116, 4079, -92 */ + { 0x005F8006, 0x804E0FF5 }, /* -6, 95, 4085, -78 */ + { 0x004B8005, 0x80400FFA }, /* -5, 75, 4090, -64 */ + { 0x00378003, 0x80310FFD }, /* -3, 55, 4093, -49 */ + { 0x00238002, 0x80211000 }, /* -2, 35, 4096, -33 */ + { 0x00118001, 0x80111001 }, /* -1, 17, 4097, -17 */ +}; --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_modes.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim/cim_modes.c 2005-12-14 11:39:00.000000000 -0700 @@ -0,0 +1,1839 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Cimarron mode tables. + * */ + +/*-------------------------------*/ +/* PREDEFINED DISPLAY TIMINGS */ +/*-------------------------------*/ + +VG_DISPLAY_MODE CimarronDisplayModes[] = +{ + /* 320 x 240 PANEL */ + + { VG_SUPPORTFLAG_75HZ | /* refresh rate = 75 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_PANEL, /* Panel Mode. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_PANELOUT | /* Panel output. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC | /* negative syncs */ + VG_MODEFLAG_QVGA, /* QVGA Panel size. */ + 320, 240, /* No scaling. */ + 320, 240, /* 320x240 active */ + 320, 240, /* 320x240 panel */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0140, 0x0148, 0x0162, 0x0180, 0x0188, 0x0190, /* horizontal timings */ + 0x00F0, 0x00F4, 0x00F9, 0x00FD, 0x00FF, 0x0104, /* vertical timings */ + (31L << 16) | ((2000L * 65536L) / 10000L), /* freq = 31.2000 MHz */ + }, + + /* 640 x 400 */ + + { VG_SUPPORTFLAG_70HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC, /* negative HSYNC */ + 640, 400, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x280, 0x288, 0x290, 0x2F0, 0x318, 0x320, /* horizontal timings */ + 0x190, 0x197, 0x19C, 0x19E, 0x1BA, 0x1C1, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (25L << 16) | ((1750L * 65536L) / 10000L), /* freq = 25.175 MHz */ + }, + + /* 640x480 */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC, /* negative syncs */ + 640, 480, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0280, 0x0288, 0x0290, 0x02E8, 0x0318, 0x0320, /* horizontal timings */ + 0x01E0, 0x01E8, 0x01EA, 0x01EC, 0x0205, 0x020D, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (25L << 16) | ((1750L * 65536L) / 10000L), /* freq = 25.175 MHz */ + }, + + { VG_SUPPORTFLAG_70HZ | /* refresh rate = 70 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + 0, + 640, 480, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0280, 0x0280, 0x0298, 0x02D8, 0x0330, 0x0330, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01E2, 0x01E5, 0x01F4, 0x01F4, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (28L << 16) | ((5600L * 65536L) / 10000L), /* freq = 28.560 MHz */ + }, + + { VG_SUPPORTFLAG_72HZ | /* refresh rate = 72 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC, /* negative syncs */ + 640, 480, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0280, 0x0288, 0x0298, 0x02c0, 0x0338, 0x0340, /* horizontal timings */ + 0x01e0, 0x01e8, 0x01e9, 0x01ec, 0x0200, 0x0208, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (31L << 16) | ((5000L * 65536L) / 10000L), /* freq = 31.5 MHz */ + }, + + { VG_SUPPORTFLAG_75HZ | /* refresh rate = 75 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC, /* negative syncs */ + 640, 480, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0280, 0x0280, 0x0290, 0x02D0, 0x0348, 0x0348, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01E1, 0x01E4, 0x01F4, 0x01F4, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (31L << 16) | ((5000L * 65536L) / 10000L), /* freq = 31.5 MHz */ + }, + + { VG_SUPPORTFLAG_85HZ | /* refresh rate = 85 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC, /* negative syncs */ + 640, 480, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0280, 0x0280, 0x02B8, 0x02F0, 0x0340, 0x0340, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01E1, 0x01E4, 0x01FD, 0x01FD, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (36L << 16) | ((0000L * 65536L) / 10000L), /* freq = 36.0 MHz */ + }, + + { VG_SUPPORTFLAG_90HZ | /* refresh rate = 90 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + 0, + 640, 480, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0280, 0x0280, 0x02A0, 0x02E0, 0x0340, 0x0340, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01E1, 0x01E4, 0x01FA, 0x01FA, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (37L << 16) | ((8890L * 65536L) / 10000L), /* freq = 37.889 MHz */ + }, + + { VG_SUPPORTFLAG_100HZ | /* refresh rate = 100 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + 0, + 640, 480, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0280, 0x0280, 0x02A8, 0x02E8, 0x0350, 0x0350, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01E1, 0x01E4, 0x01FD, 0x01FD, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (43L << 16) | ((1630L * 65536L) / 10000L), /* freq = 43.163 MHz */ + }, + + /* 640 x 480 PANEL */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_PANEL, /* Panel Mode. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_PANELOUT | /* Panel output. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC, /* negative syncs */ + 640, 480, /* No scaling. */ + 640, 480, /* 640x480 active */ + 640, 480, /* 640x480 panel */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (25L << 16) | ((1750L * 65536L) / 10000L), /* freq = 25.175 MHz */ + }, + + /* 800x600 */ + + { VG_SUPPORTFLAG_56HZ | /* refresh rate = 56 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + 0, + 800, 600, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0320, 0x0320, 0x0338, 0x0380, 0x0400, 0x0400, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025B, 0x0271, 0x0271, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (36L << 16) | ((0000L * 65536L) / 10000L), /* freq = 36.0 MHz */ + }, + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + 0, + 800, 600, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0320, 0x0328, 0x0348, 0x03D0, 0x0418, 0x0420, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025D, 0x0274, 0x0274, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (40L << 16) | ((0000L * 65536L) / 10000L), /* freq = 40.00 MHz */ + }, + + { VG_SUPPORTFLAG_70HZ | /* refresh rate = 70 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + 0, + 800, 600, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0320, 0x0320, 0x0348, 0x0398, 0x0410, 0x0410, /* horizontal timings */ + 0x0258, 0x0258, 0x025c, 0x025F, 0x0274, 0x0274, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (45L << 16) | ((7200L * 65536L) / 10000L), /* freq = 45.72 MHz */ + }, + + { VG_SUPPORTFLAG_72HZ | /* refresh rate = 72 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + 0, + 800, 600, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0320, 0x0320, 0x0358, 0x03D0, 0x0410, 0x0410, /* horizontal timings */ + 0x0258, 0x0258, 0x027D, 0x0283, 0x029A, 0x029A, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (49L << 16) | ((5000L * 65536L) / 10000L), /* freq = 49.5 MHz */ + }, + + { VG_SUPPORTFLAG_75HZ | /* refresh rate = 75 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + 0, + 800, 600, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0320, 0x0320, 0x0330, 0x0380, 0x0420, 0x0420, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025C, 0x0271, 0x0271, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (49L << 16) | ((5000L * 65536L) / 10000L), /* freq = 49.5 MHz */ + }, + + { VG_SUPPORTFLAG_85HZ | /* refresh rate = 85 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + 0, + 800, 600, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0320, 0x0320, 0x0340, 0x0380, 0x0418, 0x0418, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025C, 0x0277, 0x0277, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (56L << 16) | ((2500L * 65536L) / 10000L), /* freq = 56.25 MHz */ + }, + + { VG_SUPPORTFLAG_90HZ | /* refresh rate = 90 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + 0, + 800, 600, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0320, 0x0320, 0x0348, 0x03A0, 0x0420, 0x0420, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025C, 0x0278, 0x0278, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (60L << 16) | ((650L * 65536L) / 10000L), /* freq = 60.065 MHz */ + }, + + { VG_SUPPORTFLAG_100HZ | /* refresh rate = 100 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + 0, + 800, 600, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0320, 0x0320, 0x0350, 0x03A8, 0x0430, 0x0430, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025C, 0x0277, 0x027C, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (68L << 16) | ((1790L * 65536L) / 10000L), /* freq = 68.179 MHz */ + }, + + /* 800x600 PANEL */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_PANEL, /* Panel Mode. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_PANELOUT | /* Panel output. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC, /* negative syncs */ + 800, 600, /* No scaling. */ + 800, 600, /* 800x600 active. */ + 800, 600, /* 800x600 panel */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0320, 0x0320, 0x0348, 0x03C8, 0x0420, 0x0420, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025D, 0x0274, 0x0274, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (40L << 16) | ((0000L * 65536L) / 10000L), /* freq = 40.00 MHz */ + }, + + /* 1024x768 */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC, /* negative syncs */ + 1024, 768, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0400, 0x0400, 0x0418, 0x04A0, 0x0540, 0x0540, /* horizontal timings */ + 0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (65L << 16) | ((0000L * 65536L) / 10000L), /* freq = 65.00 MHz */ + }, + + { VG_SUPPORTFLAG_70HZ | /* refresh rate = 70 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC, /* negative syncs */ + 1024, 768, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0400, 0x0400, 0x0418, 0x04A0, 0x0530, 0x0530, /* horizontal timings */ + 0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (75L << 16) | ((0000L * 65536L) / 10000L), /* freq = 75.0 MHz */ + }, + + { VG_SUPPORTFLAG_72HZ | /* refresh rate = 72 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1024, 768, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0400, 0x0400, 0x0438, 0x04A8, 0x0550, 0x0550, /* horizontal timings */ + 0x0300, 0x0300, 0x0304, 0x0307, 0x0324, 0x0324, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (78L << 16) | ((7500L * 65536L) / 10000L), /* freq = 78.75 MHz */ + }, + + { VG_SUPPORTFLAG_75HZ | /* refresh rate = 75 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1024, 768, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0400, 0x0400, 0x0410, 0x0470, 0x0520, 0x0520, /* horizontal timings */ + 0x0300, 0x0300, 0x0301, 0x0304, 0x0320, 0x0320, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (78L << 16) | ((7500L * 65536L) / 10000L), /* freq = 78.75 MHz */ + }, + + { VG_SUPPORTFLAG_85HZ | /* refresh rate = 85 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1024, 768, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0400, 0x0400, 0x0430, 0x0490, 0x0560, 0x0560, /* horizontal timings */ + 0x0300, 0x0300, 0x0301, 0x0304, 0x0328, 0x0328, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (94L << 16) | ((5000L * 65536L) / 10000L), /* freq = 94.50 MHz */ + }, + + { VG_SUPPORTFLAG_90HZ | /* refresh rate = 90 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1024, 768, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0400, 0x0400, 0x0440, 0x04B0, 0x0560, 0x0560, /* horizontal timings */ + 0x0300, 0x0300, 0x0301, 0x0304, 0x0329, 0x0329, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (100L << 16) | ((1870L * 65536L) / 10000L), /* freq = 100.187 MHz */ + }, + + { VG_SUPPORTFLAG_100HZ | /* refresh rate = 100 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1024, 768, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0400, 0x0400, 0x0448, 0x04B8, 0x0570, 0x0570, /* horizontal timings */ + 0x0300, 0x0300, 0x0301, 0x0304, 0x032E, 0x032E, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (113L << 16) | ((3100L * 65536L) / 10000L), /* freq = 113.31 MHz */ + }, + + /* 1024x768 PANEL */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_PANEL, /* Panel Mode. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + VG_MODEFLAG_PANELOUT | /* Panel output. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC, /* negative syncs */ + 1024, 768, /* No scaling. */ + 1024, 768, /* 1024x768 active. */ + 1024, 768, /* 1024x768 panel */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0400, 0x0400, 0x0418, 0x04A0, 0x0540, 0x0540, /* horizontal timings */ + 0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (65L << 16) | ((0000L * 65536L) / 10000L), /* freq = 65.00 MHz */ + }, + + /* 1152x864 */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1152, 864, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0480, 0x0480, 0x04C0, 0x0538, 0x05F0, 0x05F0, /* horizontal timings */ + 0x0360, 0x0360, 0x0361, 0x0364, 0x037F, 0x037F, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (81L << 16) | ((6000L * 65536L) / 10000L), /* freq = 81.60 MHz */ + }, + + { VG_SUPPORTFLAG_70HZ | /* refresh rate = 70 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1152, 864, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0480, 0x0480, 0x04C8, 0x0540, 0x0600, 0x0600, /* horizontal timings */ + 0x0360, 0x0360, 0x0368, 0x036B, 0x038B, 0x038B, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (97L << 16) | ((5200L * 65536L) / 10000L), /* freq = 97.52 MHz */ + }, + + { VG_SUPPORTFLAG_72HZ | /* refresh rate = 72 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1152, 864, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0480, 0x0480, 0x04C8, 0x0548, 0x0610, 0x0610, /* horizontal timings */ + 0x0360, 0x0360, 0x0367, 0x036A, 0x038B, 0x038B, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (101L << 16) | ((4200L * 65536L) / 10000L), /* freq = 101.42 MHz */ + }, + + { VG_SUPPORTFLAG_75HZ | /* refresh rate = 75 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1152, 864, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0480, 0x0480, 0x04C0, 0x0540, 0x0640, 0x0640, /* horizontal timings */ + 0x0360, 0x0360, 0x0361, 0x0364, 0x0384, 0x0384, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (108L << 16) | ((0000L * 65536L) / 10000L), /* freq = 108.00 MHz */ + }, + + { VG_SUPPORTFLAG_85HZ | /* refresh rate = 85 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1152, 864, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0480, 0x0480, 0x04C8, 0x0548, 0x0610, 0x0610, /* horizontal timings */ + 0x0360, 0x0360, 0x0363, 0x0366, 0x038B, 0x038B, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (119L << 16) | ((6500L * 65536L) / 10000L), /* freq = 119.65 MHz */ + }, + + { VG_SUPPORTFLAG_90HZ | /* refresh rate = 90 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1152, 864, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0480, 0x0480, 0x04D0, 0x0550, 0x0620, 0x0620, /* horizontal timings */ + 0x0360, 0x0360, 0x0369, 0x036C, 0x0396, 0x0396, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (129L << 16) | ((6000L * 65536L) / 10000L), /* freq = 129.60 MHz */ + }, + + { VG_SUPPORTFLAG_100HZ | /* refresh rate = 100 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1152, 864, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0480, 0x0480, 0x04D0, 0x0550, 0x0620, 0x0620, /* horizontal timings */ + 0x0360, 0x0360, 0x0363, 0x0366, 0x0396, 0x0396, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (144L << 16) | ((0000L * 65536L) / 10000L), /* freq = 144.00 MHz */ + }, + + /* 1152x864 PANEL */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_PANEL, /* Panel Mode. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + VG_MODEFLAG_PANELOUT | /* Panel output. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC, /* negative syncs */ + 1152, 864, /* No scaling. */ + 1152, 864, /* 1152x864 active. */ + 1152, 864, /* 1152x864 panel. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0480, 0x0480, 0x04C0, 0x0538, 0x05F0, 0x05F0, /* horizontal timings */ + 0x0360, 0x0360, 0x0361, 0x0364, 0x037F, 0x037F, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (81L << 16) | ((6000L * 65536L) / 10000L), /* freq = 81.60 MHz */ + }, + + /* 1280x1024 */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1280, 1024, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0500, 0x0500, 0x0530, 0x05A0, 0x0698, 0x0698, /* horizontal timings */ + 0x0400, 0x0400, 0x0401, 0x0404, 0x042A, 0x042A, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (108L << 16) | ((0000L * 65536L) / 10000L), /* freq = 108.00 MHz */ + }, + + { VG_SUPPORTFLAG_70HZ | /* refresh rate = 70 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1280, 1024, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0500, 0x0500, 0x0558, 0x05E0, 0x06C0, 0x06C0, /* horizontal timings */ + 0x0400, 0x0400, 0x0406, 0x0409, 0x042F, 0x042F, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (129L << 16) | ((6000L * 65536L) / 10000L), /* freq = 129.60 MHz */ + }, + + { VG_SUPPORTFLAG_72HZ | /* refresh rate = 72 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1280, 1024, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0500, 0x0500, 0x0558, 0x05E0, 0x06C0, 0x06C0, /* horizontal timings */ + 0x0400, 0x0400, 0x0407, 0x040A, 0x0431, 0x0431, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (133L << 16) | ((5000L * 65536L) / 10000L), /* freq = 133.50 MHz */ + }, + + { VG_SUPPORTFLAG_75HZ | /* refresh rate = 75 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1280, 1024, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0500, 0x0500, 0x0510, 0x05A0, 0x0698, 0x0698, /* horizontal timings */ + 0x0400, 0x0400, 0x0401, 0x0404, 0x042A, 0x042A, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (135L << 16) | ((0000L * 65536L) / 10000L), /* freq = 135.0 MHz */ + }, + + { VG_SUPPORTFLAG_85HZ | /* refresh rate = 85 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1280, 1024, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0500, 0x0500, 0x0540, 0x05E0, 0x06C0, 0x06C0, /* horizontal timings */ + 0x0400, 0x0400, 0x0401, 0x0404, 0x0430, 0x0430, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (157L << 16) | ((5000L * 65536L) / 10000L), /* freq = 157.5 MHz */ + }, + + { VG_SUPPORTFLAG_90HZ | /* refresh rate = 90 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1280, 1024, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0500, 0x0500, 0x0560, 0x05F0, 0x06E0, 0x06E0, /* horizontal timings */ + 0x0400, 0x0400, 0x040C, 0x040F, 0x0442, 0x0442, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (172L << 16) | ((8000L * 65536L) / 10000L), /* freq = 172.80 MHz */ + }, + + { VG_SUPPORTFLAG_100HZ | /* refresh rate = 100 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + 0, + 1280, 1024, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0500, 0x0500, 0x0560, 0x05F0, 0x06E0, 0x06E0, /* horizontal timings */ + 0x0400, 0x0400, 0x0406, 0x0409, 0x0442, 0x0442, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (192L << 16) | ((0000L * 65536L) / 10000L), /* freq = 192.00 MHz */ + }, + + /* 1280x1024 PANEL */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_PANEL, /* Panel Mode. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + VG_MODEFLAG_PANELOUT | /* Panel output. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC, /* negative syncs */ + 1280, 1024, /* No scaling. */ + 1280, 1024, /* 1280x1024 active. */ + 1280, 1024, /* 1280x1024 panel */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0500, 0x0500, 0x0530, 0x05A0, 0x0698, 0x0698, /* horizontal timings */ + 0x0400, 0x0400, 0x0401, 0x0404, 0x042A, 0x042A, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (108L << 16) | ((0000L * 65536L) / 10000L), /* freq = 108.00 MHz */ + }, + + /* 1600 x 1200 */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + 0, + 1600, 1200, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (162L << 16) | ((0000L * 65536L) / 10000L), /* freq = 162.0 MHz */ + }, + + { VG_SUPPORTFLAG_70HZ | /* refresh rate = 70 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + 0, + 1600, 1200, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (189L << 16) | ((0000L * 65536L) / 10000L), /* freq = 189.0 MHz */ + }, + + { VG_SUPPORTFLAG_72HZ | /* refresh rate = 72 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + 0, + 1600, 1200, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0640, 0x0640, 0x06B0, 0x0760, 0x0880, 0x0880, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04BD, 0x04C0, 0x04EF, 0x04EF, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (198L << 16) | ((0000L * 65536L) / 10000L), /* freq = 198.0 MHz */ + }, + + { VG_SUPPORTFLAG_75HZ | /* refresh rate = 75 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + 0, + 1600, 1200, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (202L << 16) | ((5000L * 65536L) / 10000L), /* freq = 202.5 MHz */ + }, + + { VG_SUPPORTFLAG_85HZ | /* refresh rate = 85 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + 0, + 1600, 1200, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (229L << 16) | ((5000L * 65536L) / 10000L), /* freq = 229.5 MHz */ + }, + + { VG_SUPPORTFLAG_90HZ | /* refresh rate = 90 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + 0, + 1600, 1200, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0640, 0x0640, 0x06C0, 0x0770, 0x08A0, 0x08A0, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04F0, 0x04F0, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (251L << 16) | ((1820L * 65536L) / 10000L), /* freq = 251.182 MHz */ + }, + + { VG_SUPPORTFLAG_100HZ | /* refresh rate = 100 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + 0, + 1600, 1200, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0640, 0x0640, 0x06C0, 0x0770, 0x08A0, 0x08A0, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04F7, 0x04F7, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (280L << 16) | ((6400L * 65536L) / 10000L), /* freq = 280.64 MHz */ + }, + + /* 1600 x 1200 PANEL */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_PANEL, /* Panel Mode. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + VG_MODEFLAG_PANELOUT | /* Panel output. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC, /* negative syncs */ + 1600, 1200, /* No scaling. */ + 1600, 1200, /* 1600x1200 Active. */ + 1600, 1200, /* 1600x1200 Panel. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (162L << 16) | ((0000L * 65536L) / 10000L), /* freq = 162.0 MHz */ + }, + + /* 1920x1440 */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + 0, + 1920, 1440, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0780, 0x0780, 0x0800, 0x08D0, 0x0A28, 0x0A28, /* horizontal timings */ + 0x05A0, 0x05A0, 0x05A1, 0x05A4, 0x05DC, 0x05DC, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (234L << 16) | ((0000L * 65536L) / 10000L), /* freq = 234.0 MHz */ + }, + + { VG_SUPPORTFLAG_70HZ | /* refresh rate = 70 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + 0, + 1920, 1440, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0780, 0x0780, 0x0818, 0x08E8, 0x0A50, 0x0A50, /* horizontal timings */ + 0x05A0, 0x05A0, 0x05A8, 0x05AB, 0x05E2, 0x05E2, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (278L << 16) | ((4000L * 65536L) / 10000L), /* freq = 278.4 MHz */ + }, + + { VG_SUPPORTFLAG_72HZ | /* refresh rate = 70 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + 0, + 1920, 1440, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0780, 0x0780, 0x0818, 0x08E8, 0x0A50, 0x0A50, /* horizontal timings */ + 0x05A0, 0x05A0, 0x05A4, 0x05A7, 0x05EB, 0x05EB, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (288L << 16) | ((0000L * 65536L) / 10000L), /* freq = 288.0 MHz */ + }, + + { VG_SUPPORTFLAG_75HZ | /* refresh rate = 75 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + 0, + 1920, 1440, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0780, 0x0780, 0x0810, 0x08F0, 0x0A50, 0x0A50, /* horizontal timings */ + 0x05A0, 0x05A0, 0x05A1, 0x05A4, 0x05DC, 0x05DC, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (297L << 16) | ((0000L * 65536L) / 10000L), /* freq = 297.0 MHz */ + }, + + { VG_SUPPORTFLAG_85HZ | /* refresh rate = 85 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP, /* All BPP supported. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + 0, + 1920, 1440, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0780, 0x0780, 0x0818, 0x08F0, 0x0A60, 0x0A60, /* horizontal timings */ + 0x05A0, 0x05A0, 0x05A1, 0x05A4, 0x05E8, 0x05E8, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings */ + (341L << 16) | ((3490L * 65536L) / 10000L), /* freq = 341.35 MHz */ + }, + +/*-------------------------------*/ +/* PREDEFINED TV TIMINGS */ +/*-------------------------------*/ + + /* 720 x 480i NTSC */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_NTSC | /* NTSC Mode. */ + VG_SUPPORTFLAG_ADV7171 | VG_SUPPORTFLAG_SAA7127 | + VG_SUPPORTFLAG_ADV7300 | VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_INTERLACED | VG_MODEFLAG_TVOUT | /* Interlaced TV output */ + VG_MODEFLAG_HALFCLOCK | /* DotPLL = 1/2 VOP */ + VG_MODEFLAG_INT_FLICKER, /* Flicker Filter Out */ + 720, 480, /* No downscaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x02D0, 0x02D0, 0x02E1, 0x0320, 0x035A, 0x035A, /* horizontal timings */ + 0x00F0, 0x00F0, 0x00F4, 0x00F8, 0x0107, 0x0107, /* vertical timings */ + 0x00F0, 0x00F0, 0x00F4, 0x00F8, 0x0106, 0x0106, /* Even field timings */ + (27L << 16) | ((0000L * 65536L) / 10000L), /* freq = 27.0 MHz */ + }, + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_NTSC | /* NTSC Mode. */ + VG_SUPPORTFLAG_FS454 | VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC | /* negative syncs */ + VG_MODEFLAG_PANELOUT | VG_MODEFLAG_INVERT_SHFCLK, /* TFT Output. */ + 640, 480, /* No downscaling. */ + 640, 480, /* 640x480 active. */ + 640, 480, /* 640x480 panel. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0280, 0x0280, 0x0333, 0x0373, 0x03A8, 0x03A8, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01F5, 0x01F7, 0x020D, 0x020D, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings. */ + (25L << 16) | ((1750L * 65536L) / 10000L), /* freq = 25.175 MHz */ + }, + + /* 800 x 600 NTSC */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_8X6_NTSC | /* 800x600 NTSC. */ + VG_SUPPORTFLAG_FS454 | VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC | /* negative syncs */ + VG_MODEFLAG_PANELOUT | VG_MODEFLAG_INVERT_SHFCLK, /* Panel output */ + 800, 600, /* No downscaling. */ + 800, 600, /* 800x600 active. */ + 800, 600, /* 800x600 active. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0320, 0x0320, 0x03A7, 0x03E7, 0x03F0, 0x03F0, /* horizontal timings */ + 0x0258, 0x0258, 0x026A, 0x0272, 0x028A, 0x028A, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings. */ + (40L << 16) | ((0000L * 65536L) / 10000L), /* freq = 40.000 MHz */ + }, + + /* 1024 x 768 NTSC */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_10X7_NTSC | /* 1024x768 NTSC. */ + VG_SUPPORTFLAG_FS454 | VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_AVG_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC | /* negative syncs */ + VG_MODEFLAG_PANELOUT | VG_MODEFLAG_INVERT_SHFCLK, /* Panel output */ + 1024, 768, /* No downscaling. */ + 1024, 768, /* 1024x768 active. */ + 1024, 768, /* 1024x768 active. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0400, 0x0400, 0x0490, 0x04D0, 0x04E0, 0x04E0, /* horizontal timings */ + 0x0300, 0x0300, 0x031B, 0x031D, 0x0339, 0x0339, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings. */ + (65L << 16) | ((0000L * 65536L) / 10000L), /* freq = 65.00 MHz */ + }, + + /* 720 x 576i PAL */ + + { VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_PAL | /* PAL Mode. */ + VG_SUPPORTFLAG_ADV7171 | VG_SUPPORTFLAG_SAA7127 | + VG_SUPPORTFLAG_ADV7300 | VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_TVOUT | VG_MODEFLAG_INTERLACED | /* Interlaced TV out. */ + VG_MODEFLAG_HALFCLOCK | /* DotPLL = 1/2 VOP */ + VG_MODEFLAG_INT_FLICKER, /* Flicker Filter Out */ + 720, 576, /* No downscaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x02D0, 0x02D0, 0x02E4, 0x0324, 0x0360, 0x0360, /* horizontal timings */ + 0x0120, 0x0120, 0x0123, 0x0127, 0x0139, 0x0139, /* vertical timings */ + 0x0120, 0x0120, 0x0123, 0x0127, 0x0138, 0x0138, /* Even timings */ + (27L << 16) | ((0000L * 65536L) / 10000L), /* freq = 27.0 MHz */ + }, + + { VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_PAL | /* PAL Mode. */ + VG_SUPPORTFLAG_FS454 | VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC | /* negative syncs */ + VG_MODEFLAG_PANELOUT | VG_MODEFLAG_INVERT_SHFCLK, /* Panel output. */ + 640, 480, /* No downscaling. */ + 640, 480, /* No mode dimensions. */ + 640, 480, /* 640x480 active. */ + 0, 0, 0, 0, 0, /* 640x480 panel. */ + 0x0280, 0x0280, 0x030F, 0x034F, 0x0360, 0x0360, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01F5, 0x01F7, 0x020D, 0x020D, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings. */ + (25L << 16) | ((1750L * 65536L) / 10000L), /* freq = 25.175 MHz */ + }, + + /* 800 x 600 PAL */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_8X6_PAL | /* 800x600 PAL. */ + VG_SUPPORTFLAG_FS454 | VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC | /* negative syncs */ + VG_MODEFLAG_PANELOUT | VG_MODEFLAG_INVERT_SHFCLK, /* Panel output */ + 800, 600, /* No downscaling. */ + 800, 600, /* 800x600 active. */ + 800, 600, /* 800x600 active. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0320, 0x0320, 0x03A7, 0x03E7, 0x03F0, 0x03F0, /* horizontal timings */ + 0x0258, 0x0258, 0x0270, 0x0272, 0x028A, 0x028A, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings. */ + (40L << 16) | ((0000L * 65536L) / 10000L), /* freq = 40.000 MHz */ + }, + + /* 1024 x 768 PAL */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_10X7_PAL | /* 1024x768 NTSC. */ + VG_SUPPORTFLAG_FS454 | VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_AVG_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_NEG_HSYNC | VG_MODEFLAG_NEG_VSYNC | /* negative syncs */ + VG_MODEFLAG_PANELOUT | VG_MODEFLAG_INVERT_SHFCLK, /* Panel output */ + 1024, 768, /* No downscaling. */ + 1024, 768, /* 1024x768 active. */ + 1024, 768, /* 1024x768 active. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0400, 0x0400, 0x0490, 0x04d0, 0x04e0, 0x04e0, /* horizontal timings */ + 0x0300, 0x0300, 0x031b, 0x031d, 0x0339, 0x0339, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings. */ + (65L << 16) | ((0000L * 65536L) / 10000L), /* freq = 65.00 MHz */ + }, + + /* 720 x 480p HDTV */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_480P | /* 720x480P. */ + VG_SUPPORTFLAG_ADV7300 | VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_TVOUT, /* Progressive TV out. */ + 720, 480, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x02D0, 0x02D0, 0x02E0, 0x0328, 0x035A, 0x035A, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01E1, 0x01E3, 0x020D, 0x020D, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings. */ + (27L << 16) | ((0000L * 65536L) / 10000L), /* freq = 27.0 MHz */ + }, + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_480P | /* 720x480P. */ + VG_SUPPORTFLAG_FS454 | VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_LOW_BAND | /* Low bandwidth mode. */ + VG_MODEFLAG_PANELOUT | VG_MODEFLAG_INVERT_SHFCLK, /* Panel output. */ + 720, 480, /* No scaling. */ + 720, 480, /* 720x480 active. */ + 720, 480, /* 720x480 panel. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x02D0, 0x02D0, 0x02E3, 0x0323, 0x035A, 0x035A, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01E4, 0x01EA, 0x020D, 0x020D, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings. */ + (27L << 16) | ((0000L * 65536L) / 10000L), /* freq = 27.0 MHz */ + }, + + /* 1280x720p HDTV */ + + { VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_720P | /* 1280x720P */ + VG_SUPPORTFLAG_ADV7300 | VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + VG_MODEFLAG_TVOUT, /* Progressive TV out */ + 1280, 720, /* No scaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0500, 0x0500, 0x0546, 0x0596, 0x0672, 0x0672, /* horizontal timings */ + 0x02D0, 0x02D0, 0x02D3, 0x02D8, 0x02EE, 0x02EE, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* even timings */ + (74L << 16) | ((2500L * 65536L) / 10000L), /* freq = 74.25 MHz */ + }, + + { VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_720P | /* 1280x720P */ + VG_SUPPORTFLAG_FS454 | VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_AVG_BAND | /* Avg bandwidth mode. */ + VG_MODEFLAG_PANELOUT | VG_MODEFLAG_INVERT_SHFCLK, /* Panel output. */ + 1280, 720, /* No scaling. */ + 1280, 720, /* 1280x720 active. */ + 1280, 720, /* 1280x720 panel. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0500, 0x0500, 0x0547, 0x0597, 0x0672, 0x0672, /* horizontal timings */ + 0x02D0, 0x02D0, 0x02D4, 0x02D9, 0x02EE, 0x02EE, /* vertical timings */ + 0, 0, 0, 0, 0, 0, /* No even timings. */ + (74L << 16) | ((2500L * 65536L) / 10000L), /* freq = 74.25 MHz */ + }, + + /* 1920x1080i HDTV */ + + { VG_SUPPORTFLAG_60HZ | /* refresh rate = 60 */ + VG_SUPPORTFLAG_8BPP | VG_SUPPORTFLAG_12BPP | + VG_SUPPORTFLAG_15BPP | VG_SUPPORTFLAG_16BPP | + VG_SUPPORTFLAG_24BPP | VG_SUPPORTFLAG_32BPP | /* All BPP supported. */ + VG_SUPPORTFLAG_1080I | /* 1920x1080i Mode. */ + VG_SUPPORTFLAG_ADV7300 | VG_SUPPORTFLAG_FS454 | + VG_SUPPORTFLAG_TVOUT, /* TV Mode. */ + VG_MODEFLAG_HIGH_BAND | /* High bandwidth mode. */ + VG_MODEFLAG_INTERLACED | VG_MODEFLAG_TVOUT | /* Interlaced TV output */ + VG_MODEFLAG_INT_ADDRESS | VG_MODEFLAG_INVERT_SHFCLK, /* Interlaced addressing*/ + 1920, 1080, /* 2:1 downscaling. */ + 0, 0, /* No mode dimensions. */ + 0, 0, /* No panel dimensions. */ + 0, 0, 0, 0, 0, /* No panel registers */ + 0x0780, 0x0780, 0x07AD, 0x0805, 0x0898, 0x0898, /* horizontal timings */ + 0x021C, 0x021C, 0x021E, 0x0226, 0x0233, 0x0233, /* vertical timings */ + 0x021C, 0x021C, 0x021E, 0x0226, 0x0232, 0x0232, /* even field timings */ + (74L << 16) | ((2500L * 65536L) / 10000L), /* freq = 74.25 MHz */ + }, +}; + +#define NUM_CIMARRON_DISPLAY_MODES sizeof(CimarronDisplayModes) / sizeof(VG_DISPLAY_MODE) + +/*-----------------------------------*/ +/* PREDEFINED PLL FREQUENCIES */ +/*-----------------------------------*/ + +PLL_FREQUENCY CimarronPLLFrequencies[] = +{ + { 0x000031AC, (24L << 16) | ((9230L * 65536L) / 10000L) }, /* 24.9230, - 4,27,13 */ + { 0x0000215D, (25L << 16) | ((1750L * 65536L) / 10000L) }, /* 25.1750, - 3,22,14 */ + { 0x00001087, (27L << 16) | ((0000L * 65536L) / 10000L) }, /* 27.0000, - 2, 9, 8 */ + { 0x0000216C, (28L << 16) | ((3220L * 65536L) / 10000L) }, /* 28.3220, - 3,23,13 */ + { 0x0000218D, (28L << 16) | ((5600L * 65536L) / 10000L) }, /* 28.5600, - 3,25,14 */ + { 0x000010C9, (31L << 16) | ((2000L * 65536L) / 10000L) }, /* 31.2000, - 2,13,10 */ + { 0x00003147, (31L << 16) | ((5000L * 65536L) / 10000L) }, /* 31.5000, - 4,21, 8 */ + { 0x000010A7, (33L << 16) | ((320L * 65536L) / 10000L) }, /* 33.0320, - 2,11, 8 */ + { 0x00002159, (35L << 16) | ((1120L * 65536L) / 10000L) }, /* 35.1120, - 3,22,10 */ + { 0x00004249, (35L << 16) | ((5000L * 65536L) / 10000L) }, /* 35.5000, - 5,37,10 */ + { 0x00000057, (36L << 16) | ((0000L * 65536L) / 10000L) }, /* 36.0000, - 1, 6, 8 */ + { 0x0000219A, (37L << 16) | ((8890L * 65536L) / 10000L) }, /* 37.8890, - 3,26,11 */ + { 0x00002158, (39L << 16) | ((1680L * 65536L) / 10000L) }, /* 39.1680, - 3,22, 9 */ + { 0x00000045, (40L << 16) | ((0000L * 65536L) / 10000L) }, /* 40.0000, - 1, 5, 6 */ + { 0x00000089, (43L << 16) | ((1630L * 65536L) / 10000L) }, /* 43.1630, - 1, 9,10 */ + { 0x000010E7, (44L << 16) | ((9000L * 65536L) / 10000L) }, /* 44.9000, - 2,15, 8 */ + { 0x00002136, (45L << 16) | ((7200L * 65536L) / 10000L) }, /* 45.7200, - 3,20, 7 */ + { 0x00003207, (49L << 16) | ((5000L * 65536L) / 10000L) }, /* 49.5000, - 4,33, 8 */ + { 0x00002187, (50L << 16) | ((0000L * 65536L) / 10000L) }, /* 50.0000, - 3,25, 8 */ + { 0x00004286, (56L << 16) | ((2500L * 65536L) / 10000L) }, /* 56.2500, - 5,41, 7 */ + { 0x000010E5, (60L << 16) | ((650L * 65536L) / 10000L) }, /* 60.0650, - 2,15, 6 */ + { 0x00004214, (65L << 16) | ((0000L * 65536L) / 10000L) }, /* 65.0000, - 5,34, 5 */ + { 0x00001105, (68L << 16) | ((1790L * 65536L) / 10000L) }, /* 68.1790, - 2,17, 6 */ + { 0x000031E4, (74L << 16) | ((2500L * 65536L) / 10000L) }, /* 74.2500, - 4,31, 5 */ + { 0x00003183, (75L << 16) | ((0000L * 65536L) / 10000L) }, /* 75.0000, - 4,25, 4 */ + { 0x00004284, (78L << 16) | ((7500L * 65536L) / 10000L) }, /* 78.7500, - 5,41, 5 */ + { 0x00001104, (81L << 16) | ((6000L * 65536L) / 10000L) }, /* 81.6000, - 2,17, 5 */ + { 0x00006363, (94L << 16) | ((5000L * 65536L) / 10000L) }, /* 94.5000, - 7,55, 4 */ + { 0x00005303, (97L << 16) | ((5200L * 65536L) / 10000L) }, /* 97.5200, - 6,49, 4 */ + { 0x00002183, (100L << 16) | ((1870L * 65536L) / 10000L) }, /* 100.187, - 3,25, 4 */ + { 0x00002122, (101L << 16) | ((4200L * 65536L) / 10000L) }, /* 101.420, - 3,19, 3 */ + { 0x00001081, (108L << 16) | ((0000L * 65536L) / 10000L) }, /* 108.00, - 2, 9, 2 */ + { 0x00006201, (113L << 16) | ((3100L * 65536L) / 10000L) }, /* 113.31, - 7,33, 2 */ + { 0x00000041, (119L << 16) | ((6500L * 65536L) / 10000L) }, /* 119.65, - 1, 5, 2 */ + { 0x000041A1, (129L << 16) | ((6000L * 65536L) / 10000L) }, /* 129.60, - 5,27, 2 */ + { 0x00002182, (133L << 16) | ((5000L * 65536L) / 10000L) }, /* 133.50, - 3,25, 3 */ + { 0x000041B1, (135L << 16) | ((0000L * 65536L) / 10000L) }, /* 135.00, - 5,28, 2 */ + { 0x00000051, (144L << 16) | ((0000L * 65536L) / 10000L) }, /* 144.00, - 1, 6, 2 */ + { 0x000041E1, (148L << 16) | ((5000L * 65536L) / 10000L) }, /* 148.50, - 5,31, 2 */ + { 0x000062D1, (157L << 16) | ((5000L * 65536L) / 10000L) }, /* 157.50, - 7,46, 2 */ + { 0x000031A1, (162L << 16) | ((0000L * 65536L) / 10000L) }, /* 162.00, - 4,27, 2 */ + { 0x00000061, (169L << 16) | ((2030L * 65536L) / 10000L) }, /* 169.203, - 1, 7, 2 */ + { 0x00004231, (172L << 16) | ((8000L * 65536L) / 10000L) }, /* 172.800, - 5,36, 2 */ + { 0x00002151, (175L << 16) | ((5000L * 65536L) / 10000L) }, /* 175.50, - 3,22, 2 */ + { 0x000052E1, (189L << 16) | ((0000L * 65536L) / 10000L) }, /* 189.00, - 6,47, 2 */ + { 0x00000071, (192L << 16) | ((0000L * 65536L) / 10000L) }, /* 192.00, - 1, 8, 2 */ + { 0x00003201, (198L << 16) | ((0000L * 65536L) / 10000L) }, /* 198.00, - 4,33, 2 */ + { 0x00004291, (202L << 16) | ((5000L * 65536L) / 10000L) }, /* 202.50, - 5,42, 2 */ + { 0x00001101, (204L << 16) | ((7500L * 65536L) / 10000L) }, /* 204.75, - 2,17, 2 */ + { 0x00007481, (218L << 16) | ((2500L * 65536L) / 10000L) }, /* 218.25, - 8,73, 2 */ + { 0x00004170, (229L << 16) | ((5000L * 65536L) / 10000L) }, /* 229.50, - 5,24, 1 */ + { 0x00006210, (234L << 16) | ((0000L * 65536L) / 10000L) }, /* 234.00, - 7,34, 1 */ + { 0x00003140, (251L << 16) | ((1820L * 65536L) / 10000L) }, /* 251.182, - 4,21, 1 */ + { 0x00006250, (261L << 16) | ((0000L * 65536L) / 10000L) }, /* 261.00, - 7,38, 1 */ + { 0x000041C0, (278L << 16) | ((4000L * 65536L) / 10000L) }, /* 278.40, - 5,29, 1 */ + { 0x00005220, (280L << 16) | ((6400L * 65536L) / 10000L) }, /* 280.64, - 6,35, 1 */ + { 0x00000050, (288L << 16) | ((0000L * 65536L) / 10000L) }, /* 288.00, - 1, 6, 1 */ + { 0x000041E0, (297L << 16) | ((0000L * 65536L) / 10000L) }, /* 297.00, - 5,31, 1 */ + { 0x00002130, (320L << 16) | ((2070L * 65536L) / 10000L) }, /* 320.207, - 3,20, 1 */ + { 0x00006310, (341L << 16) | ((3490L * 65536L) / 10000L) } /* 341.349, - 7,50, 1 */ +}; + +#define NUM_CIMARRON_PLL_FREQUENCIES sizeof(CimarronPLLFrequencies) / sizeof(PLL_FREQUENCY) + +/*-----------------------------------*/ +/* PREDEFINED FILTER COEFFICIENTS */ +/*-----------------------------------*/ + +unsigned long CimarronHorizontalGraphicsFilter[][2] = +{ + {0x1284A7D5, 0x000017D5 }, /* -43, 297, 296, -43, 5 */ + {0x12A497D7, 0x000013D6 }, /* -41, 293, 298, -42, 4 */ + {0x12D48BD7, 0x000013D6 }, /* -41, 290, 301, -42, 4 */ + {0x13147FD7, 0x000013D5 }, /* -41, 287, 305, -43, 4 */ + {0x133473D8, 0x000013D5 }, /* -40, 284, 307, -43, 4 */ + {0x136467D8, 0x000013D5 }, /* -40, 281, 310, -43, 4 */ + {0x13945FD8, 0x000013D4 }, /* -40, 279, 313, -44, 4 */ + {0x13B453D9, 0x000013D4 }, /* -39, 276, 315, -44, 4 */ + {0x13E447D9, 0x000013D4 }, /* -39, 273, 318, -44, 4 */ + {0x14143BDA, 0x000013D3 }, /* -38, 270, 321, -45, 4 */ + {0x143433DA, 0x000013D3 }, /* -38, 268, 323, -45, 4 */ + {0x146427DA, 0x000013D3 }, /* -38, 265, 326, -45, 4 */ + {0x14941BDB, 0x000013D2 }, /* -37, 262, 329, -46, 4 */ + {0x14C40FDB, 0x000013D2 }, /* -37, 259, 332, -46, 4 */ + {0x14F407DA, 0x000017D1 }, /* -38, 257, 335, -47, 5 */ + {0x1503FBDC, 0x000013D2 }, /* -36, 254, 336, -46, 4 */ + {0x1543F3DB, 0x000017D0 }, /* -37, 252, 340, -48, 5 */ + {0x1563E3DD, 0x000013D1 }, /* -35, 248, 342, -47, 4 */ + {0x1593D7DD, 0x000013D1 }, /* -35, 245, 345, -47, 4 */ + {0x15B3CFDD, 0x000013D1 }, /* -35, 243, 347, -47, 4 */ + {0x15E3C3DE, 0x000013D0 }, /* -34, 240, 350, -48, 4 */ + {0x1613B7DE, 0x000013D0 }, /* -34, 237, 353, -48, 4 */ + {0x1633ABDF, 0x000013D0 }, /* -33, 234, 355, -48, 4 */ + {0x16639FDF, 0x000013D0 }, /* -33, 231, 358, -48, 4 */ + {0x167397E0, 0x000013D0 }, /* -32, 229, 359, -48, 4 */ + {0x16B38BE0, 0x000013CF }, /* -32, 226, 363, -49, 4 */ + {0x16E383DF, 0x000017CE }, /* -33, 224, 366, -50, 5 */ + {0x170373E1, 0x000013CF }, /* -31, 220, 368, -49, 4 */ + {0x17236BE1, 0x000013CF }, /* -31, 218, 370, -49, 4 */ + {0x17435FE2, 0x000013CF }, /* -30, 215, 372, -49, 4 */ + {0x177353E2, 0x000013CF }, /* -30, 212, 375, -49, 4 */ + {0x17B34BE1, 0x000017CD }, /* -31, 210, 379, -51, 5 */ + {0x17C33FE3, 0x000013CE }, /* -29, 207, 380, -50, 4 */ + {0x17F333E3, 0x000013CE }, /* -29, 204, 383, -50, 4 */ + {0x181327E4, 0x000013CE }, /* -28, 201, 385, -50, 4 */ + {0x18431FE3, 0x000017CD }, /* -29, 199, 388, -51, 5 */ + {0x186313E4, 0x000013CE }, /* -28, 196, 390, -50, 4 */ + {0x188307E5, 0x000013CE }, /* -27, 193, 392, -50, 4 */ + {0x18B2FBE5, 0x000013CE }, /* -27, 190, 395, -50, 4 */ + {0x18C2F3E6, 0x000013CE }, /* -26, 188, 396, -50, 4 */ + {0x18F2E7E6, 0x000013CE }, /* -26, 185, 399, -50, 4 */ + {0x1912DBE7, 0x000013CE }, /* -25, 182, 401, -50, 4 */ + {0x1952D3E6, 0x000017CC }, /* -26, 180, 405, -52, 5 */ + {0x1972CBE6, 0x000017CC }, /* -26, 178, 407, -52, 5 */ + {0x1992BFE7, 0x000017CC }, /* -25, 175, 409, -52, 5 */ + {0x19C2B3E7, 0x000017CC }, /* -25, 172, 412, -52, 5 */ + {0x19D2A7E9, 0x000013CD }, /* -23, 169, 413, -51, 4 */ + {0x1A029FE8, 0x000017CC }, /* -24, 167, 416, -52, 5 */ + {0x1A1293E9, 0x000013CE }, /* -23, 164, 417, -50, 4 */ + {0x1A3287EA, 0x000013CE }, /* -22, 161, 419, -50, 4 */ + {0x1A627FE9, 0x000017CD }, /* -23, 159, 422, -51, 5 */ + {0x1A7273EB, 0x000013CE }, /* -21, 156, 423, -50, 4 */ + {0x1AA267EB, 0x000013CE }, /* -21, 153, 426, -50, 4 */ + {0x1AC25FEB, 0x000013CE }, /* -21, 151, 428, -50, 4 */ + {0x1AE253EC, 0x000013CE }, /* -20, 148, 430, -50, 4 */ + {0x1B124BEB, 0x000017CD }, /* -21, 146, 433, -51, 5 */ + {0x1B223FED, 0x000013CE }, /* -19, 143, 434, -50, 4 */ + {0x1B5237EC, 0x000017CD }, /* -20, 141, 437, -51, 5 */ + {0x1B622BED, 0x000013CF }, /* -19, 138, 438, -49, 4 */ + {0x1B821FEE, 0x000013CF }, /* -18, 135, 440, -49, 4 */ + {0x1BA217EE, 0x000013CF }, /* -18, 133, 442, -49, 4 */ + {0x1BC20BEF, 0x000013CF }, /* -17, 130, 444, -49, 4 */ + {0x1BE203EF, 0x000013CF }, /* -17, 128, 446, -49, 4 */ + {0x1C01FBEE, 0x000017CF }, /* -18, 126, 448, -49, 5 */ + {0x1C11EFF0, 0x000013D0 }, /* -16, 123, 449, -48, 4 */ + {0x1C41E7EF, 0x000017CF }, /* -17, 121, 452, -49, 5 */ + {0x1C61DFEF, 0x000017CF }, /* -17, 119, 454, -49, 5 */ + {0x1C61D3F1, 0x000013D1 }, /* -15, 116, 454, -47, 4 */ + {0x1C91CBF0, 0x000017D0 }, /* -16, 114, 457, -48, 5 */ + {0x1CA1BFF2, 0x000013D1 }, /* -14, 111, 458, -47, 4 */ + {0x1CC1B3F2, 0x000013D2 }, /* -14, 108, 460, -46, 4 */ + {0x1CE1AFF1, 0x000017D1 }, /* -15, 107, 462, -47, 5 */ + {0x1CF1A3F3, 0x000013D2 }, /* -13, 104, 463, -46, 4 */ + {0x1D1197F3, 0x000013D3 }, /* -13, 101, 465, -45, 4 */ + {0x1D3197F2, 0x000013D2 }, /* -14, 101, 467, -46, 4 */ + {0x1D518BF3, 0x000013D2 }, /* -13, 98, 469, -46, 4 */ + {0x1D6183F3, 0x000013D3 }, /* -13, 96, 470, -45, 4 */ + {0x1D817BF3, 0x000013D3 }, /* -13, 94, 472, -45, 4 */ + {0x1D916FF4, 0x000013D4 }, /* -12, 91, 473, -44, 4 */ + {0x1DB167F4, 0x000013D4 }, /* -12, 89, 475, -44, 4 */ + {0x1DC15FF4, 0x000013D5 }, /* -12, 87, 476, -43, 4 */ + {0x1DE153F5, 0x000013D5 }, /* -11, 84, 478, -43, 4 */ + {0x1DF14BF5, 0x000013D6 }, /* -11, 82, 479, -42, 4 */ + {0x1E1143F5, 0x000013D6 }, /* -11, 80, 481, -42, 4 */ + {0x1E1137F7, 0x00000FD8 }, /* -9, 77, 481, -40, 3 */ + {0x1E3133F6, 0x000013D7 }, /* -10, 76, 483, -41, 4 */ + {0x1E412BF6, 0x000013D8 }, /* -10, 74, 484, -40, 4 */ + {0x1E611FF7, 0x000013D8 }, /* -9, 71, 486, -40, 4 */ + {0x1E7117F7, 0x000013D9 }, /* -9, 69, 487, -39, 4 */ + {0x1E810FF7, 0x000013DA }, /* -9, 67, 488, -38, 4 */ + {0x1E9107F8, 0x000013DA }, /* -8, 65, 489, -38, 4 */ + {0x1EA0FFF8, 0x000013DB }, /* -8, 63, 490, -37, 4 */ + {0x1EB0F3F9, 0x00000FDD }, /* -7, 60, 491, -35, 3 */ + {0x1ED0EFF8, 0x000013DC }, /* -8, 59, 493, -36, 4 */ + {0x1EE0E7F9, 0x00000FDD }, /* -7, 57, 494, -35, 3 */ + {0x1EF0DFF9, 0x00000FDE }, /* -7, 55, 495, -34, 3 */ + {0x1F00D7F9, 0x00000FDF }, /* -7, 53, 496, -33, 3 */ + {0x1F10CFFA, 0x00000FDF }, /* -6, 51, 497, -33, 3 */ + {0x1F20C7FA, 0x00000FE0 }, /* -6, 49, 498, -32, 3 */ + {0x1F20C3FA, 0x00000FE1 }, /* -6, 48, 498, -31, 3 */ + {0x1F30BBFA, 0x00000FE2 }, /* -6, 46, 499, -30, 3 */ + {0x1F40AFFB, 0x00000FE3 }, /* -5, 43, 500, -29, 3 */ + {0x1F50A7FB, 0x00000FE4 }, /* -5, 41, 501, -28, 3 */ + {0x1F60A3FB, 0x00000FE4 }, /* -5, 40, 502, -28, 3 */ + {0x1F709BFB, 0x00000FE5 }, /* -5, 38, 503, -27, 3 */ + {0x1F7093FC, 0x00000FE6 }, /* -4, 36, 503, -26, 3 */ + {0x1F808FFC, 0x00000BE7 }, /* -4, 35, 504, -25, 2 */ + {0x1F9087FC, 0x00000BE8 }, /* -4, 33, 505, -24, 2 */ + {0x1F9083FC, 0x00000BE9 }, /* -4, 32, 505, -23, 2 */ + {0x1FA077FD, 0x00000BEA }, /* -3, 29, 506, -22, 2 */ + {0x1FA073FD, 0x00000BEB }, /* -3, 28, 506, -21, 2 */ + {0x1FB06BFD, 0x00000BEC }, /* -3, 26, 507, -20, 2 */ + {0x1FC063FD, 0x00000BED }, /* -3, 24, 508, -19, 2 */ + {0x1FC05BFE, 0x00000BEE }, /* -2, 22, 508, -18, 2 */ + {0x1FC057FE, 0x00000BEF }, /* -2, 21, 508, -17, 2 */ + {0x1FD053FE, 0x000007F0 }, /* -2, 20, 509, -16, 1 */ + {0x1FD04BFE, 0x000007F2 }, /* -2, 18, 509, -14, 1 */ + {0x1FE043FE, 0x000007F3 }, /* -2, 16, 510, -13, 1 */ + {0x1FE03BFF, 0x000007F4 }, /* -1, 14, 510, -12, 1 */ + {0x1FE037FF, 0x000007F5 }, /* -1, 13, 510, -11, 1 */ + {0x1FE033FF, 0x000007F6 }, /* -1, 12, 510, -10, 1 */ + {0x1FF02BFF, 0x000007F7 }, /* -1, 10, 511, -9, 1 */ + {0x1FF027FF, 0x000003F9 }, /* -1, 9, 511, -7, 0 */ + {0x1FF01C00, 0x000003FA }, /* 0, 7, 511, -6, 0 */ + {0x1FF01800, 0x000003FB }, /* 0, 6, 511, -5, 0 */ + {0x1FF01400, 0x000003FC }, /* 0, 5, 511, -4, 0 */ + {0x1FF00C00, 0x000003FE }, /* 0, 3, 511, -2, 0 */ + {0x1FF00800, 0x000003FF }, /* 0, 2, 511, -1, 0 */ + {0x1FF00400, 0x00000000 }, /* 0, 1, 511, 0, 0 */ + {0x1FFFFC00, 0x00000002 }, /* 0, -1, 511, 2, 0 */ + {0x1FFFF800, 0x00000003 }, /* 0, -2, 511, 3, 0 */ + {0x1FFFF000, 0x00000005 }, /* 0, -4, 511, 5, 0 */ + {0x1FFFEC00, 0x00000006 }, /* 0, -5, 511, 6, 0 */ + {0x1FFFE800, 0x00000007 }, /* 0, -6, 511, 7, 0 */ + {0x1FFFE400, 0x000FFC09 }, /* 0, -7, 511, 9, -1 */ + {0x1FFFDC01, 0x000FFC0A }, /* 1, -9, 511, 10, -1 */ + {0x1FEFDC01, 0x000FFC0B }, /* 1, -9, 510, 11, -1 */ + {0x1FEFD401, 0x000FFC0D }, /* 1, -11, 510, 13, -1 */ + {0x1FEFD001, 0x000FFC0E }, /* 1, -12, 510, 14, -1 */ + {0x1FEFCC01, 0x000FF810 }, /* 1, -13, 510, 16, -2 */ + {0x1FDFCC01, 0x000FF811 }, /* 1, -13, 509, 17, -2 */ + {0x1FDFC401, 0x000FF813 }, /* 1, -15, 509, 19, -2 */ + {0x1FCFC002, 0x000FF814 }, /* 2, -16, 508, 20, -2 */ + {0x1FCFB802, 0x000FF816 }, /* 2, -18, 508, 22, -2 */ + {0x1FCFB402, 0x000FF418 }, /* 2, -19, 508, 24, -3 */ + {0x1FBFB402, 0x000FF419 }, /* 2, -19, 507, 25, -3 */ + {0x1FAFB002, 0x000FF41B }, /* 2, -20, 506, 27, -3 */ + {0x1FAFA802, 0x000FF41D }, /* 2, -22, 506, 29, -3 */ + {0x1F9FA802, 0x000FF01F }, /* 2, -22, 505, 31, -4 */ + {0x1F9FA402, 0x000FF020 }, /* 2, -23, 505, 32, -4 */ + {0x1F8FA002, 0x000FF022 }, /* 2, -24, 504, 34, -4 */ + {0x1F7F9803, 0x000FF024 }, /* 3, -26, 503, 36, -4 */ + {0x1F7F9403, 0x000FEC26 }, /* 3, -27, 503, 38, -5 */ + {0x1F6F9003, 0x000FEC28 }, /* 3, -28, 502, 40, -5 */ + {0x1F5F9003, 0x000FEC29 }, /* 3, -28, 501, 41, -5 */ + {0x1F4F8C03, 0x000FEC2B }, /* 3, -29, 500, 43, -5 */ + {0x1F3F8C03, 0x000FE82D }, /* 3, -29, 499, 45, -6 */ + {0x1F2F8803, 0x000FE82F }, /* 3, -30, 498, 47, -6 */ + {0x1F2F8003, 0x000FE831 }, /* 3, -32, 498, 49, -6 */ + {0x1F1F7C03, 0x000FE833 }, /* 3, -33, 497, 51, -6 */ + {0x1F0F7C03, 0x000FE435 }, /* 3, -33, 496, 53, -7 */ + {0x1EFF7803, 0x000FE437 }, /* 3, -34, 495, 55, -7 */ + {0x1EEF7403, 0x000FE439 }, /* 3, -35, 494, 57, -7 */ + {0x1EDF7004, 0x000FE03B }, /* 4, -36, 493, 59, -8 */ + {0x1EBF7403, 0x000FE43C }, /* 3, -35, 491, 60, -7 */ + {0x1EAF6C04, 0x000FE03F }, /* 4, -37, 490, 63, -8 */ + {0x1E9F6804, 0x000FE041 }, /* 4, -38, 489, 65, -8 */ + {0x1E8F6804, 0x000FDC43 }, /* 4, -38, 488, 67, -9 */ + {0x1E7F6404, 0x000FDC45 }, /* 4, -39, 487, 69, -9 */ + {0x1E6F6004, 0x000FDC47 }, /* 4, -40, 486, 71, -9 */ + {0x1E4F6404, 0x000FD849 }, /* 4, -39, 484, 73, -10 */ + {0x1E3F6004, 0x000FD84B }, /* 4, -40, 483, 75, -10 */ + {0x1E1F6003, 0x000FDC4D }, /* 3, -40, 481, 77, -9 */ + {0x1E1F5804, 0x000FD450 }, /* 4, -42, 481, 80, -11 */ + {0x1DFF5804, 0x000FD452 }, /* 4, -42, 479, 82, -11 */ + {0x1DEF5404, 0x000FD454 }, /* 4, -43, 478, 84, -11 */ + {0x1DCF5804, 0x000FD056 }, /* 4, -42, 476, 86, -12 */ + {0x1DBF5004, 0x000FD059 }, /* 4, -44, 475, 89, -12 */ + {0x1D9F5004, 0x000FD05B }, /* 4, -44, 473, 91, -12 */ + {0x1D8F5004, 0x000FCC5D }, /* 4, -44, 472, 93, -13 */ + {0x1D6F5004, 0x000FCC5F }, /* 4, -44, 470, 95, -13 */ + {0x1D5F4804, 0x000FCC62 }, /* 4, -46, 469, 98, -13 */ + {0x1D3F4C04, 0x000FC864 }, /* 4, -45, 467, 100, -14 */ + {0x1D1F4C04, 0x000FCC65 }, /* 4, -45, 465, 101, -13 */ + {0x1CFF4804, 0x000FCC68 }, /* 4, -46, 463, 104, -13 */ + {0x1CEF4405, 0x000FC46B }, /* 5, -47, 462, 107, -15 */ + {0x1CCF4804, 0x000FC86C }, /* 4, -46, 460, 108, -14 */ + {0x1CAF4404, 0x000FC86F }, /* 4, -47, 458, 111, -14 */ + {0x1C9F4005, 0x000FC072 }, /* 5, -48, 457, 114, -16 */ + {0x1C6F4404, 0x000FC474 }, /* 4, -47, 454, 116, -15 */ + {0x1C6F3C05, 0x000FBC77 }, /* 5, -49, 454, 119, -17 */ + {0x1C4F3C05, 0x000FBC79 }, /* 5, -49, 452, 121, -17 */ + {0x1C1F4004, 0x000FC07B }, /* 4, -48, 449, 123, -16 */ + {0x1C0F3C05, 0x000FB87E }, /* 5, -49, 448, 126, -18 */ + {0x1BEF3C04, 0x000FBC80 }, /* 4, -49, 446, 128, -17 */ + {0x1BCF3C04, 0x000FBC82 }, /* 4, -49, 444, 130, -17 */ + {0x1BAF3C04, 0x000FB885 }, /* 4, -49, 442, 133, -18 */ + {0x1B8F3C04, 0x000FB887 }, /* 4, -49, 440, 135, -18 */ + {0x1B6F3C04, 0x000FB48A }, /* 4, -49, 438, 138, -19 */ + {0x1B5F3405, 0x000FB08D }, /* 5, -51, 437, 141, -20 */ + {0x1B2F3804, 0x000FB48F }, /* 4, -50, 434, 143, -19 */ + {0x1B1F3405, 0x000FAC92 }, /* 5, -51, 433, 146, -21 */ + {0x1AEF3804, 0x000FB094 }, /* 4, -50, 430, 148, -20 */ + {0x1ACF3804, 0x000FAC97 }, /* 4, -50, 428, 151, -21 */ + {0x1AAF3804, 0x000FAC99 }, /* 4, -50, 426, 153, -21 */ + {0x1A7F3804, 0x000FAC9C }, /* 4, -50, 423, 156, -21 */ + {0x1A6F3405, 0x000FA49F }, /* 5, -51, 422, 159, -23 */ + {0x1A3F3804, 0x000FA8A1 }, /* 4, -50, 419, 161, -22 */ + {0x1A1F3804, 0x000FA4A4 }, /* 4, -50, 417, 164, -23 */ + {0x1A0F3005, 0x000FA0A7 }, /* 5, -52, 416, 167, -24 */ + {0x19DF3404, 0x000FA4A9 }, /* 4, -51, 413, 169, -23 */ + {0x19CF3005, 0x000F9CAC }, /* 5, -52, 412, 172, -25 */ + {0x199F3005, 0x000F9CAF }, /* 5, -52, 409, 175, -25 */ + {0x197F3005, 0x000F98B2 }, /* 5, -52, 407, 178, -26 */ + {0x195F3005, 0x000F98B4 }, /* 5, -52, 405, 180, -26 */ + {0x191F3804, 0x000F9CB6 }, /* 4, -50, 401, 182, -25 */ + {0x18FF3804, 0x000F98B9 }, /* 4, -50, 399, 185, -26 */ + {0x18CF3804, 0x000F98BC }, /* 4, -50, 396, 188, -26 */ + {0x18BF3804, 0x000F94BE }, /* 4, -50, 395, 190, -27 */ + {0x188F3804, 0x000F94C1 }, /* 4, -50, 392, 193, -27 */ + {0x186F3804, 0x000F90C4 }, /* 4, -50, 390, 196, -28 */ + {0x184F3405, 0x000F8CC7 }, /* 5, -51, 388, 199, -29 */ + {0x181F3804, 0x000F90C9 }, /* 4, -50, 385, 201, -28 */ + {0x17FF3804, 0x000F8CCC }, /* 4, -50, 383, 204, -29 */ + {0x17CF3804, 0x000F8CCF }, /* 4, -50, 380, 207, -29 */ + {0x17BF3405, 0x000F84D2 }, /* 5, -51, 379, 210, -31 */ + {0x177F3C04, 0x000F88D4 }, /* 4, -49, 375, 212, -30 */ + {0x174F3C04, 0x000F88D7 }, /* 4, -49, 372, 215, -30 */ + {0x172F3C04, 0x000F84DA }, /* 4, -49, 370, 218, -31 */ + {0x170F3C04, 0x000F84DC }, /* 4, -49, 368, 220, -31 */ + {0x16EF3805, 0x000F7CE0 }, /* 5, -50, 366, 224, -33 */ + {0x16BF3C04, 0x000F80E2 }, /* 4, -49, 363, 226, -32 */ + {0x167F4004, 0x000F80E5 }, /* 4, -48, 359, 229, -32 */ + {0x166F4004, 0x000F7CE7 }, /* 4, -48, 358, 231, -33 */ + {0x163F4004, 0x000F7CEA }, /* 4, -48, 355, 234, -33 */ + {0x161F4004, 0x000F78ED }, /* 4, -48, 353, 237, -34 */ + {0x15EF4004, 0x000F78F0 }, /* 4, -48, 350, 240, -34 */ + {0x15BF4404, 0x000F74F3 }, /* 4, -47, 347, 243, -35 */ + {0x159F4404, 0x000F74F5 }, /* 4, -47, 345, 245, -35 */ + {0x156F4404, 0x000F74F8 }, /* 4, -47, 342, 248, -35 */ + {0x154F4005, 0x000F6CFC }, /* 5, -48, 340, 252, -37 */ + {0x150F4804, 0x000F70FE }, /* 4, -46, 336, 254, -36 */ + {0x14FF4405, 0x000F6901 }, /* 5, -47, 335, 257, -38 */ + {0x14CF4804, 0x000F6D03 }, /* 4, -46, 332, 259, -37 */ + {0x149F4804, 0x000F6D06 }, /* 4, -46, 329, 262, -37 */ + {0x146F4C04, 0x000F6909 }, /* 4, -45, 326, 265, -38 */ + {0x143F4C04, 0x000F690C }, /* 4, -45, 323, 268, -38 */ + {0x141F4C04, 0x000F690E }, /* 4, -45, 321, 270, -38 */ + {0x13EF5004, 0x000F6511 }, /* 4, -44, 318, 273, -39 */ + {0x13BF5004, 0x000F6514 }, /* 4, -44, 315, 276, -39 */ + {0x139F5004, 0x000F6117 }, /* 4, -44, 313, 279, -40 */ + {0x136F5404, 0x000F6119 }, /* 4, -43, 310, 281, -40 */ + {0x133F5404, 0x000F611C }, /* 4, -43, 307, 284, -40 */ + {0x131F5404, 0x000F5D1F }, /* 4, -43, 305, 287, -41 */ + {0x12DF5C04, 0x000F5D21 }, /* 4, -41, 301, 289, -41 */ + {0x12AF5C04, 0x000F5D24 }, /* 4, -41, 298, 292, -41 */ +}; + +unsigned long CimarronVerticalGraphicsFilter[] = +{ + 0x3F840D05, /* 261, 259, -8 */ + 0x3F841D01, /* 257, 263, -8 */ + 0x3F8428FE, /* 254, 266, -8 */ + 0x3F8438FA, /* 250, 270, -8 */ + 0x3F8444F7, /* 247, 273, -8 */ + 0x3F8450F4, /* 244, 276, -8 */ + 0x3F845CF1, /* 241, 279, -8 */ + 0x3F8468EE, /* 238, 282, -8 */ + 0x3F8474EB, /* 235, 285, -8 */ + 0x3F8480E8, /* 232, 288, -8 */ + 0x3F7490E5, /* 229, 292, -9 */ + 0x3F749CE2, /* 226, 295, -9 */ + 0x3F74ACDE, /* 222, 299, -9 */ + 0x3F74B8DB, /* 219, 302, -9 */ + 0x3F74C0D9, /* 217, 304, -9 */ + 0x3F74CCD6, /* 214, 307, -9 */ + 0x3F74D8D3, /* 211, 310, -9 */ + 0x3F74E8CF, /* 207, 314, -9 */ + 0x3F74F4CC, /* 204, 317, -9 */ + 0x3F7500C9, /* 201, 320, -9 */ + 0x3F750CC6, /* 198, 323, -9 */ + 0x3F7518C3, /* 195, 326, -9 */ + 0x3F7520C1, /* 193, 328, -9 */ + 0x3F7530BD, /* 189, 332, -9 */ + 0x3F753CBA, /* 186, 335, -9 */ + 0x3F7548B7, /* 183, 338, -9 */ + 0x3F6558B4, /* 180, 342, -10 */ + 0x3F6560B2, /* 178, 344, -10 */ + 0x3F656CAF, /* 175, 347, -10 */ + 0x3F6578AC, /* 172, 350, -10 */ + 0x3F6584A9, /* 169, 353, -10 */ + 0x3F658CA7, /* 167, 355, -10 */ + 0x3F6598A4, /* 164, 358, -10 */ + 0x3F65A8A0, /* 160, 362, -10 */ + 0x3F65B09E, /* 158, 364, -10 */ + 0x3F65BC9B, /* 155, 367, -10 */ + 0x3F65C499, /* 153, 369, -10 */ + 0x3F65D096, /* 150, 372, -10 */ + 0x3F55E093, /* 147, 376, -11 */ + 0x3F55E891, /* 145, 378, -11 */ + 0x3F55F48E, /* 142, 381, -11 */ + 0x3F56008B, /* 139, 384, -11 */ + 0x3F560C88, /* 136, 387, -11 */ + 0x3F561486, /* 134, 389, -11 */ + 0x3F562083, /* 131, 392, -11 */ + 0x3F562881, /* 129, 394, -11 */ + 0x3F56347E, /* 126, 397, -11 */ + 0x3F56407B, /* 123, 400, -11 */ + 0x3F564879, /* 121, 402, -11 */ + 0x3F465876, /* 118, 406, -12 */ + 0x3F466074, /* 116, 408, -12 */ + 0x3F466872, /* 114, 410, -12 */ + 0x3F46746F, /* 111, 413, -12 */ + 0x3F467C6D, /* 109, 415, -12 */ + 0x3F46846B, /* 107, 417, -12 */ + 0x3F468C69, /* 105, 419, -12 */ + 0x3F469866, /* 102, 422, -12 */ + 0x3F46A064, /* 100, 424, -12 */ + 0x3F46AC61, /* 97, 427, -12 */ + 0x3F46B45F, /* 95, 429, -12 */ + 0x3F46BC5D, /* 93, 431, -12 */ + 0x3F46C45B, /* 91, 433, -12 */ + 0x3F46CC59, /* 89, 435, -12 */ + 0x3F36DC56, /* 86, 439, -13 */ + 0x3F36E454, /* 84, 441, -13 */ + 0x3F36EC52, /* 82, 443, -13 */ + 0x3F36F450, /* 80, 445, -13 */ + 0x3F36FC4E, /* 78, 447, -13 */ + 0x3F37004D, /* 77, 448, -13 */ + 0x3F370C4A, /* 74, 451, -13 */ + 0x3F371448, /* 72, 453, -13 */ + 0x3F371C46, /* 70, 455, -13 */ + 0x3F372444, /* 68, 457, -13 */ + 0x3F372C42, /* 66, 459, -13 */ + 0x3F373440, /* 64, 461, -13 */ + 0x3F37383F, /* 63, 462, -13 */ + 0x3F37403D, /* 61, 464, -13 */ + 0x3F37483B, /* 59, 466, -13 */ + 0x3F375039, /* 57, 468, -13 */ + 0x3F375438, /* 56, 469, -13 */ + 0x3F375C36, /* 54, 471, -13 */ + 0x3F376434, /* 52, 473, -13 */ + 0x3F376833, /* 51, 474, -13 */ + 0x3F377031, /* 49, 476, -13 */ + 0x3F377430, /* 48, 477, -13 */ + 0x3F377C2E, /* 46, 479, -13 */ + 0x3F37842C, /* 44, 481, -13 */ + 0x3F37882B, /* 43, 482, -13 */ + 0x3F47882A, /* 42, 482, -12 */ + 0x3F479028, /* 40, 484, -12 */ + 0x3F479427, /* 39, 485, -12 */ + 0x3F479C25, /* 37, 487, -12 */ + 0x3F47A024, /* 36, 488, -12 */ + 0x3F47A822, /* 34, 490, -12 */ + 0x3F47AC21, /* 33, 491, -12 */ + 0x3F47B020, /* 32, 492, -12 */ + 0x3F57B01F, /* 31, 492, -11 */ + 0x3F57B81D, /* 29, 494, -11 */ + 0x3F57BC1C, /* 28, 495, -11 */ + 0x3F57C01B, /* 27, 496, -11 */ + 0x3F57C41A, /* 26, 497, -11 */ + 0x3F67C818, /* 24, 498, -10 */ + 0x3F67CC17, /* 23, 499, -10 */ + 0x3F67D016, /* 22, 500, -10 */ + 0x3F67D415, /* 21, 501, -10 */ + 0x3F67D814, /* 20, 502, -10 */ + 0x3F77D813, /* 19, 502, -9 */ + 0x3F77DC12, /* 18, 503, -9 */ + 0x3F77E011, /* 17, 504, -9 */ + 0x3F87E010, /* 16, 504, -8 */ + 0x3F87E40F, /* 15, 505, -8 */ + 0x3F87E80E, /* 14, 506, -8 */ + 0x3F97E80D, /* 13, 506, -7 */ + 0x3F97EC0C, /* 12, 507, -7 */ + 0x3F97F00B, /* 11, 508, -7 */ + 0x3FA7F00A, /* 10, 508, -6 */ + 0x3FA7F409, /* 9, 509, -6 */ + 0x3FB7F408, /* 8, 509, -5 */ + 0x3FB7F408, /* 8, 509, -5 */ + 0x3FC7F806, /* 6, 510, -4 */ + 0x3FC7F806, /* 6, 510, -4 */ + 0x3FD7F805, /* 5, 510, -3 */ + 0x3FD7FC04, /* 4, 511, -3 */ + 0x3FE7FC03, /* 3, 511, -2 */ + 0x3FE7FC03, /* 3, 511, -2 */ + 0x3FF7FC02, /* 2, 511, -1 */ + 0x3FF7FC02, /* 2, 511, -1 */ + 0x0007FC01, /* 1, 511, 0 */ + 0x0007FC01, /* 1, 511, 0 */ + 0x0007FC01, /* 1, 511, 0 */ + 0x0027FFFF, /* -1, 511, 2 */ + 0x0027FFFF, /* -1, 511, 2 */ + 0x0037FFFE, /* -2, 511, 3 */ + 0x0037FFFE, /* -2, 511, 3 */ + 0x0047FFFD, /* -3, 511, 4 */ + 0x0047FBFE, /* -2, 510, 4 */ + 0x0057FBFD, /* -3, 510, 5 */ + 0x0067FBFC, /* -4, 510, 6 */ + 0x0077F7FC, /* -4, 509, 7 */ + 0x0077F7FC, /* -4, 509, 7 */ + 0x0087F7FB, /* -5, 509, 8 */ + 0x0097F3FB, /* -5, 508, 9 */ + 0x00A7F3FA, /* -6, 508, 10 */ + 0x00B7EFFA, /* -6, 507, 11 */ + 0x00C7EBFA, /* -6, 506, 12 */ + 0x00D7EBF9, /* -7, 506, 13 */ + 0x00E7E7F9, /* -7, 505, 14 */ + 0x00F7E3F9, /* -7, 504, 15 */ + 0x0107E3F8, /* -8, 504, 16 */ + 0x0117DFF8, /* -8, 503, 17 */ + 0x0127DBF8, /* -8, 502, 18 */ + 0x0137DBF7, /* -9, 502, 19 */ + 0x0147D7F7, /* -9, 501, 20 */ + 0x0157D3F7, /* -9, 500, 21 */ + 0x0167CFF7, /* -9, 499, 22 */ + 0x0177CBF7, /* -9, 498, 23 */ + 0x0197C7F6, /* -10, 497, 25 */ + 0x01A7C3F6, /* -10, 496, 26 */ + 0x01B7BFF6, /* -10, 495, 27 */ + 0x01C7BBF6, /* -10, 494, 28 */ + 0x01E7B3F6, /* -10, 492, 30 */ + 0x01F7B3F5, /* -11, 492, 31 */ + 0x0207AFF5, /* -11, 491, 32 */ + 0x0217ABF5, /* -11, 490, 33 */ + 0x0237A3F5, /* -11, 488, 35 */ + 0x02479FF5, /* -11, 487, 36 */ + 0x026797F5, /* -11, 485, 38 */ + 0x027793F5, /* -11, 484, 39 */ + 0x02978BF5, /* -11, 482, 41 */ + 0x02A78BF4, /* -12, 482, 42 */ + 0x02B787F4, /* -12, 481, 43 */ + 0x02D77FF4, /* -12, 479, 45 */ + 0x02F777F4, /* -12, 477, 47 */ + 0x030773F4, /* -12, 476, 48 */ + 0x03276BF4, /* -12, 474, 50 */ + 0x033767F4, /* -12, 473, 51 */ + 0x03575FF4, /* -12, 471, 53 */ + 0x037757F4, /* -12, 469, 55 */ + 0x038753F4, /* -12, 468, 56 */ + 0x03A74BF4, /* -12, 466, 58 */ + 0x03C743F4, /* -12, 464, 60 */ + 0x03E73BF4, /* -12, 462, 62 */ + 0x040737F3, /* -13, 461, 64 */ + 0x04272FF3, /* -13, 459, 66 */ + 0x044727F3, /* -13, 457, 68 */ + 0x04671FF3, /* -13, 455, 70 */ + 0x048717F3, /* -13, 453, 72 */ + 0x04A70FF3, /* -13, 451, 74 */ + 0x04C703F4, /* -12, 448, 76 */ + 0x04D6FFF4, /* -12, 447, 77 */ + 0x04F6F7F4, /* -12, 445, 79 */ + 0x0516EFF4, /* -12, 443, 81 */ + 0x0536E7F4, /* -12, 441, 83 */ + 0x0556DFF4, /* -12, 439, 85 */ + 0x0586CFF5, /* -11, 435, 88 */ + 0x05A6C7F5, /* -11, 433, 90 */ + 0x05C6BFF5, /* -11, 431, 92 */ + 0x05F6B7F4, /* -12, 429, 95 */ + 0x0616AFF4, /* -12, 427, 97 */ + 0x0636A3F5, /* -11, 424, 99 */ + 0x06569BF5, /* -11, 422, 101 */ + 0x06868FF5, /* -11, 419, 104 */ + 0x06A687F5, /* -11, 417, 106 */ + 0x06C67FF5, /* -11, 415, 108 */ + 0x06E677F5, /* -11, 413, 110 */ + 0x07166BF5, /* -11, 410, 113 */ + 0x073663F5, /* -11, 408, 115 */ + 0x07665BF4, /* -12, 406, 118 */ + 0x07964BF5, /* -11, 402, 121 */ + 0x07B643F5, /* -11, 400, 123 */ + 0x07D637F6, /* -10, 397, 125 */ + 0x08062BF6, /* -10, 394, 128 */ + 0x082623F6, /* -10, 392, 130 */ + 0x085617F6, /* -10, 389, 133 */ + 0x08760FF6, /* -10, 387, 135 */ + 0x08B603F5, /* -11, 384, 139 */ + 0x08D5F7F6, /* -10, 381, 141 */ + 0x0905EBF6, /* -10, 378, 144 */ + 0x0925E3F6, /* -10, 376, 146 */ + 0x0955D3F7, /* -9, 372, 149 */ + 0x0985C7F7, /* -9, 369, 152 */ + 0x09A5BFF7, /* -9, 367, 154 */ + 0x09D5B3F7, /* -9, 364, 157 */ + 0x0A05ABF6, /* -10, 362, 160 */ + 0x0A359BF7, /* -9, 358, 163 */ + 0x0A658FF7, /* -9, 355, 166 */ + 0x0A9587F6, /* -10, 353, 169 */ + 0x0AB57BF7, /* -9, 350, 171 */ + 0x0AE56FF7, /* -9, 347, 174 */ + 0x0B1563F7, /* -9, 344, 177 */ + 0x0B455BF6, /* -10, 342, 180 */ + 0x0B754BF7, /* -9, 338, 183 */ + 0x0BA53FF7, /* -9, 335, 186 */ + 0x0BD533F7, /* -9, 332, 189 */ + 0x0C0523F8, /* -8, 328, 192 */ + 0x0C251BF8, /* -8, 326, 194 */ + 0x0C550FF8, /* -8, 323, 197 */ + 0x0C9503F7, /* -9, 320, 201 */ + 0x0CC4F7F7, /* -9, 317, 204 */ + 0x0CF4EBF7, /* -9, 314, 207 */ + 0x0D24DBF8, /* -8, 310, 210 */ + 0x0D54CFF8, /* -8, 307, 213 */ + 0x0D84C3F8, /* -8, 304, 216 */ + 0x0DB4BBF7, /* -9, 302, 219 */ + 0x0DE4AFF7, /* -9, 299, 222 */ + 0x0E149FF8, /* -8, 295, 225 */ + 0x0E4493F8, /* -8, 292, 228 */ + 0x0E7483F9, /* -7, 288, 231 */ + 0x0EA477F9, /* -7, 285, 234 */ + 0x0ED46BF9, /* -7, 282, 237 */ + 0x0F045FF9, /* -7, 279, 240 */ + 0x0F4453F8, /* -8, 276, 244 */ + 0x0F7447F8, /* -8, 273, 247 */ + 0x0FA43BF8, /* -8, 270, 250 */ + 0x0FD42BF9, /* -7, 266, 253 */ + 0x10041FF9, /* -7, 263, 256 */ +}; --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/durango.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/durango.c 2005-12-14 11:37:00.000000000 -0700 @@ -0,0 +1,505 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This is the main file used to add Durango graphics support to a software + * project. The main reason to have a single file include the other files + * is that it centralizes the location of the compiler options. This file + * should be tuned for a specific implementation, and then modified as needed + * for new Durango releases. The releases.txt file indicates any updates to + * this main file, such as a new definition for a new hardware platform. + * + * In other words, this file should be copied from the Durango source files + * once when a software project starts, and then maintained as necessary. + * It should not be recopied with new versions of Durango unless the + * developer is willing to tune the file again for the specific project. + * */ + + + +/* COMPILER OPTIONS + * These compiler options specify how the Durango routines are compiled + * for the different hardware platforms. For best performance, a driver + * would build for a specific platform. The "dynamic" switches are set + * by diagnostic applications such as Darwin that will run on a variety + * of platforms and use the appropriate code at runtime. Each component + * may be separately dynamic, so that a driver has the option of being + * tuned for a specific 2D accelerator, but will still run with a variety + * of chipsets. + */ + +#define GFX_DISPLAY_DYNAMIC 1 /* runtime selection */ +#define GFX_DISPLAY_GU1 1 /* 1st generation display controller */ +#define GFX_DISPLAY_GU2 1 /* 2nd generation display controller */ +#define GFX_DISPLAY_GU3 1 /* 3rd generation display controller */ + +#define GFX_INIT_DYNAMIC 1 /* runtime selection */ +#define GFX_INIT_GU1 1 /* Geode family */ +#define GFX_INIT_GU2 1 /* Redcloud */ +#define GFX_INIT_GU3 1 /* Castle */ + +#define GFX_MSR_DYNAMIC 1 /* runtime selection */ +#define GFX_MSR_REDCLOUD 1 /* Redcloud */ + +#define GFX_2DACCEL_DYNAMIC 1 /* runtime selection */ +#define GFX_2DACCEL_GU1 1 /* 1st generation 2D accelerator */ +#define GFX_2DACCEL_GU2 1 /* 2nd generation 2D accelerator */ + +#define GFX_VIDEO_DYNAMIC 1 /* runtime selection */ +#define GFX_VIDEO_CS5530 1 /* support for CS5530 */ +#define GFX_VIDEO_SC1200 1 /* support for SC1200 */ +#define GFX_VIDEO_REDCLOUD 1 /* support for Redcloud */ +#define GFX_VIDEO_CASTLE 1 /* support for Castle */ + +#define GFX_VIP_DYNAMIC 1 /* runtime selection */ +#define GFX_VIP_SC1200 1 /* support for SC1200 */ + +#define GFX_DECODER_DYNAMIC 1 /* runtime selection */ +#define GFX_DECODER_SAA7114 1 /* Philips SAA7114 decoder */ + +#define GFX_TV_DYNAMIC 1 /* runtime selection */ +#define GFX_TV_FS451 1 /* Focus Enhancements FS450 */ +#define GFX_TV_SC1200 1 /* SC1200 integrated TV encoder */ + +#define GFX_I2C_DYNAMIC 1 /* runtime selection */ +#define GFX_I2C_ACCESS 1 /* support for ACCESS.BUS */ +#define GFX_I2C_GPIO 1 /* support for CS5530 GPIOs */ + +#define GFX_VGA_DYNAMIC 1 /* runtime selection */ +#define GFX_VGA_GU1 1 /* 1st generation graphics unit */ + +#define FB4MB 1 /* Set to use 4Mb video ram for Pyramid */ + +#define GFX_NO_IO_IN_WAIT_MACROS 0 /* Set to remove I/O accesses in GP bit testing */ + +/* ROUTINES TO READ VALUES + * These are routines used by Darwin or other diagnostics to read the + * current state of the hardware. Display drivers or embedded applications can + * reduce the size of the Durango code by not including these routines. + */ +#define GFX_READ_ROUTINES 1 /* add routines to read values */ + +/* VARIABLES USED FOR RUNTIME SELECTION + * If part of the graphics subsystem is declared as dynamic, then the + * following variables are used to specify which platform has been detected. + * The variables are set in the "gfx_detect_cpu" routine. The values should + * be bit flags to allow masks to be used to check for multiple platforms. + */ + +#if GFX_DISPLAY_DYNAMIC +int gfx_display_type = 0; +#endif + +#if GFX_INIT_DYNAMIC +int gfx_init_type = 0; +#endif + +#if GFX_MSR_DYNAMIC +int gfx_msr_type = 0; +#endif + +#if GFX_2DACCEL_DYNAMIC +int gfx_2daccel_type = 0; +#endif + +#if GFX_VIDEO_DYNAMIC +int gfx_video_type = 0; +#endif + +#if GFX_VIP_DYNAMIC +int gfx_vip_type = 0; +#endif + +#if GFX_DECODER_DYNAMIC +int gfx_decoder_type = 0; +#endif + +#if GFX_TV_DYNAMIC +int gfx_tv_type = 0; +#endif + +#if GFX_I2C_DYNAMIC +int gfx_i2c_type = 0; +#endif + +#if GFX_VGA_DYNAMIC +int gfx_vga_type = 0; +#endif + +/* HEADER FILE FOR DURANGO ROUTINE DEFINITIONS + * Needed since some of the Durango routines call other Durango routines. + * Also defines the size of chipset array (GFX_CSPTR_SIZE). + */ +#include "gfx_rtns.h" /* routine definitions */ + +/* INCLUDE PROTOTYPES FOR PRIVATE ROUTINES */ + +#include "gfx_priv.h" + +/* DEFINE POINTERS TO MEMORY MAPPED REGIONS + * These pointers are used by the Durango routines to access the hardware. + * The variables must be set by the project's initialization code after + * mapping the regions in the appropriate manner. + */ + +/* DEFINE VIRTUAL ADDRESSES */ +/* Note: These addresses define the starting base expected by all */ +/* Durango offsets. Under an OS that requires these pointers */ +/* to be mapped to linear addresses (i.e Windows), it may not */ +/* be possible to keep these base offsets. In these cases, */ +/* the addresses are modified to point to the beginning of the */ +/* relevant memory region and the access macros are adjusted */ +/* to subtract the offset from the default base. For example, */ +/* the register pointer could be moved to be 0x40008000, while */ +/* the WRITE_REG* macros are modified to subtract 0x8000 from */ +/* the offset. */ + +unsigned char *gfx_virt_regptr = (unsigned char *) 0x40000000; +unsigned char *gfx_virt_fbptr = (unsigned char *) 0x40800000; +unsigned char *gfx_virt_vidptr = (unsigned char *) 0x40010000; +unsigned char *gfx_virt_vipptr = (unsigned char *) 0x40015000; +unsigned char *gfx_virt_spptr = (unsigned char *) 0x40000000; +unsigned char *gfx_virt_gpptr = (unsigned char *) 0x40000000; + +/* DEFINE PHYSICAL ADDRESSES */ + +unsigned char *gfx_phys_regptr = (unsigned char *) 0x40000000; +unsigned char *gfx_phys_fbptr = (unsigned char *) 0x40800000; +unsigned char *gfx_phys_vidptr = (unsigned char *) 0x40010000; +unsigned char *gfx_phys_vipptr = (unsigned char *) 0x40015000; + +/* HEADER FILE FOR GRAPHICS REGISTER DEFINITIONS + * This contains only constant definitions, so it should be able to be + * included in any software project as is. + */ +#include "gfx_regs.h" /* graphics register definitions */ + +/* HEADER FILE FOR REGISTER ACCESS MACROS + * This file contains the definitions of the WRITE_REG32 and similar macros + * used by the Durango routines to access the hardware. The file assumes + * that the environment can handle 32-bit pointer access. If this is not + * the case, or if there are special requirements, then this header file + * should not be included and the project must define the macros itself. + * (A project may define WRITE_REG32 to call a routine, for example). + */ +#include "gfx_defs.h" /* register access macros */ + +/* IO MACROS AND ROUTINES + * These macros must be defined before the initialization or I2C + * routines will work properly. + */ + +#if defined(OS_WIN32) /* For Windows */ + +/* VSA II CALL */ + +void gfx_msr_asm_read (unsigned short msrReg, unsigned long msrAddr, unsigned long *ptrHigh, unsigned long *ptrLow) +{ + unsigned long temp1, temp2; + + _asm { + mov dx, 0x0AC1C + mov eax, 0x0FC530007 + out dx, eax + + add dl, 2 + mov ecx, msrAddr + mov cx, msrReg + in ax, dx + + ; EDX:EAX will contain MSR contents. + + mov temp1, edx + mov temp2, eax + } + + *ptrHigh = temp1; + *ptrLow = temp2; +} + +void gfx_msr_asm_write (unsigned short msrReg, unsigned long msrAddr, unsigned long *ptrHigh, unsigned long *ptrLow) +{ + unsigned long temp1 = *ptrHigh; + unsigned long temp2 = *ptrLow; + + _asm { + + mov dx, 0x0AC1C + mov eax, 0x0FC530007 + out dx, eax + + add dl, 2 + mov ecx, msrAddr ; ECX contains msrAddr | msrReg + mov cx, msrReg ; + mov ebx, temp1 ; + mov eax, temp2 ; + + mov esi, 0 ; + mov edi, 0 ; + out dx, ax + + ; MSR is written at this point + } +} + +unsigned char gfx_inb(unsigned short port) +{ + unsigned char data; + _asm { + pushf + mov dx, port + in al, dx + mov data, al + popf + } + return(data); +} + +unsigned short gfx_inw(unsigned short port) +{ + unsigned short data; + _asm { + pushf + mov dx, port + in ax, dx + mov data, ax + popf + } + return(data); +} + +unsigned long gfx_ind(unsigned short port) +{ + unsigned long data; + _asm { + pushf + mov dx, port + in eax, dx + mov data, eax + popf + } + return(data); +} + +void gfx_outb(unsigned short port, unsigned char data) +{ + _asm { + pushf + mov al, data + mov dx, port + out dx, al + popf + } +} + +void gfx_outw(unsigned short port, unsigned short data) +{ + _asm { + pushf + mov ax, data + mov dx, port + out dx, ax + popf + } +} + +void gfx_outd(unsigned short port, unsigned long data) +{ + _asm { + pushf + mov eax, data + mov dx, port + out dx, eax + popf + } +} + +#elif defined(OS_VXWORKS) || defined (OS_LINUX) /* VxWorks and Linux */ + +#if defined(OS_LINUX) +#include "asm/msr.h" +#endif + +void gfx_msr_asm_read (unsigned short msrReg, unsigned long msrAddr, unsigned long *ptrHigh, unsigned long *ptrLow) +{ + unsigned long addr, val1, val2; + + addr = msrAddr | (unsigned long)msrReg; + rdmsr(addr, val1, val2); + + *ptrHigh = val2; + *ptrLow = val1; +} + +void gfx_msr_asm_write (unsigned short msrReg, unsigned long msrAddr, unsigned long *ptrHigh, unsigned long *ptrLow) +{ + unsigned long addr, val1, val2; + + val2 = *ptrHigh; + val1 = *ptrLow; + + addr = (msrAddr & 0xFFFF0000) | (unsigned long)msrReg; + wrmsr(addr, val1, val2); +} + +unsigned char gfx_inb(unsigned short port) +{ + unsigned char value; + __asm__ volatile ("inb %1,%0" : "=a" (value) : "d" (port)); + return value; +} + +unsigned short gfx_inw(unsigned short port) +{ + unsigned short value; + __asm__ volatile ("in %1,%0" : "=a" (value) : "d" (port)); + return value; +} + +unsigned long gfx_ind(unsigned short port) +{ + unsigned long value; + __asm__ volatile ("inl %1,%0" : "=a" (value) : "d" (port)); + return value; +} + +void gfx_outb(unsigned short port, unsigned char data) +{ + __asm__ volatile ("outb %0,%1" : : "a" (data),"d" (port)); +} + +void gfx_outw(unsigned short port, unsigned short data) +{ + __asm__ volatile ("out %0,%1" : : "a" (data),"d" (port)); +} + +void gfx_outd(unsigned short port, unsigned long data) +{ + __asm__ volatile ("outl %0,%1" : : "a" (data),"d" (port)); +} + +#else /* else nothing */ + +unsigned char gfx_inb(unsigned short port) +{ + /* ADD OS SPECIFIC IMPLEMENTATION */ + return(0); +} + +unsigned short gfx_inw(unsigned short port) +{ + /* ADD OS SPECIFIC IMPLEMENTATION */ + return(0); +} + +unsigned long gfx_ind(unsigned short port) +{ + /* ADD OS SPECIFIC IMPLEMENTATION */ + return(0); +} + +void gfx_outb(unsigned short port, unsigned char data) +{ + /* ADD OS SPECIFIC IMPLEMENTATION */ +} + +void gfx_outw(unsigned short port, unsigned short data) +{ + /* ADD OS SPECIFIC IMPLEMENTATION */ +} + +void gfx_outd(unsigned short port, unsigned long data) +{ + /* ADD OS SPECIFIC IMPLEMENTATION */ +} +#endif + +#define INB(port) gfx_inb(port) +#define INW(port) gfx_inw(port) +#define IND(port) gfx_ind(port) +#define OUTB(port, data) gfx_outb(port, data) +#define OUTW(port, data) gfx_outw(port, data) +#define OUTD(port, data) gfx_outd(port, data) + +/* INITIALIZATION ROUTINES + * These routines are used during the initialization of the driver to + * perform such tasks as detecting the type of CPU and video hardware. + * The routines require the use of IO, so the above IO routines need + * to be implemented before the initialization routines will work + * properly. + */ + +#include "gfx_init.c" + +/* INCLUDE MSR ACCESS ROUTINES */ + +#include "gfx_msr.c" + +/* INCLUDE GRAPHICS ENGINE ROUTINES + * These routines are used to program the 2D graphics accelerator. If + * the project does not use graphics acceleration (direct frame buffer + * access only), then this file does not need to be included. + */ +#include "gfx_rndr.c" /* graphics engine routines */ + +/* INCLUDE DISPLAY CONTROLLER ROUTINES + * These routines are used if the display mode is set directly. If the + * project uses VGA registers to set a display mode, then these files + * do not need to be included. + */ +#include "gfx_mode.h" /* display mode tables */ +#include "gfx_disp.c" /* display controller routines */ + +/* INCLUDE VIDEO OVERLAY ROUTINES + * These routines control the video overlay hardware. + */ +#include "gfx_vid.c" /* video overlay routines */ + +/* VIDEO PORT AND VIDEO DECODER ROUTINES + * These routines rely on the I2C routines. + */ +#include "gfx_vip.c" /* video port routines */ +#include "gfx_dcdr.c" /* video decoder routines */ + +/* I2C BUS ACCESS ROUTINES + * These routines are used by the video decoder and possibly an + * external TV encoer. + */ +#include "gfx_i2c.c" /* I2C bus access routines */ + +/* TV ENCODER ROUTINES + * This file does not need to be included if the system does not + * support TV output. + */ +#include "gfx_tv.c" /* TV encoder routines */ + +/* VGA ROUTINES + * This file is used if setting display modes using VGA registers. + */ +#include "gfx_vga.c" /* VGA routines */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/vid_1200.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/vid_1200.c 2005-12-14 11:28:57.000000000 -0700 @@ -0,0 +1,2563 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to control the SC1200 video overlay hardware. + * */ + + + +/*---------------------------------------------------------------------------- + * SC1200 GAMMA RAM TABLE + *---------------------------------------------------------------------------- + */ + +unsigned long gfx_gamma_ram_1200[] = +{ + 0x00000000, 0x00040003, 0x00050104, 0x00060205, 0x00070306, 0x00080407, + 0x00090508, 0x000A0609, 0x000B070A, 0x000C080B, 0x000D090C, 0x000E0A0D, + 0x000F0B0E, 0x00100C0F, 0x00110D10, 0x00110E11, 0x00120F12, 0x00141013, + 0x00151114, 0x00161215, 0x00171316, 0x00181417, 0x00191518, 0x001A1619, + 0x001B171A, 0x001C181B, 0x001D191C, 0x001D1A1D, 0x001E1B1E, 0x00201C1F, + 0x00201D20, 0x00221E21, 0x00231F22, 0x00242023, 0x00252124, 0x00262225, + 0x00262326, 0x00282427, 0x00292528, 0x00292629, 0x002B272A, 0x002C282B, + 0x002D292C, 0x002E2A2D, 0x002F2B2E, 0x00302C2F, 0x00312D30, 0x00322E31, + 0x00332F32, 0x00343033, 0x00353134, 0x00363235, 0x00373336, 0x00383437, + 0x00393538, 0x003A3639, 0x003B373A, 0x003C383B, 0x003D393C, 0x003E3A3D, + 0x003F3B3E, 0x00403C3F, 0x00413D40, 0x00423E41, 0x00433F42, 0x00444043, + 0x00444144, 0x00454245, 0x00474346, 0x00484447, 0x00494548, 0x004A4649, + 0x004B474A, 0x004C484B, 0x004D494C, 0x004E4A4D, 0x004F4B4E, 0x00504C4F, + 0x00514D50, 0x00524E51, 0x00534F52, 0x00545053, 0x00555154, 0x00565255, + 0x00575356, 0x00585457, 0x00595558, 0x005A5659, 0x005B575A, 0x005C585B, + 0x005D595C, 0x005E5A5D, 0x005F5B5E, 0x00605C5F, 0x00615D60, 0x00625E61, + 0x00635F62, 0x00646063, 0x00656164, 0x00666265, 0x00676366, 0x00686467, + 0x00696568, 0x006A6669, 0x006B676A, 0x006C686B, 0x006D696C, 0x006E6A6D, + 0x006F6B6E, 0x00706C6F, 0x00716D70, 0x00726E71, 0x00736F72, 0x00747073, + 0x00757174, 0x00767275, 0x00777376, 0x00787477, 0x00797578, 0x007A7679, + 0x007B777A, 0x007C787B, 0x007D797C, 0x007E7A7D, 0x007F7B7E, 0x00807C7F, + 0x00817D80, 0x00827E81, 0x00837F82, 0x00848083, 0x00858184, 0x00868285, + 0x00878386, 0x00888487, 0x00898588, 0x008A8689, 0x008B878A, 0x008C888B, + 0x008D898C, 0x008E8A8D, 0x008F8B8E, 0x00908C8F, 0x00918D90, 0x00928E91, + 0x00938F92, 0x00949093, 0x00959194, 0x00969295, 0x00979396, 0x00989497, + 0x00999598, 0x009A9699, 0x009B979A, 0x009C989B, 0x009D999C, 0x009E9A9D, + 0x009F9B9E, 0x00A09C9F, 0x00A19DA0, 0x00A29EA1, 0x00A39FA2, 0x00A4A0A3, + 0x00A5A1A4, 0x00A6A2A5, 0x00A7A3A6, 0x00A8A4A7, 0x00A9A5A8, 0x00AAA6A9, + 0x00ABA7AA, 0x00ACA8AB, 0x00ADA9AC, 0x00AEAAAD, 0x00AFABAE, 0x00B0ACAF, + 0x00B1ADB0, 0x00B2AEB1, 0x00B3AFB2, 0x00B4B0B3, 0x00B5B1B4, 0x00B6B2B5, + 0x00B7B3B6, 0x00B8B4B7, 0x00B9B5B8, 0x00BAB6B9, 0x00BBB7BA, 0x00BCB8BB, + 0x00BDB9BC, 0x00BEBABD, 0x00BFBBBE, 0x00C0BCBF, 0x00C1BDC0, 0x00C2BEC1, + 0x00C3BFC2, 0x00C4C0C3, 0x00C5C1C4, 0x00C6C2C5, 0x00C7C3C6, 0x00C8C4C7, + 0x00C9C5C8, 0x00CAC6C9, 0x00CBC7CA, 0x00CCC8CB, 0x00CDC9CC, 0x00CECACD, + 0x00CFCBCE, 0x00D0CCCF, 0x00D1CDD0, 0x00D2CED1, 0x00D3CFD2, 0x00D4D0D3, + 0x00D5D1D4, 0x00D6D2D5, 0x00D7D3D6, 0x00D8D4D7, 0x00D9D5D8, 0x00DAD6D9, + 0x00DBD7DA, 0x00DCD8DB, 0x00DDD9DC, 0x00DEDADD, 0x00DFDBDE, 0x00E0DCDF, + 0x00E1DDE0, 0x00E2DEE1, 0x00E3DFE2, 0x00E4E0E3, 0x00E5E1E4, 0x00E6E2E5, + 0x00E7E3E6, 0x00E8E4E7, 0x00E9E5E8, 0x00EAE6E9, 0x00EBE7EA, 0x00ECE8EB, + 0x00EDE9EC, 0x00EEEAED, 0x00EFEBEE, 0x00F0ECEF, 0x00F1EDF0, 0x00F2EEF1, + 0x00F3EFF2, 0x00F4F0F3, 0x00F5F1F4, 0x00F6F2F5, 0x00F7F3F6, 0x00F8F4F7, + 0x00F9F5F8, 0x00FAF6F9, 0x00FBF7FA, 0x00FCF8FB, 0x00FDF9FC, 0x00FEFAFD, + 0x00FFFBFE, 0x00FFFCFE, 0x00FFFDFE, 0x00FFFFFF +}; + +/*---------------------------------------------------------------------------- + * SC1200 PLL TABLE + *---------------------------------------------------------------------------- + */ + +typedef struct tagSC1200PLL +{ + long frequency; /* 16.16 fixed point frequency */ + unsigned long clock_select; /* clock select register (0x2C) */ +} SC1200PLL; + +SC1200PLL gfx_sc1200_clock_table[] = { + { (25L << 16) | ((1750L * 65536L) / 10000L), 0x0070E00C }, /* 25.1750 (sc=24.9231) */ + { (27L << 16) | ((0000L * 65536L) / 10000L), 0x00300100 }, /* 27.0000 */ + { (28L << 16) | ((3220L * 65536L) / 10000L), 0x0070EC0C }, /* 28.3220 (SC=27.000) */ + { (31L << 16) | ((5000L * 65536L) / 10000L), 0x00500D02 }, /* 31.5000 */ + { (36L << 16) | ((0000L * 65536L) / 10000L), 0x00500F02 }, /* 36.0000 */ + { (37L << 16) | ((5000L * 65536L) / 10000L), 0x0050B108 }, /* 37.5000 */ + { (40L << 16) | ((0000L * 65536L) / 10000L), 0x0050D20D }, /* 40.0000 */ + { (44L << 16) | ((9000L * 65536L) / 10000L), 0x0050DC0D }, /* 44.9000 */ + { (49L << 16) | ((5000L * 65536L) / 10000L), 0x00501502 }, /* 49.5000 */ + { (50L << 16) | ((0000L * 65536L) / 10000L), 0x0050A404 }, /* 50.0000 */ + { (50L << 16) | ((3500L * 65536L) / 10000L), 0x0050E00C }, /* 50.3500 */ + { (54L << 16) | ((0000L * 65536L) / 10000L), 0x00300300 }, /* 54.0000 */ + { (56L << 16) | ((3916L * 65536L) / 10000L), 0x0050F40D }, /* 56.3916 */ + { (56L << 16) | ((6440L * 65536L) / 10000L), 0x0050EC0C }, /* 56.6440 */ + { (59L << 16) | ((0000L * 65536L) / 10000L), 0x0030A207 }, /* 59.0000 */ + { (63L << 16) | ((0000L * 65536L) / 10000L), 0x00300D02 }, /* 63.0000 */ + { (65L << 16) | ((0000L * 65536L) / 10000L), 0x0030CC0F }, /* 65.0000 */ + { (67L << 16) | ((5000L * 65536L) / 10000L), 0x00300400 }, /* 67.5000 */ + { (70L << 16) | ((8000L * 65536L) / 10000L), 0x00301403 }, /* 70.8000 */ + { (72L << 16) | ((0000L * 65536L) / 10000L), 0x00300F02 }, /* 72.0000 */ + { (75L << 16) | ((0000L * 65536L) / 10000L), 0x0030B108 }, /* 75.0000 */ + { (78L << 16) | ((7500L * 65536L) / 10000L), 0x0030A205 }, /* 78.7500 */ + { (80L << 16) | ((0000L * 65536L) / 10000L), 0x0030D20D }, /* 80.0000 */ + { (87L << 16) | ((2728L * 65536L) / 10000L), 0x0030E00E }, /* 87.2728 */ + { (89L << 16) | ((8000L * 65536L) / 10000L), 0x0030DC0D }, /* 89.8000 */ + { (94L << 16) | ((5000L * 65536L) / 10000L), 0x00300600 }, /* 99.0000 */ + { (99L << 16) | ((0000L * 65536L) / 10000L), 0x00301502 }, /* 99.0000 */ + { (100L << 16) | ((0000L * 65536L) / 10000L), 0x0030A404 }, /* 100.00 */ + { (108L << 16) | ((0000L * 65536L) / 10000L), 0x00100300 }, /* 108.00 */ + { (112L << 16) | ((5000L * 65536L) / 10000L), 0x00301802 }, /* 108.00 */ + { (130L << 16) | ((0000L * 65536L) / 10000L), 0x0010CC0F }, /* 130.00 */ + { (135L << 16) | ((0000L * 65536L) / 10000L), 0x00100400 }, /* 135.00 */ + { (157L << 16) | ((5000L * 65536L) / 10000L), 0x0010A205 }, /* 157.50 */ + { (162L << 16) | ((0000L * 65536L) / 10000L), 0x00100500 }, /* 162.00 */ + { (175L << 16) | ((0000L * 65536L) / 10000L), 0x0010E00E }, /* 175.50 */ + { (189L << 16) | ((0000L * 65536L) / 10000L), 0x00100600 }, /* 189.00 */ + { (202L << 16) | ((0000L * 65536L) / 10000L), 0x0010EF0E }, /* 202.50 */ + { (232L << 16) | ((0000L * 65536L) / 10000L), 0x0010AA04 }, /* 232.50 */ + + /* Precomputed inidces in the hardware */ + { 0x0018EC4D, 0x000F0000 }, /* 24.923052 */ + { 0x00192CCC, 0x00000000 }, /* 25.1750 */ + { 0x001B0000, 0x00300100 }, /* 27.0000 */ + { 0x001F8000, 0x00010000 }, /* 31.5000 */ + { 0x00240000, 0x00020000 }, /* 36.0000 */ + { 0x00280000, 0x00030000 }, /* 40.0000 */ + { 0x00318000, 0x00050000 }, /* 49.5000 */ + { 0x00320000, 0x00040000 }, /* 50.0000 */ + { 0x00384000, 0x00060000 }, /* 56.2500 */ + { 0x00410000, 0x00080000 }, /* 65.0000 */ + { 0x004E8000, 0x000A0000 }, /* 78.5000 */ + { 0x005E8000, 0x000B0000 }, /* 94.5000 */ + { 0x006C0000, 0x000C0000 }, /* 108.0000 */ + { 0x00870000, 0x000D0000 }, /* 135.0000 */ +}; + +#define NUM_SC1200_FREQUENCIES sizeof(gfx_sc1200_clock_table)/sizeof(SC1200PLL) + +/*--------------------------------------------------------------------------- + * gfx_reset_video (PRIVATE ROUTINE: NOT PART OF DURANGO API) + * + * This routine is used to disable all components of video overlay before + * performing a mode switch. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void sc1200_reset_video(void) +#else +void gfx_reset_video(void) +#endif +{ + int i; + + gfx_set_video_enable(0); + + /* SET WINDOW 0 AFTER RESET */ + + for (i = 2; i >= 0; i--) + { + gfx_select_alpha_region(i); + gfx_set_alpha_enable(0); + gfx_set_alpha_color_enable(0); + } + + /* CLEAR THE DISPLAY BUFFER SIZE TO ZERO */ + /* During a modeset,if FIFO load is enabled with a large buffer size, */ + /* the FIFO can hang. To prevent this, we set the buffer size to zero */ + /* and wait for this new size to be latched */ + + gfx_set_display_video_size (0, 0); + + if (gfx_test_timing_active()) + { + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + } +} + +/*----------------------------------------------------------------------------- + * gfx_set_display_control (PRIVATE ROUTINE: NOT PART OF DURANGO API) + * + * This routine configures the display output. + * + * "sync_polarities" is used to set the polarities of the sync pulses according + * to the following mask: + * + * Bit 0: If set to 1, negative horizontal polarity is programmed, + * otherwise positive horizontal polarity is programmed. + * Bit 1: If set to 1, negative vertical polarity is programmed, + * otherwise positive vertical polarity is programmed. + * + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_display_control(int sync_polarities) +#else +int gfx_set_display_control(int sync_polarities) +#endif +{ + unsigned long dcfg; + + /* CONFIGURE DISPLAY OUTPUT FROM VIDEO PROCESSOR */ + + dcfg = READ_VID32(SC1200_DISPLAY_CONFIG); + dcfg &= ~(SC1200_DCFG_CRT_SYNC_SKW_MASK | SC1200_DCFG_PWR_SEQ_DLY_MASK | + SC1200_DCFG_CRT_HSYNC_POL | SC1200_DCFG_CRT_VSYNC_POL | + SC1200_DCFG_FP_PWR_EN | SC1200_DCFG_FP_DATA_EN); + + dcfg |= (SC1200_DCFG_CRT_SYNC_SKW_INIT | + SC1200_DCFG_PWR_SEQ_DLY_INIT | + SC1200_DCFG_GV_PAL_BYP); + + if (PanelEnable) + dcfg |= SC1200_DCFG_FP_PWR_EN; + + /* SET APPROPRIATE SYNC POLARITIES */ + + if (sync_polarities & 0x1) + dcfg |= SC1200_DCFG_CRT_HSYNC_POL; + if (sync_polarities & 0x2) + dcfg |= SC1200_DCFG_CRT_VSYNC_POL; + + WRITE_VID32(SC1200_DISPLAY_CONFIG, dcfg); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_clock_frequency + * + * This routine sets the clock frequency, specified as a 16.16 fixed point + * value (0x00318000 = 49.5 MHz). It will set the closest frequency found + * in the lookup table. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void sc1200_set_clock_frequency(unsigned long frequency) +#else +void gfx_set_clock_frequency(unsigned long frequency) +#endif +{ + unsigned int index; + unsigned long value, pll; + long min, diff; + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + + value = gfx_sc1200_clock_table[0].clock_select; + min = (long) gfx_sc1200_clock_table[0].frequency - frequency; + if (min < 0L) min = -min; + for (index = 1; index < NUM_SC1200_FREQUENCIES; index++) + { + diff = (long) gfx_sc1200_clock_table[index].frequency - frequency; + if (diff < 0L) diff = -diff; + if (diff < min) + { + min = diff; + value = gfx_sc1200_clock_table[index].clock_select; + } + } + + /* SET THE DOT CLOCK REGISTER */ + + pll = READ_VID32(SC1200_VID_MISC); + WRITE_VID32(SC1200_VID_MISC, pll | SC1200_PLL_POWER_NORMAL); + WRITE_VID32(SC1200_VID_CLOCK_SELECT, value); + return; +} + +/*--------------------------------------------------------------------------- + * gfx_set_screen_enable (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine enables or disables the graphics display logic of the video processor. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_screen_enable(int enable) +#else +int gfx_set_screen_enable(int enable) +#endif +{ + unsigned long config; + config = READ_VID32(SC1200_DISPLAY_CONFIG); + if (enable) + WRITE_VID32(SC1200_DISPLAY_CONFIG, config | SC1200_DCFG_DIS_EN); + else + WRITE_VID32(SC1200_DISPLAY_CONFIG, config & ~SC1200_DCFG_DIS_EN); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_crt_enable + * + * This routine enables or disables the CRT output from the video processor. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_crt_enable(int enable) +#else +int gfx_set_crt_enable(int enable) +#endif +{ + unsigned long config, misc; + config = READ_VID32(SC1200_DISPLAY_CONFIG); + misc = READ_VID32(SC1200_VID_MISC); + + /* + * IMPORTANT: For all modes do NOT disable the graphics display logic + * because it might be needed for TV + */ + + switch (enable) + { + case CRT_DISABLE: /* HSync:Off VSync:Off */ + WRITE_VID32(SC1200_DISPLAY_CONFIG, config & ~(SC1200_DCFG_HSYNC_EN + | SC1200_DCFG_VSYNC_EN + | SC1200_DCFG_DAC_BL_EN)); + WRITE_VID32(SC1200_VID_MISC, misc | SC1200_DAC_POWER_DOWN); + break; + case CRT_ENABLE: /* Enable CRT display, including display logic */ + WRITE_VID32(SC1200_DISPLAY_CONFIG, config | SC1200_DCFG_HSYNC_EN + | SC1200_DCFG_VSYNC_EN + | SC1200_DCFG_DAC_BL_EN); + WRITE_VID32(SC1200_VID_MISC, misc & ~SC1200_DAC_POWER_DOWN); + + /* ENABLE GRAPHICS DISPLAY LOGIC */ + gfx_set_screen_enable(1); + break; + case CRT_STANDBY: /* HSync:Off VSync:On */ + WRITE_VID32(SC1200_DISPLAY_CONFIG, (config & ~(SC1200_DCFG_HSYNC_EN + | SC1200_DCFG_DAC_BL_EN)) + | SC1200_DCFG_VSYNC_EN); + WRITE_VID32(SC1200_VID_MISC, misc | SC1200_DAC_POWER_DOWN); + break; + case CRT_SUSPEND: /* HSync:On VSync:Off */ + WRITE_VID32(SC1200_DISPLAY_CONFIG, (config & ~(SC1200_DCFG_VSYNC_EN + | SC1200_DCFG_DAC_BL_EN)) + | SC1200_DCFG_HSYNC_EN); + WRITE_VID32(SC1200_VID_MISC, misc | SC1200_DAC_POWER_DOWN); + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_enable + * + * This routine enables or disables the video overlay functionality. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_enable(int enable) +#else +int gfx_set_video_enable(int enable) +#endif +{ + unsigned long vcfg; + + /* WAIT FOR VERTICAL BLANK TO START */ + /* Otherwise a glitch can be observed. */ + + if (gfx_test_timing_active()) + { + if (!gfx_test_vertical_active()) + { + while(!gfx_test_vertical_active()); + } + while(gfx_test_vertical_active()); + } + + vcfg = READ_VID32(SC1200_VIDEO_CONFIG); + if (enable) + { + /* ENABLE SC1200 VIDEO OVERLAY */ + + vcfg |= SC1200_VCFG_VID_EN; + WRITE_VID32(SC1200_VIDEO_CONFIG, vcfg); + } + else + { + /* DISABLE SC1200 VIDEO OVERLAY */ + + vcfg &= ~SC1200_VCFG_VID_EN; + WRITE_VID32(SC1200_VIDEO_CONFIG, vcfg); + } + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_format + * + * Sets input video format type, to one of the YUV formats or to RGB. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_format(unsigned long format) +#else +int gfx_set_video_format(unsigned long format) +#endif +{ + unsigned long ctrl, vcfg = 0; + + /* SET THE SC1200 VIDEO INPUT FORMAT */ + + vcfg = READ_VID32(SC1200_VIDEO_CONFIG); + ctrl = READ_VID32(SC1200_VID_ALPHA_CONTROL); + ctrl &= ~(SC1200_VIDEO_INPUT_IS_RGB); + vcfg &= ~(SC1200_VCFG_VID_INP_FORMAT | SC1200_VCFG_4_2_0_MODE); + switch(format) + { + case VIDEO_FORMAT_UYVY: + vcfg |= SC1200_VCFG_UYVY_FORMAT; + break; + case VIDEO_FORMAT_YUYV: + vcfg |= SC1200_VCFG_YUYV_FORMAT; + break; + case VIDEO_FORMAT_Y2YU: + vcfg |= SC1200_VCFG_Y2YU_FORMAT; + break; + case VIDEO_FORMAT_YVYU: + vcfg |= SC1200_VCFG_YVYU_FORMAT; + break; + case VIDEO_FORMAT_Y0Y1Y2Y3: + vcfg |= SC1200_VCFG_UYVY_FORMAT; + vcfg |= SC1200_VCFG_4_2_0_MODE; + break; + case VIDEO_FORMAT_Y3Y2Y1Y0: + vcfg |= SC1200_VCFG_Y2YU_FORMAT; + vcfg |= SC1200_VCFG_4_2_0_MODE; + break; + case VIDEO_FORMAT_Y1Y0Y3Y2: + vcfg |= SC1200_VCFG_YUYV_FORMAT; + vcfg |= SC1200_VCFG_4_2_0_MODE; + break; + case VIDEO_FORMAT_Y1Y2Y3Y0: + vcfg |= SC1200_VCFG_YVYU_FORMAT; + vcfg |= SC1200_VCFG_4_2_0_MODE; + break; + case VIDEO_FORMAT_RGB: + ctrl |= SC1200_VIDEO_INPUT_IS_RGB; + vcfg |= SC1200_VCFG_UYVY_FORMAT; + break; + case VIDEO_FORMAT_P2M_P2L_P1M_P1L: + ctrl |= SC1200_VIDEO_INPUT_IS_RGB; + vcfg |= SC1200_VCFG_Y2YU_FORMAT; + break; + case VIDEO_FORMAT_P1M_P1L_P2M_P2L: + ctrl |= SC1200_VIDEO_INPUT_IS_RGB; + vcfg |= SC1200_VCFG_YUYV_FORMAT; + break; + case VIDEO_FORMAT_P1M_P2L_P2M_P1L: + ctrl |= SC1200_VIDEO_INPUT_IS_RGB; + vcfg |= SC1200_VCFG_YVYU_FORMAT; + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + + /* ALWAYS DISABLE GRAPHICS CSC */ + /* This is enabled in the function gfx_set_color_space_YUV for */ + /* YUV blending on TV. */ + + ctrl &= ~SC1200_CSC_GFX_RGB_TO_YUV; + + if (ctrl & SC1200_VIDEO_INPUT_IS_RGB) + ctrl &= ~SC1200_CSC_VIDEO_YUV_TO_RGB; + else + ctrl |= SC1200_CSC_VIDEO_YUV_TO_RGB; + + WRITE_VID32(SC1200_VIDEO_CONFIG, vcfg); + WRITE_VID32(SC1200_VID_ALPHA_CONTROL, ctrl); + + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_size + * + * This routine specifies the size of the source data. It is used only + * to determine how much data to transfer per frame, and is not used to + * calculate the scaling value (that is handled by a separate routine). + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_size(unsigned short width, unsigned short height) +#else +int gfx_set_video_size(unsigned short width, unsigned short height) +#endif +{ + unsigned long size, vcfg; + + /* SET THE SC1200 VIDEO LINE SIZE */ + + vcfg = READ_VID32(SC1200_VIDEO_CONFIG); + vcfg &= ~(SC1200_VCFG_LINE_SIZE_LOWER_MASK | SC1200_VCFG_LINE_SIZE_UPPER); + size = (width >> 1); + vcfg |= (size & 0x00FF) << 8; + if (size & 0x0100) vcfg |= SC1200_VCFG_LINE_SIZE_UPPER; + WRITE_VID32(SC1200_VIDEO_CONFIG, vcfg); + + /* SET TOTAL VIDEO BUFFER SIZE IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + /* Add 1 line to bypass issue #803 */ + gfx_set_display_video_size(width, (unsigned short)(height + 2)); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_offset + * + * This routine sets the starting offset for the video buffer when only + * one offset needs to be specified. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_offset(unsigned long offset) +#else +int gfx_set_video_offset(unsigned long offset) +#endif +{ + /* SAVE VALUE FOR FUTURE CLIPPING OF THE TOP OF THE VIDEO WINDOW */ + + gfx_vid_offset = offset; + + /* SET VIDEO BUFFER OFFSET IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_offset(offset); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_upscale + * + * This routine sets the scale factor for the video overlay window. The + * size of the source and destination regions are specified in pixels. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_upscale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +#else +int gfx_set_video_upscale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +#endif +{ + unsigned long xscale, yscale; + + /* SAVE PARAMETERS (unless don't-care zero destination arguments are used) */ + /* These are needed for clipping the video window later. */ + + if (dstw != 0) { + gfx_vid_srcw = srcw; + gfx_vid_dstw = dstw; + } + if (dsth != 0) { + gfx_vid_srch = srch; + gfx_vid_dsth = dsth; + } + + /* CALCULATE SC1200 SCALE FACTORS */ + + if (dstw == 0) xscale = READ_VID32(SC1200_VIDEO_UPSCALE) & 0xffff; /* keep previous if don't-care argument */ + else if (dstw <= srcw) xscale = 0x2000l; /* horizontal downscaling is currently done in a separate function */ + else if ((srcw == 1) || (dstw == 1)) return GFX_STATUS_BAD_PARAMETER; + else xscale = (0x2000l * (srcw - 1l)) / (dstw - 1l); + + if (dsth == 0) yscale = (READ_VID32(SC1200_VIDEO_UPSCALE) & 0xffff0000) >> 16; /* keep previous if don't-care argument */ + else if (dsth <= srch) yscale = 0x2000l; /* No vertical downscaling in SC1200 so force to 1x if attempted */ + else if ((srch == 1) || (dsth == 1)) return GFX_STATUS_BAD_PARAMETER; + else yscale = (0x2000l * (srch - 1l)) / (dsth - 1l); + + WRITE_VID32(SC1200_VIDEO_UPSCALE, (yscale << 16) | xscale); + + /* CALL ROUTINE TO UPDATE WINDOW POSITION */ + /* This is required because the scale values effect the number of */ + /* source data pixels that need to be clipped, as well as the */ + /* amount of data that needs to be transferred. */ + + gfx_set_video_window(gfx_vid_xpos, gfx_vid_ypos, gfx_vid_width, gfx_vid_height); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_scale + * + * This routine sets the scale factor for the video overlay window. The + * size of the source and destination regions are specified in pixels. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +#else +int gfx_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +#endif +{ + return gfx_set_video_upscale(srcw, srch, dstw, dsth); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_downscale_config + * + * This routine sets the downscale type and factor for the video overlay window. + * Note: No downscaling support for RGB565 and YUV420 video formats. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_downscale_config(unsigned short type, unsigned short m) +#else +int gfx_set_video_downscale_config(unsigned short type, unsigned short m) +#endif +{ + unsigned long downscale; + + if ((m < 1) || (m > 16)) return GFX_STATUS_BAD_PARAMETER; + + downscale = READ_VID32(SC1200_VIDEO_DOWNSCALER_CONTROL); + downscale &= ~(SC1200_VIDEO_DOWNSCALE_FACTOR_MASK | SC1200_VIDEO_DOWNSCALE_TYPE_MASK); + downscale |= ((m - 1l) << SC1200_VIDEO_DOWNSCALE_FACTOR_POS); + switch(type) + { + case VIDEO_DOWNSCALE_KEEP_1_OF: + downscale |= SC1200_VIDEO_DOWNSCALE_TYPE_A; + break; + case VIDEO_DOWNSCALE_DROP_1_OF: + downscale |= SC1200_VIDEO_DOWNSCALE_TYPE_B; + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + WRITE_VID32(SC1200_VIDEO_DOWNSCALER_CONTROL, downscale); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_downscale_coefficients + * + * This routine sets the downscale filter coefficients. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_downscale_coefficients(unsigned short coef1, unsigned short coef2, + unsigned short coef3, unsigned short coef4) +#else +int gfx_set_video_downscale_coefficients(unsigned short coef1, unsigned short coef2, + unsigned short coef3, unsigned short coef4) +#endif +{ + if ((coef1 + coef2 + coef3 + coef4) != 16) + return GFX_STATUS_BAD_PARAMETER; + + WRITE_VID32(SC1200_VIDEO_DOWNSCALER_COEFFICIENTS, ((unsigned long)coef1 << SC1200_VIDEO_DOWNSCALER_COEF1_POS) | + ((unsigned long)coef2 << SC1200_VIDEO_DOWNSCALER_COEF2_POS) | + ((unsigned long)coef3 << SC1200_VIDEO_DOWNSCALER_COEF3_POS) | + ((unsigned long)coef4 << SC1200_VIDEO_DOWNSCALER_COEF4_POS)); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_downscale_enable + * + * This routine enables or disables downscaling for the video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_downscale_enable(int enable) +#else +int gfx_set_video_downscale_enable(int enable) +#endif +{ + unsigned long downscale; + + downscale = READ_VID32(SC1200_VIDEO_DOWNSCALER_CONTROL); + downscale &= ~SC1200_VIDEO_DOWNSCALE_ENABLE; + if (enable) + downscale |= SC1200_VIDEO_DOWNSCALE_ENABLE; + WRITE_VID32(SC1200_VIDEO_DOWNSCALER_CONTROL, downscale); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_window + * + * This routine sets the position and size of the video overlay window. The + * y position is specified in screen relative coordinates, and may be negative. + * The size of destination region is specified in pixels. The line size + * indicates the number of bytes of source data per scanline. + * For the effect of negative x values, call the function + * gfx_set_video_left_crop(). + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_window(short x, short y, unsigned short w, unsigned short h) +#else +int gfx_set_video_window(short x, short y, unsigned short w, unsigned short h) +#endif +{ + unsigned long control; + unsigned long hadjust, vadjust; + unsigned long xstart, ystart, xend, yend; + + /* For left cropping call the function gfx_set_video_left_crop() */ + + if (x < 0) + return GFX_STATUS_BAD_PARAMETER; + + /* SAVE PARAMETERS */ + /* These are needed to call this routine if the scale value changes. */ + /* In the case of SC1200 they are also needed for restoring when video is re-enabled */ + + gfx_vid_xpos = x; + gfx_vid_ypos = y; + gfx_vid_width = w; + gfx_vid_height = h; + + /* GET ADJUSTMENT VALUES */ + /* Use routines to abstract version of display controller. */ + + hadjust = gfx_get_htotal() - gfx_get_hsync_end() - 14l; + vadjust = gfx_get_vtotal() - gfx_get_vsync_end() + 1l; + + /* HORIZONTAL START */ + + xstart = (unsigned long)x + hadjust; + + /* HORIZONTAL END */ + /* End positions in register are non-inclusive (one more than the actual end) */ + + if ((x + w) < gfx_get_hactive()) + xend = (unsigned long)x + (unsigned long)w + hadjust; + else /* right clipping needed */ + xend = (unsigned long)gfx_get_hactive() + hadjust; + + /* VERTICAL START */ + + ystart = (unsigned long)y + vadjust; + + /* VERTICAL END */ + + if ((y + h) < gfx_get_vactive()) + yend = (unsigned long)y + (unsigned long)h + vadjust; + else /* bottom clipping needed */ + yend = (unsigned long)gfx_get_vactive() + vadjust; + + /* SET VIDEO LINE INVERT BIT */ + + control = READ_VID32(SC1200_VID_ALPHA_CONTROL); + if (y & 0x1) + WRITE_VID32(SC1200_VID_ALPHA_CONTROL, control | SC1200_VIDEO_LINE_OFFSET_ODD); + else + WRITE_VID32(SC1200_VID_ALPHA_CONTROL, control & ~SC1200_VIDEO_LINE_OFFSET_ODD); + + /* SET VIDEO POSITION */ + + WRITE_VID32(SC1200_VIDEO_X_POS, (xend << 16) | xstart); + WRITE_VID32(SC1200_VIDEO_Y_POS, (yend << 16) | ystart); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_left_crop + * + * This routine sets the number of pixels which will be cropped from the + * beginning of each video line. The video window will begin to display only + * from the pixel following the cropped pixels, and the cropped pixels + * will be ignored. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_left_crop(unsigned short x) +#else +int gfx_set_video_left_crop(unsigned short x) +#endif +{ + unsigned long vcfg, initread; + + /* CLIPPING ON LEFT */ + /* Adjust initial read for scale, checking for divide by zero */ + + if (gfx_vid_dstw) + initread = (unsigned long)x * gfx_vid_srcw / gfx_vid_dstw; + else initread = 0l; + + /* SET INITIAL READ ADDRESS */ + + vcfg = READ_VID32(SC1200_VIDEO_CONFIG); + vcfg &= ~SC1200_VCFG_INIT_READ_MASK; + vcfg |= (initread << 15) & SC1200_VCFG_INIT_READ_MASK; + WRITE_VID32(SC1200_VIDEO_CONFIG, vcfg); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_color_key + * + * This routine specifies the color key value and mask for the video overlay + * hardware. To disable color key, the color and mask should both be set to + * zero. The hardware uses the color key in the following equation: + * + * ((source data) & (color key mask)) == ((color key) & (color key mask)) + * + * If "graphics" is set to TRUE, the source data is graphics, and color key + * is an RGB value. If "graphics" is set to FALSE, the source data is the video, + * and color key is a YUV value. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_color_key(unsigned long key, unsigned long mask, + int graphics) +#else +int gfx_set_video_color_key(unsigned long key, unsigned long mask, + int graphics) +#endif +{ + unsigned long dcfg = 0; + + /* SET SC1200 COLOR KEY VALUE */ + + WRITE_VID32(SC1200_VIDEO_COLOR_KEY, key); + WRITE_VID32(SC1200_VIDEO_COLOR_MASK, mask); + + /* SELECT GRAPHICS OR VIDEO DATA TO COMPARE TO THE COLOR KEY */ + + dcfg = READ_VID32(SC1200_DISPLAY_CONFIG); + if (graphics & 0x01) dcfg &= ~SC1200_DCFG_VG_CK; + else dcfg |= SC1200_DCFG_VG_CK; + WRITE_VID32(SC1200_DISPLAY_CONFIG, dcfg); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_filter + * + * This routine enables or disables the video overlay filters. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_filter(int xfilter, int yfilter) +#else +int gfx_set_video_filter(int xfilter, int yfilter) +#endif +{ + unsigned long vcfg = 0; + + /* ENABLE OR DISABLE SC1200 VIDEO OVERLAY FILTERS */ + + vcfg = READ_VID32(SC1200_VIDEO_CONFIG); + vcfg &= ~(SC1200_VCFG_X_FILTER_EN | SC1200_VCFG_Y_FILTER_EN); + if (xfilter) vcfg |= SC1200_VCFG_X_FILTER_EN; + if (yfilter) vcfg |= SC1200_VCFG_Y_FILTER_EN; + WRITE_VID32(SC1200_VIDEO_CONFIG, vcfg); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette + * + * This routine loads the video hardware palette. If a NULL pointer is + * specified, the palette is bypassed (for SC1200, this means loading the + * palette with identity values). + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_palette(unsigned long *palette) +#else +int gfx_set_video_palette(unsigned long *palette) +#endif +{ + unsigned long i, entry; + unsigned long dcfg, misc; + + /* WAIT FOR VERTICAL BLANK TO END */ + /* Otherwise palette will not be written properly. */ + + if (gfx_test_timing_active()) + { + if (gfx_test_vertical_active()) + { + while(gfx_test_vertical_active()); + } + while(!gfx_test_vertical_active()); + } + + /* LOAD SC1200 VIDEO PALETTE */ + + WRITE_VID32(SC1200_PALETTE_ADDRESS, 0); + for (i = 0; i < 256; i++) + { + if (palette) entry = palette[i]; + else entry = gfx_gamma_ram_1200[i] << 8; + WRITE_VID32(SC1200_PALETTE_DATA, entry); + } + + /* ENABLE THE VIDEO PALETTE */ + /* Ensure that the video palette has an effect by routing video data */ + /* through the palette RAM and clearing the 'Bypass Both' bit. */ + + dcfg = READ_VID32 (SC1200_DISPLAY_CONFIG); + misc = READ_VID32 (SC1200_VID_MISC); + + dcfg |= SC1200_DCFG_GV_PAL_BYP; + misc &= ~SC1200_GAMMA_BYPASS_BOTH; + + WRITE_VID32 (SC1200_DISPLAY_CONFIG, dcfg); + WRITE_VID32 (SC1200_VID_MISC, misc); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette_entry + * + * This routine loads a single entry of the video hardware palette. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_palette_entry(unsigned long index, unsigned long palette) +#else +int gfx_set_video_palette_entry(unsigned long index, unsigned long palette) +#endif +{ + unsigned long dcfg, misc; + + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + /* WAIT FOR VERTICAL BLANK TO END */ + /* Otherwise palette will not be written properly. */ + + if (gfx_test_timing_active()) + { + if (gfx_test_vertical_active()) + { + while(gfx_test_vertical_active()); + } + while(!gfx_test_vertical_active()); + } + + /* SET A SINGLE ENTRY */ + + WRITE_VID32(SC1200_PALETTE_ADDRESS, index); + WRITE_VID32(SC1200_PALETTE_DATA, palette); + + /* ENABLE THE VIDEO PALETTE */ + /* Ensure that the video palette has an effect by routing video data */ + /* through the palette RAM and clearing the 'Bypass Both' bit. */ + + dcfg = READ_VID32 (SC1200_DISPLAY_CONFIG); + misc = READ_VID32 (SC1200_VID_MISC); + + dcfg |= SC1200_DCFG_GV_PAL_BYP; + misc &= ~SC1200_GAMMA_BYPASS_BOTH; + + WRITE_VID32 (SC1200_DISPLAY_CONFIG, dcfg); + WRITE_VID32 (SC1200_VID_MISC, misc); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette_bypass + * + * This routine enables/disables the pallete RAM bypass. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_palette_bypass (int enable) +#else +int gfx_set_video_palette_bypass (int enable) +#endif +{ + unsigned long misc; + + misc = READ_VID32 (SC1200_VID_MISC); + + if (enable) misc |= SC1200_GAMMA_BYPASS_BOTH; + else misc &= ~SC1200_GAMMA_BYPASS_BOTH; + + WRITE_VID32 (SC1200_VID_MISC, misc); + + return 0; +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_request() + * + * This routine sets the horizontal (pixel) and vertical (line) video request + * values. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_request(short x, short y) +#else +int gfx_set_video_request(short x, short y) +#endif +{ + /* SET SC1200 VIDEO REQUEST */ + + x += gfx_get_htotal() - gfx_get_hsync_end() - 2; + y += gfx_get_vtotal() - gfx_get_vsync_end() + 1; + + if ((x < 0) || (x > SC1200_VIDEO_REQUEST_MASK) || + (y < 0) || (y > SC1200_VIDEO_REQUEST_MASK)) + return GFX_STATUS_BAD_PARAMETER; + + WRITE_VID32(SC1200_VIDEO_REQUEST, ((unsigned long)x << SC1200_VIDEO_X_REQUEST_POS) | + ((unsigned long)y << SC1200_VIDEO_Y_REQUEST_POS)); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_source() + * + * This routine sets the video source to either memory or Direct VIP. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_source(VideoSourceType source) +#else +int gfx_set_video_source(VideoSourceType source) +#endif +{ + unsigned long display_mode; + display_mode = READ_VID32(SC1200_VIDEO_DISPLAY_MODE); + + /* SET SC1200 VIDEO SOURCE */ + switch (source) + { + case VIDEO_SOURCE_MEMORY: + WRITE_VID32(SC1200_VIDEO_DISPLAY_MODE, (display_mode & ~SC1200_VIDEO_SOURCE_MASK) | SC1200_VIDEO_SOURCE_GX1); + break; + case VIDEO_SOURCE_DVIP: + WRITE_VID32(SC1200_VIDEO_DISPLAY_MODE, (display_mode & ~SC1200_VIDEO_SOURCE_MASK) | SC1200_VIDEO_SOURCE_DVIP); + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_vbi_source() + * + * This routine sets the vbi source to either memory or Direct VIP. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_vbi_source(VbiSourceType source) +#else +int gfx_set_vbi_source(VbiSourceType source) +#endif +{ + unsigned long display_mode; + display_mode = READ_VID32(SC1200_VIDEO_DISPLAY_MODE); + + /* SET SC1200 VBI SOURCE */ + switch (source) + { + case VBI_SOURCE_MEMORY: + WRITE_VID32(SC1200_VIDEO_DISPLAY_MODE, (display_mode & ~SC1200_VBI_SOURCE_MASK) | SC1200_VBI_SOURCE_GX1); + break; + case VBI_SOURCE_DVIP: + WRITE_VID32(SC1200_VIDEO_DISPLAY_MODE, (display_mode & ~SC1200_VBI_SOURCE_MASK) | SC1200_VBI_SOURCE_DVIP); + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_vbi_lines() + * + * This routine sets the VBI lines to pass to the TV encoder. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_vbi_lines(unsigned long even, unsigned long odd) +#else +int gfx_set_vbi_lines(unsigned long even, unsigned long odd) +#endif +{ + /* SET SC1200 VBI LINES */ + WRITE_VID32(SC1200_VIDEO_EVEN_VBI_LINE_ENABLE, even & SC1200_VIDEO_VBI_LINE_ENABLE_MASK); + WRITE_VID32(SC1200_VIDEO_ODD_VBI_LINE_ENABLE, odd & SC1200_VIDEO_VBI_LINE_ENABLE_MASK); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_vbi_total() + * + * This routine sets the total number of VBI bytes for each field. + * The total is needed when both VBI and active video are received from memory. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_vbi_total(unsigned long even, unsigned long odd) +#else +int gfx_set_vbi_total(unsigned long even, unsigned long odd) +#endif +{ + /* SET SC1200 VBI TOTAL */ + WRITE_VID32(SC1200_VIDEO_EVEN_VBI_TOTAL_COUNT, even & SC1200_VIDEO_VBI_TOTAL_COUNT_MASK); + WRITE_VID32(SC1200_VIDEO_ODD_VBI_TOTAL_COUNT, odd & SC1200_VIDEO_VBI_TOTAL_COUNT_MASK); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_interlaced() + * + * This routine configures the video processor video overlay mode to be + * interlaced YUV. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_interlaced(int enable) +#else +int gfx_set_video_interlaced(int enable) +#endif +{ + unsigned long control; + control = READ_VID32(SC1200_VID_ALPHA_CONTROL); + /* SET INTERLACED VIDEO */ + if (enable) + WRITE_VID32(SC1200_VID_ALPHA_CONTROL, control | SC1200_VIDEO_IS_INTERLACED); + else + WRITE_VID32(SC1200_VID_ALPHA_CONTROL, control & ~SC1200_VIDEO_IS_INTERLACED); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_color_space_YUV() + * + * This routine configures the video processor to process graphics and video + * in either YUV or RGB color space. The mode should be set to tune image + * quality. + * Setting "enable" to TRUE improves image quality on TV, + * but in this mode colors on CRT will not be correct. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_color_space_YUV(int enable) +#else +int gfx_set_color_space_YUV(int enable) +#endif +{ + unsigned long control; + control = READ_VID32(SC1200_VID_ALPHA_CONTROL); + + /* SET SC1200 VIDEO COLOR SPACE TO YUV OR RGB */ + + if (enable) + { + /* ENABLE YUV BLENDING */ + /* YUV blending cannot be enabled in RGB video formats */ + + control |= SC1200_CSC_GFX_RGB_TO_YUV; /* Convert graphics to YUV */ + control &= ~SC1200_CSC_VIDEO_YUV_TO_RGB; /* Leave video in YUV */ + + if (control & SC1200_VIDEO_INPUT_IS_RGB) + return(GFX_STATUS_UNSUPPORTED); /* Can't convert video from RGB to YUV */ + } + else + { + /* RGB BLENDING */ + + control &= ~SC1200_CSC_GFX_RGB_TO_YUV; /* Leave graphics in RGB */ + if (control & SC1200_VIDEO_INPUT_IS_RGB) + control &= ~SC1200_CSC_VIDEO_YUV_TO_RGB; /* Leave video in RGB */ + else + control |= SC1200_CSC_VIDEO_YUV_TO_RGB; /* Convert video to RGB */ + } + WRITE_VID32(SC1200_VID_ALPHA_CONTROL, control); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_vertical_scaler_offset() + * + * This routine sets the value by which the odd frame is shifted with respect + * to the even frame. This is useful for de-interlacing in Bob method, by + * setting the shift value to be one line. + * If offset is 0, no shifting occurs. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_vertical_scaler_offset(char offset) +#else +int gfx_set_vertical_scaler_offset(char offset) +#endif +{ + unsigned long control; + control = READ_VID32(SC1200_VID_ALPHA_CONTROL); + if (offset == 1) { + control &= ~SC1200_VERTICAL_SCALER_SHIFT_MASK; /* Clear shifting value */ + control |= SC1200_VERTICAL_SCALER_SHIFT_INIT; /* Set shifting value */ + control |= SC1200_VERTICAL_SCALER_SHIFT_EN; /* Enable odd frame shifting */ + } else if (offset == 0) { + control &= ~SC1200_VERTICAL_SCALER_SHIFT_EN; /* No shifting occurs */ + control &= ~SC1200_VERTICAL_SCALER_SHIFT_MASK; /* Clear shifting value */ + } + else + return(GFX_STATUS_BAD_PARAMETER); /* TODO: how to program other values ? */ + WRITE_VID32(SC1200_VID_ALPHA_CONTROL, control); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_top_line_in_odd() + * + * This routine sets the field in which the top line of input video resides. + * If enable is "0", this is the even field (default). [not to be confused + * with the odd field being the top field on TV]. + * If enable is "1", this is the odd field. + * Use enable "1" for input devices whose field indication is reversed from + * normal, i.e. an indication of "odd" field is given for even field data, + * and vice versa. + * This setting affects the video processor only when it is in either interlaced + * or Bob (scaler offset active) modes. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_top_line_in_odd(int enable) +#else +int gfx_set_top_line_in_odd(int enable) +#endif +{ + unsigned long control; + control = READ_VID32(SC1200_VID_ALPHA_CONTROL); + if (enable) + control |= SC1200_TOP_LINE_IN_ODD; /* Set shifting value */ + else + control &= ~SC1200_TOP_LINE_IN_ODD; /* No shifting occurs */ + WRITE_VID32(SC1200_VID_ALPHA_CONTROL, control); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_genlock_delay() + * + * This routine sets the delay between VIP VSYNC and display controller VSYNC. + * The delay is in 27 MHz clocks. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_genlock_delay(unsigned long delay) +#else +int gfx_set_genlock_delay(unsigned long delay) +#endif +{ + /* SET SC1200 GENLOCK DELAY */ + WRITE_VID32(SC1200_GENLOCK_DELAY, delay & SC1200_GENLOCK_DELAY_MASK); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_genlock_enable() + * + * This routine sets and configures the genlock according to the flags parameter. + * Flags value of 0 disables genlock and resets its configuration. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_genlock_enable(int flags) +#else +int gfx_set_genlock_enable(int flags) +#endif +{ + unsigned long genlock = 0; + + if (flags) + { + /* SET SC1200 GENLOCK CONFIGURATION */ + if (flags & GENLOCK_SINGLE) genlock |= SC1200_GENLOCK_SINGLE_ENABLE; + if (flags & GENLOCK_FIELD_SYNC) genlock |= SC1200_GENLOCK_FIELD_SYNC_ENABLE; + if (flags & GENLOCK_CONTINUOUS) genlock |= SC1200_GENLOCK_CONTINUOUS_ENABLE; + if (flags & GENLOCK_SYNCED_EDGE_FALLING) genlock |= SC1200_GENLOCK_GX_VSYNC_FALLING_EDGE; + if (flags & GENLOCK_SYNCING_EDGE_FALLING) genlock |= SC1200_GENLOCK_VIP_VSYNC_FALLING_EDGE; + if (flags & GENLOCK_TIMEOUT) genlock |= SC1200_GENLOCK_TIMEOUT_ENABLE; + if (flags & GENLOCK_TVENC_RESET_EVEN_FIELD) genlock |= SC1200_GENLOCK_TVENC_RESET_EVEN_FIELD; + if (flags & GENLOCK_TVENC_RESET_BEFORE_DELAY) genlock |= SC1200_GENLOCK_TVENC_RESET_BEFORE_DELAY; + if (flags & GENLOCK_TVENC_RESET) genlock |= SC1200_GENLOCK_TVENC_RESET_ENABLE; + if (flags & GENLOCK_SYNC_TO_TVENC) genlock |= SC1200_GENLOCK_SYNC_TO_TVENC; + } + WRITE_VID32(SC1200_GENLOCK, genlock); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_cursor() + * + * This routine configures the video hardware cursor. + * If the "mask"ed bits in the graphics pixel match "key", then either "color1" + * or "color2" will be used for this pixel, according to the value of bit + * number "select_color2" of the graphics pixel. + * + * key - 24 bit RGB value + * mask - 24 bit mask + * color1, color2 - RGB or YUV, depending on the current color space conversion + * select_color2 - value between 0 to 23 + * + * To disable match, a "mask" and "key" value of 0xffffff should be set, + * because the graphics pixels incoming to the video processor have maximum 16 + * bits set (0xF8FCF8). + * + * This feature is useful for disabling alpha blending of the cursor. + * Otherwise cursor image would be blurred (or completely invisible if video + * alpha is maximum value). + * Note: the cursor pixel replacements take place both inside and outside the + * video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_video_cursor(unsigned long key, unsigned long mask, unsigned short select_color2, + unsigned long color1, unsigned long color2) +#else +int gfx_set_video_cursor(unsigned long key, unsigned long mask, unsigned short select_color2, + unsigned long color1, unsigned long color2) +#endif +{ + if (select_color2 > SC1200_CURSOR_COLOR_BITS) return GFX_STATUS_BAD_PARAMETER; + key = (key & SC1200_COLOR_MASK) | ((unsigned long)select_color2 << SC1200_CURSOR_COLOR_KEY_OFFSET_POS); + WRITE_VID32(SC1200_CURSOR_COLOR_KEY, key); + WRITE_VID32(SC1200_CURSOR_COLOR_MASK, mask); + WRITE_VID32(SC1200_CURSOR_COLOR_1, color1); + WRITE_VID32(SC1200_CURSOR_COLOR_2, color2); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_enable + * + * This routine enables or disables the currently selected alpha region. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_alpha_enable(int enable) +#else +int gfx_set_alpha_enable(int enable) +#endif +{ + unsigned long address = 0, value = 0; + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = SC1200_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 4); + value = READ_VID32(address); + if (enable) value |= (SC1200_ACTRL_WIN_ENABLE | SC1200_ACTRL_LOAD_ALPHA); + else value &= ~(SC1200_ACTRL_WIN_ENABLE); + WRITE_VID32(address, value); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_window + * + * This routine sets the size of the currently selected alpha region. + * Note: "x" and "y" are signed to enable using negative values needed for + * implementing workarounds of hardware issues. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_alpha_window(short x, short y, + unsigned short width, unsigned short height) +#else +int gfx_set_alpha_window(short x, short y, + unsigned short width, unsigned short height) +#endif +{ + unsigned long address = 0; + + /* CHECK FOR CLIPPING */ + + if ((x + width) > gfx_get_hactive()) width = gfx_get_hactive() - x; + if ((y + height) > gfx_get_vactive()) height = gfx_get_vactive() - y; + + /* ADJUST POSITIONS */ + + x += gfx_get_htotal() - gfx_get_hsync_end() - 2; + y += gfx_get_vtotal() - gfx_get_vsync_end() + 1; + + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = SC1200_ALPHA_XPOS_1 + ((unsigned long)gfx_alpha_select << 4); + + /* End positions in register are non-inclusive (one more than the actual end) */ + + WRITE_VID32(address, (unsigned long) x | + ((unsigned long) (x + width) << 16)); + WRITE_VID32(address + 4l, (unsigned long) y | + ((unsigned long) (y + height) << 16)); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_value + * + * This routine sets the alpha value for the currently selected alpha + * region. It also specifies an increment/decrement value for fading. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_alpha_value(unsigned char alpha, char delta) +#else +int gfx_set_alpha_value(unsigned char alpha, char delta) +#endif +{ + unsigned long address = 0, value = 0; + unsigned char new_value = 0; + int loop = 1; + + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = SC1200_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 4); + value = READ_VID32(address); + value &= SC1200_ACTRL_WIN_ENABLE; /* keep only enable bit */ + value |= (unsigned long) alpha; + value |= (((unsigned long) delta) & 0xff) << 8; + value |= SC1200_ACTRL_LOAD_ALPHA; + WRITE_VID32(address, value); + + /* WORKAROUND FOR ISSUE #1187 */ + /* Need to verify that the alpha operation succeeded */ + + while (1) + { + /* WAIT FOR VERTICAL BLANK TO END */ + if (gfx_test_timing_active()) + { + if (gfx_test_vertical_active()) + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + } + new_value = (unsigned char)((READ_VID32(SC1200_ALPHA_WATCH) >> (gfx_alpha_select << 3)) & 0xff); + if (new_value == alpha) + return GFX_STATUS_OK; + if (++loop > 10) + return GFX_STATUS_ERROR; + WRITE_VID32(address, value); + } +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_priority + * + * This routine sets the priority of the currently selected alpha region. + * A higher value indicates a higher priority. + * Note: Priority of enabled alpha windows must be different. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_alpha_priority(int priority) +#else +int gfx_set_alpha_priority(int priority) +#endif +{ + unsigned long pos = 0, value = 0; + if (priority > 3) return(GFX_STATUS_BAD_PARAMETER); + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + value = READ_VID32(SC1200_VID_ALPHA_CONTROL); + pos = 16 + (gfx_alpha_select << 1); + value &= ~(0x03l << pos); + value |= (unsigned long)priority << pos; + WRITE_VID32(SC1200_VID_ALPHA_CONTROL, value); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_color + * + * This routine sets the color to be displayed inside the currently selected + * alpha window when there is a color key match (when the alpha color + * mechanism is enabled). + * "color" is a 24 bit RGB value (for RGB blending) or YUV value (for YUV blending). + * In Interlaced YUV blending mode, Y/2 value should be used. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_alpha_color(unsigned long color) +#else +int gfx_set_alpha_color(unsigned long color) +#endif +{ + unsigned long address = 0; + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = SC1200_ALPHA_COLOR_1 + ((unsigned long)gfx_alpha_select << 4); + + /* ONLY 24 VALID BITS */ + color &= 0xffffffl; + + /* KEEP UPPER BYTE UNCHANGED */ + WRITE_VID32(address, (color | (READ_VID32(address) & ~0xffffffl))); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_color_enable + * + * Enable or disable the color mechanism in the alpha window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_alpha_color_enable(int enable) +#else +int gfx_set_alpha_color_enable(int enable) +#endif +{ + unsigned long color; + unsigned long address = 0; + + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = SC1200_ALPHA_COLOR_1 + ((unsigned long)gfx_alpha_select << 4); + color = READ_VID32(address); + if (enable) + color |= SC1200_ALPHA_COLOR_ENABLE; + else + color &= ~SC1200_ALPHA_COLOR_ENABLE; + WRITE_VID32(address, color); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_no_ck_outside_alpha + * + * This function affects where inside the video window color key or chroma + * key comparison is done: + * If enable is TRUE, color/chroma key comparison is performed only inside + * the enabled alpha windows. Outside the (enabled) alpha windows, only video + * is displayed if color key is used, and only graphics is displayed if chroma + * key is used. + * If enable is FALSE, color/chroma key comparison is performed in all the + * video window area. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_no_ck_outside_alpha(int enable) +#else +int gfx_set_no_ck_outside_alpha(int enable) +#endif +{ + unsigned long value; + value = READ_VID32(SC1200_VID_ALPHA_CONTROL); + if (enable) + WRITE_VID32(SC1200_VID_ALPHA_CONTROL, value | SC1200_NO_CK_OUTSIDE_ALPHA); + else + WRITE_VID32(SC1200_VID_ALPHA_CONTROL, value & ~SC1200_NO_CK_OUTSIDE_ALPHA); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_macrovision_enable + * + * This routine enables or disables macrovision on the tv encoder output. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_set_macrovision_enable(int enable) +#else +int gfx_set_macrovision_enable(int enable) +#endif +{ + if (enable) + WRITE_VID32(SC1200_TVENC_MV_CONTROL, SC1200_TVENC_MV_ENABLE); + else + WRITE_VID32(SC1200_TVENC_MV_CONTROL, 0); + return(GFX_STATUS_OK); +} + +#define SC1200_VIDEO_PCI_44 0x80009444 + +/*--------------------------------------------------------------------------- + * gfx_disable_softvga + * + * Disables SoftVga. This function is only valid with VSA2, Returns 1 if + * SoftVga can be disabled; 0 if not. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_disable_softvga(void) +#else +int gfx_disable_softvga(void) +#endif +{ + unsigned long reg_val; + + /* get the current value */ + reg_val = gfx_pci_config_read(SC1200_VIDEO_PCI_44); + /* setting video PCI register 44 bit 0 to 1 disables SoftVga */ + reg_val |= 0x1; + gfx_pci_config_write(SC1200_VIDEO_PCI_44, reg_val); + + /* see if we set the bit and return the appropriate value */ + reg_val = gfx_pci_config_read(SC1200_VIDEO_PCI_44); + if((reg_val & 0x1) == 0x1) + return(1); + else + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_enable_softvga + * + * Enables SoftVga. This function is only valid with VSA2, Returns 1 if + * SoftVga can be enbled; 0 if not. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_enable_softvga(void) +#else +int gfx_enable_softvga(void) +#endif +{ + unsigned long reg_val; + + /* get the current value */ + reg_val = gfx_pci_config_read(SC1200_VIDEO_PCI_44); + /* clearing video PCI register 44 bit 0 enables SoftVga */ + gfx_pci_config_write(SC1200_VIDEO_PCI_44, reg_val & 0xfffffffel); + + /* see if we cleared the bit and return the appropriate value */ + reg_val = gfx_pci_config_read(SC1200_VIDEO_PCI_44); + if((reg_val & 0x1) == 0) + return(1); + else + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_clock_frequency + * + * This routine returns the current clock frequency in 16.16 format. + * It reads the current register value and finds the match in the table. + * If no match is found, this routine returns 0. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_clock_frequency(void) +#else +unsigned long gfx_get_clock_frequency(void) +#endif +{ + unsigned int index; + unsigned long value, mask; + mask = 0x007FFF0F; + value = READ_VID32(SC1200_VID_CLOCK_SELECT) & mask; + for (index = 0; index < NUM_SC1200_FREQUENCIES; index++) + { + if ((gfx_sc1200_clock_table[index].clock_select & mask) == value) + return(gfx_sc1200_clock_table[index].frequency); + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_max_video_width + * + * This routine returns the maximum theoretical video width for the current + * display mode. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_max_video_width(void) +#else +unsigned long gfx_get_max_video_width(void) +#endif +{ + /* RETURN MPEG2 MAXIMUM */ + + return 720; +} + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +#if GFX_READ_ROUTINES + +/*--------------------------------------------------------------------------- + * gfx_get_vsa2_softvga_enable + * + * This function returns the enable status of SoftVGA. It is valid + * only if VSAII is present. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_vsa2_softvga_enable(void) +#else +int gfx_get_vsa2_softvga_enable(void) +#endif +{ + unsigned long reg_val; + + reg_val = gfx_pci_config_read(SC1200_VIDEO_PCI_44); + if((reg_val & 0x1) == 0) + return(1); + else + return(0); + +} + +/*--------------------------------------------------------------------------- + * gfx_get_sync_polarities + * + * This routine returns the polarities of the sync pulses: + * Bit 0: Set if negative horizontal polarity. + * Bit 1: Set if negative vertical polarity. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_sync_polarities(void) +#else +int gfx_get_sync_polarities(void) +#endif +{ + int polarities = 0; + if (READ_VID32(SC1200_DISPLAY_CONFIG) & SC1200_DCFG_CRT_HSYNC_POL) polarities |= 1; + if (READ_VID32(SC1200_DISPLAY_CONFIG) & SC1200_DCFG_CRT_VSYNC_POL) polarities |= 2; + return(polarities); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_palette_entry + * + * This routine returns a single palette entry. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_video_palette_entry(unsigned long index, unsigned long *palette) +#else +int gfx_get_video_palette_entry(unsigned long index, unsigned long *palette) +#endif +{ + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + /* READ A SINGLE ENTRY */ + + WRITE_VID32 (SC1200_PALETTE_ADDRESS, index); + *palette = READ_VID32 (SC1200_PALETTE_DATA); + + return (GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_enable + * + * This routine returns the value "one" if video overlay is currently enabled, + * otherwise it returns the value "zero". + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_video_enable(void) +#else +int gfx_get_video_enable(void) +#endif +{ + if (READ_VID32(SC1200_VIDEO_CONFIG) & SC1200_VCFG_VID_EN) return(1); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_format + * + * This routine returns the current video overlay format. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_video_format(void) +#else +int gfx_get_video_format(void) +#endif +{ + unsigned long ctrl, vcfg; + + ctrl = READ_VID32(SC1200_VID_ALPHA_CONTROL); + vcfg = READ_VID32(SC1200_VIDEO_CONFIG); + + if (ctrl & SC1200_VIDEO_INPUT_IS_RGB) + { + switch (vcfg & SC1200_VCFG_VID_INP_FORMAT) + { + case SC1200_VCFG_UYVY_FORMAT: return VIDEO_FORMAT_RGB; + case SC1200_VCFG_Y2YU_FORMAT: return VIDEO_FORMAT_P2M_P2L_P1M_P1L; + case SC1200_VCFG_YUYV_FORMAT: return VIDEO_FORMAT_P1M_P1L_P2M_P2L; + case SC1200_VCFG_YVYU_FORMAT: return VIDEO_FORMAT_P1M_P2L_P2M_P1L; + } + } + + if (vcfg & SC1200_VCFG_4_2_0_MODE) + { + switch (vcfg & SC1200_VCFG_VID_INP_FORMAT) + { + case SC1200_VCFG_UYVY_FORMAT: return VIDEO_FORMAT_Y0Y1Y2Y3; + case SC1200_VCFG_Y2YU_FORMAT: return VIDEO_FORMAT_Y3Y2Y1Y0; + case SC1200_VCFG_YUYV_FORMAT: return VIDEO_FORMAT_Y1Y0Y3Y2; + case SC1200_VCFG_YVYU_FORMAT: return VIDEO_FORMAT_Y1Y2Y3Y0; + } + } + else + { + switch (vcfg & SC1200_VCFG_VID_INP_FORMAT) + { + case SC1200_VCFG_UYVY_FORMAT: return VIDEO_FORMAT_UYVY; + case SC1200_VCFG_Y2YU_FORMAT: return VIDEO_FORMAT_Y2YU; + case SC1200_VCFG_YUYV_FORMAT: return VIDEO_FORMAT_YUYV; + case SC1200_VCFG_YVYU_FORMAT: return VIDEO_FORMAT_YVYU; + } + } + return (GFX_STATUS_ERROR); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_src_size + * + * This routine returns the size of the source video overlay buffer. The + * return value is (height << 16) | width. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_video_src_size(void) +#else +unsigned long gfx_get_video_src_size(void) +#endif +{ + unsigned long width = 0, height = 0; + + /* DETERMINE SOURCE WIDTH FROM THE SC1200 VIDEO LINE SIZE */ + + width = (READ_VID32(SC1200_VIDEO_CONFIG) >> 7) & 0x000001FE; + if (READ_VID32(SC1200_VIDEO_CONFIG) & SC1200_VCFG_LINE_SIZE_UPPER) + width += 512l; + + if (width) + { + /* DETERMINE HEIGHT BY DIVIDING TOTAL SIZE BY WIDTH */ + /* Get total size from display controller - abtracted. */ + + height = gfx_get_display_video_size() / (width << 1); + } + return((height << 16) | width); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_line_size + * + * This routine returns the line size of the source video overlay buffer, in + * pixels. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_video_line_size(void) +#else +unsigned long gfx_get_video_line_size(void) +#endif +{ + unsigned long width = 0; + + /* DETERMINE SOURCE WIDTH FROM THE SC1200 VIDEO LINE SIZE */ + + width = (READ_VID32(SC1200_VIDEO_CONFIG) >> 7) & 0x000001FE; + if (READ_VID32(SC1200_VIDEO_CONFIG) & SC1200_VCFG_LINE_SIZE_UPPER) + width += 512l; + return(width); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_xclip + * + * This routine returns the number of bytes clipped on the left side of a + * video overlay line (skipped at beginning). + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_video_xclip(void) +#else +unsigned long gfx_get_video_xclip(void) +#endif +{ + unsigned long clip = 0; + + /* DETERMINE SOURCE WIDTH FROM THE SC1200 VIDEO LINE SIZE */ + + clip = (READ_VID32(SC1200_VIDEO_CONFIG) >> 14) & 0x000007FC; + return(clip); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_offset + * + * This routine returns the current offset for the video overlay buffer. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_video_offset(void) +#else +unsigned long gfx_get_video_offset(void) +#endif +{ + return(gfx_get_display_video_offset()); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_upscale + * + * This routine returns the scale factor for the video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_video_upscale(void) +#else +unsigned long gfx_get_video_upscale(void) +#endif +{ + return(READ_VID32(SC1200_VIDEO_UPSCALE)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_scale + * + * This routine returns the scale factor for the video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_video_scale(void) +#else +unsigned long gfx_get_video_scale(void) +#endif +{ + return gfx_get_video_upscale(); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_downscale_config + * + * This routine returns the current type and value of video downscaling. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_video_downscale_config(unsigned short *type, unsigned short *m) +#else +int gfx_get_video_downscale_config(unsigned short *type, unsigned short *m) +#endif +{ + unsigned long downscale; + + downscale = READ_VID32(SC1200_VIDEO_DOWNSCALER_CONTROL); + *m = (unsigned short)((downscale & SC1200_VIDEO_DOWNSCALE_FACTOR_MASK) >> SC1200_VIDEO_DOWNSCALE_FACTOR_POS) + 1; + + switch(downscale & SC1200_VIDEO_DOWNSCALE_TYPE_MASK) + { + case SC1200_VIDEO_DOWNSCALE_TYPE_A: + *type = VIDEO_DOWNSCALE_KEEP_1_OF; + break; + case SC1200_VIDEO_DOWNSCALE_TYPE_B: + *type = VIDEO_DOWNSCALE_DROP_1_OF; + break; + default: + return GFX_STATUS_ERROR; + break; + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_downscale_coefficients + * + * This routine returns the current video downscaling coefficients. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void sc1200_get_video_downscale_coefficients(unsigned short *coef1, unsigned short *coef2, + unsigned short *coef3, unsigned short *coef4) +#else +void gfx_get_video_downscale_coefficients(unsigned short *coef1, unsigned short *coef2, + unsigned short *coef3, unsigned short *coef4) +#endif +{ + unsigned long coef; + + coef = READ_VID32(SC1200_VIDEO_DOWNSCALER_COEFFICIENTS); + *coef1 = (unsigned short)((coef >> SC1200_VIDEO_DOWNSCALER_COEF1_POS) & SC1200_VIDEO_DOWNSCALER_COEF_MASK); + *coef2 = (unsigned short)((coef >> SC1200_VIDEO_DOWNSCALER_COEF2_POS) & SC1200_VIDEO_DOWNSCALER_COEF_MASK); + *coef3 = (unsigned short)((coef >> SC1200_VIDEO_DOWNSCALER_COEF3_POS) & SC1200_VIDEO_DOWNSCALER_COEF_MASK); + *coef4 = (unsigned short)((coef >> SC1200_VIDEO_DOWNSCALER_COEF4_POS) & SC1200_VIDEO_DOWNSCALER_COEF_MASK); + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_downscale_enable + * + * This routine returns 1 if video downscaling is currently enabled, + * or 0 if it is currently disabled. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void sc1200_get_video_downscale_enable(int *enable) +#else +void gfx_get_video_downscale_enable(int *enable) +#endif +{ + if (READ_VID32(SC1200_VIDEO_DOWNSCALER_CONTROL) & SC1200_VIDEO_DOWNSCALE_ENABLE) + *enable = 1; + else + *enable = 0; + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_dst_size + * + * This routine returns the size of the displayed video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_video_dst_size(void) +#else +unsigned long gfx_get_video_dst_size(void) +#endif +{ + unsigned long xsize, ysize; + + xsize = READ_VID32(SC1200_VIDEO_X_POS); + xsize = ((xsize >> 16) & 0x7FF) - (xsize & 0x7FF); + ysize = READ_VID32(SC1200_VIDEO_Y_POS); + ysize = ((ysize >> 16) & 0x7FF) - (ysize & 0x7FF); + return((ysize << 16) | xsize); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_position + * + * This routine returns the position of the video overlay window. The + * return value is (ypos << 16) | xpos. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_video_position(void) +#else +unsigned long gfx_get_video_position(void) +#endif +{ + unsigned long hadjust, vadjust; + unsigned long xpos, ypos; + + /* READ HARDWARE POSITION */ + + xpos = READ_VID32(SC1200_VIDEO_X_POS) & 0x000007FF; + ypos = READ_VID32(SC1200_VIDEO_Y_POS) & 0x000007FF; + + /* GET ADJUSTMENT VALUES */ + /* Use routines to abstract version of display controller. */ + + hadjust = (unsigned long)gfx_get_htotal() - (unsigned long)gfx_get_hsync_end() - 14l; + vadjust = (unsigned long)gfx_get_vtotal() - (unsigned long)gfx_get_vsync_end() + 1l; + xpos -= hadjust; + ypos -= vadjust; + return((ypos << 16) | (xpos & 0x0000FFFF)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key + * + * This routine returns the current video color key value. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_video_color_key(void) +#else +unsigned long gfx_get_video_color_key(void) +#endif +{ + return(READ_VID32(SC1200_VIDEO_COLOR_KEY)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key_mask + * + * This routine returns the current video color mask value. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_video_color_key_mask(void) +#else +unsigned long gfx_get_video_color_key_mask(void) +#endif +{ + return(READ_VID32(SC1200_VIDEO_COLOR_MASK)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key_src + * + * This routine returns 0 for video data compare, 1 for graphics data. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_video_color_key_src(void) +#else +int gfx_get_video_color_key_src(void) +#endif +{ + if (READ_VID32(SC1200_DISPLAY_CONFIG) & SC1200_DCFG_VG_CK) return(0); + return(1); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_filter + * + * This routine returns if the filters are currently enabled. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_video_filter(void) +#else +int gfx_get_video_filter(void) +#endif +{ + int retval = 0; + if (READ_VID32(SC1200_VIDEO_CONFIG) & SC1200_VCFG_X_FILTER_EN) + retval |= 1; + if (READ_VID32(SC1200_VIDEO_CONFIG) & SC1200_VCFG_Y_FILTER_EN) + retval |= 2; + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_request + * + * This routine returns the horizontal (pixel) and vertical (lines) video + * request values. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_video_request(short *x, short *y) +#else +int gfx_get_video_request(short *x, short *y) +#endif +{ + int request = 0; + request = (int)(READ_VID32(SC1200_VIDEO_REQUEST)); + *x = (request >> SC1200_VIDEO_X_REQUEST_POS) & SC1200_VIDEO_REQUEST_MASK; + *y = (request >> SC1200_VIDEO_Y_REQUEST_POS) & SC1200_VIDEO_REQUEST_MASK; + + *x -= gfx_get_htotal() - gfx_get_hsync_end() - 2; + *y -= gfx_get_vtotal() - gfx_get_vsync_end() + 1; + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_source + * + * This routine returns the current video source. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_video_source(VideoSourceType *source) +#else +int gfx_get_video_source(VideoSourceType *source) +#endif +{ + switch(READ_VID32(SC1200_VIDEO_DISPLAY_MODE) & SC1200_VIDEO_SOURCE_MASK) + { + case SC1200_VIDEO_SOURCE_GX1: + *source = VIDEO_SOURCE_MEMORY; + break; + case SC1200_VIDEO_SOURCE_DVIP: + *source = VIDEO_SOURCE_DVIP; + break; + default: + return GFX_STATUS_ERROR; + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vbi_source + * + * This routine returns the current vbi source. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_vbi_source(VbiSourceType *source) +#else +int gfx_get_vbi_source(VbiSourceType *source) +#endif +{ + switch(READ_VID32(SC1200_VIDEO_DISPLAY_MODE) & SC1200_VBI_SOURCE_MASK) + { + case SC1200_VBI_SOURCE_GX1: + *source = VBI_SOURCE_MEMORY; + break; + case SC1200_VBI_SOURCE_DVIP: + *source = VBI_SOURCE_DVIP; + break; + default: + return GFX_STATUS_ERROR; + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vbi_lines + * + * This routine returns the VBI lines which are sent to the TV encoder. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_vbi_lines(int odd) +#else +unsigned long gfx_get_vbi_lines(int odd) +#endif +{ + if (odd) return(READ_VID32(SC1200_VIDEO_ODD_VBI_LINE_ENABLE) & SC1200_VIDEO_VBI_LINE_ENABLE_MASK); + return(READ_VID32(SC1200_VIDEO_EVEN_VBI_LINE_ENABLE) & SC1200_VIDEO_VBI_LINE_ENABLE_MASK); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vbi_total + * + * This routine returns the total number of VBI bytes in the field. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_vbi_total(int odd) +#else +unsigned long gfx_get_vbi_total(int odd) +#endif +{ + if (odd) return(READ_VID32(SC1200_VIDEO_ODD_VBI_TOTAL_COUNT) & SC1200_VIDEO_VBI_TOTAL_COUNT_MASK); + return(READ_VID32(SC1200_VIDEO_EVEN_VBI_TOTAL_COUNT) & SC1200_VIDEO_VBI_TOTAL_COUNT_MASK); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_interlaced() + * + * This routine returns "1" if input video is currently in interlaced mode. + * "0" otherwise. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_video_interlaced(void) +#else +int gfx_get_video_interlaced(void) +#endif +{ + if (READ_VID32(SC1200_VID_ALPHA_CONTROL) & SC1200_VIDEO_IS_INTERLACED) + return(1); + else + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_color_space_YUV() + * + * This routine returns "1" if video processor color space mode is currently + * YUV. "0" otherwise. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_color_space_YUV(void) +#else +int gfx_get_color_space_YUV(void) +#endif +{ + unsigned long control; + control = READ_VID32(SC1200_VID_ALPHA_CONTROL); + + /* IS SC1200 VIDEO COLOR SPACE RGB OR CONVERTED TO RGB */ + if ((control & SC1200_VIDEO_INPUT_IS_RGB) || (control & SC1200_CSC_VIDEO_YUV_TO_RGB)) + return(0); + else + return(1); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vertical_scaler_offset() + * + * This routine sets "offset" to the value by which odd frames are shifted, + * if insert is enabled, and to 0 if no shifting occurs. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_vertical_scaler_offset(char *offset) +#else +int gfx_get_vertical_scaler_offset(char *offset) +#endif +{ + unsigned long control; + control = READ_VID32(SC1200_VID_ALPHA_CONTROL); + if (control & SC1200_VERTICAL_SCALER_SHIFT_EN) { + if ((control & SC1200_VERTICAL_SCALER_SHIFT_MASK) == SC1200_VERTICAL_SCALER_SHIFT_INIT) + *offset = 1; + else + return GFX_STATUS_ERROR; /* TODO: find the interpretation of other values */ + } else + *offset = 0; + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_genlock_delay + * + * This routine returns the genlock delay in 27 MHz clocks. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_get_genlock_delay(void) +#else +unsigned long gfx_get_genlock_delay(void) +#endif +{ + return(READ_VID32(SC1200_GENLOCK_DELAY) & SC1200_GENLOCK_DELAY_MASK); +} + +/*--------------------------------------------------------------------------- + * gfx_get_genlock_enable + * + * This routine returns "1" if genlock is currently enabled, "0" otherwise. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_genlock_enable(void) +#else +int gfx_get_genlock_enable(void) +#endif +{ + if (READ_VID32(SC1200_GENLOCK) & + (SC1200_GENLOCK_SINGLE_ENABLE | SC1200_GENLOCK_CONTINUOUS_ENABLE)) + return(1); + else + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_cursor() + * + * This routine configures the video hardware cursor. + * If the "mask"ed bits in the graphics pixel match "key", then either "color1" + * or "color2" will be used for this pixel, according to the value of the bit + * in offset "select_color2". + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_video_cursor(unsigned long *key, unsigned long *mask, unsigned short *select_color2, + unsigned long *color1, unsigned short *color2) +#else +int gfx_get_video_cursor(unsigned long *key, unsigned long *mask, unsigned short *select_color2, + unsigned long *color1, unsigned short *color2) +#endif +{ + *select_color2 = (unsigned short)(READ_VID32(SC1200_CURSOR_COLOR_KEY) >> SC1200_CURSOR_COLOR_KEY_OFFSET_POS); + *key = READ_VID32(SC1200_CURSOR_COLOR_KEY) & SC1200_COLOR_MASK; + *mask = READ_VID32(SC1200_CURSOR_COLOR_MASK) & SC1200_COLOR_MASK; + *color1 = READ_VID32(SC1200_CURSOR_COLOR_1) & SC1200_COLOR_MASK; + *color2 = (unsigned short)(READ_VID32(SC1200_CURSOR_COLOR_2) & SC1200_COLOR_MASK); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_read_crc + * + * This routine returns the hardware CRC value, which is used for automated + * testing. The value is like a checksum, but will change if pixels move + * locations. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long sc1200_read_crc(void) +#else +unsigned long gfx_read_crc(void) +#endif +{ + unsigned long crc = 0xFFFFFFFF; + if (gfx_test_timing_active()) + { + /* WAIT UNTIL ACTIVE DISPLAY */ + + while(!gfx_test_vertical_active()); + + /* RESET CRC DURING ACTIVE DISPLAY */ + + WRITE_VID32(SC1200_VID_CRC, 0); + WRITE_VID32(SC1200_VID_CRC, 1); + + /* WAIT UNTIL NOT ACTIVE, THEN ACTIVE, NOT ACTIVE, THEN ACTIVE */ + + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + crc = READ_VID32(SC1200_VID_CRC) >> 8; + } + return(crc); +} + +/*----------------------------------------------------------------------------- + * gfx_get_macrovision_enable + * + * This routine returns the value "one" if macrovision currently enabled in the + * TV encoder, otherwise it returns the value "zero". + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int sc1200_get_macrovision_enable(void) +#else +int gfx_get_macrovision_enable(void) +#endif +{ + if (READ_VID32(SC1200_TVENC_MV_CONTROL) == SC1200_TVENC_MV_ENABLE) return(1); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_enable + * + * This routine returns 1 if the selected alpha window is currently + * enabled, or 0 if it is currently disabled. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void sc1200_get_alpha_enable(int *enable) +#else +void gfx_get_alpha_enable(int *enable) +#endif +{ + unsigned long value = 0; + *enable = 0; + if (gfx_alpha_select <= 2) + { + value = READ_VID32(SC1200_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 4)); + if (value & SC1200_ACTRL_WIN_ENABLE) *enable = 1; + } + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_size + * + * This routine returns the size of the currently selected alpha region. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void sc1200_get_alpha_size(unsigned short *x, unsigned short *y, + unsigned short *width, unsigned short *height) +#else +void gfx_get_alpha_size(unsigned short *x, unsigned short *y, + unsigned short *width, unsigned short *height) +#endif +{ + unsigned long value = 0; + *x = 0; + *y = 0; + *width = 0; + *height = 0; + if (gfx_alpha_select <= 2) + { + value = READ_VID32(SC1200_ALPHA_XPOS_1 + ((unsigned long)gfx_alpha_select << 4)); + *x = (unsigned short) (value & 0x000007FF); + *width = (unsigned short) ((value >> 16) & 0x000007FF) - *x; + value = READ_VID32(SC1200_ALPHA_YPOS_1 + ((unsigned long)gfx_alpha_select << 4)); + *y = (unsigned short) (value & 0x000007FF); + *height = (unsigned short) ((value >> 16) & 0x000007FF) - *y; + } + *x -= gfx_get_htotal() - gfx_get_hsync_end() - 2; + *y -= gfx_get_vtotal() - gfx_get_vsync_end() + 1; + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_value + * + * This routine returns the alpha value and increment/decrement value of + * the currently selected alpha region. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void sc1200_get_alpha_value(unsigned char *alpha, char *delta) +#else +void gfx_get_alpha_value(unsigned char *alpha, char *delta) +#endif +{ + unsigned long value = 0; + *alpha = 0; + *delta = 0; + if (gfx_alpha_select <= 2) + { + value = READ_VID32(SC1200_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 4)); + *alpha = (unsigned char) (value & 0x00FF); + *delta = (char) ((value >> 8) & 0x00FF); + } + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_priority + * + * This routine returns the priority of the currently selected alpha region. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void sc1200_get_alpha_priority(int *priority) +#else +void gfx_get_alpha_priority(int *priority) +#endif +{ + unsigned long pos = 0, value = 0; + *priority = 0; + if (gfx_alpha_select <= 2) + { + value = READ_VID32(SC1200_VID_ALPHA_CONTROL); + pos = 16 + (gfx_alpha_select << 1); + *priority = (int) ((value >> pos) & 3); + } + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_color + * + * This routine returns the color register value for the currently selected + * alpha region. Bit 24 is set if the color register is enabled. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void sc1200_get_alpha_color(unsigned long *color) +#else +void gfx_get_alpha_color(unsigned long *color) +#endif +{ + *color = 0; + if (gfx_alpha_select <= 2) + { + *color = READ_VID32(SC1200_ALPHA_COLOR_1 + ((unsigned long)gfx_alpha_select << 4)); + } + return; +} + +#endif /* GFX_READ_ROUTINES */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/vid_5530.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/vid_5530.c 2005-12-14 11:28:47.000000000 -0700 @@ -0,0 +1,1271 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to control the CS5530 video overlay hardware. + * */ + + + +/*---------------------------------------------------------------------------- + * CS5530 PLL TABLE + *---------------------------------------------------------------------------- + */ +typedef struct tagCS5530PLLENTRY +{ + long frequency; /* 16.16 fixed point frequency */ + unsigned long pll_value; /* associated register value */ +} CS5530PLLENTRY; + +CS5530PLLENTRY CS5530_PLLtable[] = { + { 0x00192CCC, 0x31C45801, }, /* 25.1750 */ + { 0x001C526E, 0x20E36802, }, /* 28.3220 */ + { 0x001F8000, 0x33915801, }, /* 31.5000 */ + { 0x00240000, 0x31EC4801, }, /* 36.0000 */ + { 0x00258000, 0x21E22801, }, /* 37.5000 */ + { 0x00280000, 0x33088801, }, /* 40.0000 */ + { 0x002CE666, 0x33E22801, }, /* 44.9000 */ + { 0x00318000, 0x336C4801, }, /* 49.5000 */ + { 0x00320000, 0x23088801, }, /* 50.0000 */ + { 0x00325999, 0x23088801, }, /* 50.3500 */ + { 0x00360000, 0x3708A801, }, /* 54.0000 */ + { 0x00384000, 0x23E36802, }, /* 56.2500 */ + { 0x0038643F, 0x23E36802, }, /* 56.3916 */ + { 0x0038A4DD, 0x23E36802, }, /* 56.6444 */ + { 0x003B0000, 0x37C45801, }, /* 59.0000 */ + { 0x003F0000, 0x23EC4801, }, /* 63.0000 */ + { 0x00410000, 0x37911801, }, /* 65.0000 */ + { 0x00438000, 0x37963803, }, /* 67.5000 */ + { 0x0046CCCC, 0x37058803, }, /* 70.8000 */ + { 0x00480000, 0x3710C805, }, /* 72.0000 */ + { 0x004B0000, 0x37E22801, }, /* 75.0000 */ + { 0x004EC000, 0x27915801, }, /* 78.7500 */ + { 0x00500000, 0x37D8D802, }, /* 80.0000 */ + { 0x0059CCCC, 0x27588802, }, /* 89.8000 */ + { 0x005E8000, 0x27EC4802, }, /* 94.5000 */ + { 0x00630000, 0x27AC6803, }, /* 99.0000 */ + { 0x00640000, 0x27088801, }, /* 100.0000 */ + { 0x006C0000, 0x2710C805, }, /* 108.0000 */ + { 0x00708000, 0x27E36802, }, /* 112.5000 */ + { 0x00820000, 0x27C58803, }, /* 130.0000 */ + { 0x00870000, 0x27316803, }, /* 135.0000 */ + { 0x009D8000, 0x2F915801, }, /* 157.5000 */ + { 0x00A20000, 0x2F08A801, }, /* 162.0000 */ + { 0x00AF0000, 0x2FB11802, }, /* 175.0000 */ + { 0x00BD0000, 0x2FEC4802, }, /* 189.0000 */ + { 0x00CA0000, 0x2F963803, }, /* 202.0000 */ + { 0x00E80000, 0x2FB1B802, }, /* 232.0000 */ +}; + +#define NUM_CS5530_FREQUENCIES sizeof(CS5530_PLLtable)/sizeof(CS5530PLLENTRY) + +/*--------------------------------------------------------------------------- + * gfx_set_crt_enable + * + * This routine enables or disables the CRT output from the video processor. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_crt_enable(int enable) +#else +int gfx_set_crt_enable(int enable) +#endif +{ + unsigned long config; + config = READ_VID32(CS5530_DISPLAY_CONFIG); + + switch (enable) + { + case CRT_DISABLE: /* Disable everything */ + + WRITE_VID32(CS5530_DISPLAY_CONFIG, config & ~(CS5530_DCFG_DIS_EN | CS5530_DCFG_HSYNC_EN + | CS5530_DCFG_VSYNC_EN | CS5530_DCFG_DAC_BL_EN + | CS5530_DCFG_DAC_PWDNX)); + break; + + case CRT_ENABLE: /* Enable CRT display, including display logic */ + + WRITE_VID32(CS5530_DISPLAY_CONFIG, config | CS5530_DCFG_DIS_EN | CS5530_DCFG_HSYNC_EN + | CS5530_DCFG_VSYNC_EN | CS5530_DCFG_DAC_BL_EN + | CS5530_DCFG_DAC_PWDNX); + break; + + case CRT_STANDBY: /* HSync:Off VSync:On */ + + WRITE_VID32(CS5530_DISPLAY_CONFIG, (config & ~(CS5530_DCFG_DIS_EN | CS5530_DCFG_HSYNC_EN + | CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWDNX)) + | CS5530_DCFG_VSYNC_EN ); + break; + + case CRT_SUSPEND: /* HSync:On VSync:Off */ + + WRITE_VID32(CS5530_DISPLAY_CONFIG, (config & ~(CS5530_DCFG_DIS_EN | CS5530_DCFG_VSYNC_EN + | CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWDNX)) + | CS5530_DCFG_HSYNC_EN ); + break; + + default: + return (GFX_STATUS_BAD_PARAMETER); + } + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_reset_video (PRIVATE ROUTINE: NOT PART OF DURANGO API) + * + * This routine is used to disable all components of video overlay before + * performing a mode switch. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void cs5530_reset_video(void) +#else +void gfx_reset_video(void) +#endif +{ + gfx_set_video_enable(0); + + /* CLEAR THE DISPLAY BUFFER SIZE TO ZERO */ + /* During a modeset,if FIFO load is enabled with a large buffer size, */ + /* the FIFO can hang. To prevent this, we set the buffer size to zero */ + /* and wait for this new size to be latched */ + + gfx_set_display_video_size (0, 0); + + if (gfx_test_timing_active()) + { + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + } +} + +/*----------------------------------------------------------------------------- + * gfx_set_display_control (PRIVATE ROUTINE: NOT PART OF DURANGO API) + * + * This routine configures the display output. + * + * "sync_polarities" is used to set the polarities of the sync pulses according + * to the following mask: + * + * Bit 0: If set to 1, negative horizontal polarity is programmed, + * otherwise positive horizontal polarity is programmed. + * Bit 1: If set to 1, negative vertical polarity is programmed, + * otherwise positive vertical polarity is programmed. + * + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_display_control(int sync_polarities) +#else +int gfx_set_display_control(int sync_polarities) +#endif +{ + unsigned long dcfg; + + /* ENABLE DISPLAY OUTPUT FROM CX5530 */ + + dcfg = READ_VID32(CS5530_DISPLAY_CONFIG); + + /* CLEAR RELEVANT FIELDS */ + + dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK | + CS5530_DCFG_CRT_HSYNC_POL | CS5530_DCFG_CRT_VSYNC_POL | + CS5530_DCFG_FP_PWR_EN | CS5530_DCFG_FP_DATA_EN); + + /* INITIALIZATION */ + + dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | + CS5530_DCFG_PWR_SEQ_DLY_INIT | + CS5530_DCFG_GV_PAL_BYP); + + if (PanelEnable) + { + dcfg |= CS5530_DCFG_FP_PWR_EN; + dcfg |= CS5530_DCFG_FP_DATA_EN; + } + + /* SET APPROPRIATE SYNC POLARITIES */ + + if (sync_polarities & 1) + dcfg |= CS5530_DCFG_CRT_HSYNC_POL; + if (sync_polarities & 2) + dcfg |= CS5530_DCFG_CRT_VSYNC_POL; + + WRITE_VID32(CS5530_DISPLAY_CONFIG, dcfg); + return (0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_clock_frequency + * + * This routine sets the clock frequency, specified as a 16.16 fixed point + * value (0x00318000 = 49.5 MHz). It will set the closest frequency found + * in the lookup table. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void cs5530_set_clock_frequency(unsigned long frequency) +#else +void gfx_set_clock_frequency(unsigned long frequency) +#endif +{ + unsigned int index; + unsigned long value; + long min, diff; + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + + value = CS5530_PLLtable[0].pll_value; + min = (long) CS5530_PLLtable[0].frequency - frequency; + if (min < 0L) min = -min; + for (index = 1; index < NUM_CS5530_FREQUENCIES; index++) + { + diff = (long) CS5530_PLLtable[index].frequency - frequency; + if (diff < 0L) diff = -diff; + if (diff < min) + { + min = diff; + value = CS5530_PLLtable[index].pll_value; + } + } + + /* SET THE DOT CLOCK REGISTER */ + + WRITE_VID32(CS5530_DOT_CLK_CONFIG, value); + WRITE_VID32(CS5530_DOT_CLK_CONFIG, value | 0x80000100); /* set reset/bypass */ + gfx_delay_milliseconds(1); /* wait for PLL to settle */ + WRITE_VID32(CS5530_DOT_CLK_CONFIG, value & 0x7FFFFFFF); /* clear reset */ + WRITE_VID32(CS5530_DOT_CLK_CONFIG, value & 0x7FFFFEFF); /* clear bypass */ + return; +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_enable + * + * This routine enables or disables the video overlay functionality. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_video_enable(int enable) +#else +int gfx_set_video_enable(int enable) +#endif +{ + unsigned long vcfg; + + /* WAIT FOR VERTICAL BLANK TO START */ + /* Otherwise a glitch can be observed. */ + + if (gfx_test_timing_active()) + { + if (!gfx_test_vertical_active()) + { + while(!gfx_test_vertical_active()); + } + while(gfx_test_vertical_active()); + } + vcfg = READ_VID32(CS5530_VIDEO_CONFIG); + if (enable) + { + /* SET CS5530 BUS CONTROL PARAMETERS */ + /* Currently always high speed, 8-bit interface. */ + + vcfg |= CS5530_VCFG_HIGH_SPD_INT; + vcfg &= ~(CS5530_VCFG_EARLY_VID_RDY | CS5530_VCFG_16_BIT_EN); + + /* ENABLE CS5530 VIDEO OVERLAY */ + + vcfg |= CS5530_VCFG_VID_EN; + WRITE_VID32(CS5530_VIDEO_CONFIG, vcfg); + } + else + { + /* DISABLE CS5530 VIDEO OVERLAY */ + + vcfg &= ~CS5530_VCFG_VID_EN; + WRITE_VID32(CS5530_VIDEO_CONFIG, vcfg); + } + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_format + * + * Currently only sets 4:2:0 format, Y1 V Y0 U. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_video_format(unsigned long format) +#else +int gfx_set_video_format(unsigned long format) +#endif +{ + unsigned long vcfg = 0; + + /* SET THE CS5530 VIDEO INPUT FORMAT */ + + vcfg = READ_VID32(CS5530_VIDEO_CONFIG); + vcfg &= ~(CS5530_VCFG_VID_INP_FORMAT | CS5530_VCFG_4_2_0_MODE); + vcfg &= ~(CS5530_VCFG_CSC_BYPASS); + vcfg &= ~(CS5530_VCFG_GV_SEL); + + if (format < 4) + vcfg |= (format << 2); + else + { + if (format == VIDEO_FORMAT_Y0Y1Y2Y3) + { + vcfg |= CS5530_VCFG_4_2_0_MODE; + vcfg |= 1 << 2; + } + if (format == VIDEO_FORMAT_RGB) + { + vcfg |= CS5530_VCFG_CSC_BYPASS; + vcfg |= CS5530_VCFG_GV_SEL; + } + } + + WRITE_VID32(CS5530_VIDEO_CONFIG, vcfg); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_size + * + * This routine specifies the size of the source data. It is used only + * to determine how much data to transfer per frame, and is not used to + * calculate the scaling value (that is handled by a separate routine). + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_video_size(unsigned short width, unsigned short height) +#else +int gfx_set_video_size(unsigned short width, unsigned short height) +#endif +{ + unsigned long size, vcfg; + + /* SET THE CS5530 VIDEO LINE SIZE */ + + vcfg = READ_VID32(CS5530_VIDEO_CONFIG); + vcfg &= ~(CS5530_VCFG_LINE_SIZE_LOWER_MASK | CS5530_VCFG_LINE_SIZE_UPPER); + size = (width >> 1); + vcfg |= (size & 0x00FF) << 8; + if (size & 0x0100) vcfg |= CS5530_VCFG_LINE_SIZE_UPPER; + WRITE_VID32(CS5530_VIDEO_CONFIG, vcfg); + + /* SET TOTAL VIDEO BUFFER SIZE IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_size(width, height); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_offset + * + * This routine sets the starting offset for the video buffer when only + * one offset needs to be specified. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_video_offset(unsigned long offset) +#else +int gfx_set_video_offset(unsigned long offset) +#endif +{ + /* SAVE VALUE FOR FUTURE CLIPPING OF THE TOP OF THE VIDEO WINDOW */ + + gfx_vid_offset = offset; + + /* SET VIDEO BUFFER OFFSET IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_offset(offset); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_scale + * + * This routine sets the scale factor for the video overlay window. The + * size of the source and destination regions are specified in pixels. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +#else +int gfx_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +#endif +{ + unsigned long xscale, yscale; + + /* SAVE PARAMETERS */ + /* These are needed for clipping the video window later. */ + + gfx_vid_srcw = srcw; + gfx_vid_srch = srch; + gfx_vid_dstw = dstw; + gfx_vid_dsth = dsth; + + /* CALCULATE CS5530 SCALE FACTORS */ + /* No downscaling in CS5530 so force to 1x if attempted. */ + + if (dstw <= srcw) xscale = 0x1FFF; + else if (dstw == 1 || srcw == 1) return GFX_STATUS_BAD_PARAMETER; + else xscale = (0x2000l * (srcw - 1l)) / (dstw - 1l); + if (dsth <= srch) yscale = 0x1FFF; + else if (dsth == 1 || srch == 1) return GFX_STATUS_BAD_PARAMETER; + else yscale = (0x2000l * (srch - 1l)) / (dsth - 1l); + WRITE_VID32(CS5530_VIDEO_SCALE, (yscale << 16) | xscale); + + /* CALL ROUTINE TO UPDATE WINDOW POSITION */ + /* This is required because the scale values effect the number of */ + /* source data pixels that need to be clipped, as well as the */ + /* amount of data that needs to be transferred. */ + + gfx_set_video_window(gfx_vid_xpos, gfx_vid_ypos, gfx_vid_width, + gfx_vid_height); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_window + * + * This routine sets the position and size of the video overlay window. The + * position is specified in screen relative coordinates, and may be negative. + * The size of destination region is specified in pixels. The line size + * indicates the number of bytes of source data per scanline. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_video_window(short x, short y, unsigned short w, + unsigned short h) +#else +int gfx_set_video_window(short x, short y, unsigned short w, + unsigned short h) +#endif +{ + unsigned long vcfg = 0; + unsigned long hadjust, vadjust; + unsigned long xstart, ystart, xend, yend; + unsigned long offset, line_size; + + /* SAVE PARAMETERS */ + /* These are needed to call this routine if the scale value changes. */ + + gfx_vid_xpos = x; + gfx_vid_ypos = y; + gfx_vid_width = w; + gfx_vid_height = h; + + /* GET ADJUSTMENT VALUES */ + /* Use routines to abstract version of display controller. */ + + hadjust = gfx_get_htotal() - gfx_get_hsync_end() - 13l; + vadjust = gfx_get_vtotal() - gfx_get_vsync_end() + 1l; + + /* LEFT CLIPPING */ + + if (x < 0) + { + gfx_set_video_left_crop ((unsigned short)(-x)); + xstart = hadjust; + } + else + { + gfx_set_video_left_crop (0); + xstart = (unsigned long)x + hadjust; + } + + /* CLIPPING ON RIGHT */ + + xend = x + w; + if (xend > gfx_get_hactive()) xend = gfx_get_hactive(); + xend += hadjust; + + /* CLIPPING ON TOP */ + + offset = gfx_vid_offset; + if (y >= 0) + { + ystart = y + vadjust; + } + else + { + ystart = vadjust; + line_size = (READ_VID32(CS5530_VIDEO_CONFIG) >> 7) & 0x000001FE; + if (READ_VID32(CS5530_VIDEO_CONFIG) & CS5530_VCFG_LINE_SIZE_UPPER) + line_size += 512l; + if (gfx_vid_dsth) + offset = gfx_vid_offset + (line_size << 1) * + (((-y) * gfx_vid_srch) / gfx_vid_dsth); + } + + /* CLIPPING ON BOTTOM */ + + yend = y + h; + if (yend >= gfx_get_vactive()) yend = gfx_get_vactive(); + yend += vadjust; + + /* SET VIDEO BUFFER OFFSET IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_offset(offset); + + /* DISABLE REGISTER UPDATES */ + + vcfg = READ_VID32(CS5530_VIDEO_CONFIG); + vcfg &= ~CS5530_VCFG_VID_REG_UPDATE; + WRITE_VID32(CS5530_VIDEO_CONFIG, vcfg); + + /* SET VIDEO POSITION */ + + WRITE_VID32(CS5530_VIDEO_X_POS, (xend << 16) | xstart); + WRITE_VID32(CS5530_VIDEO_Y_POS, (yend << 16) | ystart); + + vcfg |= CS5530_VCFG_VID_REG_UPDATE; + WRITE_VID32(CS5530_VIDEO_CONFIG, vcfg); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_left_crop + * + * This routine sets the number of pixels which will be cropped from the + * beginning of each video line. The video window will begin to display only + * from the pixel following the cropped pixels, and the cropped pixels + * will be ignored. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_video_left_crop(unsigned short x) +#else +int gfx_set_video_left_crop(unsigned short x) +#endif +{ + unsigned long vcfg, initread; + + /* CLIPPING ON LEFT */ + /* Adjust initial read for scale, checking for divide by zero */ + + if (gfx_vid_dstw) + initread = (unsigned long)x * gfx_vid_srcw / gfx_vid_dstw; + else initread = 0; + + /* SET INITIAL READ ADDRESS AND ENABLE REGISTER UPDATES */ + + vcfg = READ_VID32(CS5530_VIDEO_CONFIG); + vcfg &= ~CS5530_VCFG_INIT_READ_MASK; + vcfg |= (initread << 15) & CS5530_VCFG_INIT_READ_MASK; + vcfg |= CS5530_VCFG_VID_REG_UPDATE; + WRITE_VID32(CS5530_VIDEO_CONFIG, vcfg); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_color_key + * + * This routine specifies the color key value and mask for the video overlay + * hardware. To disable color key, the color and mask should both be set to + * zero. The hardware uses the color key in the following equation: + * + * ((source data) & (color key mask)) == ((color key) & (color key mask)) + * + * The source data can be either graphics data or video data. The bluescreen + * parameter is set to have the hardware compare video data and clear to + * comapare graphics data. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_video_color_key(unsigned long key, unsigned long mask, + int graphics) +#else +int gfx_set_video_color_key(unsigned long key, unsigned long mask, + int graphics) +#endif +{ + unsigned long dcfg = 0; + + /* SET CS5530 COLOR KEY VALUE */ + + WRITE_VID32(CS5530_VIDEO_COLOR_KEY, key); + WRITE_VID32(CS5530_VIDEO_COLOR_MASK, mask); + + /* SELECT GRAPHICS OR VIDEO DATA TO COMPARE TO THE COLOR KEY */ + + dcfg = READ_VID32(CS5530_DISPLAY_CONFIG); + if (graphics & 0x01) dcfg &= ~CS5530_DCFG_VG_CK; + else dcfg |= CS5530_DCFG_VG_CK; + WRITE_VID32(CS5530_DISPLAY_CONFIG, dcfg); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_filter + * + * This routine enables or disables the video overlay filters. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_video_filter(int xfilter, int yfilter) +#else +int gfx_set_video_filter(int xfilter, int yfilter) +#endif +{ + unsigned long vcfg = 0; + + /* ENABLE OR DISABLE CS5530 VIDEO OVERLAY FILTERS */ + + vcfg = READ_VID32(CS5530_VIDEO_CONFIG); + vcfg &= ~(CS5530_VCFG_X_FILTER_EN | CS5530_VCFG_Y_FILTER_EN); + if (xfilter) vcfg |= CS5530_VCFG_X_FILTER_EN; + if (yfilter) vcfg |= CS5530_VCFG_Y_FILTER_EN; + WRITE_VID32(CS5530_VIDEO_CONFIG, vcfg); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette + * + * This routine loads the video hardware palette. If a NULL pointer is + * specified, the palette is bypassed (for CS5530, this means loading the + * palette with identity values). + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_video_palette(unsigned long *palette) +#else +int gfx_set_video_palette(unsigned long *palette) +#endif +{ + unsigned long i, entry; + + /* LOAD CS5530 VIDEO PALETTE */ + + WRITE_VID32(CS5530_PALETTE_ADDRESS, 0); + for (i = 0; i < 256; i++) + { + if (palette) entry = palette[i]; + else entry = i | (i << 8) | (i << 16); + WRITE_VID32(CS5530_PALETTE_DATA, entry); + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette_entry + * + * This routine loads a single entry of the video hardware palette. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_set_video_palette_entry(unsigned long index, unsigned long palette) +#else +int gfx_set_video_palette_entry(unsigned long index, unsigned long palette) +#endif +{ + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + /* SET A SINGLE ENTRY */ + + WRITE_VID32(CS5530_PALETTE_ADDRESS, index); + WRITE_VID32(CS5530_PALETTE_DATA, palette); + + return(0); +} + +#define CX55xx_VIDEO_PCI_44 0x80009444 + +/*--------------------------------------------------------------------------- + * gfx_disable_softvga + * + * Disables SoftVga. This function is only valid with VSA2, Returns 1 if + * SoftVga can be disabled; 0 if not. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_disable_softvga(void) +#else +int gfx_disable_softvga(void) +#endif +{ + unsigned long reg_val; + + /* get the current value */ + reg_val = gfx_pci_config_read(CX55xx_VIDEO_PCI_44); + /* setting video PCI register 44 bit 0 to 1 disables SoftVga */ + reg_val |= 0x1; + gfx_pci_config_write(CX55xx_VIDEO_PCI_44, reg_val); + + /* see if we set the bit and return the appropriate value */ + reg_val = gfx_pci_config_read(CX55xx_VIDEO_PCI_44); + if((reg_val & 0x1) == 0x1) + return(1); + else + return(0); + +} + +/*--------------------------------------------------------------------------- + * gfx_enable_softvga + * + * Enables SoftVga. This function is only valid with VSA2, Returns 1 if + * SoftVga can be enbled; 0 if not. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_enable_softvga(void) +#else +int gfx_enable_softvga(void) +#endif +{ + unsigned long reg_val; + + /* get the current value */ + reg_val = gfx_pci_config_read(CX55xx_VIDEO_PCI_44); + /* clearing video PCI register 44 bit 0 enables SoftVga */ + gfx_pci_config_write(CX55xx_VIDEO_PCI_44, reg_val & 0xfffffffe); + + /* see if we cleared the bit and return the appropriate value */ + reg_val = gfx_pci_config_read(CX55xx_VIDEO_PCI_44); + if((reg_val & 0x1) == 0) + return(1); + else + return(0); + +} + +/*--------------------------------------------------------------------------- + * gfx_get_clock_frequency + * + * This routine returns the current clock frequency in 16.16 format. + * It reads the current register value and finds the match in the table. + * If no match is found, this routine returns 0. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long cs5530_get_clock_frequency(void) +#else +unsigned long gfx_get_clock_frequency(void) +#endif +{ + unsigned int index; + unsigned long value, mask; + mask = 0x7FFFFEDC; + value = READ_VID32(CS5530_DOT_CLK_CONFIG) & mask; + for (index = 0; index < NUM_CS5530_FREQUENCIES; index++) + { + if ((CS5530_PLLtable[index].pll_value & mask) == value) + return(CS5530_PLLtable[index].frequency); + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_max_video_width + * + * This routine returns the maximum theoretical video width for the current + * display mode. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long cs5530_get_max_video_width(void) +#else +unsigned long gfx_get_max_video_width(void) +#endif +{ + unsigned long htotal, vidclk, dotpll; + unsigned long low, high, sublow, subhigh; + unsigned long width, value; + unsigned long temp0, temp1; + unsigned long highshift; + unsigned long divisor, dividend; + + htotal = gfx_get_htotal(); + + vidclk = gfx_cpu_frequency << 15; + if (READ_REG32 (DC_GENERAL_CFG) & DC_GCFG_VCLK_DIV) + vidclk >>= 1; + + dotpll = gfx_get_clock_frequency (); + + /* CHECK FOR UNKNOWN DOT CLOCK */ + + if (!dotpll) + return 0; + + /* DERIVE THEORETICAL MAXIMUM */ + /* The GX/CS5530 video interface transfers 8 bytes for every 9 video */ + /* clocks. This implies that 4 video pixels are transferred for every */ + /* 9 clocks. The time allowed to fill a line buffer is an entire */ + /* display line, or (HTotal * DotPll). The time needed to fill the */ + /* line buffer is thus ((4/9) * VidClk * VidWidth). Solving for */ + /* equality yields the theoretical maximum: */ + /* */ + /* 4 * VidClk * HTotal */ + /* VidWidth = ----------------------- */ + /* 9 * DotPLL */ + + /* CALCULATE TOP OF EQUATION */ + /* The equation as it stands will overflow 32-bit integer math. We must */ + /* therefore use tricks to perform a 64-bit equation to calculate the */ + /* correct value. We assume in this equation that the upper 16 bits of */ + /* htotal are 0, i.e. that htotal is never greater than 65535. */ + + vidclk <<= 2; + + low = (vidclk & 0xFFFF) * (htotal & 0xFFFF); + temp0 = (vidclk >> 16) * (htotal & 0xFFFF); + temp1 = temp0 << 16; + + high = temp0 >> 16; + if ((0xFFFFFFFF - temp1) < low) + high++; + low += temp1; + + /* DIVIDE BY BOTTOM OF EQUATION */ + /* Use an iterative divide to avoid floating point or inline assembly */ + /* Costly, but so is the price of OS independence. */ + + divisor = 9 * dotpll; + highshift = 0; + width = 0; + while (highshift <= 32) + { + if (highshift == 0) dividend = high; + else if (highshift == 32) dividend = low; + else dividend = (high << highshift) | (low >> (32 - highshift)); + + value = dividend / divisor; + + width = (width << 4) + value; + + value *= divisor; + + subhigh = value >> highshift; + sublow = value << (32 - highshift); + + if (low < sublow) high = high - subhigh - 1; + else high = high - subhigh; + + low -= sublow; + + highshift += 4; + } + + /* ALIGN TO 8 PIXEL BOUNDARY */ + + width &= 0xFFFC; + + return width; +} + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +#if GFX_READ_ROUTINES + +/*--------------------------------------------------------------------------- + * gfx_get_vsa2_softvga_enable + * + * This function returns the enable status of SoftVGA. It is valid + * only if VSAII is present. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_get_vsa2_softvga_enable(void) +#else +int gfx_get_vsa2_softvga_enable(void) +#endif +{ + unsigned long reg_val; + + reg_val = gfx_pci_config_read(CX55xx_VIDEO_PCI_44); + if((reg_val & 0x1) == 0) + return(1); + else + return(0); + +} + +/*--------------------------------------------------------------------------- + * gfx_get_sync_polarities + * + * This routine returns the polarities of the sync pulses: + * Bit 0: Set if negative horizontal polarity. + * Bit 1: Set if negative vertical polarity. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_get_sync_polarities(void) +#else +int gfx_get_sync_polarities(void) +#endif +{ + int polarities = 0; + if (READ_VID32(CS5530_DISPLAY_CONFIG) & 0x00000100) polarities |= 1; + if (READ_VID32(CS5530_DISPLAY_CONFIG) & 0x00000200) polarities |= 2; + return(polarities); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_palette_entry + * + * This routine returns a single palette entry. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_get_video_palette_entry(unsigned long index, unsigned long *palette) +#else +int gfx_get_video_palette_entry(unsigned long index, unsigned long *palette) +#endif +{ + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + /* READ A SINGLE ENTRY */ + + WRITE_VID32 (CS5530_PALETTE_ADDRESS, index); + *palette = READ_VID32 (CS5530_PALETTE_DATA); + + return (GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_enable + * + * This routine returns the value "one" if video overlay is currently enabled, + * otherwise it returns the value "zero". + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_get_video_enable(void) +#else +int gfx_get_video_enable(void) +#endif +{ + if (READ_VID32(CS5530_VIDEO_CONFIG) & CS5530_VCFG_VID_EN) return(1); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_format + * + * This routine returns the current video overlay format. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_get_video_format(void) +#else +int gfx_get_video_format(void) +#endif +{ + unsigned long vcfg; + vcfg = READ_VID32(CS5530_VIDEO_CONFIG); + if (vcfg & CS5530_VCFG_CSC_BYPASS) return(VIDEO_FORMAT_RGB); + if (vcfg & CS5530_VCFG_4_2_0_MODE) return(VIDEO_FORMAT_Y0Y1Y2Y3); + + return ((int)((vcfg >> 2) & 3)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_src_size + * + * This routine returns the size of the source video overlay buffer. The + * return value is (height << 16) | width. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long cs5530_get_video_src_size(void) +#else +unsigned long gfx_get_video_src_size(void) +#endif +{ + unsigned long width = 0, height = 0; + + /* DETERMINE SOURCE WIDTH FROM THE CS5530 VIDEO LINE SIZE */ + + width = (READ_VID32(CS5530_VIDEO_CONFIG) >> 7) & 0x000001FE; + if (READ_VID32(CS5530_VIDEO_CONFIG) & CS5530_VCFG_LINE_SIZE_UPPER) + width += 512l; + + if (width) + { + /* DETERMINE HEIGHT BY DIVIDING TOTAL SIZE BY WIDTH */ + /* Get total size from display controller - abtracted. */ + + height = gfx_get_display_video_size() / (width << 1); + } + return((height << 16) | width); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_line_size + * + * This routine returns the line size of the source video overlay buffer, in + * pixels. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long cs5530_get_video_line_size(void) +#else +unsigned long gfx_get_video_line_size(void) +#endif +{ + unsigned long width = 0; + + /* DETERMINE SOURCE WIDTH FROM THE CS5530 VIDEO LINE SIZE */ + + width = (READ_VID32(CS5530_VIDEO_CONFIG) >> 7) & 0x000001FE; + if (READ_VID32(CS5530_VIDEO_CONFIG) & CS5530_VCFG_LINE_SIZE_UPPER) + width += 512l; + return(width); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_xclip + * + * This routine returns the number of bytes clipped on the left side of a + * video overlay line (skipped at beginning). + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long cs5530_get_video_xclip(void) +#else +unsigned long gfx_get_video_xclip(void) +#endif +{ + unsigned long clip = 0; + + /* DETERMINE SOURCE WIDTH FROM THE CS5530 VIDEO LINE SIZE */ + + clip = (READ_VID32(CS5530_VIDEO_CONFIG) >> 14) & 0x000007FC; + return(clip); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_offset + * + * This routine returns the current offset for the video overlay buffer. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long cs5530_get_video_offset(void) +#else +unsigned long gfx_get_video_offset(void) +#endif +{ + return(gfx_get_display_video_offset()); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_scale + * + * This routine returns the scale factor for the video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long cs5530_get_video_scale(void) +#else +unsigned long gfx_get_video_scale(void) +#endif +{ + return(READ_VID32(CS5530_VIDEO_SCALE)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_dst_size + * + * This routine returns the size of the displayed video overlay window. + * NOTE: This is the displayed window size, which may be different from + * the real window size if clipped. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long cs5530_get_video_dst_size(void) +#else +unsigned long gfx_get_video_dst_size(void) +#endif +{ + unsigned long xsize, ysize; + + xsize = READ_VID32(CS5530_VIDEO_X_POS); + xsize = ((xsize >> 16) & 0x7FF) - (xsize & 0x07FF); + ysize = READ_VID32(CS5530_VIDEO_Y_POS); + ysize = ((ysize >> 16) & 0x7FF) - (ysize & 0x07FF); + return((ysize << 16) | xsize); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_position + * + * This routine returns the position of the video overlay window. The + * return value is (ypos << 16) | xpos. + * NOTE: This is the displayed window position, which may be different from + * the real window position if clipped. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long cs5530_get_video_position(void) +#else +unsigned long gfx_get_video_position(void) +#endif +{ + unsigned long hadjust, vadjust; + unsigned long xpos, ypos; + + /* READ HARDWARE POSITION */ + + xpos = READ_VID32(CS5530_VIDEO_X_POS) & 0x000007FF; + ypos = READ_VID32(CS5530_VIDEO_Y_POS) & 0x000007FF; + + /* GET ADJUSTMENT VALUES */ + /* Use routines to abstract version of display controller. */ + + hadjust = gfx_get_htotal() - gfx_get_hsync_end() - 13l; + vadjust = gfx_get_vtotal() - gfx_get_vsync_end() + 1l; + xpos -= hadjust; + ypos -= vadjust; + return((ypos << 16) | (xpos & 0x0000FFFF)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key + * + * This routine returns the current video color key value. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long cs5530_get_video_color_key(void) +#else +unsigned long gfx_get_video_color_key(void) +#endif +{ + return(READ_VID32(CS5530_VIDEO_COLOR_KEY)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key_mask + * + * This routine returns the current video color mask value. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long cs5530_get_video_color_key_mask(void) +#else +unsigned long gfx_get_video_color_key_mask(void) +#endif +{ + return(READ_VID32(CS5530_VIDEO_COLOR_MASK)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key_src + * + * This routine returns 0 for video data compare, 1 for graphics data. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_get_video_color_key_src(void) +#else +int gfx_get_video_color_key_src(void) +#endif +{ + if (READ_VID32(CS5530_DISPLAY_CONFIG) & CS5530_DCFG_VG_CK) return(0); + return(1); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_filter + * + * This routine returns if the filters are currently enabled. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int cs5530_get_video_filter(void) +#else +int gfx_get_video_filter(void) +#endif +{ + int retval = 0; + if (READ_VID32(CS5530_VIDEO_CONFIG) & CS5530_VCFG_X_FILTER_EN) + retval |= 1; + if (READ_VID32(CS5530_VIDEO_CONFIG) & CS5530_VCFG_Y_FILTER_EN) + retval |= 2; + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_read_crc + * + * This routine returns the hardware CRC value, which is used for automated + * testing. The value is like a checksum, but will change if pixels move + * locations. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long cs5530_read_crc(void) +#else +unsigned long gfx_read_crc(void) +#endif +{ + unsigned long crc = 0xFFFFFFFF; + if (gfx_test_timing_active()) + { + /* WAIT UNTIL ACTIVE DISPLAY */ + + while(!gfx_test_vertical_active()); + + /* RESET CRC DURING ACTIVE DISPLAY */ + + WRITE_VID32(CS5530_CRCSIG_TFT_TV, 0); + WRITE_VID32(CS5530_CRCSIG_TFT_TV, 1); + + /* WAIT UNTIL NOT ACTIVE, THEN ACTIVE, NOT ACTIVE, THEN ACTIVE */ + + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + crc = READ_VID32(CS5530_CRCSIG_TFT_TV) >> 8; + } + return(crc); +} + +#endif /* GFX_READ_ROUTINES */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/i2c_acc.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/i2c_acc.c 2005-12-14 11:31:04.000000000 -0700 @@ -0,0 +1,855 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to write to and read from the I2C bus using + * the ACCESS.bus hardware in the SC1200. + * */ + + +/* SUPER IO DEFINITIONS */ + +#define INDEX_1 0x15C /* base address 1 selected */ +#define DATA_1 0x15D +#define INDEX_2 0x2E /* base address 2 selected */ +#define DATA_2 0x2F +#define PCI_INDEX 0xCF8 /* PCI configuration space INDEX */ +#define PCI_DATA 0xCFC /* PCI configuration space DATA */ +#define BASE_ADR_MSB_REG 0x60 /* base address MSB register */ +#define BASE_ADR_LSB_REG 0x61 /* base address LSB register */ + +#define SIO_BASE_ADR_15C_15D 0x6000000 +#define SIO_BASE_ADR_2E_2F 0x4000000 + +/* SUPER IO GLOBALS */ + +unsigned short index_reg, data_reg; + +/* ACCESS BUS DEFINITIONS */ + +#define ACC_I2C_TIMEOUT 1000000 /* Number of reads before timing out */ +#define ACB1_BASE 0x810 /* ACCESS.bus base addresses */ +#define ACB2_BASE 0x820 +#define ACBSDA 0 /* ACB serial data */ +#define ACBST 1 /* ACB status */ +#define ACBCST 2 /* ACB control status */ +#define ACBCTL1 3 /* ACB control 1 */ +#define ACBADDR 4 /* ACB own address */ +#define ACBCTL2 5 /* ACB control 2 */ +#define LDN 0x7 /* Logical Device Numbers */ +#define ACB1_LDN 0x5 +#define ACB2_LDN 0x6 + +/* INITIAL ACCESS.bus BASE ADDRESS VALUES */ + +unsigned short base_address_array[3] = {0, ACB1_BASE, ACB2_BASE}; +char Freq = 0x71; + +/* LOCAL ACCESS.bus FUNCTION DECLARATIONS */ + +void acc_i2c_start(unsigned char busnum); +void acc_i2c_stop(unsigned char busnum); +void acc_i2c_abort_data(unsigned char busnum); +void acc_i2c_bus_recovery(unsigned char busnum); +void acc_i2c_stall_after_start(unsigned char busnum, int state); +void acc_i2c_send_address(unsigned char busnum, unsigned char cData); +int acc_i2c_ack(unsigned char busnum, int fPut, int negAck); +void acc_i2c_stop_clock(unsigned char busnum); +void acc_i2c_activate_clock(unsigned char busnum); +void acc_i2c_write_byte(unsigned char busnum, unsigned char cData); +unsigned char acc_i2c_read_byte(unsigned char busnum, int last_byte); +void acc_i2c_reset_bus(unsigned char busnum); +int acc_i2c_request_master(unsigned char busnum); +void acc_i2c_config(unsigned char busnum, short adr, char freq); +char acc_i2c_set_freq(unsigned char busnum, char freq); +unsigned short acc_i2c_set_base_address(unsigned char busnum, short adr); + +/* LOCAL HELPER ROUTINES */ + +void OsPciReadDWord(int bus, int dev, int func, int address, unsigned long * data); +int sio_set_index_data_reg(void); +void sio_write_reg(unsigned char reg, unsigned char data); +unsigned char sio_read_reg(unsigned char reg); + +/*--------------------------------------------------------------------------- + * OsPciReadDWord + * + * This routine reads one double word from the PCI configuration header + * defined by 'bus', 'dev', 'func' and 'address' to the double word + * pointed to by 'data'. + * + * Returns : None. + *--------------------------------------------------------------------------- + */ +void OsPciReadDWord (int bus, int dev, int func, int address, unsigned long * data) +{ + /* + * The address of a double word in the Configuration Header is built in + * the following way : + * {10000000,bus[23:16],device[15:11],function[10:8],address[7:2],00} + */ + long addr = (0x80000000 | + ((bus & 0xff) << 16) | + ((dev & 0x1f) << 11) | + ((func & 0x7) << 8) | + (address & 0xff)); + OUTD(PCI_INDEX, addr); + *data = IND(PCI_DATA); +} + +/*--------------------------------------------------------------------------- + * sio_set_index_data_reg + * + * This routine checks which index and data registers to use + * in order to access the Super I/O registers + * + * Returns : 1 - OK + * 0 - Super I/O disabled or configuration access disabled + * + *--------------------------------------------------------------------------- + */ +int sio_set_index_data_reg(void) +{ + unsigned long xbus_expention_bar, io_control_reg1; + + OsPciReadDWord (0, 0x12, 5, 0x10, &xbus_expention_bar); + xbus_expention_bar = xbus_expention_bar & 0xfffffffe; + io_control_reg1 = IND((unsigned short)xbus_expention_bar); + + if ((io_control_reg1) & (SIO_BASE_ADR_15C_15D)) + { + index_reg = INDEX_1; + data_reg = DATA_1; + return(1); + } + + if ((io_control_reg1) & (SIO_BASE_ADR_2E_2F)) + { + index_reg = INDEX_2; + data_reg = DATA_2; + return(1); + } + + return(0); +} + +/*--------------------------------------------------------------------------- + * sio_write_reg + * + * This routine writes 'data' to 'reg' Super I/O register + * + * Returns : None + *--------------------------------------------------------------------------- + */ +void sio_write_reg(unsigned char reg, unsigned char data) +{ + OUTB(index_reg, reg); + OUTB(data_reg, data); +} + +/*--------------------------------------------------------------------------- + * sio_read_reg + * + * This routine reads data from 'reg' Super I/O register + * + * Returns : The data read from the requested register + *--------------------------------------------------------------------------- + */ +unsigned char sio_read_reg(unsigned char reg) +{ + OUTB(index_reg, reg); + return INB(data_reg); +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_reset + * + * This routine resets the I2C bus as follows : + * · Sets the base address of the ACCESS.bus + * · Sets the frequency of the ACCESS.bus + * · Resets the ACCESS.bus + * + * If 'adr' is -1 the address is read from the hardware. + * If 'freq' is -1 the frequency is set to 56 clock cycles. + *--------------------------------------------------------------------------- + */ +#if GFX_I2C_DYNAMIC +int acc_i2c_reset(unsigned char busnum, short adr, char freq) +#else +int gfx_i2c_reset(unsigned char busnum, short adr, char freq) +#endif +{ + if ((busnum != 1) && (busnum != 2)) + return GFX_STATUS_BAD_PARAMETER; + acc_i2c_config(busnum, adr, freq); + if (base_address_array[busnum] == 0) + return GFX_STATUS_ERROR; + acc_i2c_reset_bus(busnum); + return GFX_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_select_gpio + * + * This routine selects which GPIO pins to use. + *--------------------------------------------------------------------------- + */ +#if GFX_I2C_DYNAMIC +int acc_i2c_select_gpio(int clock, int data) +#else +int gfx_i2c_select_gpio(int clock, int data) +#endif +{ + /* THIS ROUTINE DOES NOT APPLY TO THE ACCESS.bus IMPLEMENTATION. */ + + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_write + * + * This routine writes data to the specified I2C address. + * busnum - ACCESS.bus number (1 or 2). + *--------------------------------------------------------------------------- + */ +#if GFX_I2C_DYNAMIC +int acc_i2c_write(unsigned char busnum, unsigned char chipadr, unsigned char subadr, + unsigned char bytes, unsigned char * data) +#else +int gfx_i2c_write(unsigned char busnum, unsigned char chipadr, unsigned char subadr, + unsigned char bytes, unsigned char * data) +#endif +{ + int loop = 0; + + if ((busnum != 1) && (busnum != 2)) + return GFX_STATUS_BAD_PARAMETER; + + /* REQUEST MASTER */ + + if (!acc_i2c_request_master(busnum)) return(GFX_STATUS_ERROR); + + /* WRITE ADDRESS COMMAND */ + + acc_i2c_ack(busnum, 1, 0); + acc_i2c_stall_after_start(busnum, 1); + acc_i2c_send_address(busnum, (unsigned char)(chipadr & 0xFE)); + acc_i2c_stall_after_start(busnum, 0); + if (!acc_i2c_ack(busnum, 0, 0)) return(GFX_STATUS_ERROR); + + /* WRITE COMMAND */ + + acc_i2c_write_byte(busnum, subadr); + if (!acc_i2c_ack(busnum, 0, 0)) return(GFX_STATUS_ERROR); + + /* WRITE DATA */ + + for(loop = 0; loop < bytes; loop++) + { + acc_i2c_write_byte(busnum, *data); + if (loop < (bytes - 1)) + data += sizeof(unsigned char); + if (!acc_i2c_ack(busnum, 0, 0)) return(GFX_STATUS_ERROR); + } + data -= (bytes - 1); + acc_i2c_stop(busnum); + + return GFX_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_read + * + * This routine reads data from the specified I2C address. + * busnum - ACCESS.bus number (1 or 2). + *--------------------------------------------------------------------------- + */ +#if GFX_I2C_DYNAMIC +int acc_i2c_read(unsigned char busnum, unsigned char chipadr, unsigned char subadr, + unsigned char bytes, unsigned char * data) +#else +int gfx_i2c_read(unsigned char busnum, unsigned char chipadr, unsigned char subadr, + unsigned char bytes, unsigned char * data) +#endif +{ + unsigned char bytesRead; + + if ((busnum != 1) && (busnum != 2)) + return GFX_STATUS_BAD_PARAMETER; + + if (bytes == 0) + return GFX_STATUS_OK; + + /* REQUEST MASTER */ + + if (!acc_i2c_request_master(busnum)) return(GFX_STATUS_ERROR); + + /* WRITE ADDRESS COMMAND */ + + acc_i2c_ack(busnum, 1, 0); + acc_i2c_stall_after_start(busnum, 1); + acc_i2c_send_address(busnum, (unsigned char)(chipadr & 0xFE)); + acc_i2c_stall_after_start(busnum, 0); + if (!acc_i2c_ack(busnum, 0, 0)) return(GFX_STATUS_ERROR); + + /* WRITE COMMAND */ + + acc_i2c_write_byte(busnum, subadr); + if (!acc_i2c_ack(busnum, 0, 0)) return(GFX_STATUS_ERROR); + + /* START THE READ */ + + acc_i2c_start(busnum); + + /* WRITE ADDRESS COMMAND */ + + acc_i2c_ack(busnum, 1, 1); + acc_i2c_stall_after_start(busnum, 1); + acc_i2c_send_address(busnum, (unsigned char)(chipadr | 0x01)); + + /* IF LAST BYTE */ + + if (bytes == 1) + acc_i2c_ack(busnum, 1, 1); + else + acc_i2c_ack(busnum, 1, 0); + + acc_i2c_stall_after_start(busnum, 0); + + if (!acc_i2c_ack(busnum, 0, 0)) return(GFX_STATUS_ERROR); + + /* READ COMMAND */ + + for(bytesRead = 0; bytesRead < bytes; bytesRead += 1) + { + if (bytesRead < (bytes - 2)) + { + data[bytesRead] = acc_i2c_read_byte(busnum, 0); + acc_i2c_ack(busnum, 1, 0); + } + else if (bytesRead == (bytes - 2)) /* TWO BYTES LEFT */ + { + acc_i2c_ack(busnum, 1, 1); + data[bytesRead] = acc_i2c_read_byte(busnum, 0); + acc_i2c_ack(busnum, 1, 1); + } + else /* LAST BYTE */ + { + data[bytesRead] = acc_i2c_read_byte(busnum, 1); + acc_i2c_stop(busnum); + } + + /* WHILE NOT LAST BYTE */ + + if ((!(bytesRead == (bytes - 1))) && (!acc_i2c_ack(busnum, 0, 0))) + return(bytesRead); + } + + return GFX_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_init + * + * This routine initializes the use of the ACCESS.BUS. + *--------------------------------------------------------------------------- + */ +#if GFX_I2C_DYNAMIC +int acc_i2c_init(void) +#else +int gfx_i2c_init(void) +#endif +{ + /* ### ADD ### THIS ROUTINE IS NOT YET IMPLEMENTED FOR ACCESS.bus */ + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_cleanup + * + * This routine ends the use of the ACCESS.BUS. + *--------------------------------------------------------------------------- + */ +#if GFX_I2C_DYNAMIC +void acc_i2c_cleanup(void) +#else +void gfx_i2c_cleanup(void) +#endif +{ + /* ### ADD ### THIS ROUTINE IS NOT YET IMPLEMENTED FOR ACCESS.bus */ +} + +/*--------------------------------------------------------*/ +/* LOCAL ROUTINES SPECIFIC TO ACCESS.bus IMPLEMENTATION */ +/*--------------------------------------------------------*/ + +/*--------------------------------------------------------------------------- + * acc_i2c_reset_bus + * + * This routine resets the I2C bus. + *--------------------------------------------------------------------------- + */ +void acc_i2c_reset_bus(unsigned char busnum) +{ + unsigned char reg; + unsigned short bus_base_address = base_address_array[busnum]; + + /* Disable the ACCESS.bus device and */ + /* Configure the SCL frequency */ + OUTB((unsigned short)(bus_base_address + ACBCTL2), (unsigned char)(Freq & 0xFE)); + + /* Configure no interrupt mode (polling) and */ + /* Disable global call address */ + OUTB((unsigned short)(bus_base_address + ACBCTL1), 0x0); + + /* Disable slave address */ + OUTB((unsigned short)(bus_base_address + ACBADDR), 0x0); + + /* Enable the ACCESS.bus device */ + reg = INB((unsigned short)(bus_base_address + ACBCTL2)); + reg |= 0x01; + OUTB((unsigned short)(bus_base_address + ACBCTL2), reg); + + /* Issue STOP event */ + + acc_i2c_stop(busnum); + + /* Clear NEGACK, STASTR and BER bits */ + OUTB((unsigned short)(bus_base_address + ACBST), 0x38); + + /* Clear BB (BUS BUSY) bit */ + reg = INB((unsigned short)(bus_base_address + ACBCST)); + reg |= 0x02; + OUTB((unsigned short)(bus_base_address + ACBCST), reg); +} + +/*--------------------------------------------------------------------------- + * acc_i2c_start + * + * This routine starts a transfer on the I2C bus. + *--------------------------------------------------------------------------- + */ +void acc_i2c_start(unsigned char busnum) +{ + unsigned char reg; + unsigned short bus_base_address = base_address_array[busnum]; + reg = INB((unsigned short)(bus_base_address + ACBCTL1)); + reg |= 0x01; + OUTB((unsigned short)(bus_base_address + ACBCTL1), reg); +} + +/*--------------------------------------------------------------------------- + * acc_i2c_stop + * + * This routine stops a transfer on the I2C bus. + *--------------------------------------------------------------------------- + */ +void acc_i2c_stop(unsigned char busnum) +{ + unsigned char reg; + unsigned short bus_base_address = base_address_array[busnum]; + reg = INB((unsigned short)(bus_base_address + ACBCTL1)); + reg |= 0x02; + OUTB((unsigned short)(bus_base_address + ACBCTL1), reg); +} + +/*--------------------------------------------------------------------------- + * acc_i2c_abort_data + *--------------------------------------------------------------------------- + */ +void acc_i2c_abort_data(unsigned char busnum) +{ + unsigned char reg; + unsigned short bus_base_address = base_address_array[busnum]; + acc_i2c_stop(busnum); + reg = INB((unsigned short)(bus_base_address + ACBCTL1)); + reg |= 0x10; + OUTB((unsigned short)(bus_base_address + ACBCTL1), reg); +} + +/*--------------------------------------------------------------------------- + * acc_i2c_bus_recovery + *--------------------------------------------------------------------------- + */ +void acc_i2c_bus_recovery(unsigned char busnum) +{ + acc_i2c_abort_data(busnum); + acc_i2c_reset_bus(busnum); +} + +/*--------------------------------------------------------------------------- + * acc_i2c_stall_after_start + *--------------------------------------------------------------------------- + */ +void acc_i2c_stall_after_start(unsigned char busnum, int state) +{ + unsigned char reg; + unsigned short bus_base_address = base_address_array[busnum]; + reg = INB((unsigned short)(bus_base_address + ACBCTL1)); + if (state) reg |= 0x80; + else reg &= 0x7F; + OUTB((unsigned short)(bus_base_address + ACBCTL1), reg); + + if (!state) + { + reg = INB((unsigned short)(bus_base_address + ACBST)); + reg |= 0x08; + OUTB((unsigned short)(bus_base_address + ACBST), reg); + } +} + +/*--------------------------------------------------------------------------- + * acc_i2c_send_address + *--------------------------------------------------------------------------- + */ +void acc_i2c_send_address(unsigned char busnum, unsigned char cData) +{ + unsigned char reg; + unsigned short bus_base_address = base_address_array[busnum]; + unsigned long timeout = 0; + + /* WRITE THE DATA */ + + OUTB((unsigned short)(bus_base_address + ACBSDA), cData); + while (1) { + reg = INB((unsigned short)(bus_base_address + ACBST)); + if ((reg & 0x38) != 0) /* check STASTR, BER and NEGACK */ + break; + if (timeout++ == ACC_I2C_TIMEOUT) + { + acc_i2c_bus_recovery(busnum); + return; + } + } + + /* CHECK FOR BUS ERROR */ + + if (reg & 0x20) + { + acc_i2c_bus_recovery(busnum); + return; + } + + /* CHECK NEGATIVE ACKNOWLEDGE */ + + if (reg & 0x10) + { + acc_i2c_abort_data(busnum); + return; + } + +} + +/*--------------------------------------------------------------------------- + * acc_i2c_ack + * + * This routine looks for acknowledge on the I2C bus. + *--------------------------------------------------------------------------- + */ +int acc_i2c_ack(unsigned char busnum, int fPut, int negAck) +{ + unsigned char reg; + unsigned short bus_base_address = base_address_array[busnum]; + unsigned long timeout = 0; + + if (fPut) { /* read operation */ + if (!negAck) { + /* Push Ack onto I2C bus */ + reg = INB((unsigned short)(bus_base_address + ACBCTL1)); + reg &= 0xE7; + OUTB((unsigned short)(bus_base_address + ACBCTL1), reg); + } + else { + /* Push negAck onto I2C bus */ + reg = INB((unsigned short)(bus_base_address + ACBCTL1)); + reg |= 0x10; + OUTB((unsigned short)(bus_base_address + ACBCTL1), reg); + } + } else { /* write operation */ + /* Receive Ack from I2C bus */ + while (1) { + reg = INB((unsigned short)(bus_base_address + ACBST)); + if ((reg & 0x70) != 0) /* check SDAST, BER and NEGACK */ + break; + if (timeout++ == ACC_I2C_TIMEOUT) + { + acc_i2c_bus_recovery(busnum); + return(0); + } + } + + /* CHECK FOR BUS ERROR */ + + if (reg & 0x20) + { + acc_i2c_bus_recovery(busnum); + return(0); + } + + /* CHECK NEGATIVE ACKNOWLEDGE */ + + if (reg & 0x10) + { + acc_i2c_abort_data(busnum); + return(0); + } + } + return (1); +} + +/*--------------------------------------------------------------------------- + * acc_i2c_stop_clock + * + * This routine stops the ACCESS.bus clock. + *--------------------------------------------------------------------------- + */ +void acc_i2c_stop_clock(unsigned char busnum) +{ + unsigned char reg; + unsigned short bus_base_address = base_address_array[busnum]; + reg = INB((unsigned short)(bus_base_address + ACBCTL2)); + reg &= ~0x01; + OUTB((unsigned short)(bus_base_address + ACBCTL2), reg); +} + +/*--------------------------------------------------------------------------- + * acc_i2c_activate_clock + * + * This routine activates the ACCESS.bus clock. + *--------------------------------------------------------------------------- + */ +void acc_i2c_activate_clock(unsigned char busnum) +{ + unsigned char reg; + unsigned short bus_base_address = base_address_array[busnum]; + reg = INB((unsigned short)(bus_base_address + ACBCTL2)); + reg |= 0x01; + OUTB((unsigned short)(bus_base_address + ACBCTL2), reg); +} + +/*--------------------------------------------------------------------------- + * acc_i2c_write_byte + * + * This routine writes a byte to the I2C bus + *--------------------------------------------------------------------------- + */ +void acc_i2c_write_byte(unsigned char busnum, unsigned char cData) +{ + unsigned char reg; + unsigned short bus_base_address = base_address_array[busnum]; + unsigned long timeout = 0; + + while (1) { + reg = INB((unsigned short)(bus_base_address + ACBST)); + if (reg & 0x70) break; + if (timeout++ == ACC_I2C_TIMEOUT) + { + acc_i2c_bus_recovery(busnum); + return; + } + } + + /* CHECK FOR BUS ERROR */ + + if (reg & 0x20) + { + acc_i2c_bus_recovery(busnum); + return; + } + + /* CHECK NEGATIVE ACKNOWLEDGE */ + + if (reg & 0x10) + { + acc_i2c_abort_data(busnum); + return; + } + + /* WRITE THE DATA */ + + OUTB((unsigned short)(bus_base_address + ACBSDA), cData); +} + +/*--------------------------------------------------------------------------- + * acc_i2c_read_byte + * + * This routine reads a byte from the I2C bus + *--------------------------------------------------------------------------- + */ +unsigned char acc_i2c_read_byte(unsigned char busnum, int last_byte) +{ + unsigned char cData, reg; + unsigned short bus_base_address = base_address_array[busnum]; + unsigned long timeout = 0; + + while (1) { + reg = INB((unsigned short)(bus_base_address + ACBST)); + if (reg & 0x60) break; + if (timeout++ == ACC_I2C_TIMEOUT) + { + acc_i2c_bus_recovery(busnum); + return(0xEF); + } + } + + /* CHECK FOR BUS ERROR */ + + if (reg & 0x20) + { + acc_i2c_bus_recovery(busnum); + return(0xEE); + } + + /* READ DATA */ + if (last_byte) + acc_i2c_stop_clock(busnum); + cData = INB((unsigned short)(bus_base_address + ACBSDA)); + if (last_byte) + acc_i2c_activate_clock(busnum); + + return (cData); +} + +/*--------------------------------------------------------------------------- + * acc_i2c_request_master + *--------------------------------------------------------------------------- + */ +int acc_i2c_request_master(unsigned char busnum) +{ + unsigned char reg; + unsigned short bus_base_address = base_address_array[busnum]; + unsigned long timeout = 0; + + acc_i2c_start(busnum); + while (1) { + reg = INB((unsigned short)(bus_base_address + ACBST)); + if (reg & 0x60) break; + if (timeout++ == ACC_I2C_TIMEOUT) + { + acc_i2c_bus_recovery(busnum); + return(0); + } + } + + /* CHECK FOR BUS ERROR */ + + if (reg & 0x20) + { + acc_i2c_abort_data(busnum); + return(0); + } + + /* CHECK NEGATIVE ACKNOWLEDGE */ + + if (reg & 0x10) + { + acc_i2c_abort_data(busnum); + return(0); + } + return(1); +} + +/*--------------------------------------------------------*/ +/* LOCAL ROUTINES SPECIFIC TO ACCESS.bus INITIALIZATION */ +/*--------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * acc_i2c_config + * + * This routine configures the I2C bus + *---------------------------------------------------------------------------- + */ +void acc_i2c_config(unsigned char busnum, short adr, char freq) +{ + base_address_array[busnum] = acc_i2c_set_base_address(busnum, adr); + Freq = acc_i2c_set_freq(busnum, freq); +} + +/*---------------------------------------------------------------------------- + * acc_i2c_set_freq + * + * This routine sets the frequency of the I2C bus + *---------------------------------------------------------------------------- + */ +char acc_i2c_set_freq(unsigned char busnum, char freq) +{ + unsigned short bus_base_address = base_address_array[busnum]; + + OUTB((unsigned short)(bus_base_address + ACBCTL2), 0x0); + + if (freq == -1) + freq = 0x71; + else + { + freq = freq << 1; + freq |= 0x01; + } + + OUTB((unsigned short)(bus_base_address + ACBCTL2), freq); + return (freq); +} + +/*--------------------------------------------------------------------------- + * acc_i2c_set_base_address + * + * This routine sets the base address of the I2C bus + *--------------------------------------------------------------------------- + */ +unsigned short acc_i2c_set_base_address(unsigned char busnum, short adr) +{ + unsigned short ab_base_addr; + + /* Get Super I/O Index and Data registers */ + if (!sio_set_index_data_reg()) + return (0); + + /* Configure LDN to current ACB */ + if (busnum == 1) + sio_write_reg(LDN, ACB1_LDN); + if (busnum == 2) + sio_write_reg(LDN, ACB2_LDN); + + if (adr == -1) { + /* Get ACCESS.bus base address */ + ab_base_addr = sio_read_reg(BASE_ADR_MSB_REG); + ab_base_addr = ab_base_addr << 8; + ab_base_addr |= sio_read_reg(BASE_ADR_LSB_REG); + if (ab_base_addr != 0) + return ab_base_addr; + else + adr = (busnum == 1 ? ACB1_BASE : ACB2_BASE); + } + + /* Set ACCESS.bus base address */ + sio_write_reg(BASE_ADR_LSB_REG, (unsigned char)(adr & 0xFF)); + sio_write_reg(BASE_ADR_MSB_REG, (unsigned char)(adr >> 8)); + + return adr; +} + +/* END OF FILE */ + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/init_gu1.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/init_gu1.c 2005-12-14 11:30:47.000000000 -0700 @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines used in the initialization of Geode-family + * processors. + * */ + +/*----------------------------------------------------------------------------- + * gfx_gxm_config_read + * + * This routine reads the value of the specified GXm configuration register. + *----------------------------------------------------------------------------- + */ +unsigned char gfx_gxm_config_read(unsigned char index) +{ + unsigned char value = 0xFF; + unsigned char lock; + + OUTB(0x22, GXM_CONFIG_CCR3); + lock = INB(0x23); + OUTB(0x22, GXM_CONFIG_CCR3); + OUTB(0x23, (unsigned char) (lock | 0x10)); + OUTB(0x22, index); + value = INB(0x23); + OUTB(0x22, GXM_CONFIG_CCR3); + OUTB(0x23, lock); + return(value); +} + +/*----------------------------------------------------------------------------- + * gfx_get_core_freq + * + * This routine returns the core clock frequency of a GXm if valid jumper settings are + * detected; 0 It assumes that a 33.3 MHz PCI clock is being used for GX1. + * For SCx2xx, the fast PCI divisor is read. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu1_get_core_freq(void) +#else +unsigned long gfx_get_core_freq(void) +#endif +{ + unsigned char dir0, dir1; + unsigned long cpu_speed; + + dir0 = gfx_gxm_config_read(GXM_CONFIG_DIR0) & 0x0F; + dir1 = gfx_gxm_config_read(GXM_CONFIG_DIR1); + + /* REVISION 4.0 AND UP */ + + if(dir1 >= 0x50) + { + switch(dir0) + { + case 0: + case 2: cpu_speed = 133; break; + + case 5: cpu_speed = 166; break; + case 3: cpu_speed = 200; break; + case 6: cpu_speed = 233; break; + case 7: cpu_speed = 266; break; + case 4: cpu_speed = 300; break; + case 1: cpu_speed = 333; break; + default: + return(0); + } + } + else + { + switch(dir0) + { + case 0: + case 2: cpu_speed = 133; break; + + case 7: cpu_speed = 166; break; + + case 1: + case 3: cpu_speed = 200; break; + + case 4: + case 6: cpu_speed = 233; break; + + case 5: cpu_speed = 266; break; + default: + return(0); + } + } + + if ((gfx_cpu_version & 0xFF) == GFX_CPU_SC1200) + { + cpu_speed = (cpu_speed * gfx_pci_speed_khz) / 33300; + } + return(cpu_speed); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cpu_register_base + * + * This routine returns the base address for graphics registers. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu1_get_cpu_register_base(void) +#else +unsigned long gfx_get_cpu_register_base(void) +#endif +{ + unsigned long base; + base = (unsigned long) gfx_gxm_config_read(GXM_CONFIG_GCR); + base = (base & 0x03) << 30; + return(base); +} + +/*----------------------------------------------------------------------------- + * gfx_get_frame_buffer_base + * + * This routine returns the base address for graphics memory. This is an + * offset of 0x00800000 from the base address specified in the GCR register. + * + * The function returns zero if the GCR indicates the graphics subsystem + * is disabled. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu1_get_frame_buffer_base(void) +#else +unsigned long gfx_get_frame_buffer_base(void) +#endif +{ + unsigned long base; + base = (unsigned long) gfx_gxm_config_read(GXM_CONFIG_GCR); + base = (base & 0x03) << 30; + if (base) base |= 0x00800000; + return(base); +} + +/*----------------------------------------------------------------------------- + * gfx_get_frame_buffer_size + * + * This routine returns the total size of graphics memory, in bytes. + * + * Currently this routine is hardcoded to return 2 Meg. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu1_get_frame_buffer_size(void) +#else +unsigned long gfx_get_frame_buffer_size(void) +#endif +{ +#if FB4MB + return(0x00400000); +#else + return(0x00200000); +#endif +} + +/*----------------------------------------------------------------------------- + * gfx_get_vid_register_base + * + * This routine returns the base address for the video hardware. It assumes + * an offset of 0x00010000 from the base address specified by the GCR. + * + * The function returns zero if the GCR indicates the graphics subsystem + * is disabled. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu1_get_vid_register_base(void) +#else +unsigned long gfx_get_vid_register_base(void) +#endif +{ + unsigned long base; + base = (unsigned long) gfx_gxm_config_read(GXM_CONFIG_GCR); + base = (base & 0x03) << 30; + if (base) base |= 0x00010000; + return(base); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vip_register_base + * + * This routine returns the base address for the VIP hardware. This is + * only applicable to the SC1200, for which this routine assumes an offset + * of 0x00015000 from the base address specified by the GCR. + * + * The function returns zero if the GCR indicates the graphics subsystem + * is disabled. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu1_get_vip_register_base(void) +#else +unsigned long gfx_get_vip_register_base(void) +#endif +{ + unsigned long base = 0; + if ((gfx_cpu_version & 0xFF) == GFX_CPU_SC1200) + { + base = (unsigned long) gfx_gxm_config_read(GXM_CONFIG_GCR); + base = (base & 0x03) << 30; + if (base) base |= 0x00015000; + } + return(base); +} + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/init_gu2.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/init_gu2.c 2005-12-14 11:30:38.000000000 -0700 @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines used in Redcloud initialization. + * */ + + +/*----------------------------------------------------------------------------- + * gfx_get_core_freq + * + * Returns the core clock frequency of a GX2. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu2_get_core_freq(void) +#else +unsigned long gfx_get_core_freq(void) +#endif +{ + unsigned long value; + + /* CPU SPEED IS REPORTED BY A VSM IN VSA II */ + /* Virtual Register Class = 0x12 (Sysinfo) */ + /* CPU Speed Register = 0x01 */ + + OUTW (0xAC1C, 0xFC53); + OUTW (0xAC1C, 0x1201); + + value = (unsigned long)(INW (0xAC1E)); + + return (value); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cpu_register_base + * + * This routine returns the base address for display controller registers. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu2_get_cpu_register_base(void) +#else +unsigned long gfx_get_cpu_register_base(void) +#endif +{ + return gfx_pci_config_read (0x80000918); +} + +/*----------------------------------------------------------------------------- + * gfx_get_graphics_register_base + * + * This routine returns the base address for the graphics acceleration. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu2_get_graphics_register_base(void) +#else +unsigned long gfx_get_graphics_register_base(void) +#endif +{ + return gfx_pci_config_read (0x80000914); +} + +/*----------------------------------------------------------------------------- + * gfx_get_frame_buffer_base + * + * This routine returns the base address for graphics memory. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu2_get_frame_buffer_base(void) +#else +unsigned long gfx_get_frame_buffer_base(void) +#endif +{ + return gfx_pci_config_read (0x80000910); +} + +/*----------------------------------------------------------------------------- + * gfx_get_frame_buffer_size + * + * This routine returns the total size of graphics memory, in bytes. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu2_get_frame_buffer_size(void) +#else +unsigned long gfx_get_frame_buffer_size(void) +#endif +{ + unsigned long value; + + /* FRAME BUFFER SIZE IS REPORTED BY A VSM IN VSA II */ + /* Virtual Register Class = 0x02 */ + /* VG_MEM_SIZE (512KB units) = 0x00 */ + + OUTW (0xAC1C, 0xFC53); + OUTW (0xAC1C, 0x0200); + + value = (unsigned long)(INW (0xAC1E)) & 0xFFl; + + return (value << 19); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vid_register_base + * + * This routine returns the base address for the video hardware. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu2_get_vid_register_base(void) +#else +unsigned long gfx_get_vid_register_base(void) +#endif +{ + return gfx_pci_config_read (0x8000091C); +} + + + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/init_gu3.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/init_gu3.c 2005-12-14 11:30:27.000000000 -0700 @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines used in Redcloud initialization. + * */ + +/*----------------------------------------------------------------------------- + * gfx_get_core_freq + * + * Returns the core clock frequency of a GX3. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu3_get_core_freq(void) +#else +unsigned long gfx_get_core_freq(void) +#endif +{ + unsigned long value; + + /* CPU SPEED IS REPORTED BY A VSM IN VSA II */ + /* Virtual Register Class = 0x12 (Sysinfo) */ + /* CPU Speed Register = 0x01 */ + + OUTW (0xAC1C, 0xFC53); + OUTW (0xAC1C, 0x1201); + + value = (unsigned long)(INW (0xAC1E)); + + return (value); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cpu_register_base + * + * This routine returns the base address for display controller registers. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu3_get_cpu_register_base(void) +#else +unsigned long gfx_get_cpu_register_base(void) +#endif +{ + return gfx_pci_config_read (0x80000918); +} + +/*----------------------------------------------------------------------------- + * gfx_get_graphics_register_base + * + * This routine returns the base address for the graphics acceleration. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu3_get_graphics_register_base(void) +#else +unsigned long gfx_get_graphics_register_base(void) +#endif +{ + return gfx_pci_config_read (0x80000914); +} + +/*----------------------------------------------------------------------------- + * gfx_get_frame_buffer_base + * + * This routine returns the base address for graphics memory. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu3_get_frame_buffer_base(void) +#else +unsigned long gfx_get_frame_buffer_base(void) +#endif +{ + return gfx_pci_config_read (0x80000910); +} + +/*----------------------------------------------------------------------------- + * gfx_get_frame_buffer_size + * + * This routine returns the total size of graphics memory, in bytes. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu3_get_frame_buffer_size(void) +#else +unsigned long gfx_get_frame_buffer_size(void) +#endif +{ + unsigned long value; + + /* FRAME BUFFER SIZE IS REPORTED BY A VSM IN VSA II */ + /* Virtual Register Class = 0x02 */ + /* VG_MEM_SIZE (1MB units) = 0x00 */ + + OUTW (0xAC1C, 0xFC53); + OUTW (0xAC1C, 0x0200); + + value = (unsigned long)(INW (0xAC1E)) & 0xFEl; + + /* LIMIT FRAME BUFFER SIZE TO 16MB TO MATCH LEGACY */ + + if ((value << 20) > 0x1000000) + return 0x1000000; + + return (value << 20); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vid_register_base + * + * This routine returns the base address for the video hardware. + *----------------------------------------------------------------------------- + */ +#if GFX_INIT_DYNAMIC +unsigned long gu3_get_vid_register_base(void) +#else +unsigned long gfx_get_vid_register_base(void) +#endif +{ + return gfx_pci_config_read (0x8000091C); +} + + + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/vip_1200.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/vip_1200.c 2005-12-14 11:28:12.000000000 -0700 @@ -0,0 +1,573 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to control the SC1200 video input port (VIP) hardware. + * */ + +/*----------------------------------------------------------------------------- + * gfx_set_vip_enable + * + * This routine enables or disables the writes to memory from the video port. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vip_enable(int enable) +#else +int gfx_set_vip_enable(int enable) +#endif +{ + unsigned long value; + value = READ_VIP32(SC1200_VIP_CONTROL); + if (enable) + value |= SC1200_VIP_DATA_CAPTURE_EN; + else + value &= ~SC1200_VIP_DATA_CAPTURE_EN; + WRITE_VIP32(SC1200_VIP_CONTROL, value); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vip_capture_run_mode + * + * This routine selects VIP capture run mode. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vip_capture_run_mode(int mode) +#else +int gfx_set_vip_capture_run_mode(int mode) +#endif +{ + unsigned long value; + value = READ_VIP32(SC1200_VIP_CONTROL); + value &= ~SC1200_CAPTURE_RUN_MODE_MASK; + switch(mode) + { + case VIP_CAPTURE_STOP_LINE: + value |= SC1200_CAPTURE_RUN_MODE_STOP_LINE; + break; + case VIP_CAPTURE_STOP_FIELD: + value |= SC1200_CAPTURE_RUN_MODE_STOP_FIELD; + break; + case VIP_CAPTURE_START_FIELD: + value |= SC1200_CAPTURE_RUN_MODE_START; + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + WRITE_VIP32(SC1200_VIP_CONTROL, value); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vip_base + * + * This routine sets the odd and even base address values for the VIP memory + * buffer. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vip_base(unsigned long even, unsigned long odd) +#else +int gfx_set_vip_base(unsigned long even, unsigned long odd) +#endif +{ + /* TRUE OFFSET IS SPECIFIED, NEED TO SET BIT 23 FOR HARDWARE */ + + if (even) WRITE_VIP32(SC1200_VIP_EVEN_BASE, even + (unsigned long)gfx_phys_fbptr); + if (odd) WRITE_VIP32(SC1200_VIP_ODD_BASE, odd + (unsigned long)gfx_phys_fbptr); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vip_pitch + * + * This routine sets the number of bytes between scanlines for the VIP data. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vip_pitch(unsigned long pitch) +#else +int gfx_set_vip_pitch(unsigned long pitch) +#endif +{ + WRITE_VIP32(SC1200_VIP_PITCH, pitch & SC1200_VIP_PITCH_MASK); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vip_mode + * + * This routine sets the VIP operating mode. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vip_mode(int mode) +#else +int gfx_set_vip_mode(int mode) +#endif +{ + unsigned long config; + + config = READ_VIP32(SC1200_VIP_CONFIG); + config &= ~SC1200_VIP_MODE_MASK; + switch(mode) + { + case VIP_MODE_C: + WRITE_VIP32(SC1200_VIP_CONFIG, config | SC1200_VIP_MODE_C); + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vbi_enable + * + * This routine enables or disables the VBI data capture. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vbi_enable(int enable) +#else +int gfx_set_vbi_enable(int enable) +#endif +{ + unsigned long value; + value = READ_VIP32(SC1200_VIP_CONTROL); + if (enable) value |= SC1200_VIP_VBI_CAPTURE_EN; + else value &= ~SC1200_VIP_VBI_CAPTURE_EN; + WRITE_VIP32(SC1200_VIP_CONTROL, value); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vbi_mode + * + * This routine sets the VBI data types captured to memory. + * It receives a mask of all enabled types. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vbi_mode(int mode) +#else +int gfx_set_vbi_mode(int mode) +#endif +{ + unsigned long config; + + config = READ_VIP32(SC1200_VIP_CONFIG); + config &= ~(SC1200_VBI_ANCILLARY_TO_MEMORY | SC1200_VBI_TASK_A_TO_MEMORY | SC1200_VBI_TASK_B_TO_MEMORY); + + if (mode & VBI_ANCILLARY) config |= SC1200_VBI_ANCILLARY_TO_MEMORY; + if (mode & VBI_TASK_A) config |= SC1200_VBI_TASK_A_TO_MEMORY; + if (mode & VBI_TASK_B) config |= SC1200_VBI_TASK_B_TO_MEMORY; + WRITE_VIP32(SC1200_VIP_CONFIG, config); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vbi_base + * + * This routine sets the odd and even base address values for VBI capture. + * + * "even" and "odd" should contain 16-byte aligned physical addresses. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vbi_base(unsigned long even, unsigned long odd) +#else +int gfx_set_vbi_base(unsigned long even, unsigned long odd) +#endif +{ + /* VIP HW REQUIRES THAT BASE ADDRESSES BE 16-BYTE ALIGNED */ + + if (even) WRITE_VIP32(SC1200_VBI_EVEN_BASE, even & ~0xf); + if (odd) WRITE_VIP32(SC1200_VBI_ODD_BASE, odd & ~0xf); + + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vbi_pitch + * + * This routine sets the number of bytes between scanlines for VBI capture. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vbi_pitch(unsigned long pitch) +#else +int gfx_set_vbi_pitch(unsigned long pitch) +#endif +{ + WRITE_VIP32(SC1200_VBI_PITCH, pitch & SC1200_VBI_PITCH_MASK); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vbi_direct + * + * This routine sets the VBI lines to be passed to the Direct VIP. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines) +#else +int gfx_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines) +#endif +{ + WRITE_VIP32(SC1200_EVEN_DIRECT_VBI_LINE_ENABLE, even_lines & SC1200_DIRECT_VBI_LINE_ENABLE_MASK); + WRITE_VIP32(SC1200_ODD_DIRECT_VBI_LINE_ENABLE, odd_lines & SC1200_DIRECT_VBI_LINE_ENABLE_MASK); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vbi_interrupt + * + * This routine enables or disables the VBI field interrupt. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vbi_interrupt(int enable) +#else +int gfx_set_vbi_interrupt(int enable) +#endif +{ + unsigned long value; + value = READ_VIP32(SC1200_VIP_CONTROL); + if (enable) + value |= SC1200_VIP_VBI_FIELD_INTERRUPT_EN; + else + value &= ~SC1200_VIP_VBI_FIELD_INTERRUPT_EN; + WRITE_VIP32(SC1200_VIP_CONTROL, value); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vip_bus_request_threshold_high + * + * This routine sets the VIP FIFO bus request threshold. + * If enable is TRUE, VIP FIFO will be set to issue a bus request when it filled with 64 bytes. + * If enable is FALSE, VIP FIFO will be set to issue a bus request when it filled with 32 bytes. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vip_bus_request_threshold_high(int enable) +#else +int gfx_set_vip_bus_request_threshold_high(int enable) +#endif +{ + unsigned long value; + value = READ_VIP32(SC1200_VIP_CONFIG); + if (enable) + value &= ~SC1200_VIP_BUS_REQUEST_THRESHOLD; + else + value |= SC1200_VIP_BUS_REQUEST_THRESHOLD; + WRITE_VIP32(SC1200_VIP_CONFIG, value); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vip_last_line + * + * This routine sets the maximum number of lines captured in each field. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_set_vip_last_line(int last_line) +#else +int gfx_set_vip_last_line(int last_line) +#endif +{ + unsigned long value; + + /* This feature is implemented in Rev C1 */ + if (gfx_chip_revision < SC1200_REV_C1) return(GFX_STATUS_OK); + + value = READ_VIP32(SC1200_VIP_LINE_TARGET); + value &= ~SC1200_VIP_LAST_LINE_MASK; + value |= ((last_line & 0x3FF) << 16); + WRITE_VIP32(SC1200_VIP_LINE_TARGET, value); + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_test_vip_odd_field + * + * This routine returns 1 if the current VIP field is odd. Otherwise returns 0. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_test_vip_odd_field(void) +#else +int gfx_test_vip_odd_field(void) +#endif +{ + if (READ_VIP32(SC1200_VIP_STATUS) & SC1200_VIP_CURRENT_FIELD_ODD) + return(1); + else + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_test_vip_bases_updated + * + * This routine returns 1 if all of the VIP base registers have been updated, + * i.e. there is no base register which has been written with a new address, + * that VIP has not already captured or started capturing into the new address. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_test_vip_bases_updated(void) +#else +int gfx_test_vip_bases_updated(void) +#endif +{ + if (READ_VIP32(SC1200_VIP_STATUS) & SC1200_VIP_BASE_NOT_UPDATED) + return(0); + else + return(1); +} + +/*----------------------------------------------------------------------------- + * gfx_test_vip_fifo_overflow + * + * This routine returns 1 if an overflow occurred on the FIFO between the VIP + * and the fast X-bus, 0 otherwise. + * If an overflow occurred, the overflow status indication is reset. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_test_vip_fifo_overflow(void) +#else +int gfx_test_vip_fifo_overflow(void) +#endif +{ + if (READ_VIP32(SC1200_VIP_STATUS) & SC1200_VIP_FIFO_OVERFLOW) { + /* Bits in vip status register are either read only or reset by writing 1 */ + WRITE_VIP32(SC1200_VIP_STATUS, SC1200_VIP_FIFO_OVERFLOW); + return(1); + } else { + return(0); + } +} + +/*----------------------------------------------------------------------------- + * gfx_get_vip_line + * + * This routine returns the number of the current video line being + * received by the VIP interface. + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_get_vip_line(void) +#else +int gfx_get_vip_line(void) +#endif +{ + return (int)(READ_VIP32(SC1200_VIP_CURRENT_LINE) & SC1200_VIP_CURRENT_LINE_MASK); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vip_base + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +unsigned long sc1200_get_vip_base(int odd) +#else +unsigned long gfx_get_vip_base(int odd) +#endif +{ + /* MASK BIT 23 AND ABOVE TO MAKE IT A TRUE OFFSET */ + + if (odd) return(READ_VIP32(SC1200_VIP_ODD_BASE)); + return(READ_VIP32(SC1200_VIP_EVEN_BASE)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vbi_pitch + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +unsigned long sc1200_get_vbi_pitch(void) +#else +unsigned long gfx_get_vbi_pitch(void) +#endif +{ + return(READ_VIP32(SC1200_VBI_PITCH) & SC1200_VBI_PITCH_MASK); +} + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +#if GFX_READ_ROUTINES + +/*----------------------------------------------------------------------------- + * gfx_get_vip_enable + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_get_vip_enable(void) +#else +int gfx_get_vip_enable(void) +#endif +{ + if (READ_VIP32(SC1200_VIP_CONTROL) & SC1200_VIP_DATA_CAPTURE_EN) return(1); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vip_pitch + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +unsigned long sc1200_get_vip_pitch(void) +#else +unsigned long gfx_get_vip_pitch(void) +#endif +{ + return(READ_VIP32(SC1200_VIP_PITCH) & SC1200_VIP_PITCH_MASK); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vip_mode + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_get_vip_mode(void) +#else +int gfx_get_vip_mode(void) +#endif +{ + switch(READ_VIP32(SC1200_VIP_CONFIG) & SC1200_VIP_MODE_MASK) + { + case SC1200_VIP_MODE_C: return VIP_MODE_C; + default: return(0); + } +} + +/*----------------------------------------------------------------------------- + * gfx_get_vbi_enable + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_get_vbi_enable(void) +#else +int gfx_get_vbi_enable(void) +#endif +{ + if (READ_VIP32(SC1200_VIP_CONTROL) & SC1200_VIP_VBI_CAPTURE_EN) return(1); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vbi_mode + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_get_vbi_mode(void) +#else +int gfx_get_vbi_mode(void) +#endif +{ + int config; + int mode = 0; + config = (int)(READ_VIP32(SC1200_VIP_CONFIG) & (SC1200_VBI_ANCILLARY_TO_MEMORY | SC1200_VBI_TASK_A_TO_MEMORY | + SC1200_VBI_TASK_B_TO_MEMORY)); + if (config & SC1200_VBI_ANCILLARY_TO_MEMORY) mode |= VBI_ANCILLARY; + if (config & SC1200_VBI_TASK_A_TO_MEMORY) mode |= VBI_TASK_A; + if (config & SC1200_VBI_TASK_B_TO_MEMORY) mode |= VBI_TASK_B; + return mode; +} + +/*----------------------------------------------------------------------------- + * gfx_get_vbi_base + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +unsigned long sc1200_get_vbi_base(int odd) +#else +unsigned long gfx_get_vbi_base(int odd) +#endif +{ + /* MASK BIT 23 AND ABOVE TO MAKE IT A TRUE OFFSET */ + + if (odd) return(READ_VIP32(SC1200_VBI_ODD_BASE)); + return(READ_VIP32(SC1200_VBI_EVEN_BASE)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vbi_direct + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +unsigned long sc1200_get_vbi_direct(int odd) +#else +unsigned long gfx_get_vbi_direct(int odd) +#endif +{ + /* MASK BIT 23 AND ABOVE TO MAKE IT A TRUE OFFSET */ + + if (odd) return(READ_VIP32(SC1200_ODD_DIRECT_VBI_LINE_ENABLE) & SC1200_DIRECT_VBI_LINE_ENABLE_MASK); + return(READ_VIP32(SC1200_EVEN_DIRECT_VBI_LINE_ENABLE) & SC1200_DIRECT_VBI_LINE_ENABLE_MASK); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vbi_interrupt + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_get_vbi_interrupt(void) +#else +int gfx_get_vbi_interrupt(void) +#endif +{ + if (READ_VIP32(SC1200_VIP_CONTROL) & SC1200_VIP_VBI_FIELD_INTERRUPT_EN) return(1); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vip_bus_request_threshold_high + *----------------------------------------------------------------------------- + */ +#if GFX_VIP_DYNAMIC +int sc1200_get_vip_bus_request_threshold_high(void) +#else +int gfx_get_vip_bus_request_threshold_high(void) +#endif +{ + if (READ_VIP32(SC1200_VIP_CONFIG) & SC1200_VIP_BUS_REQUEST_THRESHOLD) return(1); + return(0); +} + +#endif /* GFX_READ_ROUTINES */ + +/* END OF FILE */ + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_dcdr.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_dcdr.c 2005-12-14 11:36:52.000000000 -0700 @@ -0,0 +1,450 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to control the video decoder. + * + * gfx_set_decoder_defaults + * gfx_set_decoder_analog_input + * gfx_set_decoder_brightness + * gfx_set_decoder_contrast + * gfx_set_decoder_luminance_filter + * gfx_set_decoder_hue + * gfx_set_decoder_saturation + * gfx_set_decoder_input_offset + * gfx_set_decoder_input_size + * gfx_set_decoder_output_size + * gfx_set_decoder_scale + * gfx_set_decoder_TV_standard + * gfx_set_decoder_vbi_enable + * gfx_set_decoder_vbi_format + * gfx_set_decoder_vbi_upscale + * gfx_decoder_software_reset + * gfx_decoder_detect_macrovision + * gfx_decoder_detect_video + * + * And the following routines if GFX_READ_ROUTINES is set: + * + * gfx_get_decoder_brightness + * gfx_get_decoder_contrast + * gfx_get_decoder_hue + * gfx_get_decoder_saturation + * gfx_get_decoder_input_offset + * gfx_get_decoder_input_size + * gfx_get_decoder_output_size + * gfx_get_decoder_vbi_format + * */ + + +/* INCLUDE SUPPORT FOR PHILIPS SAA7114 DECODER, IF SPECIFIED */ + +#if GFX_DECODER_SAA7114 +#include "saa7114.c" +#endif + +/* WRAPPERS IF DYNAMIC SELECTION */ +/* Extra layer to call various decoders. Currently only the Pillips */ +/* decoder is supported, but still organized to easily expand later. */ + +#if GFX_DECODER_DYNAMIC + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_defaults + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_defaults(void) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_defaults(); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_analog_input + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_analog_input(unsigned char input) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_analog_input(input); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_brightness + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_brightness(unsigned char brightness) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_brightness(brightness); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_contrast + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_contrast(unsigned char contrast) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_contrast(contrast); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_hue + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_hue(char hue) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_hue(hue); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_saturation + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_saturation(unsigned char saturation) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_saturation(saturation); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_input_offset + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_input_offset(unsigned short x, unsigned short y) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_input_offset(x, y); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_input_size + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_input_size(unsigned short width, unsigned short height) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_input_size(width, height); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_output_size + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_output_size(unsigned short width, unsigned short height) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_output_size(width, height); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_scale + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_scale(srcw, srch, dstw, dsth); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_vbi_format + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_vbi_format(int start, int end, int format) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_vbi_format(start, end, format); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_vbi_enable + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_vbi_enable(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_vbi_enable(enable); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_vbi_upscale + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_vbi_upscale(void) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_vbi_upscale(); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_TV_standard + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_TV_standard(TVStandardType TVStandard) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_TV_standard(TVStandard); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_luminance_filter + *----------------------------------------------------------------------------- + */ +int gfx_set_decoder_luminance_filter(unsigned char lufi) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_set_decoder_luminance_filter(lufi); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_decoder_software_reset + *----------------------------------------------------------------------------- + */ +int gfx_decoder_software_reset(void) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_decoder_software_reset(); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_decoder_detect_macrovision + *----------------------------------------------------------------------------- + */ +int gfx_decoder_detect_macrovision(void) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_decoder_detect_macrovision(); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_decoder_detect_video + *----------------------------------------------------------------------------- + */ +int gfx_decoder_detect_video(void) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + status = saa7114_decoder_detect_video(); +#endif + return(status); +} + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +#if GFX_READ_ROUTINES + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_brightness + *----------------------------------------------------------------------------- + */ +unsigned char gfx_get_decoder_brightness(void) +{ + unsigned char brightness = 0; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + brightness = saa7114_get_decoder_brightness(); +#endif + return(brightness); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_contrast + *----------------------------------------------------------------------------- + */ +unsigned char gfx_get_decoder_contrast(void) +{ + unsigned char contrast = 0; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + contrast = saa7114_get_decoder_contrast(); +#endif + return(contrast); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_hue + *----------------------------------------------------------------------------- + */ +char gfx_get_decoder_hue(void) +{ + unsigned char hue = 0; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + hue = saa7114_get_decoder_hue(); +#endif + return((char)hue); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_saturation + *----------------------------------------------------------------------------- + */ +unsigned char gfx_get_decoder_saturation(void) +{ + unsigned char saturation = 0; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + saturation = saa7114_get_decoder_saturation(); +#endif + return(saturation); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_input_offset + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_decoder_input_offset() +{ + unsigned long offset = 0; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + offset = saa7114_get_decoder_input_offset(); +#endif + return(offset); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_input_size + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_decoder_input_size() +{ + unsigned long size = 0; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + size = saa7114_get_decoder_input_size(); +#endif + return(size); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_output_size + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_decoder_output_size() +{ + unsigned long size = 0; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + size = saa7114_get_decoder_output_size(); +#endif + return(size); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_vbi_format + *----------------------------------------------------------------------------- + */ +int gfx_get_decoder_vbi_format(int line) +{ + int format = 0; +#if GFX_DECODER_SAA7114 + if (gfx_decoder_type == GFX_DECODER_SAA7114) + format = saa7114_get_decoder_vbi_format(line); +#endif + return(format); +} + +#endif /* GFX_READ_ROUTINES */ + +#endif /* GFX_DECODER_DYNAMIC */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_defs.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_defs.h 2005-12-14 11:36:40.000000000 -0700 @@ -0,0 +1,333 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This header file contains the macros used to access the hardware. These + * macros assume that 32-bit access is possible, which is true for most + * applications. Projects using 16-bit compilers (the Windows98 display + * driver) and special purpose applications (such as Darwin) need to define + * their own versions of these macros, which typically call a subroutine. + * */ + + +/* ACCESS TO THE CPU REGISTERS */ + +#define WRITE_REG8(offset, value) \ + (*(volatile unsigned char *)(gfx_virt_regptr + (offset))) = (value) + +#define WRITE_REG16(offset, value) \ + (*(volatile unsigned short *)(gfx_virt_regptr + (offset))) = (value) + +#define WRITE_REG32(offset, value) \ + (*(volatile unsigned long *)(gfx_virt_regptr + (offset))) = (value) + +#define READ_REG16(offset) \ + (*(volatile unsigned short *)(gfx_virt_regptr + (offset))) + +#define READ_REG32(offset) \ + (*(volatile unsigned long *)(gfx_virt_regptr + (offset))) + +/* ACCESS TO THE ACCELERATOR REGISTERS (REDCLOUD ONLY) */ + +#define WRITE_GP8(offset, value) \ + (*(volatile unsigned char *)(gfx_virt_gpptr + (offset))) = (value) + +#define WRITE_GP16(offset, value) \ + (*(volatile unsigned short *)(gfx_virt_gpptr + (offset))) = (value) + +#define WRITE_GP32(offset, value) \ + (*(volatile unsigned long *)(gfx_virt_gpptr + (offset))) = (value) + +#define READ_GP16(offset) \ + (*(volatile unsigned short *)(gfx_virt_gpptr + (offset))) + +#define READ_GP32(offset) \ + (*(volatile unsigned long *)(gfx_virt_gpptr + (offset))) + +/* ACCESS TO THE FRAME BUFFER */ + +#define WRITE_FB32(offset, value) \ + (*(volatile unsigned long *)(gfx_virt_fbptr + (offset))) = (value) + +#define WRITE_FB16(offset, value) \ + (*(volatile unsigned short *)(gfx_virt_fbptr + (offset))) = (value) + +#define WRITE_FB8(offset, value) \ + (*(volatile unsigned char *)(gfx_virt_fbptr + (offset))) = (value) + +/* ACCESS TO THE VIDEO HARDWARE */ + +#define READ_VID32(offset) \ + (*(volatile unsigned long *)(gfx_virt_vidptr + (offset))) + +#define WRITE_VID32(offset, value) \ + (*(volatile unsigned long *)(gfx_virt_vidptr + (offset))) = (value) + +/* ACCESS TO THE VIP HARDWARE */ + +#define READ_VIP32(offset) \ + (*(volatile unsigned long *)(gfx_virt_vipptr + (offset))) + +#define WRITE_VIP32(offset, value) \ + (*(volatile unsigned long *)(gfx_virt_vipptr + (offset))) = (value) + +/* ACCESS TO THE SCRATCHPAD RAM */ + +#define WRITE_SCRATCH32(offset, value) \ + (*(volatile unsigned long *)(gfx_virt_spptr + (offset))) = (value) + +#define WRITE_SCRATCH16(offset, value) \ + (*(volatile unsigned short *)(gfx_virt_spptr + (offset))) = (value) + +#define WRITE_SCRATCH8(offset, value) \ + (*(volatile unsigned char *)(gfx_virt_spptr + (offset))) = (value) + +#define READ_SCRATCH16(offset) \ + (*(volatile unsigned short *)(gfx_virt_spptr + (offset))) + +#define READ_SCRATCH32(offset) \ + (*(volatile unsigned long *)(gfx_virt_spptr + (offset))) + +/* ACCESS TO MSRS */ + +void gfx_msr_asm_write (unsigned short msrReg, unsigned long msrAddr, unsigned long *ptrHigh, unsigned long *ptrLow); +void gfx_msr_asm_read (unsigned short msrReg, unsigned long msrAddr, unsigned long *ptrHigh, unsigned long *ptrLow); + +#define MSR_READ( MBD_MSR_CAP, address, valueHigh_ptr, valueLow_ptr ) \ + gfx_msr_asm_read( ((unsigned short)(MBD_MSR_CAP)), address, valueHigh_ptr, valueLow_ptr ) + +#define MSR_WRITE( MBD_MSR_CAP, address, valueHigh_ptr, valueLow_ptr ) \ + gfx_msr_asm_write( ((unsigned short)(MBD_MSR_CAP)), address, valueHigh_ptr, valueLow_ptr ) + +/* OPTIMIZATION MACROS */ +/* The following macros have been added to allow more complete optimization of the */ +/* bitmap-to-screen routines in Durango. These routines also allow Durango to run */ +/* properly within a 16-bit environment. */ + +/************************************************************************************ + * Macro: SET_SCRATCH_BASE + * Purpose: Record the base address of the BLT buffers. The WRITE_SCRATCH_STRINGxx + * macros assume that this address is used as the base for all writes. + * + * Arguments: + * scratch_base - offset into the GX base for the first BLT buffer byte. + ************************************************************************************/ + +#define SET_SCRATCH_BASE(scratch_base) \ + { gfx_gx1_scratch_base = (unsigned long)gfx_virt_spptr + scratch_base; } + +#ifdef GFX_OPTIMIZE_ASSEMBLY + +/************************************************************************************ + * Macro: WRITE_SCRATCH_STRING + * Purpose: Write multiple bytes to the scratchpad buffer + * + * Arguments: + * dword_bytes - number of bytes to transfer. This number will always. + * be a multiple of 4. It cannot be modified within the + * macro (ex. bytes -= 4) + * bytes_extra - number of non-DWORD aligned bytes + * array - pointer to an array of unsigned characters. + * array_offset - offset into the array from which to pull the first character. + ************************************************************************************/ + +#define WRITE_SCRATCH_STRING(dwords, bytes, array, array_offset) \ +{ \ + _asm { mov edi, gfx_gx1_scratch_base } \ + _asm { mov esi, array } \ + _asm { add esi, array_offset } \ + _asm { mov ecx, dwords } \ + _asm { shr ecx, 2 } \ + _asm { rep movsd } \ + _asm { mov ecx, bytes } \ + _asm { rep movsb } \ +} + +/************************************************************************************ + * Macro: WRITE_FRAME_BUFFER_STRING32 + * Purpose: Write multiple dwords to the Frame buffer + * + * Arguments: + * fboffset - offset to the beginning frame buffer location. + * bytes - number of bytes to transfer. This number will always. + * be a multiple of 4. It cannot be modified within the + * macro (ex. bytes -= 4) + * array - pointer to an array of unsigned characters. + * array_offset - offset into the array from which to pull the first character. + ************************************************************************************/ + +#define WRITE_FRAME_BUFFER_STRING32(fboffset, bytes, array, array_offset) \ +{ \ + _asm { mov ecx, bytes } \ + _asm { shr ecx, 2 } \ + _asm { cld } \ + _asm { mov edi, gfx_virt_fbptr } \ + _asm { add edi, fboffset } \ + _asm { mov esi, array } \ + _asm { add esi, array_offset } \ + _asm { rep movsd } \ +} + +#else + +/************************************************************************************ + * Macro: WRITE_SCRATCH_STRING + * Purpose: Write multiple bytes to the scratchpad buffer + * + * Arguments: + * dword_bytes - number of bytes to transfer. This number will always. + * be a multiple of 4. It cannot be modified within the + * macro (ex. bytes -= 4) + * bytes_extra - number of non-DWORD aligned bytes + * array - pointer to an array of unsigned characters. + * array_offset - offset into the array from which to pull the first character. + ************************************************************************************/ + +#define WRITE_SCRATCH_STRING(dword_bytes, bytes_extra, array, array_offset) \ +{ \ + unsigned long i, j; \ + unsigned long aroffset = (unsigned long)array + (array_offset); \ + \ + /* WRITE DWORDS */ \ + \ + for (i = 0; i < dword_bytes; i += 4) \ + *((volatile unsigned long *)(gfx_gx1_scratch_base + i)) = *((unsigned long *)(aroffset + i)); \ + \ + /* WRITE BYTES */ \ + \ + j = i + bytes_extra; \ + while (i < j) \ + { \ + *((volatile unsigned char *)(gfx_gx1_scratch_base + i)) = *((unsigned char *)(aroffset + i)); \ + i++; \ + } \ +} + +/************************************************************************************ + * Macro: WRITE_FRAME_BUFFER_STRING32 + * Purpose: Write multiple dwords to the Frame buffer + * + * Arguments: + * fboffset - offset to the beginning frame buffer location. + * bytes - number of bytes to transfer. This number will always. + * be a multiple of 4. It cannot be modified within the + * macro (ex. bytes -= 4) + * array - pointer to an array of unsigned characters. + * array_offset - offset into the array from which to pull the first character. + ************************************************************************************/ + +#define WRITE_FRAME_BUFFER_STRING32(fboffset, bytes, array, array_offset) \ +{ \ + unsigned long i; \ + unsigned long aroffset = (unsigned long)array + (array_offset); \ + for (i = 0; i < bytes; i += 4) \ + WRITE_FB32 ((fboffset) + i, *((unsigned long *)(aroffset + i))); \ +} + +#endif + +/************************************************************************************ + * Macro: WRITE_FRAME_BUFFER_STRING8 + * Purpose: Write multiple bytes to the frame buffer + * + * Arguments: + * spoffset - offset to the beginning frame buffer location. + * bytes - number of bytes to transfer. This number cannot be modified within the + * macro (ex. bytes -= 4) + * array - pointer to an array of unsigned characters. + * array_offset - offset into the array from which to pull the first character. + ************************************************************************************/ + +#define WRITE_FRAME_BUFFER_STRING8(fboffset, bytes, array, array_offset) \ +{ \ + unsigned long i; \ + unsigned long aroffset = (unsigned long)array + (array_offset); \ + for (i = 0; i < bytes; i++) \ + WRITE_FB8 ((fboffset) + i, *((unsigned char *)(aroffset + i))); \ +} + +/************************************************************************************ + * Macro: WRITE_GPREG_STRING32 + * Purpose: Write multiple dwords to one GP register. + * + * Arguments: + * regoffset - Offset of the GP register to be written. + * dwords - number of dwords to transfer. It cannot be modified within the + * macro (ex. dwords--) + * counter - name of a counter variable that can be used in a loop. This + * is used to optimize macros written in C. + * array - pointer to an array of unsigned characters. + * array_offset - offset into the array from which to pull the first character. + * temp - name of a temporary variable that can be used for calculations. + * This argument is also used for C-only macros. + ************************************************************************************/ + +#define WRITE_GPREG_STRING32(regoffset, dwords, counter, array, array_offset, temp) \ +{ \ + temp = (unsigned long)array + (array_offset); \ + for (counter = 0; counter < dwords; counter++) \ + WRITE_GP32 (regoffset, *((unsigned long *)temp + counter)); \ +} + +/************************************************************************************ + * Macro: WRITE_GPREG_STRING8 + * Purpose: Write 4 or less bytes to one GP register. + * + * Arguments: + * regoffset - Offset of the GP register to be written. + * bytes - number of bytes to transfer. This number will always. + * be less than 4. It cannot be modified within the + * macro (ex. bytes--) + * shift - name of a shift variable that can be used as a shift count. + * This variable holds the initial shift value into the GP register. + * counter - name of a counter variable that can be used in a loop. This + * is used to optimize macros written in C. + * array - pointer to an array of unsigned characters. + * array_offset - offset into the array from which to pull the first character. + * temp1 - name of a temporary variable that can be used for calculations. + * This argument is also used for C-only macros. + * temp2 - name of a temporary variable that can be used for calculations. + * This argument is also used for C-only macros. + ************************************************************************************/ +#define WRITE_GPREG_STRING8(regoffset, bytes, shift, counter, array, array_offset, temp1, temp2) \ +{ \ + if (bytes) \ + { \ + temp1 = (unsigned long)array + (array_offset); \ + temp2 = 0; \ + for (counter = 0; counter < bytes; counter++) \ + { \ + temp2 |= ((unsigned long)(*((unsigned char *)(temp1 + counter)))) << shift; \ + shift += 8; \ + } \ + WRITE_GP32 (regoffset, temp2); \ + } \ +} + + +/* END OF FILE */ + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_disp.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_disp.c 2005-12-14 11:36:30.000000000 -0700 @@ -0,0 +1,2596 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to program the display controller. + * + * The "disp_gu1.c" and "disp_gu2.c" files implement the following routines: + * + * gfx_get_display_mode_count + * gfx_get_display_mode + * gfx_is_display_mode_supported + * gfx_get_display_details + * gfx_set_display_mode + * gfx_set_display_bpp + * gfx_set_display_timings + * gfx_set_vtotal + * gfx_get_display_pitch + * gfx_set_display_pitch + * gfx_set_display_offset + * gfx_set_display_palette + * gfx_set_display_palette_entry + * gfx_set_cursor_enable + * gfx_set_cursor_colors + * gfx_set_cursor_position + * gfx_set_cursor_shape32 + * gfx_set_cursor_shape64 + * gfx_set_compression_enable + * gfx_set_compression_offset + * gfx_set_compression_pitch + * gfx_set_compression_size + * gfx_set_display_priority_high + * gfx_test_timing_active + * gfx_test_vertical_active + * gfx_wait_vertical_blank + * gfx_reset_timing_lock + * + * And the following routines if GFX_READ_ROUTINES is set: + * + * gfx_get_hactive + * gfx_get_hblank_start + * gfx_get_hsync_start + * gfx_get_hsync_end + * gfx_get_hblank_end + * gfx_get_htotal + * gfx_get_vactive + * gfx_get_vblank_start + * gfx_get_vsync_start + * gfx_get_vsync_end + * gfx_get_vblank_end + * gfx_get_vtotal + * gfx_get_vline + * gfx_get_display_bpp + * gfx_get_display_offset + * gfx_get_display_palette + * gfx_get_cursor_enable + * gfx_get_cursor_base + * gfx_get_cursor_position + * gfx_get_cursor_offset + * gfx_get_cursor_color + * gfx_get_compression_enable + * gfx_get_compression_offset + * gfx_get_compression_pitch + * gfx_get_compression_size + * gfx_get_display_priority_high + * gfx_get_valid_bit + * */ + + +unsigned short PanelWidth=0; +unsigned short PanelHeight=0; +unsigned short PanelEnable=0; +unsigned short ModeWidth; +unsigned short ModeHeight; + +int DeltaX=0; +int DeltaY=0; +unsigned long prevstartAddr =0; +unsigned long panelTop =0; +unsigned long panelLeft =0; + +int gbpp=8; + +int gfx_compression_enabled = 0; +int gfx_compression_active = 0; +int gfx_line_double = 0; +int gfx_pixel_double = 0; +int gfx_timing_lock = 0; +DISPLAYMODE gfx_display_mode; + +/* DISPLAY MODE TIMINGS */ + +DISPLAYMODE DisplayParams[] = { + +/* 320 x 200 */ + +{ GFX_MODE_70HZ | /* refresh rate = 60 */ + GFX_MODE_8BPP | GFX_MODE_16BPP | /* 8 and 16 BPP valid */ + GFX_MODE_NEG_HSYNC | /* negative HSYNC */ + GFX_MODE_PIXEL_DOUBLE | /* Double width */ + GFX_MODE_LINE_DOUBLE, /* Double height */ + 0x140, 0x288, 0x290, 0x2F0, 0x318, 0x320, /* horizontal timings */ + 0x0C8, 0x197, 0x19C, 0x19E, 0x1BA, 0x1C1, /* vertical timings */ + 0x00192CCC, /* freq = 25.175 MHz */ +}, + +/* 320 x 240 */ + +{ GFX_MODE_75HZ | /* refresh rate = 75 */ + GFX_MODE_8BPP | GFX_MODE_16BPP | /* 8 and 16 BPP valid */ + GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC | /* negative syncs */ + GFX_MODE_PIXEL_DOUBLE | /* Double width */ + GFX_MODE_LINE_DOUBLE, /* Double height */ + 0x0140, 0x0280, 0x0290, 0x02D0, 0x0348, 0x0348, /* horizontal timings */ + 0x00F0, 0x01E0, 0x01E1, 0x01E4, 0x01F4, 0x01F4, /* vertical timings */ + 0x001F8000, /* freq = 31.5 MHz */ +}, + +/* 400 x 300 */ + +{ GFX_MODE_75HZ | /* refresh rate = 75 */ + GFX_MODE_8BPP | GFX_MODE_16BPP | /* 8 and 16 BPP valid */ + GFX_MODE_PIXEL_DOUBLE | /* Double width */ + GFX_MODE_LINE_DOUBLE, /* Double height */ + 0x0190, 0x0320, 0x0330, 0x0380, 0x0420, 0x0420, /* horizontal timings */ + 0x012C, 0x0258, 0x0259, 0x025C, 0x0271, 0x0271, /* vertical timings */ + 0x00318000, /* freq = 49.5 MHz */ +}, + +/* 512 x 384 */ + +{ GFX_MODE_75HZ | /* refresh rate = 75 */ + GFX_MODE_8BPP | GFX_MODE_16BPP | /* 8 and 16 BPP valid */ + GFX_MODE_PIXEL_DOUBLE | /* Double width */ + GFX_MODE_LINE_DOUBLE, /* Double height */ + 0x0200, 0x0400, 0x0410, 0x0470, 0x0520, 0x0520, /* horizontal timings */ + 0x0180, 0x0300, 0x0301, 0x0304, 0x0320, 0x0320, /* vertical timings */ + 0x004EC000, /* freq = 78.75 MHz */ +}, + +/* 640 x 400 */ + +{ GFX_MODE_70HZ | /* refresh rate = 60 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP | + GFX_MODE_NEG_HSYNC, /* negative HSYNC */ + 0x280, 0x288, 0x290, 0x2F0, 0x318, 0x320, /* horizontal timings */ + 0x190, 0x197, 0x19C, 0x19E, 0x1BA, 0x1C1, /* vertical timings */ + 0x00192CCC, /* freq = 25.175 MHz */ +}, + +/* 640x480 */ + +{ GFX_MODE_60HZ | /* refresh rate = 60 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP | + GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC, /* negative syncs */ + 0x0280, 0x0288, 0x0290, 0x02E8, 0x0318, 0x0320, /* horizontal timings */ + 0x01E0, 0x01E8, 0x01EA, 0x01EC, 0x0205, 0x020D, /* vertical timings */ + 0x00192CCC, /* freq = 25.175 MHz */ +}, + +{ GFX_MODE_70HZ | /* refresh rate = 60 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0280, 0x0280, 0x0298, 0x02D8, 0x0330, 0x0330, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01E2, 0x01E5, 0x01F4, 0x01F4, /* vertical timings */ + 0x001C8F5C, /* freq = 28.560 MHz */ +}, + +{ GFX_MODE_72HZ | /* refresh rate = 72 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP | + GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC, /* negative syncs */ + 0x0280, 0x0288, 0x0298, 0x02c0, 0x0338, 0x0340, /* horizontal timings */ + 0x01e0, 0x01e8, 0x01e9, 0x01ec, 0x0200, 0x0208, /* vertical timings */ + 0x001F8000, /* freq = 31.5 MHz */ +}, + +{ GFX_MODE_75HZ | /* refresh rate = 75 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP | + GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC, /* negative syncs */ + 0x0280, 0x0280, 0x0290, 0x02D0, 0x0348, 0x0348, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01E1, 0x01E4, 0x01F4, 0x01F4, /* vertical timings */ + 0x001F8000, /* freq = 31.5 MHz */ +}, + +{ GFX_MODE_85HZ | /* refresh rate = 85 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP | + GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC, /* negative syncs */ + 0x0280, 0x0280, 0x02B8, 0x02F0, 0x0340, 0x0340, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01E1, 0x01E4, 0x01FD, 0x01FD, /* vertical timings */ + 0x00240000, /* freq = 36.0 MHz */ +}, + +{ GFX_MODE_90HZ | /* refresh rate = 90 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0280, 0x0280, 0x02A0, 0x02E0, 0x0340, 0x0340, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01E1, 0x01E4, 0x01FA, 0x01FA, /* vertical timings */ + 0x0025E395, /* freq = 37.889 MHz */ +}, + +{ GFX_MODE_100HZ | /* refresh rate = 100 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0280, 0x0280, 0x02A8, 0x02E8, 0x0350, 0x0350, /* horizontal timings */ + 0x01E0, 0x01E0, 0x01E1, 0x01E4, 0x01FD, 0x01FD, /* vertical timings */ + 0x002B29BA, /* freq = 43.163 MHz */ +}, + +/* 800x600 */ + +{ GFX_MODE_56HZ | /* refresh rate = 56 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0320, 0x0320, 0x0338, 0x0380, 0x0400, 0x0400, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025B, 0x0271, 0x0271, /* vertical timings */ + 0x00240000, /* freq = 36.00 MHz */ +}, + +{ GFX_MODE_60HZ | /* refresh rate = 60 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0320, 0x0328, 0x0348, 0x03D0, 0x0418, 0x0420, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025D, 0x0274, 0x0274, /* vertical timings */ + 0x00280000, /* freq = 40.00 MHz */ +}, + +{ GFX_MODE_70HZ | /* refresh rate = 70 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0320, 0x0320, 0x0348, 0x0398, 0x0410, 0x0410, /* horizontal timings */ + 0x0258, 0x0258, 0x025c, 0x025F, 0x0274, 0x0274, /* vertical timings */ + 0x002DB851, /* freq = 45.72 MHz */ +}, + +{ GFX_MODE_72HZ | /* refresh rate = 72 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0320, 0x0320, 0x0358, 0x03D0, 0x0410, 0x0410, /* horizontal timings */ + 0x0258, 0x0258, 0x027D, 0x0283, 0x029A, 0x029A, /* vertical timings */ + 0x00320000, /* freq = 49.5 MHz */ +}, + +{ GFX_MODE_75HZ | /* refresh rate = 75 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0320, 0x0320, 0x0330, 0x0380, 0x0420, 0x0420, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025C, 0x0271, 0x0271, /* vertical timings */ + 0x00318000, /* freq = 49.5 MHz */ +}, + +{ GFX_MODE_85HZ | /* refresh rate = 85 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0320, 0x0320, 0x0340, 0x0380, 0x0418, 0x0418, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025C, 0x0277, 0x0277, /* vertical timings */ + 0x00384000, /* freq = 56.25 MHz */ +}, + +{ GFX_MODE_90HZ | /* refresh rate = 90 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0320, 0x0320, 0x0348, 0x03A0, 0x0420, 0x0420, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025C, 0x0278, 0x0278, /* vertical timings */ + 0x003C10A3, /* freq = 60.065 MHz */ +}, + +{ GFX_MODE_100HZ | /* refresh rate = 100 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0320, 0x0320, 0x0350, 0x03A8, 0x0430, 0x0430, /* horizontal timings */ + 0x0258, 0x0258, 0x0259, 0x025C, 0x0277, 0x027C, /* vertical timings */ + 0x00442DD2, /* freq = 68.179 MHz */ +}, + +/* 1024x768 */ + +{ GFX_MODE_60HZ | /* refresh rate = 60 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP | + GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC, /* negative syncs */ + 0x0400, 0x0400, 0x0418, 0x04A0, 0x0540, 0x0540, /* horizontal timings */ + 0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326, /* vertical timings */ + 0x00410000, /* freq = 65.00 MHz */ +}, + +{ GFX_MODE_70HZ | /* refresh rate = 70 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP | + GFX_MODE_NEG_HSYNC | GFX_MODE_NEG_VSYNC, /* negative syncs */ + 0x0400, 0x0400, 0x0418, 0x04A0, 0x0530, 0x0530, /* horizontal timings */ + 0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326, /* vertical timings */ + 0x004B0000, /* freq = 75.00 MHz */ +}, + +{ GFX_MODE_72HZ | /* refresh rate = 72 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0400, 0x0400, 0x0438, 0x04A8, 0x0550, 0x0550, /* horizontal timings */ + 0x0300, 0x0300, 0x0304, 0x0307, 0x0324, 0x0324, /* vertical timings */ + 0x004EC000, /* freq = 78.75 MHz */ +}, + +{ GFX_MODE_75HZ | /* refresh rate = 75 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0400, 0x0400, 0x0410, 0x0470, 0x0520, 0x0520, /* horizontal timings */ + 0x0300, 0x0300, 0x0301, 0x0304, 0x0320, 0x0320, /* vertical timings */ + 0x004EC000, /* freq = 78.75 MHz */ +}, + +{ GFX_MODE_85HZ | /* refresh rate = 85 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0400, 0x0400, 0x0430, 0x0490, 0x0560, 0x0560, /* horizontal timings */ + 0x0300, 0x0300, 0x0301, 0x0304, 0x0328, 0x0328, /* vertical timings */ + 0x005E8000, /* freq = 94.50 MHz */ +}, + +{ GFX_MODE_90HZ | /* refresh rate = 90 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0400, 0x0400, 0x0440, 0x04B0, 0x0560, 0x0560, /* horizontal timings */ + 0x0300, 0x0300, 0x0301, 0x0304, 0x0329, 0x0329, /* vertical timings */ + 0x00642FDF, /* freq = 100.187 MHz */ +}, + +{ GFX_MODE_100HZ | /* refresh rate = 100 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0400, 0x0400, 0x0448, 0x04B8, 0x0570, 0x0570, /* horizontal timings */ + 0x0300, 0x0300, 0x0301, 0x0304, 0x032E, 0x032E, /* vertical timings */ + 0x00714F1A, /* freq = 113.309 MHz */ +}, + +/* 1152x864 */ + +{ GFX_MODE_60HZ | /* refresh rate = 60 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0480, 0x0480, 0x04C0, 0x0538, 0x05F0, 0x05F0, /* horizontal timings */ + 0x0360, 0x0360, 0x0361, 0x0364, 0x037F, 0x037F, /* vertical timings */ + 0x00519999, /* freq = 81.60 MHz */ +}, + +{ GFX_MODE_70HZ | /* refresh rate = 70 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0480, 0x0480, 0x04C8, 0x0540, 0x0600, 0x0600, /* horizontal timings */ + 0x0360, 0x0360, 0x0368, 0x036B, 0x038B, 0x038B, /* vertical timings */ + 0x00618560, /* freq = 97.521 MHz */ +}, + +{ GFX_MODE_72HZ | /* refresh rate = 70 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0480, 0x0480, 0x04C8, 0x0548, 0x0610, 0x0610, /* horizontal timings */ + 0x0360, 0x0360, 0x0367, 0x036A, 0x038B, 0x038B, /* vertical timings */ + 0x00656B85, /* freq = 101.42 MHz */ +}, + +{ GFX_MODE_75HZ | /* refresh rate = 75 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0480, 0x0480, 0x04C0, 0x0540, 0x0640, 0x0640, /* horizontal timings */ + 0x0360, 0x0360, 0x0361, 0x0364, 0x0384, 0x0384, /* vertical timings */ + 0x006C0000, /* freq = 108.00 MHz */ +}, + +{ GFX_MODE_85HZ | /* refresh rate = 85 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0480, 0x0480, 0x04C8, 0x0548, 0x0610, 0x0610, /* horizontal timings */ + 0x0360, 0x0360, 0x0363, 0x0366, 0x038B, 0x038B, /* vertical timings */ + 0x0077A666, /* freq = 119.65 MHz */ +}, + +{ GFX_MODE_90HZ | /* refresh rate = 90 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0480, 0x0480, 0x04D0, 0x0550, 0x0620, 0x0620, /* horizontal timings */ + 0x0360, 0x0360, 0x0363, 0x0366, 0x038E, 0x038E, /* vertical timings */ + 0x00806666, /* freq = 128.40 MHz */ +}, + +{ GFX_MODE_100HZ | /* refresh rate = 100 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0480, 0x0480, 0x04D0, 0x0550, 0x0620, 0x0620, /* horizontal timings */ + 0x0360, 0x0360, 0x0365, 0x0368, 0x0398, 0x0398, /* vertical timings */ + 0x00906147, /* freq = 144.38 MHz */ +}, + +/* 1280x1024 */ + +{ GFX_MODE_60HZ | /* refresh rate = 60 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0500, 0x0500, 0x0530, 0x05A0, 0x0698, 0x0698, /* horizontal timings */ + 0x0400, 0x0400, 0x0401, 0x0404, 0x042A, 0x042A, /* vertical timings */ + 0x006C0000, /* freq = 108.0 MHz */ +}, + +{ GFX_MODE_70HZ | /* refresh rate = 70 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0500, 0x0500, 0x0558, 0x05E0, 0x06C0, 0x06C0, /* horizontal timings */ + 0x0400, 0x0400, 0x040A, 0x040D, 0x0433, 0x0433, /* vertical timings */ + 0x00821999, /* freq = 130.1 MHz */ +}, + +{ GFX_MODE_72HZ | /* refresh rate = 72 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0500, 0x0500, 0x0558, 0x05E0, 0x06C0, 0x06C0, /* horizontal timings */ + 0x0400, 0x0400, 0x0407, 0x040A, 0x0431, 0x0431, /* vertical timings */ + 0x00858000, /* freq = 133.5 MHz */ +}, + +{ GFX_MODE_75HZ | /* refresh rate = 75 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0500, 0x0500, 0x0510, 0x05A0, 0x0698, 0x0698, /* horizontal timings */ + 0x0400, 0x0400, 0x0401, 0x0404, 0x042A, 0x042A, /* vertical timings */ + 0x00870000, /* freq = 135.0 MHz */ +}, + +{ GFX_MODE_85HZ | /* refresh rate = 85 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0500, 0x0500, 0x0540, 0x05E0, 0x06C0, 0x06C0, /* horizontal timings */ + 0x0400, 0x0400, 0x0401, 0x0404, 0x0430, 0x0430, /* vertical timings */ + 0x009D8000, /* freq = 157.5 MHz */ +}, + +{ GFX_MODE_90HZ | /* refresh rate = 90 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0500, 0x0500, 0x0560, 0x05E8, 0x06D0, 0x06D0, /* horizontal timings */ + 0x0400, 0x0400, 0x0401, 0x0404, 0x0436, 0x0436, /* vertical timings */ + 0x00A933F7, /* freq = 169.203 MHz */ +}, + +{ GFX_MODE_100HZ | /* refresh rate = 100 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0500, 0x0500, 0x0560, 0x05F0, 0x06E0, 0x06E0, /* horizontal timings */ + 0x0400, 0x0400, 0x0401, 0x0404, 0x043D, 0x043D, /* vertical timings */ + 0x00BEF5C2, /* freq = 190.96 MHz */ +}, + +/*********************************/ +/* BEGIN REDCLOUD-SPECIFIC MODES */ +/*-------------------------------*/ + +/* 1600 x 1200 */ + +{ GFX_MODE_60HZ | /* refresh rate = 60 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2, /* vertical timings */ + 0x00A20000, /* freq = 162.0 MHz */ +}, + +{ GFX_MODE_70HZ | /* refresh rate = 70 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2, /* vertical timings */ + 0x00BD0000, /* freq = 189.0 MHz */ +}, + +{ GFX_MODE_72HZ | /* refresh rate = 72 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0640, 0x0640, 0x06B0, 0x0760, 0x0880, 0x0880, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04BD, 0x04C0, 0x04EF, 0x04EF, /* vertical timings */ + 0x00C60000, /* freq = 198.0 MHz */ +}, + +{ GFX_MODE_75HZ | /* refresh rate = 75 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2, /* vertical timings */ + 0x00CA8000, /* freq = 202.5 MHz */ +}, + +{ GFX_MODE_85HZ | /* refresh rate = 85 */ + GFX_MODE_8BPP | GFX_MODE_12BPP | GFX_MODE_15BPP | /* all BPP valid */ + GFX_MODE_16BPP | GFX_MODE_24BPP, + 0x0640, 0x0640, 0x0680, 0x0740, 0x0870, 0x0870, /* horizontal timings */ + 0x04B0, 0x04B0, 0x04B1, 0x04B4, 0x04E2, 0x04E2, /* vertical timings */ + 0x00E58000, /* freq = 229.5 MHz */ +}, +}; + +/* UPDATE THIS VARIABLE WHENEVER NEW REDCLOUD-SPECIFIC MODES ARE ADDED */ + +#define REDCLOUD_SPECIFIC_MODES 4 + +#define NUM_RC_DISPLAY_MODES sizeof(DisplayParams) / sizeof(DISPLAYMODE) +#define NUM_GX_DISPLAY_MODES (NUM_RC_DISPLAY_MODES - REDCLOUD_SPECIFIC_MODES) + + +FIXEDTIMINGS FixedParams[] = { +/* 640x480 Panel */ +{ 640 , 480, 640, 480, + 0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320, + 0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D, + 0x00192CCC, +}, + +{ 640 , 480, 800, 600, + 0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320, + 0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D, + 0x00192CCC, +}, + +{ 640 , 480, 1024 , 768, + 0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320, + 0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D, + 0x00192CCC, +}, + +{ 640 , 480, 1152 , 864, + 0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320, + 0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D, + 0x00192CCC, +}, + +{ 640 , 480, 1280, 1024, + 0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320, + 0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D, + 0x00192CCC, +}, + +{ 640 , 480, 1600, 1200, + 0x0280, 0x0280, 0x0290, 0x02E8, 0x0318, 0x0320, + 0x01E0, 0x01E0, 0x01EA, 0x01EC, 0x0205, 0x020D, + 0x00192CCC, +}, + + +/* 800x600 Panel */ +{ 800 , 600, 640, 480, + 0x0280, 0x2d0, 0x2f8, 0x378, 0x3d0, 0x420, + 0x1e0, 0x21c, 0x21d, 0x221, 0x238, 0x274, + 0x00280000, +}, + +{ 800 , 600, 800, 600, + 0x320, 0x320, 0x348, 0x3c8, 0x420, 0x420, + 0x258, 0x258, 0x259, 0x25d, 0x274, 0x274, + 0x00280000, +}, + +{ 800 , 600, 1024, 768, + 0x320, 0x320, 0x348, 0x3c8, 0x420, 0x420, + 0x258, 0x258, 0x259, 0x25d, 0x274, 0x274, + 0x00280000, +}, + +{ 800 , 600, 1152, 864, + 0x320, 0x320, 0x348, 0x3c8, 0x420, 0x420, + 0x258, 0x258, 0x259, 0x25d, 0x274, 0x274, + 0x00280000, +}, + +{ 800 , 600, 1280, 1024, + 0x320, 0x320, 0x348, 0x3c8, 0x420, 0x420, + 0x258, 0x258, 0x259, 0x25d, 0x274, 0x274, + 0x00280000, +}, + +{ 800 , 600, 1600, 1200, + 0x320, 0x320, 0x348, 0x3c8, 0x420, 0x420, + 0x258, 0x258, 0x259, 0x25d, 0x274, 0x274, + 0x00280000, +}, + +/* 1024x768 panel */ +{ 1024 , 768, 640, 480, + 0x0280, 0x340, 0x368, 0x3e8, 0x480, 0x540, + 0x1e0, 0x270, 0x271, 0x275, 0x296, 0x326, + 0x00410000, +}, + +{ 1024 , 768, 800, 600, + 0x0320, 0x390, 0x3b8, 0x438, 0x4D0, 0x540, + 0x258, 0x2ac, 0x2ad, 0x2b1, 0x2D2, 0x326, + 0x00410000, +}, + +{ 1024 , 768, 1024, 768, + 0x0400, 0x0400, 0x0418, 0x04A0, 0x0540, 0x0540, + 0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326, + 0x00410000, +}, + + +{ 1024 , 768, 1152, 864, + 0x0400, 0x0400, 0x0418, 0x04A0, 0x0540, 0x0540, + 0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326, + 0x00410000, +}, + +{ 1024 , 768, 1280, 1024, + 0x0400, 0x0400, 0x0418, 0x04A0, 0x0540, 0x0540, + 0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326, + 0x00410000, +}, + +{ 1024 , 768, 1600, 1200, + 0x0400, 0x0400, 0x0418, 0x04A0, 0x0540, 0x0540, + 0x0300, 0x0300, 0x0303, 0x0309, 0x0326, 0x0326, + 0x00410000, +}, + +/* 1280x1024 panel */ +{ 1280 , 1024, 640, 480, + 640, 960, 1008, 1120, 1368, 1688, + 480, 752, 753, 756, 794, 1066, + 0x006C0000, +}, + +{ 1280 , 1024, 800, 600, + 800, 1040, 1088, 1200, 1448, 1688, + 600, 812, 813, 816, 854, 1066, + 0x006C0000, +}, + +{ 1280 , 1024, 1024, 768, + 1024, 1152, 1200, 1312, 1560, 1688, + 768, 896, 897, 900, 938, 1066, + 0x006C0000, +}, + +{ 1280 , 1024, 1152, 864, + 1152, 1216, 1264, 1376, 1624, 1688, + 864, 944, 945, 948, 986, 1066, + 0x006C0000, +}, + +{ 1280 , 1024, 1280, 1024, + 1280, 1280, 1328, 1440, 1688, 1688, + 1024, 1024, 1025, 1028, 1066, 1066, + 0x006C0000, +}, + +}; + + +#define NUM_FIXED_TIMINGS_MODES sizeof(FixedParams)/sizeof(FIXEDTIMINGS) + + +/* INCLUDE SUPPORT FOR FIRST GENERATION, IF SPECIFIED. */ + +#if GFX_DISPLAY_GU1 +#include "disp_gu1.c" +#endif + +/* INCLUDE SUPPORT FOR SECOND GENERATION, IF SPECIFIED. */ + +#if GFX_DISPLAY_GU2 +#include "disp_gu2.c" +#endif + +#if GFX_DISPLAY_GU3 +#include "disp_gu3.c" +#endif + +/*--------------------------------------------------------------------------- + * gfx_reset_timing_lock + * + * This routine resets the timing change lock. The lock can only be set by + * setting a flag when calling mode set. + *--------------------------------------------------------------------------- + */ +void gfx_reset_timing_lock(void) +{ + gfx_timing_lock = 0; +} + +/* WRAPPERS IF DYNAMIC SELECTION */ +/* Extra layer to call either first or second generation routines. */ + +#if GFX_DISPLAY_DYNAMIC + +/*--------------------------------------------------------------------------- + * gfx_set_display_bpp + *--------------------------------------------------------------------------- + */ +int gfx_set_display_bpp(unsigned short bpp) +{ + int retval = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + retval = gu1_set_display_bpp(bpp); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + retval = gu2_set_display_bpp(bpp); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + retval = gu3_set_display_bpp(bpp); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_is_display_mode_supported + * check if given mode supported, + * return the supported mode on success, -1 on fail + *--------------------------------------------------------------------------- + */ +int gfx_is_display_mode_supported(int xres, int yres, int bpp, int hz) +{ + int retval = -1; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + retval = gu1_is_display_mode_supported(xres, yres, bpp, hz); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + retval = gu2_is_display_mode_supported(xres, yres, bpp, hz); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + retval = gu3_is_display_mode_supported(xres, yres, bpp, hz); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_mode + *--------------------------------------------------------------------------- + */ +int gfx_set_display_mode(int xres, int yres, int bpp, int hz) +{ + int retval = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + retval = gu1_set_display_mode(xres, yres, bpp, hz); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + retval = gu2_set_display_mode(xres, yres, bpp, hz); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + retval = gu3_set_display_mode(xres, yres, bpp, hz); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_timings + *--------------------------------------------------------------------------- + */ +int gfx_set_display_timings(unsigned short bpp, unsigned short flags, + unsigned short hactive, unsigned short hblankstart, + unsigned short hsyncstart, unsigned short hsyncend, + unsigned short hblankend, unsigned short htotal, + unsigned short vactive, unsigned short vblankstart, + unsigned short vsyncstart, unsigned short vsyncend, + unsigned short vblankend, unsigned short vtotal, + unsigned long frequency) +{ + int retval = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + retval = gu1_set_display_timings(bpp, flags, + hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal, + vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal, + frequency); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + retval = gu2_set_display_timings(bpp, flags, + hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal, + vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal, + frequency); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + retval = gu3_set_display_timings(bpp, flags, + hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal, + vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal, + frequency); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_pitch + *--------------------------------------------------------------------------- + */ +void gfx_set_display_pitch(unsigned short pitch) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_set_display_pitch(pitch); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_display_pitch(pitch); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_display_pitch(pitch); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_offset + *--------------------------------------------------------------------------- + */ +void gfx_set_display_offset(unsigned long offset) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_set_display_offset(offset); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_display_offset(offset); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_display_offset(offset); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_palette_entry + *--------------------------------------------------------------------------- + */ +int gfx_set_display_palette_entry(unsigned long index, unsigned long palette) +{ + int status = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_set_display_palette_entry(index, palette); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_set_display_palette_entry(index, palette); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_set_display_palette_entry(index, palette); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_palette + *--------------------------------------------------------------------------- + */ +int gfx_set_display_palette(unsigned long *palette) +{ + int status = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_set_display_palette(palette); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_set_display_palette(palette); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_set_display_palette(palette); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_enable + *--------------------------------------------------------------------------- + */ +void gfx_set_cursor_enable(int enable) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_set_cursor_enable(enable); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_cursor_enable(enable); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_cursor_enable(enable); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_colors + *--------------------------------------------------------------------------- + */ +void gfx_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_set_cursor_colors(bkcolor, fgcolor); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_cursor_colors(bkcolor, fgcolor); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_cursor_colors(bkcolor, fgcolor); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_position + *--------------------------------------------------------------------------- + */ +void gfx_set_cursor_position(unsigned long memoffset, + unsigned short xpos, unsigned short ypos, + unsigned short xhotspot, unsigned short yhotspot) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_set_cursor_position(memoffset, xpos, ypos, xhotspot, yhotspot); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_cursor_position(memoffset, xpos, ypos, xhotspot, yhotspot); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_cursor_position(memoffset, xpos, ypos, xhotspot, yhotspot); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_shape32 + *--------------------------------------------------------------------------- + */ +void gfx_set_cursor_shape32(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_set_cursor_shape32(memoffset, andmask, xormask); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_cursor_shape32(memoffset, andmask, xormask); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_cursor_shape32(memoffset, andmask, xormask); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_shape64 + *--------------------------------------------------------------------------- + */ +void gfx_set_cursor_shape64(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +{ +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_cursor_shape64(memoffset, andmask, xormask); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_cursor_shape64(memoffset, andmask, xormask); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_icon_enable + *--------------------------------------------------------------------------- + */ +void gfx_set_icon_enable(int enable) +{ +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_icon_enable(enable); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_icon_colors + *--------------------------------------------------------------------------- + */ +void gfx_set_icon_colors (unsigned long color0, unsigned long color1, unsigned long color2) +{ +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_icon_colors (color0, color1, color2); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_icon_position + *--------------------------------------------------------------------------- + */ +void gfx_set_icon_position(unsigned long memoffset, unsigned short xpos) +{ +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_icon_position(memoffset, xpos); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_icon_shape64 + *--------------------------------------------------------------------------- + */ +void gfx_set_icon_shape64(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask, unsigned int lines) +{ +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_icon_shape64(memoffset, andmask, xormask, lines); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_enable + *--------------------------------------------------------------------------- + */ +int gfx_set_compression_enable(int enable) +{ + int status = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_set_compression_enable(enable); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_set_compression_enable(enable); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_set_compression_enable(enable); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_offset + *--------------------------------------------------------------------------- + */ +int gfx_set_compression_offset(unsigned long offset) +{ + int status = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_set_compression_offset(offset); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_set_compression_offset(offset); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_set_compression_offset(offset); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_pitch + *--------------------------------------------------------------------------- + */ +int gfx_set_compression_pitch(unsigned short pitch) +{ + int status = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_set_compression_pitch(pitch); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_set_compression_pitch(pitch); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_set_compression_pitch(pitch); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_size + *--------------------------------------------------------------------------- + */ +int gfx_set_compression_size(unsigned short size) +{ + int status = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_set_compression_size(size); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_set_compression_size(size); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_set_compression_size(size); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_priority_high + *--------------------------------------------------------------------------- + */ +void gfx_set_display_priority_high(int enable) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_set_display_priority_high(enable); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_format (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_format". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +void gfx_set_display_video_format(unsigned long format) +{ +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_display_video_format(format); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_display_video_format(format); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_color_key (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_color_key". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +void gfx_set_display_video_color_key (unsigned long key, unsigned long mask, int enable) +{ +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_display_video_color_key (key, mask, enable); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_enable (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_enable". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +void gfx_set_display_video_enable(int enable) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_set_display_video_enable(enable); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_display_video_enable(enable); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_display_video_enable(enable); +#endif + return; +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_size (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_size". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +void gfx_set_display_video_size(unsigned short width, unsigned short height) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_set_display_video_size(width, height); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_display_video_size(width, height); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_display_video_size(width, height); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_offset (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_offset". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +void gfx_set_display_video_offset(unsigned long offset) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_set_display_video_offset(offset); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_display_video_offset(offset); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_display_video_offset(offset); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_yuv_offsets (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_yuv_offsets". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +void gfx_set_display_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, + unsigned long voffset) +{ +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_display_video_yuv_offsets(yoffset, uoffset, voffset); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_display_video_yuv_offsets(yoffset, uoffset, voffset); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_yuv_pitch (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_yuv_pitch". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +void gfx_set_display_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch) +{ +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_display_video_yuv_pitch (ypitch, uvpitch); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_set_display_video_yuv_pitch (ypitch, uvpitch); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_downscale (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_vertical_downscale". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +void gfx_set_display_video_downscale (unsigned short srch, unsigned short dsth) +{ +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_display_video_downscale (srch, dsth); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_vertical_downscale_enable (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_vertical_downscale_enable". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +void gfx_set_display_video_vertical_downscale_enable (int enable) +{ +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_set_display_video_vertical_downscale_enable (enable); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_test_timing_active + *--------------------------------------------------------------------------- + */ +int gfx_test_timing_active(void) +{ + int status = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_test_timing_active(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_test_timing_active(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_test_timing_active(); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_test_vertical_active + *--------------------------------------------------------------------------- + */ +int gfx_test_vertical_active(void) +{ + int status = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_test_vertical_active(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_test_vertical_active(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_test_vertical_active(); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_wait_vertical_blank + *--------------------------------------------------------------------------- + */ +int gfx_wait_vertical_blank(void) +{ + int status = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_wait_vertical_blank(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_wait_vertical_blank(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_wait_vertical_blank(); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_delay_milliseconds + *--------------------------------------------------------------------------- + */ +void gfx_delay_milliseconds(unsigned long milliseconds) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_delay_milliseconds(milliseconds); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_delay_milliseconds(milliseconds); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_delay_milliseconds(milliseconds); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_delay_microseconds + *--------------------------------------------------------------------------- + */ +void gfx_delay_microseconds(unsigned long microseconds) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_delay_microseconds(microseconds); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_delay_microseconds(microseconds); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_delay_microseconds(microseconds); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_enable_panning + * + * This routine enables the panning when the Mode is bigger than the panel + * size. + *--------------------------------------------------------------------------- + */ +void gfx_enable_panning(int x, int y) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_enable_panning( x, y); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_enable_panning( x, y); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_enable_panning( x, y); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_is_panel_mode_supported + *--------------------------------------------------------------------------- + */ +int gfx_is_panel_mode_supported(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +{ + int status = -1; + +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_is_panel_mode_supported(panelResX, panelResY, width, height, bpp); +#endif + + return (status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_fixed_timings + *--------------------------------------------------------------------------- + */ +int gfx_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +{ + int status = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_set_fixed_timings( panelResX, panelResY, width, height, bpp); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_set_fixed_timings( panelResX, panelResY, width, height, bpp); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_set_fixed_timings( panelResX, panelResY, width, height, bpp); +#endif + return (status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_panel_present + *--------------------------------------------------------------------------- + */ +int gfx_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +{ + int status = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_set_panel_present( panelResX, panelResY, width, height, bpp); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_set_panel_present( panelResX, panelResY, width, height, bpp); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_set_panel_present( panelResX, panelResY, width, height, bpp); +#endif + return (status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_vtotal + *--------------------------------------------------------------------------- + */ +int gfx_set_vtotal(unsigned short vtotal) +{ + int retval = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + retval = gu1_set_vtotal(vtotal); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + retval = gu2_set_vtotal(vtotal); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + retval = gu3_set_vtotal(vtotal); +#endif + return(retval); +} + +/*-----------------------------------------------------------------------* + * THE FOLLOWING READ ROUTINES ARE ALWAYS INCLUDED: * + * gfx_get_hsync_end, gfx_get_htotal, gfx_get_vsync_end, gfx_get_vtotal * + * are used by the video overlay routines. * + * * + * gfx_get_vline and gfx_vactive are used to prevent an issue for the * + * SC1200. * + * * + * The others are part of the Durango API. * + *-----------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * gfx_mode_frequency_supported + *---------------------------------------------------------------------------- + */ +int gfx_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency) +{ + int freq = 0; + +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + freq = gu1_mode_frequency_supported(xres, yres, bpp, frequency); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + freq = gu2_mode_frequency_supported(xres, yres, bpp, frequency); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + freq = gu3_mode_frequency_supported(xres, yres, bpp, frequency); +#endif + return(freq); +} + +/*---------------------------------------------------------------------------- + * gfx_refreshrate_from_frequency + *---------------------------------------------------------------------------- + */ +int gfx_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_get_refreshrate_from_frequency(xres, yres, bpp, hz, frequency); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_get_refreshrate_from_frequency(xres, yres, bpp, hz, frequency); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_get_refreshrate_from_frequency(xres, yres, bpp, hz, frequency); +#endif + + return(1); +} + +/*---------------------------------------------------------------------------- + * gfx_refreshrate_from_mode + *---------------------------------------------------------------------------- + */ +int gfx_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_get_refreshrate_from_mode(xres, yres, bpp, hz, frequency); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_get_refreshrate_from_mode(xres, yres, bpp, hz, frequency); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_get_refreshrate_from_mode(xres, yres, bpp, hz, frequency); +#endif + + return(1); +} + +/*---------------------------------------------------------------------------- + * gfx_get_frequency_from_refreshrate + *---------------------------------------------------------------------------- + */ +int gfx_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency) +{ + int retval = -1; + +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + retval = gu1_get_frequency_from_refreshrate(xres, yres, bpp, hz, frequency); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + retval = gu2_get_frequency_from_refreshrate(xres, yres, bpp, hz, frequency); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + retval = gu3_get_frequency_from_refreshrate(xres, yres, bpp, hz, frequency); +#endif + + return retval; +} + +/*--------------------------------------------------------------------------- + * gfx_get_max_supported_pixel_clock + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_max_supported_pixel_clock (void) +{ + unsigned long status = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_get_max_supported_pixel_clock(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_get_max_supported_pixel_clock(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_get_max_supported_pixel_clock(); +#endif + return (status); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_pitch + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_display_pitch(void) +{ + unsigned short pitch = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + pitch = gu1_get_display_pitch(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + pitch = gu2_get_display_pitch(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + pitch = gu3_get_display_pitch(); +#endif + return(pitch); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_mode_count + * return # of modes supported. + *--------------------------------------------------------------------------- + */ +int gfx_get_display_mode_count(void) +{ + int retval = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + retval = gu1_get_display_mode_count(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + retval = gu2_get_display_mode_count(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + retval = gu3_get_display_mode_count(); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_get_frame_buffer_line_size + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_frame_buffer_line_size(void) +{ + unsigned long retval = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + retval = gu1_get_frame_buffer_line_size(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + retval = gu2_get_frame_buffer_line_size(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + retval = gu3_get_frame_buffer_line_size(); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_mode + * get the curent mode set, + * return the supported mode on success, -1 on fail + *--------------------------------------------------------------------------- + */ +int gfx_get_display_mode(int *xres, int *yres, int *bpp, int *hz) +{ + int retval = -1; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + retval = gu1_get_display_mode(xres, yres, bpp, hz); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + retval = gu2_get_display_mode(xres, yres, bpp, hz); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + retval = gu3_get_display_mode(xres, yres, bpp, hz); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_details + * given the mode get's the resoultion details, width, height, freq + *--------------------------------------------------------------------------- + */ +int gfx_get_display_details(unsigned int mode, int *xres, int *yres, int *hz) +{ + int retval = -1; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + retval = gu1_get_display_details(mode, xres, yres, hz); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + retval = gu2_get_display_details(mode, xres, yres, hz); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + retval = gu3_get_display_details(mode, xres, yres, hz); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hactive + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_hactive(void) +{ + unsigned short hactive = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + hactive = gu1_get_hactive(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + hactive = gu2_get_hactive(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + hactive = gu3_get_hactive(); +#endif + return(hactive); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hsync_start + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_hsync_start(void) +{ + unsigned short hsync_start = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + hsync_start = gu1_get_hsync_start(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + hsync_start = gu2_get_hsync_start(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + hsync_start = gu3_get_hsync_start(); +#endif + return(hsync_start); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hsync_end + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_hsync_end(void) +{ + unsigned short hsync_end = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + hsync_end = gu1_get_hsync_end(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + hsync_end = gu2_get_hsync_end(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + hsync_end = gu3_get_hsync_end(); +#endif + return(hsync_end); +} + +/*--------------------------------------------------------------------------- + * gfx_get_htotal + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_htotal(void) +{ + unsigned short htotal = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + htotal = gu1_get_htotal(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + htotal = gu2_get_htotal(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + htotal = gu3_get_htotal(); +#endif + return(htotal); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vactive + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_vactive(void) +{ + unsigned short vactive = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + vactive = gu1_get_vactive(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + vactive = gu2_get_vactive(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + vactive = gu3_get_vactive(); +#endif + return(vactive); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vsync_end + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_vsync_end(void) +{ + unsigned short vsync_end = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + vsync_end = gu1_get_vsync_end(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + vsync_end = gu2_get_vsync_end(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + vsync_end = gu3_get_vsync_end(); +#endif + return(vsync_end); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vtotal + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_vtotal(void) +{ + unsigned short vtotal = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + vtotal = gu1_get_vtotal(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + vtotal = gu2_get_vtotal(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + vtotal = gu3_get_vtotal(); +#endif + return(vtotal); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_bpp + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_display_bpp(void) +{ + unsigned short bpp = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + bpp = gu1_get_display_bpp(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + bpp = gu2_get_display_bpp(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + bpp = gu3_get_display_bpp(); +#endif + return(bpp); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vline + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_vline(void) +{ + unsigned short vline = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + vline = gu1_get_vline(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + vline = gu2_get_vline(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + vline = gu3_get_vline(); +#endif + return(vline); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_offset + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_display_offset(void) +{ + unsigned long offset = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + offset = gu1_get_display_offset(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + offset = gu2_get_display_offset(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + offset = gu3_get_display_offset(); +#endif + return(offset); +} + +/*--------------------------------------------------------------------------- + * gfx_get_cursor_offset + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_cursor_offset(void) +{ + unsigned long base = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + base = gu1_get_cursor_offset(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + base = gu2_get_cursor_offset(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + base = gu3_get_cursor_offset(); +#endif + return(base); +} + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +#if GFX_READ_ROUTINES + +/*--------------------------------------------------------------------------- + * gfx_get_hblank_start + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_hblank_start(void) +{ + unsigned short hblank_start = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + hblank_start = gu1_get_hblank_start(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + hblank_start = gu2_get_hblank_start(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + hblank_start = gu3_get_hblank_start(); +#endif + return(hblank_start); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hblank_end + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_hblank_end(void) +{ + unsigned short hblank_end = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + hblank_end = gu1_get_hblank_end(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + hblank_end = gu2_get_hblank_end(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + hblank_end = gu3_get_hblank_end(); +#endif + return(hblank_end); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vblank_start + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_vblank_start(void) +{ + unsigned short vblank_start = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + vblank_start = gu1_get_vblank_start(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + vblank_start = gu2_get_vblank_start(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + vblank_start = gu3_get_vblank_start(); +#endif + return(vblank_start); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vsync_start + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_vsync_start(void) +{ + unsigned short vsync_start = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + vsync_start = gu1_get_vsync_start(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + vsync_start = gu2_get_vsync_start(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + vsync_start = gu3_get_vsync_start(); +#endif + return(vsync_start); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vblank_end + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_vblank_end(void) +{ + unsigned short vblank_end = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + vblank_end = gu1_get_vblank_end(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + vblank_end = gu2_get_vblank_end(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + vblank_end = gu3_get_vblank_end(); +#endif + return(vblank_end); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_palette_entry + *--------------------------------------------------------------------------- + */ +int gfx_get_display_palette_entry(unsigned long index, unsigned long *palette) +{ + int status = 0; + +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + status = gu1_get_display_palette_entry(index, palette); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + status = gu2_get_display_palette_entry(index, palette); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + status = gu3_get_display_palette_entry(index, palette); +#endif + + return status; +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_palette + *--------------------------------------------------------------------------- + */ +void gfx_get_display_palette(unsigned long *palette) +{ +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + gu1_get_display_palette(palette); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_get_display_palette(palette); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_get_display_palette(palette); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_get_cursor_enable + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_cursor_enable(void) +{ + unsigned long enable = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + enable = gu1_get_cursor_enable(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + enable = gu2_get_cursor_enable(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + enable = gu3_get_cursor_enable(); +#endif + return(enable); +} + +/*--------------------------------------------------------------------------- + * gfx_get_cursor_position + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_cursor_position(void) +{ + unsigned long position = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + position = gu1_get_cursor_position(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + position = gu2_get_cursor_position(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + position = gu3_get_cursor_position(); +#endif + return(position); +} + +/*--------------------------------------------------------------------------- + * gfx_get_cursor_clip + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_cursor_clip(void) +{ + unsigned long offset = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + offset = gu1_get_cursor_clip(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + offset = gu2_get_cursor_clip(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + offset = gu3_get_cursor_clip(); +#endif + return(offset); +} + +/*--------------------------------------------------------------------------- + * gfx_get_cursor_color + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_cursor_color(int index) +{ + unsigned long color = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + color = gu1_get_cursor_color(index); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + color = gu2_get_cursor_color(index); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + color = gu3_get_cursor_color(index); +#endif + return(color); +} + +/*--------------------------------------------------------------------------- + * gfx_get_icon_enable + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_icon_enable(void) +{ + unsigned long enable = 0; +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + enable = gu2_get_icon_enable(); +#endif + return(enable); +} + +/*--------------------------------------------------------------------------- + * gfx_get_icon_offset + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_icon_offset(void) +{ + unsigned long base = 0; + +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + base = gu2_get_icon_offset(); +#endif + + return(base); +} + +/*--------------------------------------------------------------------------- + * gfx_get_icon_position + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_icon_position(void) +{ + unsigned long position = 0; + +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + position = gu2_get_icon_position(); +#endif + + return(position); +} + +/*--------------------------------------------------------------------------- + * gfx_get_icon_color + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_icon_color(int index) +{ + unsigned long color = 0; + +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + color = gu2_get_icon_color(index); +#endif + + return(color); +} + +/*--------------------------------------------------------------------------- + * gfx_get_compression_enable + *--------------------------------------------------------------------------- + */ +int gfx_get_compression_enable(void) +{ + int enable = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + enable = gu1_get_compression_enable(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + enable = gu2_get_compression_enable(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + enable = gu3_get_compression_enable(); +#endif + return(enable); +} + +/*--------------------------------------------------------------------------- + * gfx_get_compression_offset + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_compression_offset(void) +{ + unsigned long offset = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + offset = gu1_get_compression_offset(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + offset = gu2_get_compression_offset(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + offset = gu3_get_compression_offset(); +#endif + return(offset); +} + +/*--------------------------------------------------------------------------- + * gfx_get_compression_pitch + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_compression_pitch(void) +{ + unsigned short pitch = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + pitch = gu1_get_compression_pitch(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + pitch = gu2_get_compression_pitch(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + pitch = gu3_get_compression_pitch(); +#endif + return(pitch); +} + +/*--------------------------------------------------------------------------- + * gfx_get_compression_size + *--------------------------------------------------------------------------- + */ +unsigned short gfx_get_compression_size(void) +{ + unsigned short size = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + size = gu1_get_compression_size(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + size = gu2_get_compression_size(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + size = gu3_get_compression_size(); +#endif + return(size); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_priority_high + *--------------------------------------------------------------------------- + */ +int gfx_get_display_priority_high(void) +{ + int high = GFX_STATUS_UNSUPPORTED; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + high = gu1_get_display_priority_high(); +#endif + return(high); +} + +/*--------------------------------------------------------------------------- + * gfx_get_valid_bit + *--------------------------------------------------------------------------- + */ +int gfx_get_valid_bit(int line) +{ + int valid = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + valid = gu1_get_valid_bit(line); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + valid = gu2_get_valid_bit(line); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + valid = gu3_get_valid_bit(line); +#endif + return(valid); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_color_key + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_display_video_color_key(void) +{ + unsigned long value = 0; +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + value = gu3_get_display_video_color_key(); +#endif + return(value); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_offset + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_display_video_offset(void) +{ + unsigned long offset = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + offset = gu1_get_display_video_offset(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + offset = gu2_get_display_video_offset(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + offset = gu3_get_display_video_offset(); +#endif + return(offset); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_yuv_offsets + *--------------------------------------------------------------------------- + */ +void gfx_get_display_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset) +{ +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_get_display_video_yuv_offsets(yoffset, uoffset, voffset); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_get_display_video_yuv_offsets(yoffset, uoffset, voffset); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_yuv_offsets + *--------------------------------------------------------------------------- + */ +void gfx_get_display_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch) +{ +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + gu2_get_display_video_yuv_pitch(ypitch, uvpitch); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + gu3_get_display_video_yuv_pitch(ypitch, uvpitch); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_downscale_delta + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_display_video_downscale_delta(void) +{ + unsigned long ret_value = 0; + +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + ret_value = gu2_get_display_video_downscale_delta(); +#endif + + return ret_value; +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_downscale_delta + *--------------------------------------------------------------------------- + */ +int gfx_get_display_video_downscale_enable(void) +{ + int ret_value = 0; + +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + ret_value = gu2_get_display_video_downscale_enable(); +#endif + + return ret_value; +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_size + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_display_video_size(void) +{ + unsigned long size = 0; +#if GFX_DISPLAY_GU1 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU1) + size = gu1_get_display_video_size(); +#endif +#if GFX_DISPLAY_GU2 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU2) + size = gu2_get_display_video_size(); +#endif +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + size = gu3_get_display_video_size(); +#endif + return(size); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_color_key_mask + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_display_video_color_key_mask(void) +{ + unsigned long mask = 0; +#if GFX_DISPLAY_GU3 + if (gfx_display_type & GFX_DISPLAY_TYPE_GU3) + mask = gu3_get_display_video_color_key_mask(); +#endif + return(mask); +} + +#endif /* GFX_READ_ROUTINES */ + +#endif /* GFX_DISPLAY_DYNAMIC */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/tv_1200.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/tv_1200.c 2005-12-14 11:29:34.000000000 -0700 @@ -0,0 +1,871 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to control the SC1200 TVOUT and TV encoder. + * */ + + + +/*----------------------------------------------------------------------------- + * gfx_set_tv_format + * + * This routine sets the TV encoder registers to the specified format + * and resolution. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_set_tv_format(TVStandardType format, GfxOnTVType resolution) +#else +int gfx_set_tv_format(TVStandardType format, GfxOnTVType resolution) +#endif +{ + unsigned long ctrl2, mode; + + /* Save TV output mode */ + ctrl2 = READ_VID32(SC1200_TVENC_TIM_CTRL_2) & (SC1200_TVENC_OUTPUT_YCBCR | SC1200_TVENC_CFS_MASK); + /* Save flicker filter setting */ + mode = READ_VID32(SC1200_TVOUT_HORZ_SCALING) & SC1200_TVOUT_FLICKER_FILTER_MASK; + + switch (format) { + case TV_STANDARD_NTSC : + /* Horizontal Sync Start is 848 */ + /* Horizontal Sync End is 856 */ + WRITE_VID32(SC1200_TVOUT_HORZ_SYNC, 0x03580350); + /* Vertical Sync Start is 0 */ + /* Vertical Sync End is 1 */ + /* Vertical Display Start Skew is 1 */ + /* Vertical Display End Skew is 1 */ + WRITE_VID32(SC1200_TVOUT_VERT_SYNC, 0x05001000); + /* Disable vertical down scaling, take all lines */ + if (gfx_chip_revision <= SC1200_REV_B3) + WRITE_VID32(SC1200_TVOUT_VERT_DOWNSCALE, 0xffffffff); + /* Enable video timing */ + /* Reset sub carrier every two frames */ + /* Disable BLANK */ + /* Enable color burst */ + /* Add the IRE offset */ + /* NTSC color encoding */ + /* Video generator timing is 525 lines / 60Hz */ + /* Horizontal and Vertical counters are initialized to HPHASE & VPHASE */ + /* VPHASE is 2, HPHASE is 0x50 */ + WRITE_VID32(SC1200_TVENC_TIM_CTRL_1, 0xa2a01050); + /* Increase horizontal blanking interval */ + /* Low Water Mark for Y is 0x1F */ + /* Low Water Mark for Cb is 0xF */ + /* HUE is 0 */ + /* SCPHASE is 0xF9 */ + WRITE_VID32(SC1200_TVENC_TIM_CTRL_2, 0x9ff000f9 | ctrl2); + /* Subcarrier Frequency is 3.579545 MHz */ + WRITE_VID32(SC1200_TVENC_SUB_FREQ, 0x21f07c1f); + /* VSTART is 18, HSTART is 113 */ + WRITE_VID32(SC1200_TVENC_DISP_POS, 0x00120071); + /* Display size: HEIGHT is 239, WIDTH is 719 */ + WRITE_VID32(SC1200_TVENC_DISP_SIZE, 0x00ef02cf); + switch (resolution) { + case GFX_ON_TV_SQUARE_PIXELS : + if (gfx_chip_revision <= SC1200_REV_B3) { + /* Horizontal Display start is 116 */ + /* Total number of pixels per line is 857 */ + WRITE_VID32(SC1200_TVOUT_HORZ_TIM, 0x00740359); + /* HSYNC generated in the TV Encoder module */ + /* Interval between resets of TV Encoder is once every odd field */ + /* Enable Horizontal interpolation */ + /* Enable Horizontal up scaling 9/8 */ + /* Disable Horizontal downscale */ + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, 0x10020700 | mode); + /* Horizontal display end is 919, i.e. 720 active pixels */ + /* Total number of display lines per field is 240 */ + WRITE_VID32(SC1200_TVOUT_LINE_END, 0x039700f0); + } else { /* Use new scaler available in Rev. C */ + /* Horizontal Display start is 111 */ + /* Total number of pixels per line is 857 */ + WRITE_VID32(SC1200_TVOUT_HORZ_TIM, 0x006f0359); + /* HSYNC generated in the TV Encoder module */ + /* Interval between resets of TV Encoder is once every odd field */ + /* Enable Horizontal interpolation */ + /* Disable Horizontal up scaling 9/8 */ + /* Disable Horizontal downscale */ + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, 0x10020500 | mode); + /* Set Horizontal upscaling to 64/58 (~ 11/10) */ + WRITE_VID32(SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE, 0x3A000000); + /* Horizontal display end is 900, i.e. 706 active pixels */ + /* Total number of display lines per field is 240 */ + WRITE_VID32(SC1200_TVOUT_LINE_END, 0x038400f0); + } + break; + case GFX_ON_TV_NO_SCALING : + /* Horizontal Display start is 116 */ + /* Total number of pixels per line is 857 */ + WRITE_VID32(SC1200_TVOUT_HORZ_TIM, 0x00740359); + /* HSYNC generated in the TV Encoder module */ + /* Interval between resets of TV Encoder is once every odd field */ + /* Enable Horizontal interpolation */ + /* Disable Horizontal up scaling 9/8 */ + /* Disable Horizontal downscale */ + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, 0x10020500 | mode); + /* Disable Horizontal scaling (set to 64/64) */ + if (gfx_chip_revision >= SC1200_REV_C1) + WRITE_VID32(SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE, 0x40000000); + /* Horizontal display end is 919, i.e. 720 active pixels */ + /* Total number of display lines per field is 240 */ + WRITE_VID32(SC1200_TVOUT_LINE_END, 0x039700f0); + break; + default : + return(GFX_STATUS_BAD_PARAMETER); + } + break; + case TV_STANDARD_PAL : + /* Horizontal Sync Start is 854 */ + /* Horizontal Sync End is 862 */ + WRITE_VID32(SC1200_TVOUT_HORZ_SYNC, 0x035e0356); + /* Vertical Sync Start is 0 */ + /* Vertical Sync End is 1 */ + /* Vertical Display Start Skew is 1 */ + /* Vertical Display End Skew is 1 */ + WRITE_VID32(SC1200_TVOUT_VERT_SYNC, 0x05001000); + /* Disable vertical down scaling, take all lines */ + if (gfx_chip_revision <= SC1200_REV_B3) + WRITE_VID32(SC1200_TVOUT_VERT_DOWNSCALE, 0xffffffff); + /* Enable video timing */ + /* Never reset sub carrier (should be every 4 frames but doesn't work with genlock) */ + /* Disable BLANK */ + /* Enable color burst */ + /* Do not add the IRE offset */ + /* NTSC color encoding */ + /* Video generator timing is 625 lines / 50Hz */ + /* Horizontal and Vertical counters are initialized to HPHASE & VPHASE */ + /* VPHASE is 2, HPHASE is 50 */ + WRITE_VID32(SC1200_TVENC_TIM_CTRL_1, 0xB1201050); + /* Increase horizontal blanking interval */ + /* Low Water Mark for Y is 0x1F */ + /* Low Water Mark for Cb is 0xF */ + /* HUE is 0 */ + /* SCPHASE is 0xD9 */ + WRITE_VID32(SC1200_TVENC_TIM_CTRL_2, 0x9ff000d9 | ctrl2); + /* Subcarrier Frequency is 4.43361875 MHz */ + WRITE_VID32(SC1200_TVENC_SUB_FREQ, 0x2a098acb); + /* VSTART is 22, HSTART is 123 */ + WRITE_VID32(SC1200_TVENC_DISP_POS, 0x0016007b); + /* Display size: HEIGHT is 287, WIDTH is 719 */ + WRITE_VID32(SC1200_TVENC_DISP_SIZE, 0x011f02cf); + switch (resolution) { + case GFX_ON_TV_NO_SCALING : + /* Horizontal Display start is 124 */ + /* Total number of pixels per line is 863 */ + WRITE_VID32(SC1200_TVOUT_HORZ_TIM, 0x007c035f); + /* HSYNC generated in the TV Encoder module */ + /* Interval between resets of TV Encoder is once every odd field */ + /* Enable Horizontal interpolation */ + /* Disable Horizontal up scaling 9/8 */ + /* Disable Horizontal downscale */ + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, 0x10020500 | mode); + /* Disable Horizontal scaling (set to 64/64) */ + if (gfx_chip_revision >= SC1200_REV_C1) + WRITE_VID32(SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE, 0x40000000); + /* Horizontal display end is 924, i.e. 720 active pixels */ + /* Total number of display lines per field is 288 */ + WRITE_VID32(SC1200_TVOUT_LINE_END, 0x039c0120); + break; + case GFX_ON_TV_SQUARE_PIXELS : + /* Horizontal Display start is 122 */ + /* Total number of pixels per line is 863 */ + WRITE_VID32(SC1200_TVOUT_HORZ_TIM, 0x007a035f); + if (gfx_chip_revision <= SC1200_REV_B3) { + /* HSYNC generated in the TV Encoder module */ + /* Interval between resets of TV Encoder is once every odd field */ + /* Enable Horizontal interpolation */ + /* Disable Horizontal up scaling 9/8 */ + /* Horizontal downscale m/(m+1), m = 11, (i.e. 11/12 - closest possible to 54/59) */ + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, 0x1002040b | mode); + /* Horizontal display end is 906, i.e. 704 active pixels */ + /* Total number of display lines per field is 288 */ + WRITE_VID32(SC1200_TVOUT_LINE_END, 0x038a0120); + } else { + /* HSYNC generated in the TV Encoder module */ + /* Interval between resets of TV Encoder is once every odd field */ + /* Enable Horizontal interpolation */ + /* Disable Horizontal up scaling 9/8 */ + /* Disable Horizontal downscale */ + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, 0x10020500 | mode); + /* Set Horizontal down scaling to 64/70 (closest possible to 54/59) */ + WRITE_VID32(SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE, 0x46000000); + /* Horizontal display end is 904, i.e. 702 active pixels */ + /* Total number of display lines per field is 288 */ + WRITE_VID32(SC1200_TVOUT_LINE_END, 0x03880120); + } + break; + default : + return(GFX_STATUS_BAD_PARAMETER); + } + break; + default : + return(GFX_STATUS_BAD_PARAMETER); + } + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_output + * + * This routine sets the TV encoder registers to the specified output type. + * Supported output types are : S-VIDEO, Composite, YUV and SCART. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_set_tv_output(int output) +#else +int gfx_set_tv_output(int output) +#endif +{ + unsigned long ctrl2, ctrl3; + + ctrl2 = READ_VID32(SC1200_TVENC_TIM_CTRL_2); + ctrl3 = READ_VID32(SC1200_TVENC_TIM_CTRL_3); + ctrl2 &= ~(SC1200_TVENC_OUTPUT_YCBCR | SC1200_TVENC_CFS_MASK); + ctrl3 &= ~(SC1200_TVENC_CM | SC1200_TVENC_SYNCMODE_MASK | SC1200_TVENC_CS); + switch (output) { + case TV_OUTPUT_COMPOSITE : + /* Analog outputs provide Y, C and CVBS */ + /* Chrominance Lowpass filter is 1.3MHz (for composite video output) */ + WRITE_VID32(SC1200_TVENC_TIM_CTRL_2, ctrl2 | SC1200_TVENC_CFS_CVBS); + WRITE_VID32(SC1200_TVENC_TIM_CTRL_3, ctrl3); + break; + case TV_OUTPUT_S_VIDEO : + /* Analog outputs provide Y, C and CVBS */ + /* Chrominance Lowpass filter is 1.8MHz (for S-video output) */ + WRITE_VID32(SC1200_TVENC_TIM_CTRL_2, ctrl2 | SC1200_TVENC_CFS_SVIDEO); + WRITE_VID32(SC1200_TVENC_TIM_CTRL_3, ctrl3); + break; + case TV_OUTPUT_YUV : + /* Analog outputs provide Y, Cb and Cr */ + /* A 7.5 IRE setup is applied to the output */ + WRITE_VID32(SC1200_TVENC_TIM_CTRL_2, ctrl2 | SC1200_TVENC_OUTPUT_YCBCR | SC1200_TVENC_CFS_BYPASS); + WRITE_VID32(SC1200_TVENC_TIM_CTRL_3, ctrl3 | SC1200_TVENC_CM | SC1200_TVENC_CS); + break; + case TV_OUTPUT_SCART : + /* Analog outputs provide SCART (RGB and CVBS) */ + /* Sync is added to green signal */ + WRITE_VID32(SC1200_TVENC_TIM_CTRL_2, ctrl2 | SC1200_TVENC_CFS_CVBS); + WRITE_VID32(SC1200_TVENC_TIM_CTRL_3, ctrl3 | SC1200_TVENC_CM | SC1200_TVENC_SYNC_ON_GREEN); + break; + default : + return(GFX_STATUS_BAD_PARAMETER); + } + + /* Adjusts the internal voltage reference */ + ctrl2 = READ_VID32(SC1200_TVENC_DAC_CONTROL); + ctrl2 &= ~SC1200_TVENC_TRIM_MASK; + + /* Bypass for issue #926 : Inadequate chroma level of S-Video output */ + if ((gfx_chip_revision == SC1200_REV_B3) && (output == TV_OUTPUT_S_VIDEO)) + ctrl2 |= 0x7; + else + ctrl2 |= 0x5; + + WRITE_VID32(SC1200_TVENC_DAC_CONTROL, ctrl2); + + /* Disable 4:2:2 to 4:4:4 converter interpolation */ + WRITE_VID32(SC1200_TVOUT_DEBUG, SC1200_TVOUT_CONVERTER_INTERPOLATION); + + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_enable + * + * This routine enables or disables the TV output. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_set_tv_enable(int enable) +#else +int gfx_set_tv_enable(int enable) +#endif +{ + unsigned long value_tim, value_dac; + value_tim = READ_VID32(SC1200_TVENC_TIM_CTRL_1); + value_dac = READ_VID32(SC1200_TVENC_DAC_CONTROL); + + if (enable) { + value_tim |= SC1200_TVENC_VIDEO_TIMING_ENABLE; + value_dac &= ~SC1200_TVENC_POWER_DOWN; + /* ENABLE GRAPHICS DISPLAY LOGIC IN VIDEO PROCESSOR */ + gfx_set_screen_enable(1); + } else { + value_tim &= ~SC1200_TVENC_VIDEO_TIMING_ENABLE; + value_dac |= SC1200_TVENC_POWER_DOWN; + /* Do not disable the graphics display logic because it might be needed for CRT */ + } + + WRITE_VID32(SC1200_TVENC_TIM_CTRL_1, value_tim); + WRITE_VID32(SC1200_TVENC_DAC_CONTROL, value_dac); + + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_flicker_filter + * + * This routine configures the TV out flicker filter. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_set_tv_flicker_filter(int ff) +#else +int gfx_set_tv_flicker_filter(int ff) +#endif +{ + unsigned long mode; + mode = READ_VID32(SC1200_TVOUT_HORZ_SCALING); + mode &= ~SC1200_TVOUT_FLICKER_FILTER_MASK; + switch (ff) + { + case TV_FLICKER_FILTER_NONE: + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, mode | SC1200_TVOUT_FLICKER_FILTER_DISABLED); + break; + case TV_FLICKER_FILTER_NORMAL: + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, mode | SC1200_TVOUT_FLICKER_FILTER_FOURTH_HALF_FOURTH); + break; + case TV_FLICKER_FILTER_INTERLACED: + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, mode | SC1200_TVOUT_FLICKER_FILTER_HALF_ONE_HALF); + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_sub_carrier_reset + * + * This routine configures the TV encoder sub carrier reset interval. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_set_tv_sub_carrier_reset(int screset) +#else +int gfx_set_tv_sub_carrier_reset(int screset) +#endif +{ + unsigned long mode; + mode = READ_VID32(SC1200_TVENC_TIM_CTRL_1); + mode &= ~SC1200_TVENC_SUB_CARRIER_RESET_MASK; + switch (screset) + { + case TV_SUB_CARRIER_RESET_NEVER: + WRITE_VID32(SC1200_TVENC_TIM_CTRL_1, mode | SC1200_TVENC_SUB_CARRIER_RESET_NEVER); + break; + case TV_SUB_CARRIER_RESET_EVERY_TWO_LINES: + WRITE_VID32(SC1200_TVENC_TIM_CTRL_1, mode | SC1200_TVENC_SUB_CARRIER_RESET_EVERY_TWO_LINES); + break; + case TV_SUB_CARRIER_RESET_EVERY_TWO_FRAMES: + WRITE_VID32(SC1200_TVENC_TIM_CTRL_1, mode | SC1200_TVENC_SUB_CARRIER_RESET_EVERY_TWO_FRAMES); + break; + case TV_SUB_CARRIER_RESET_EVERY_FOUR_FRAMES: + WRITE_VID32(SC1200_TVENC_TIM_CTRL_1, mode | SC1200_TVENC_SUB_CARRIER_RESET_EVERY_FOUR_FRAMES); + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_vphase + * + * This routine sets the tv encoder VPHASE value. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_set_tv_vphase(int vphase) +#else +int gfx_set_tv_vphase(int vphase) +#endif +{ + unsigned long mode = READ_VID32(SC1200_TVENC_TIM_CTRL_1); + mode &= ~SC1200_TVENC_VPHASE_MASK; + mode |= (vphase << SC1200_TVENC_VPHASE_POS) & SC1200_TVENC_VPHASE_MASK; + WRITE_VID32(SC1200_TVENC_TIM_CTRL_1, mode); + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_YC_delay + * + * This routine configures the TV out Y/C delay. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_set_tv_YC_delay(int delay) +#else +int gfx_set_tv_YC_delay(int delay) +#endif +{ + unsigned long mode; + + /* This feature is implemented in Rev C1 */ + if (gfx_chip_revision < SC1200_REV_C1) return(GFX_STATUS_OK); + + mode = READ_VID32(SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE); + mode &= ~SC1200_TVOUT_YC_DELAY_MASK; + switch (delay) + { + case TV_YC_DELAY_NONE: + WRITE_VID32(SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE, mode | SC1200_TVOUT_YC_DELAY_NONE); + break; + case TV_Y_DELAY_ONE_PIXEL: + WRITE_VID32(SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE, mode | SC1200_TVOUT_Y_DELAY_ONE_PIXEL); + break; + case TV_C_DELAY_ONE_PIXEL: + WRITE_VID32(SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE, mode | SC1200_TVOUT_C_DELAY_ONE_PIXEL); + break; + case TV_C_DELAY_TWO_PIXELS: + WRITE_VID32(SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE, mode | SC1200_TVOUT_C_DELAY_TWO_PIXELS); + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tvenc_reset_interval + * + * This routine sets the interval between external resets of the TV encoder + * timing generator by the TV out. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_set_tvenc_reset_interval(int interval) +#else +int gfx_set_tvenc_reset_interval(int interval) +#endif +{ + unsigned long value; + value = READ_VID32(SC1200_TVOUT_HORZ_SCALING); + value &= ~SC1200_TVENC_EXTERNAL_RESET_INTERVAL_MASK; + switch (interval) + { + case TVENC_RESET_EVERY_ODD_FIELD: + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, value | SC1200_TVENC_EXTERNAL_RESET_EVERY_ODD_FIELD); + break; + case TVENC_RESET_EVERY_EVEN_FIELD: + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, value | SC1200_TVENC_EXTERNAL_RESET_EVERY_EVEN_FIELD); + break; + case TVENC_RESET_NEXT_ODD_FIELD: + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, value | SC1200_TVENC_EXTERNAL_RESET_NEXT_ODD_FIELD); + break; + case TVENC_RESET_NEXT_EVEN_FIELD: + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, value | SC1200_TVENC_EXTERNAL_RESET_NEXT_EVEN_FIELD); + break; + case TVENC_RESET_EVERY_FIELD: + WRITE_VID32(SC1200_TVOUT_HORZ_SCALING, value | SC1200_TVENC_EXTERNAL_RESET_EVERY_FIELD); + break; + case TVENC_RESET_EVERY_X_ODD_FIELDS: + case TVENC_RESET_EVERY_X_EVEN_FIELDS: + return GFX_STATUS_UNSUPPORTED; + default: + return GFX_STATUS_BAD_PARAMETER; + } + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_cc_enable + * + * This routine enables or disables the use of the hardware CC registers + * in the TV encoder. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_set_tv_cc_enable(int enable) +#else +int gfx_set_tv_cc_enable(int enable) +#endif +{ + unsigned long value; + value = READ_VID32(SC1200_TVENC_CC_CONTROL); + value &= ~(0x0005F); + if (enable) value |= 0x51; + WRITE_VID32(SC1200_TVENC_CC_CONTROL, value); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_tv_display + * + * This routine sets the timings in the display controller to support a + * TV resolution. + *--------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_set_tv_display(int width, int height) +#else +int gfx_set_tv_display(int width, int height) +#endif +{ + DISPLAYMODE *pMode; + unsigned int i; + + for (i = 0; i < NUM_TV_MODES; i++) + { + pMode = &TVTimings[i]; + if ((unsigned)width == pMode->hactive && (unsigned)height == pMode->vactive) + break; + } + + if (i == NUM_TV_MODES) + return 0; + + gfx_set_display_timings (gfx_get_display_bpp(), (unsigned short)pMode->flags, pMode->hactive, pMode->hblankstart, + pMode->hsyncstart, pMode->hsyncend, pMode->hblankend, + pMode->htotal, pMode->vactive, pMode->vblankstart, + pMode->vsyncstart, pMode->vsyncend, pMode->vblankend, + pMode->vtotal, pMode->frequency); + + return 1; +} + +/*----------------------------------------------------------------------------- + * cc_add_parity_bit + * + * This routine adds the (odd) parity bit to the data character. + *----------------------------------------------------------------------------- + */ +unsigned char cc_add_parity_bit(unsigned char data) +{ + int i, num = 0; + unsigned char d = data; + + for (i = 0; i < 7; i++) + { + if (d & 0x1) + num++; + d >>= 1; + } + if (num & 0x1) + return (data & ~0x80); + else + return (data | 0x80); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_cc_data + * + * This routine writes the two specified characters to the CC data register + * of the TV encoder. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_set_tv_cc_data(unsigned char data1, unsigned char data2) +#else +int gfx_set_tv_cc_data(unsigned char data1, unsigned char data2) +#endif +{ + unsigned long value; + value = cc_add_parity_bit(data1) | (cc_add_parity_bit(data2) << 8); + WRITE_VID32(SC1200_TVENC_CC_DATA, value); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_test_tvout_odd_field + * + * This routine returns 1 if the current TVout field is odd. Otherwise returns 0. + *--------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_test_tvout_odd_field(void) +#else +int gfx_test_tvout_odd_field(void) +#endif +{ + unsigned long debug = READ_VID32(SC1200_TVOUT_DEBUG); + WRITE_VID32(SC1200_TVOUT_DEBUG, debug | SC1200_TVOUT_FIELD_STATUS_TV); + if (READ_VID32(SC1200_TVOUT_DEBUG) & SC1200_TVOUT_FIELD_STATUS_EVEN) + return(0); + else return(1); +} + +/*--------------------------------------------------------------------------- + * gfx_test_tvenc_odd_field + * + * This routine returns 1 if the current TV encoder field is odd. Otherwise returns 0. + *--------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_test_tvenc_odd_field(void) +#else +int gfx_test_tvenc_odd_field(void) +#endif +{ + unsigned long debug = READ_VID32(SC1200_TVOUT_DEBUG); + WRITE_VID32(SC1200_TVOUT_DEBUG, debug & ~SC1200_TVOUT_FIELD_STATUS_TV); + if (READ_VID32(SC1200_TVOUT_DEBUG) & SC1200_TVOUT_FIELD_STATUS_EVEN) + return(0); + else return(1); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_field_status_invert + * + * This routines determines whether the tvout/tvencoder field status bit is + * inverted (enable = 1) or not (enable = 0). + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_set_tv_field_status_invert(int enable) +#else +int gfx_set_tv_field_status_invert(int enable) +#endif +{ + unsigned long value; + value = READ_VID32(SC1200_TVOUT_DEBUG); + + if (enable) { + value |= SC1200_TVOUT_FIELD_STATUS_INVERT; + } else { + value &= ~(SC1200_TVOUT_FIELD_STATUS_INVERT); + } + + WRITE_VID32(SC1200_TVOUT_DEBUG, value); + + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_get_tv_vphase + * + * This routine returns the tv encoder vertical phase. + *--------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_get_tv_vphase(void) +#else +int gfx_get_tv_vphase(void) +#endif +{ + unsigned long mode = READ_VID32(SC1200_TVENC_TIM_CTRL_1); + return (int)((mode & SC1200_TVENC_VPHASE_MASK) >> SC1200_TVENC_VPHASE_POS); +} + +/*--------------------------------------------------------------------------- + * gfx_get_tv_enable + * + * This routine returns the current tv enable status + *--------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_get_tv_enable(unsigned int *p_on) +#else +int gfx_get_tv_enable(unsigned int *p_on) +#endif +{ + unsigned long control = READ_VID32 (SC1200_TVENC_DAC_CONTROL); + + *p_on = (unsigned int)(!(control & SC1200_TVENC_POWER_DOWN)); + + return GFX_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * gfx_get_tv_output + * + * This routine returns the current programmed TV output type. It does not + * detect invalid configurations. + *--------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_get_tv_output(void) +#else +int gfx_get_tv_output(void) +#endif +{ + unsigned long ctrl2, ctrl3; + int format = 0; + + ctrl2 = READ_VID32 (SC1200_TVENC_TIM_CTRL_2); + ctrl3 = READ_VID32 (SC1200_TVENC_TIM_CTRL_3); + + if ((ctrl2 & SC1200_TVENC_CFS_MASK) == SC1200_TVENC_CFS_SVIDEO) + format = TV_OUTPUT_S_VIDEO; + else if (ctrl2 & SC1200_TVENC_OUTPUT_YCBCR) + format = TV_OUTPUT_YUV; + else if ((ctrl2 & SC1200_TVENC_CFS_MASK) == SC1200_TVENC_CFS_CVBS) + { + if (ctrl3 & SC1200_TVENC_CM) format = TV_OUTPUT_SCART; + else format = TV_OUTPUT_COMPOSITE; + } + + return format; +} + +/*--------------------------------------------------------------------------- + * gfx_get_tv_mode_count + * + * This routine returns the number of valid TV out resolutions. + *--------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_get_tv_mode_count(TVStandardType format) +#else +int gfx_get_tv_mode_count(TVStandardType format) +#endif +{ + unsigned int mode, count = 0; + unsigned long flag; + + switch (format) + { + case TV_STANDARD_NTSC: flag = GFX_MODE_TV_NTSC; break; + case TV_STANDARD_PAL: flag = GFX_MODE_TV_PAL; break; + default: return 0; + } + + for (mode = 0; mode < NUM_TV_MODES; mode++) + { + if (TVTimings[mode].flags & flag) + count++; + } + + return count; +} + +/*--------------------------------------------------------------------------- + * gfx_get_tv_display_mode + * + * This routine returns the current TV display parameters. + *--------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_get_tv_display_mode (int *width, int *height, int *bpp, int *hz) +#else +int gfx_get_tv_display_mode (int *width, int *height, int *bpp, int *hz) +#endif +{ + unsigned long frequency; + unsigned long mode, flags; + + *width = gfx_get_hactive(); + *height = gfx_get_vactive(); + *bpp = gfx_get_display_bpp (); + frequency = gfx_get_clock_frequency (); + + for (mode = 0; mode < NUM_TV_MODES; mode++) + { + if (TVTimings[mode].hactive == (unsigned short)(*width) && + TVTimings[mode].vactive == (unsigned short)(*height) && + TVTimings[mode].frequency == frequency) + { + flags = TVTimings[mode].flags; + + if (flags & GFX_MODE_TV_NTSC) *hz = 60; + else if (flags & GFX_MODE_TV_PAL) *hz = 50; + else *hz = 0; + return (1); + } + } + + return -1; +} + +/*--------------------------------------------------------------------------- + * gfx_get_tv_display_mode_frequency + * + * This routine returns the PLL frequency of a given TV mode. + *--------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_get_tv_display_mode_frequency (unsigned short width, unsigned short height, + TVStandardType format, int *frequency) +#else +int gfx_get_tv_display_mode_frequency (unsigned short width, unsigned short height, + TVStandardType format, int *frequency) +#endif +{ + unsigned long mode, flag; + int retval = -1; + + *frequency = 0; + + switch (format) + { + case TV_STANDARD_NTSC: flag = GFX_MODE_TV_NTSC; break; + case TV_STANDARD_PAL: flag = GFX_MODE_TV_PAL; break; + default: return -1; + } + + for (mode = 0; mode < NUM_TV_MODES; mode++) + { + if ((TVTimings[mode].hactive == width) && + (TVTimings[mode].vactive == height) && + (TVTimings[mode].flags & flag)) + { + *frequency = TVTimings[mode].frequency; + retval = 1; + } + } + return retval; +} + +/*--------------------------------------------------------------------------- + * gfx_is_tv_display_mode_supported + * + * Returns >= 0 if the mode is available, -1 if the mode could not be found + *--------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int sc1200_is_tv_display_mode_supported (unsigned short width, unsigned short height, TVStandardType format) +#else +int gfx_is_tv_display_mode_supported (unsigned short width, unsigned short height, TVStandardType format) +#endif +{ + unsigned long mode, flag; + + switch (format) + { + case TV_STANDARD_NTSC: flag = GFX_MODE_TV_NTSC; break; + case TV_STANDARD_PAL: flag = GFX_MODE_TV_PAL; break; + default: return -1; + } + + for (mode = 0; mode < NUM_TV_MODES; mode++) + { + if (TVTimings[mode].hactive == width && + TVTimings[mode].vactive == height && + (TVTimings[mode].flags & flag)) + { + return ((int)mode); + } + } + + return -1; +} + + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/rndr_gu1.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/rndr_gu1.c 2005-12-14 11:30:09.000000000 -0700 @@ -0,0 +1,1564 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * $Workfile: rndr_gu1.c $ + * + * This file contains routines to program the 2D acceleration hardware for + * the first generation graphics unit (GXLV, SC1200). + * + * gfx_set_bpp + * gfx_set_solid_pattern + * gfx_set_mono_pattern + * gfx_set_color_pattern + * gfx_set_solid_source + * gfx_set_mono_source + * gfx_set_raster_operation + * gfx_pattern_fill + * gfx_screen_to_screen_blt + * gfx_screen_to_screen_xblt + * gfx_color_bitmap_to_screen_blt + * gfx_color_bitmap_to_screen_xblt + * gfx_mono_bitmap_to_screen_blt + * gfx_bresenham_line + * gfx_wait_until_idle + * */ + + + +#if GFX_NO_IO_IN_WAIT_MACROS +#define GFX_WAIT_PENDING while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_PENDING) { ; } +#define GFX_WAIT_BUSY while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_BUSY) { ; } +#define GFX_WAIT_PIPELINE while (READ_REG16(GP_BLIT_STATUS) & BS_PIPELINE_BUSY) { ; } +#else +#define GFX_WAIT_PENDING while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_PENDING) { INB (0x80); } +#define GFX_WAIT_BUSY while(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_BUSY) { INB (0x80); } +#define GFX_WAIT_PIPELINE while (READ_REG16(GP_BLIT_STATUS) & BS_PIPELINE_BUSY) { INB (0x80); } +#endif + +void gu1_detect_blt_buffer_base(void); + +/*--------------------------------------------------------------------------- + * GFX_SET_BPP + * + * This routine sets the bits per pixel value in the graphics engine. + * It is also stored in a static variable to use in the future calls to + * the rendering routines. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu1_set_bpp(unsigned short bpp) +#else +void gfx_set_bpp(unsigned short bpp) +#endif +{ + int control = 0; + unsigned short pitch = gfx_get_display_pitch(); + GFXbpp = bpp; + + /* DETECT BASE ADDRESSES FOR BLT BUFFERS */ + /* Different for 2K or 3K of scratchpad. Also need to calculate */ + /* the number of pixels that can fit in a BLT buffer - need to */ + /* subtract 16 for alignment considerations. The 2K case, for */ + /* example, is 816 bytes wide, allowing 800 pixels in 8 BPP, which */ + /* means rendering operations won't be split for 800x600. */ + + gu1_detect_blt_buffer_base(); + GFXbufferWidthPixels = GFXbb1Base - GFXbb0Base - 16; + if( bpp > 8 ) { + /* If 16bpp, divide GFXbufferWidthPixels by 2 */ + GFXbufferWidthPixels >>= 1; + } + + /* SET THE GRAPHICS CONTROLLER BPP AND PITCH */ + if( bpp > 8 ) { + /* Set the 16bpp bit if necessary */ + control = BC_16BPP; + } + if((gfx_cpu_version == GFX_CPU_PYRAMID) && ( pitch > 2048 )) { + control |= BC_FB_WIDTH_4096; + } else if ( pitch > 1024) { + control |= BC_FB_WIDTH_2048; + } + GFX_WAIT_BUSY; + WRITE_REG32(GP_BLIT_STATUS, control); +} + +/* +//--------------------------------------------------------------------------- +// GFX_SET_SOLID_SOURCE +// +// This routine is used to specify a solid source color. For the Xfree96 +// display driver, the source color is used to specify a planemask and the +// ROP is adjusted accordingly. +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_set_solid_source(unsigned long color) +#else +void gfx_set_solid_source(unsigned long color) +#endif +{ + /* CLEAR TRANSPARENCY FLAG */ + + GFXsourceFlags = 0; + + /* FORMAT 8 BPP COLOR */ + /* GX requires 8BPP color data be duplicated into bits [15:8]. */ + + if (GFXbpp == 8) + { + color &= 0x00FF; + color |= (color << 8); + } + + /* POLL UNTIL ABLE TO WRITE THE SOURCE COLOR */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_SRC_COLOR_0, (unsigned short) color); + WRITE_REG16(GP_SRC_COLOR_1, (unsigned short) color); +} + +/* +//--------------------------------------------------------------------------- +// GFX_SET_MONO_SOURCE +// +// This routine is used to specify the monochrome source colors. +// It must be called *after* loading any pattern data (those routines +// clear the source flags). +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_set_mono_source(unsigned long bgcolor, unsigned long fgcolor, + unsigned short transparent) +#else +void gfx_set_mono_source(unsigned long bgcolor, unsigned long fgcolor, + unsigned short transparent) +#endif +{ + /* SET TRANSPARENCY FLAG */ + + GFXsourceFlags = transparent ? RM_SRC_TRANSPARENT : 0; + + /* FORMAT 8 BPP COLOR */ + /* GX requires 8BPP color data be duplicated into bits [15:8]. */ + + if (GFXbpp == 8) + { + bgcolor &= 0x00FF; + bgcolor |= (bgcolor << 8); + fgcolor &= 0x00FF; + fgcolor |= (fgcolor << 8); + } + + /* POLL UNTIL ABLE TO WRITE THE SOURCE COLOR */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_SRC_COLOR_0, (unsigned short) bgcolor); + WRITE_REG16(GP_SRC_COLOR_1, (unsigned short) fgcolor); +} + +/* +//--------------------------------------------------------------------------- +// GFX_SET_SOLID_PATTERN +// +// This routine is used to specify a solid pattern color. It is called +// before performing solid rectangle fills or more complicated BLTs that +// use a solid pattern color. +// +// The driver should always call "gfx_load_raster_operation" after a call +// to this routine to make sure that the pattern flags are set appropriately. +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_set_solid_pattern(unsigned long color) +#else +void gfx_set_solid_pattern(unsigned long color) +#endif +{ + /* CLEAR TRANSPARENCY FLAG */ + + GFXsourceFlags = 0; + + /* SET PATTERN FLAGS */ + + GFXpatternFlags = 0; + + /* FORMAT 8 BPP COLOR */ + /* GX requires 8BPP color data be duplicated into bits [15:8]. */ + + if (GFXbpp == 8) + { + color &= 0x00FF; + color |= (color << 8); + } + + /* SAVE THE REFORMATTED COLOR FOR LATER */ + /* Used to call the "GFX_solid_fill" routine for special cases. */ + + GFXsavedColor = color; + + /* POLL UNTIL ABLE TO WRITE THE PATTERN COLOR */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_PAT_COLOR_0, (unsigned short) color); +} + +/* +//--------------------------------------------------------------------------- +// GFX_SET_MONO_PATTERN +// +// This routine is used to specify a monochrome pattern. +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, unsigned char transparent) +#else +void gfx_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, unsigned char transparent) +#endif +{ + /* CLEAR TRANSPARENCY FLAG */ + + GFXsourceFlags = 0; + + /* SET PATTERN FLAGS */ + + GFXpatternFlags = transparent ? RM_PAT_MONO | RM_PAT_TRANSPARENT : + RM_PAT_MONO; + + /* FORMAT 8 BPP COLOR */ + /* GXm requires 8BPP color data be duplicated into bits [15:8]. */ + + if (GFXbpp == 8) + { + bgcolor &= 0x00FF; + bgcolor |= (bgcolor << 8); + fgcolor &= 0x00FF; + fgcolor |= (fgcolor << 8); + } + + /* POLL UNTIL ABLE TO WRITE THE PATTERN COLORS AND DATA */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_PAT_COLOR_0, (unsigned short) bgcolor); + WRITE_REG16(GP_PAT_COLOR_1, (unsigned short) fgcolor); + WRITE_REG32(GP_PAT_DATA_0, data0); + WRITE_REG32(GP_PAT_DATA_1, data1); +} + +/* +//--------------------------------------------------------------------------- +// GFX_SET_COLOR_PATTERN +// +// This routine is used to specify a color pattern. +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_set_color_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1,unsigned long data2,unsigned long data3, unsigned char transparent) +#else +void gfx_set_color_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, unsigned long data2,unsigned long data3,unsigned char transparent) +#endif +{ + /* CLEAR TRANSPARENCY FLAG */ + + GFXsourceFlags = 0; + + /* SET PATTERN FLAGS */ + + GFXpatternFlags = transparent ? RM_PAT_MONO | RM_PAT_TRANSPARENT : + RM_PAT_MONO; + + GFXpatternFlags |= RM_PAT_COLOR; + /* FORMAT 8 BPP COLOR */ + /* GXm requires 8BPP color data be duplicated into bits [15:8]. */ + + if (GFXbpp == 8) + { + bgcolor &= 0x00FF; + bgcolor |= (bgcolor << 8); + fgcolor &= 0x00FF; + fgcolor |= (fgcolor << 8); + } + + /* POLL UNTIL ABLE TO WRITE THE PATTERN COLORS AND DATA */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_PAT_COLOR_0, (unsigned short) bgcolor); + WRITE_REG16(GP_PAT_COLOR_1, (unsigned short) fgcolor); + WRITE_REG32(GP_PAT_DATA_0, data0); + WRITE_REG32(GP_PAT_DATA_1, data1); + if (GFXbpp > 8) + { + WRITE_REG32(GP_PAT_DATA_2, data2); + WRITE_REG32(GP_PAT_DATA_3, data3); + } +} + +/* +//--------------------------------------------------------------------------- +// GFX_LOAD_COLOR_PATTERN_LINE +// +// This routine is used to load a single line of a 8x8 color pattern. +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_load_color_pattern_line (short y, unsigned long *pattern_8x8) +#else +void gfx_load_color_pattern_line (short y, unsigned long *pattern_8x8) +#endif +{ + /* CLEAR TRANSPARENCY FLAG */ + + GFXsourceFlags = 0; + + /* SET PATTERN FLAGS */ + + GFXpatternFlags = RM_PAT_COLOR; + + y &= 7; + + if (GFXbpp > 8) + pattern_8x8 += (y << 2); + else + pattern_8x8 += (y << 1); + + /* POLL UNTIL ABLE TO WRITE THE PATTERN COLORS AND DATA */ + + GFX_WAIT_PENDING; + WRITE_REG32(GP_PAT_DATA_0, pattern_8x8[0]); + WRITE_REG32(GP_PAT_DATA_1, pattern_8x8[1]); + if (GFXbpp > 8) + { + WRITE_REG32(GP_PAT_DATA_2, pattern_8x8[2]); + WRITE_REG32(GP_PAT_DATA_3, pattern_8x8[3]); + } +} + +/* +//--------------------------------------------------------------------------- +// GFX_SET_RASTER_OPERATION +// +// This routine loads the specified raster operation. It sets the pattern +// flags appropriately. +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_set_raster_operation(unsigned char rop) +#else +void gfx_set_raster_operation(unsigned char rop) +#endif +{ + unsigned short rop16; + + /* GENERATE 16-BIT VERSION OF ROP WITH PATTERN FLAGS */ + + rop16 = (unsigned short) rop | GFXpatternFlags; + if ((rop & 0x33) ^ ((rop >> 2) & 0x33)) + rop16 |= GFXsourceFlags; + + /* SAVE ROP FOR LATER COMPARISONS */ + /* Need to have the pattern flags included */ + + GFXsavedRop = rop16; + + /* SET FLAG INDICATING ROP REQUIRES DESTINATION DATA */ + /* True if even bits (0:2:4:6) do not equal the correspinding */ + /* even bits (1:3:5:7). */ + + GFXusesDstData = ((rop & 0x55) ^ ((rop >> 1) & 0x55)); + + /* POLL UNTIL ABLE TO WRITE THE PATTERN COLOR */ + /* Only one operation can be pending at a time. */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_RASTER_MODE, rop16); +} + +/* +//--------------------------------------------------------------------------- +// GFX_SOLID_FILL +// +// This routine MUST be used when performing a solid rectangle fill with +// the ROPs of PATCOPY (0xF0), BLACKNESS (0x00), WHITENESS (0xFF), or +// PATINVERT (0x0F). There is a bug in GXm for these cases that requires a +// workaround. +// +// For BLACKNESS (ROP = 0x00), set the color to 0x0000. +// For WHITENESS (ROP = 0xFF), set the color to 0xFFFF. +// For PATINVERT (ROP = 0x0F), invert the desired color. +// +// X screen X position (left) +// Y screen Y position (top) +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +// COLOR fill color +// +// THIS ROUTINE SHOULD NOT BE DIRECTLY CALLED FROM THE DRIVER. The driver +// should always use GFX_pattern_fill and let that routine call this one +// when approipriate. This is to hide quirks specific to MediaGX hardware. +//--------------------------------------------------------------------------- +*/ +void gu1_solid_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height, unsigned long color) +{ + unsigned short section; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Only one operation can be pending at a time. */ + + GFX_WAIT_PENDING; + + /* SET REGISTERS TO DRAW RECTANGLE */ + + WRITE_REG16(GP_DST_XCOOR, x); + WRITE_REG16(GP_DST_YCOOR, y); + WRITE_REG16(GP_HEIGHT, height); + WRITE_REG16(GP_RASTER_MODE, 0x00F0); /* PATCOPY */ + WRITE_REG16(GP_PAT_COLOR_0, (unsigned short) color); + + /* CHECK WIDTH FOR GX BUG WORKAROUND */ + + if (width <= 16) + { + /* OK TO DRAW SMALL RECTANGLE IN ONE PASS */ + + WRITE_REG16(GP_WIDTH, width); + WRITE_REG16(GP_BLIT_MODE, 0); + } + else + { + /* DRAW FIRST PART OF RECTANGLE */ + /* Get to a 16 pixel boundary. */ + + section = 0x10 - (x & 0x0F); + WRITE_REG16(GP_WIDTH, section); + WRITE_REG16(GP_BLIT_MODE, 0); + + /* POLL UNTIL ABLE TO LOAD THE SECOND RECTANGLE */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_DST_XCOOR, x + section); + WRITE_REG16(GP_DST_YCOOR, y); + WRITE_REG16(GP_WIDTH, width - section); + WRITE_REG16(GP_BLIT_MODE, 0); + } +} + +/* +//---------------------------------------------------------------------------- +// GFX_PATTERN_FILL +// +// This routine is used to fill a rectangular region. The pattern must +// be previously loaded using one of GFX_load_*_pattern routines. Also, the +// raster operation must be previously specified using the +// "GFX_load_raster_operation" routine. +// +// X screen X position (left) +// Y screen Y position (top) +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height) +#else +void gfx_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height) +#endif +{ + unsigned short section, buffer_width, blit_mode; + + /* CHECK IF OPTIMIZED SOLID CASES */ + /* Check all 16 bits of the ROP to include solid pattern flags. */ + + switch(GFXsavedRop) + { + /* CHECK FOR SPECIAL CASES WITHOUT DESTINATION DATA */ + /* Need hardware workaround for fast "burst write" cases. */ + + case 0x00F0: + gu1_solid_fill(x, y, width, height, (unsigned short) GFXsavedColor); + break; + case 0x000F: + gu1_solid_fill(x, y, width, height, + (unsigned short) ~GFXsavedColor); + break; + case 0x0000: + gu1_solid_fill(x, y, width, height, 0x0000); + break; + case 0x00FF: + gu1_solid_fill(x, y, width, height, 0xFFFF); + break; + + /* REMAINING CASES REQUIRE DESTINATION DATA OR NOT SOLID COLOR */ + + default: + + /* DETERMINE BLT MODE VALUE */ + /* Still here for non-solid patterns without destination data. */ + + blit_mode = GFXusesDstData ? BM_READ_DST_FB0 : 0; + + /* SET SOURCE EXPANSION MODE */ + /* If the ROP requires source data, then the source data is all 1's */ + /* and then expanded into the desired color in GP_SRC_COLOR_1. */ + + blit_mode |= BM_SOURCE_EXPAND; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Write the registers that do not change for each section. */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_HEIGHT, height); + + /* SINCE ONLY DESTINATION DATA, WE CAN USE BOTH BB0 AND BB1. */ + /* Therefore, width available = BLT buffer width * 2. */ + + buffer_width = GFXbufferWidthPixels << 1; + + /* REPEAT UNTIL FINISHED WITH RECTANGLE */ + /* Perform BLT in vertical sections, as wide as the BLT buffer */ + /* allows. Hardware does not split the operations, so */ + /* software must do it to avoid large scanlines that would */ + /* overflow the BLT buffers. */ + + while(width > 0) + { + /* DETERMINE WIDTH OF SECTION */ + + if (width > buffer_width) section = buffer_width; + else section = width; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_DST_XCOOR, x); + WRITE_REG16(GP_DST_YCOOR, y); + WRITE_REG16(GP_WIDTH, section); + WRITE_REG16(GP_BLIT_MODE, blit_mode); + + /* ADJUST PARAMETERS FOR NEXT SECTION */ + + width -= section; + x += section; + } + break; + } +} + +/* +//---------------------------------------------------------------------------- +// GFX_COLOR_PATTERN_FILL +// +// This routine is used to render a rectangle using the current raster +// operation and the specified color pattern. It allows an 8x8 color +// pattern to be rendered without multiple calls to the gfx_set_color_pattern +// and gfx_pattern_fill routines. +// +// X screen X position (left) +// Y screen Y position (top) +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +// *PATTERN pointer to 8x8 color pattern data +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_color_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height, unsigned long *pattern) +#else +void gfx_color_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height, unsigned long *pattern) +#endif +{ + unsigned short blit_mode, passes, cur_y, pat_y, i; + unsigned short buffer_width, line_width; + unsigned short bpp_shift, section, cur_x; + + /* SET APPROPRIATE INCREMENT */ + + bpp_shift = (GFXbpp > 8) ? 2 : 1; + + /* SET DESTINATION REQUIRED */ + + blit_mode = GFXusesDstData ? BM_READ_DST_FB0 : 0; + + /* SET SOURCE EXPANSION */ + + blit_mode |= BM_SOURCE_EXPAND; + + /* OVERRIDE RASTER MODE TO FORCE A COLOR PATTERN */ + + GFX_WAIT_PENDING; + WRITE_REG16 (GP_RASTER_MODE, (GFXsavedRop & ~RM_PAT_MASK & ~RM_PAT_TRANSPARENT) | RM_PAT_COLOR); + + /* WRITE THE REGISTERS THAT DO NOT CHANGE */ + /* If destination data is required, the width and */ + /* x position will be overwritten. */ + + WRITE_REG16 (GP_HEIGHT, 1); + WRITE_REG16 (GP_WIDTH, width); + WRITE_REG16 (GP_DST_XCOOR, x); + + /* THE ENTIRE PATTERN WILL NOT BE DRAWN IF THE HEIGHT IS LESS THAN 8 */ + + passes = (height < 8) ? height : 8; + + /* SINCE ONLY DESTINATION DATA, WE CAN USE BOTH BB0 AND BB1. */ + /* Therefore, width available = BLT buffer width * 2. */ + + buffer_width = GFXbufferWidthPixels << 1; + + + for (i = 0; i < passes; i++) + { + pat_y = ((y + i) & 7) << bpp_shift; + cur_y = y + i; + + /* WRITE THE PATTERN DATA FOR THE ACTIVE LINE */ + + GFX_WAIT_PENDING; + WRITE_REG32 (GP_PAT_DATA_0, pattern[pat_y]); + WRITE_REG32 (GP_PAT_DATA_1, pattern[pat_y + 1]); + + if (GFXbpp > 8) + { + WRITE_REG32 (GP_PAT_DATA_2, pattern[pat_y + 2]); + WRITE_REG32 (GP_PAT_DATA_3, pattern[pat_y + 3]); + } + + /* SPLIT BLT LINE INTO SECTIONS IF REQUIRED */ + /* If no destination data is required, we can ignore */ + /* the BLT buffers. Otherwise, we must separate the BLT */ + /* so as not to overflow the buffers */ + + if (blit_mode & BM_READ_DST_BB0) + { + line_width = width; + cur_x = x; + + while (line_width) + { + section = (line_width > buffer_width) ? buffer_width : line_width; + cur_y = y + i; + + GFX_WAIT_PENDING; + WRITE_REG16 (GP_DST_XCOOR, cur_x); + WRITE_REG16 (GP_WIDTH, section); + + while (cur_y < y + height) + { + GFX_WAIT_PENDING; + WRITE_REG16 (GP_DST_YCOOR, cur_y); + WRITE_REG16 (GP_BLIT_MODE, blit_mode); + cur_y += 8; + } + + cur_x += section; + line_width -= section; + } + + } + else + { + while (cur_y < y + height) + { + GFX_WAIT_PENDING; + WRITE_REG16 (GP_DST_YCOOR, cur_y); + WRITE_REG16 (GP_BLIT_MODE, blit_mode); + cur_y += 8; + } + } + + } + + + /* RESTORE ORIGINAL ROP AND FLAGS */ + + GFX_WAIT_PENDING; + WRITE_REG16 (GP_RASTER_MODE, GFXsavedRop); + +} + +/* +//---------------------------------------------------------------------------- +// SCREEN TO SCREEN BLT +// +// This routine should be used to perform a screen to screen BLT when the +// ROP does not require destination data. +// +// SRCX screen X position to copy from +// SRCY screen Y position to copy from +// DSTX screen X position to copy to +// DSTY screen Y position to copy to +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_screen_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height) +#else +void gfx_screen_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height) +#endif +{ + unsigned short section, buffer_width; + unsigned short blit_mode; + + /* CHECK IF RASTER OPERATION REQUIRES DESTINATION DATA */ + + blit_mode = GFXusesDstData ? BM_READ_DST_FB1 | BM_READ_SRC_FB : + BM_READ_SRC_FB; + + /* CHECK Y DIRECTION */ + /* Hardware has support for negative Y direction. */ + + if (dsty > srcy) + { + blit_mode |= BM_REVERSE_Y; + srcy += height - 1; + dsty += height - 1; + } + + /* CHECK X DIRECTION */ + /* Hardware does not support negative X direction since at the time */ + /* of development all supported resolutions could fit a scanline of */ + /* data at once into the BLT buffers (using both BB0 and BB1). This */ + /* code is more generic to allow for any size BLT buffer. */ + + if (dstx > srcx) + { + srcx += width; + dstx += width; + } + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Write the registers that do not change for each section. */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_HEIGHT, height); + + /* CHECK AVAILABLE BLT BUFFER SIZE */ + /* Can use both BLT buffers if no destination data is required. */ + + buffer_width = GFXusesDstData ? GFXbufferWidthPixels : + GFXbufferWidthPixels << 1; + + /* REPEAT UNTIL FINISHED WITH RECTANGLE */ + /* Perform BLT in vertical sections, as wide as the BLT buffer allows. */ + /* Hardware does not split the operations, so software must do it to */ + /* avoid large scanlines that would overflow the BLT buffers. */ + + while(width > 0) + { + /* CHECK WIDTH OF CURRENT SECTION */ + + if (width > buffer_width) section = buffer_width; + else section = width; + + /* PROGRAM REGISTERS THAT ARE THE SAME FOR EITHER X DIRECTION */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_SRC_YCOOR, srcy); + WRITE_REG16(GP_DST_YCOOR, dsty); + WRITE_REG16(GP_WIDTH, section); + + /* CHECK X DIRECTION */ + + if (dstx > srcx) + { + /* NEGATIVE X DIRECTION */ + /* Still positive X direction within the section. */ + + srcx -= section; + dstx -= section; + WRITE_REG16(GP_SRC_XCOOR, srcx); + WRITE_REG16(GP_DST_XCOOR, dstx); + WRITE_REG16(GP_BLIT_MODE, blit_mode); + } + else + { + /* POSITIVE X DIRECTION */ + + WRITE_REG16(GP_SRC_XCOOR, srcx); + WRITE_REG16(GP_DST_XCOOR, dstx); + WRITE_REG16(GP_BLIT_MODE, blit_mode); + dstx += section; + srcx += section; + } + width -= section; + } +} + +/* +//---------------------------------------------------------------------------- +// SCREEN TO SCREEN TRANSPARENT BLT +// +// This routine should be used to perform a screen to screen BLT when a +// specified color should by transparent. The only supported ROP is SRCCOPY. +// +// SRCX screen X position to copy from +// SRCY screen Y position to copy from +// DSTX screen X position to copy to +// DSTY screen Y position to copy to +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +// COLOR transparent color +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_screen_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned long color) +#else +void gfx_screen_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned long color) +#endif +{ + unsigned short section, buffer_width; + unsigned short blit_mode = BM_READ_SRC_FB; + + /* CHECK Y DIRECTION */ + /* Hardware has support for negative Y direction. */ + + if (dsty > srcy) + { + blit_mode |= BM_REVERSE_Y; + srcy += height - 1; + dsty += height - 1; + } + + /* CHECK X DIRECTION */ + /* Hardware does not support negative X direction since at the time */ + /* of development all supported resolutions could fit a scanline of */ + /* data at once into the BLT buffers (using both BB0 and BB1). This */ + /* code is more generic to allow for any size BLT buffer. */ + + if (dstx > srcx) + { + srcx += width; + dstx += width; + } + + /* CALCULATE BLT BUFFER SIZE */ + /* Need to use BB1 to store the BLT buffer data. */ + + buffer_width = GFXbufferWidthPixels; + + /* WRITE TRANSPARENCY COLOR TO BLT BUFFER 1 */ + + if (GFXbpp == 8) + { + color &= 0x00FF; + color |= (color << 8); + } + color = (color & 0x0000FFFF) | (color << 16); + + /* WAIT UNTIL PIPELINE IS NOT BUSY BEFORE LOADING DATA INTO BB1 */ + /* Need to make sure any previous BLT using BB1 is complete. */ + /* Only need to load 32 bits of BB1 for the 1 pixel BLT that follows. */ + + GFX_WAIT_BUSY; + WRITE_SCRATCH32(GFXbb1Base, color); + + /* DO BOGUS BLT TO LATCH DATA FROM BB1 */ + /* Already know graphics pipeline is idle. */ + /* Only need to latch data into the holding registers for the current */ + /* data from BB1. A 1 pixel wide BLT will suffice. */ + + WRITE_REG32(GP_DST_XCOOR, 0); + WRITE_REG32(GP_SRC_XCOOR, 0); + WRITE_REG32(GP_WIDTH, 0x00010001); + WRITE_REG16(GP_RASTER_MODE, 0x00CC); + WRITE_REG16(GP_BLIT_MODE, BM_READ_SRC_FB | BM_READ_DST_BB1); + + /* WRITE REGISTERS FOR REAL SCREEN TO SCREEN BLT */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_HEIGHT, height); + WRITE_REG16(GP_RASTER_MODE, 0x10C6); + WRITE_REG32(GP_PAT_COLOR_0, 0xFFFFFFFF); + + /* REPEAT UNTIL FINISHED WITH RECTANGLE */ + /* Perform BLT in vertical sections, as wide as the BLT buffer allows. */ + /* Hardware does not split the operations, so software must do it to */ + /* avoid large scanlines that would overflow the BLT buffers. */ + + while(width > 0) + { + /* CHECK WIDTH OF CURRENT SECTION */ + + if (width > buffer_width) section = buffer_width; + else section = width; + + /* PROGRAM REGISTERS THAT ARE THE SAME FOR EITHER X DIRECTION */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_SRC_YCOOR, srcy); + WRITE_REG16(GP_DST_YCOOR, dsty); + WRITE_REG16(GP_WIDTH, section); + + /* CHECK X DIRECTION */ + /* Again, this must be done in software, and can be removed if the */ + /* display driver knows that the BLT buffers will always be large */ + /* enough to contain an entire scanline of a screen to screen BLT. */ + + if (dstx > srcx) + { + /* NEGATIVE X DIRECTION */ + /* Still positive X direction within the section. */ + + srcx -= section; + dstx -= section; + WRITE_REG16(GP_SRC_XCOOR, srcx); + WRITE_REG16(GP_DST_XCOOR, dstx); + WRITE_REG16(GP_BLIT_MODE, blit_mode); + } + else + { + /* POSITIVE X DIRECTION */ + + WRITE_REG16(GP_SRC_XCOOR, srcx); + WRITE_REG16(GP_DST_XCOOR, dstx); + WRITE_REG16(GP_BLIT_MODE, blit_mode); + dstx += section; + srcx += section; + } + width -= section; + } +} + +/* +//---------------------------------------------------------------------------- +// COLOR BITMAP TO SCREEN BLT +// +// This routine transfers color bitmap data to the screen. For most cases, +// when the ROP is SRCCOPY, it may be faster to write a separate routine that +// copies the data to the frame buffer directly. This routine should be +// used when the ROP requires destination data. +// +// Transparency is handled by another routine. +// +// SRCX X offset within source bitmap +// SRCY Y offset within source bitmap +// DSTX screen X position to render data +// DSTY screen Y position to render data +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +// *DATA pointer to bitmap data +// PITCH pitch of bitmap data (bytes between scanlines) +//---------------------------------------------------------------------------- +*/ + +#if GFX_2DACCEL_DYNAMIC +void gu1_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch) +#else +void gfx_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch) +#endif +{ + unsigned short section, buffer_width; + unsigned short blit_mode = BM_READ_SRC_BB0; + unsigned short temp_height; + unsigned long dword_bytes_needed, bytes_extra; + unsigned long bpp_shift; + long array_offset; + + /* CHECK SIZE OF BLT BUFFER */ + + buffer_width = GFXbufferWidthPixels; + + /* CHECK IF RASTER OPERATION REQUIRES DESTINATION DATA */ + /* If no destination data, we have twice the room for */ + /* source data. */ + + if (GFXusesDstData) + blit_mode |= BM_READ_DST_FB1; + else + buffer_width <<= 1; + + /* SET THE SCRATCHPAD BASE */ + + SET_SCRATCH_BASE (GFXbb0Base); + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Write the registers that do not change for each section. */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_HEIGHT, 1); + + bpp_shift = (GFXbpp + 7) >> 4; + + while (width > 0) + { + if (width > buffer_width) section = buffer_width; + else section = width; + + dword_bytes_needed = (section << bpp_shift) & ~3l; + bytes_extra = (section << bpp_shift) & 3l; + + temp_height = height; + + /* WRITE THE REGISTERS FOR EACH SECTION */ + /* The GX hardware will auto-increment the Y coordinate, meaning */ + /* that we don't have to. */ + + WRITE_REG16 (GP_WIDTH, section); + WRITE_REG16 (GP_DST_XCOOR, dstx); + WRITE_REG16 (GP_DST_YCOOR, dsty); + + /* CALCULATE THE BITMAP OFFSET */ + + array_offset = (unsigned long)srcy * (long)pitch + ((long)srcx << bpp_shift); + + while (temp_height--) + { + GFX_WAIT_PIPELINE; + + /* WRITE ALL DATA TO THE BLT BUFFERS */ + /* The WRITE_SCRATCH_STRING macro assumes that the data begins at the */ + /* scratchpad offset set by the SET_SCRATCH_BASE macro. */ + + WRITE_SCRATCH_STRING (dword_bytes_needed, bytes_extra, data, array_offset); + WRITE_REG16 (GP_BLIT_MODE, blit_mode); + + array_offset += pitch; + } + + width -= section; + srcx += section; + dstx += section; + } +} + +/* +//---------------------------------------------------------------------------- +// COLOR BITMAP TO SCREEN TRANSPARENT BLT +// +// This routine transfers color bitmap data to the screen with transparency. +// The transparent color is specified. The only supported ROP is SRCCOPY, +// meaning that transparency cannot be applied if the ROP requires +// destination data (this is a hardware restriction). +// +// SRCX X offset within source bitmap +// SRCY Y offset within source bitmap +// DSTX screen X position to render data +// DSTY screen Y position to render data +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +// *DATA pointer to bitmap data +// PITCH pitch of bitmap data (bytes between scanlines) +// COLOR transparent color +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_color_bitmap_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch, + unsigned long color) +#else +void gfx_color_bitmap_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch, + unsigned long color) +#endif +{ + unsigned short section, buffer_width; + unsigned short temp_height; + unsigned long dword_bytes_needed, bytes_extra; + unsigned long bpp_shift; + long array_offset; + + /* CHECK SIZE OF BLT BUFFER */ + + buffer_width = GFXbufferWidthPixels; + + /* WRITE TRANSPARENCY COLOR TO BLT BUFFER 1 */ + + if (GFXbpp == 8) + { + color &= 0x00FF; + color |= (color << 8); + } + color = (color & 0x0000FFFF) | (color << 16); + + /* WAIT UNTIL PIPELINE IS NOT BUSY BEFORE LOADING DATA INTO BB1 */ + /* Need to make sure any previous BLT using BB1 is complete. */ + /* Only need to load 32 bits of BB1 for the 1 pixel BLT that follows. */ + + GFX_WAIT_PIPELINE; + GFX_WAIT_PENDING; + WRITE_SCRATCH32(GFXbb1Base, color); + + /* DO BOGUS BLT TO LATCH DATA FROM BB1 */ + /* Already know graphics pipeline is idle. */ + /* Only need to latch data into the holding registers for the current */ + /* data from BB1. A 1 pixel wide BLT will suffice. */ + + WRITE_REG32(GP_DST_XCOOR, 0); + WRITE_REG32(GP_SRC_XCOOR, 0); + WRITE_REG32(GP_WIDTH, 0x00010001); + WRITE_REG16(GP_RASTER_MODE, 0x00CC); + WRITE_REG16(GP_BLIT_MODE, BM_READ_SRC_FB | BM_READ_DST_BB1); + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Write the registers that do not change for each section. */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_HEIGHT, 1); + WRITE_REG16(GP_RASTER_MODE, 0x10C6); + WRITE_REG32(GP_PAT_COLOR_0, 0xFFFFFFFF); + + bpp_shift = (GFXbpp + 7) >> 4; + + /* SET THE SCRATCHPAD BASE */ + + SET_SCRATCH_BASE (GFXbb0Base); + + while (width > 0) + { + if (width > buffer_width) section = buffer_width; + else section = width; + + dword_bytes_needed = (section << bpp_shift) & ~3l; + bytes_extra = (section << bpp_shift) & 3l; + + temp_height = height; + + /* WRITE THE REGISTERS FOR EACH SECTION */ + /* The GX hardware will auto-increment the Y coordinate, meaning */ + /* that we don't have to. */ + + WRITE_REG16 (GP_WIDTH, section); + WRITE_REG16 (GP_DST_XCOOR, dstx); + WRITE_REG16 (GP_DST_YCOOR, dsty); + + /* CALCULATE THE BITMAP OFFSET */ + + array_offset = (unsigned long)srcy * (long)pitch + ((long)srcx << bpp_shift); + + while (temp_height--) + { + GFX_WAIT_PIPELINE; + + /* WRITE ALL DATA TO THE BLT BUFFERS */ + /* The WRITE_SCRATCH_STRING macro assumes that the data begins at the */ + /* scratchpad offset set by the SET_SCRATCH_BASE macro. */ + + WRITE_SCRATCH_STRING (dword_bytes_needed, bytes_extra, data, array_offset); + WRITE_REG16 (GP_BLIT_MODE, BM_READ_SRC_BB0); + + array_offset += pitch; + } + + width -= section; + srcx += section; + dstx += section; + } +} + +/* +//---------------------------------------------------------------------------- +// MONOCHROME BITMAP TO SCREEN BLT +// +// This routine transfers monochrome bitmap data to the screen. +// +// SRCX X offset within source bitmap +// SRCY Y offset within source bitmap +// DSTX screen X position to render data +// DSTY screen Y position to render data +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +// *DATA pointer to bitmap data +// PITCH pitch of bitmap data (bytes between scanlines) +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, short pitch) +#else +void gfx_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, short pitch) +#endif +{ + unsigned short section, buffer_width; + unsigned short blit_mode = BM_READ_SRC_BB0 | BM_SOURCE_EXPAND; + unsigned short temp_height; + unsigned long dword_bytes_needed, bytes_extra; + long array_offset; + + /* CHECK IF RASTER OPERATION REQUIRES DESTINATION DATA */ + /* If no destination data, the source data will always fit. */ + /* So, in that event we will set the buffer width to a */ + /* fictitiously large value such that the BLT is never split. */ + + if (GFXusesDstData) + { + buffer_width = GFXbufferWidthPixels; + blit_mode |= BM_READ_DST_FB1; + } + else + buffer_width = 3200; + + /* CHECK IF DATA ALREADY IN BLIT BUFFER */ + /* If the pointer is NULL, data for the full BLT is already there */ + /* WARNING: This could cause problems if destination data is */ + /* involved and it overflows the BLT buffer. Need to remove */ + /* this option and change the drivers to use a temporary buffer. */ + + if (!data) + { + GFX_WAIT_PENDING; + WRITE_REG16(GP_SRC_XCOOR, srcx & 7); + WRITE_REG16(GP_DST_XCOOR, dstx); + WRITE_REG16(GP_DST_YCOOR, dsty); + WRITE_REG16(GP_WIDTH, width); + WRITE_REG16(GP_HEIGHT, height); + WRITE_REG16(GP_BLIT_MODE, blit_mode); + return; + } + + /* SET THE SCRATCHPAD BASE */ + + SET_SCRATCH_BASE (GFXbb0Base); + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Write the registers that do not change for each section. */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_HEIGHT, 1); + + while (width > 0) + { + if (width > buffer_width) section = buffer_width; + else section = width; + + /* CALCULATE BYTES NEEDED */ + /* Add 1 for possible alignment issues. */ + + dword_bytes_needed = ((section + 7 + (srcx & 7)) >> 3) & ~3l; + bytes_extra = ((section + 7 + (srcx & 7)) >> 3) & 3l; + + temp_height = height; + + /* WRITE THE REGISTERS FOR EACH SECTION */ + /* The GX hardware will auto-increment the Y coordinate, meaning */ + /* that we don't have to. */ + + WRITE_REG16 (GP_WIDTH, section); + WRITE_REG16 (GP_DST_XCOOR, dstx); + WRITE_REG16 (GP_DST_YCOOR, dsty); + WRITE_REG16 (GP_SRC_XCOOR, srcx & 7); + + /* CALCULATE THE BITMAP OFFSET */ + + array_offset = (unsigned long)srcy * (long)pitch + ((long)srcx >> 3); + + while (temp_height--) + { + GFX_WAIT_PIPELINE; + + /* WRITE ALL DATA TO THE BLT BUFFERS */ + /* The WRITE_SCRATCH_STRING macro assumes that the data begins at the */ + /* scratchpad offset set by the SET_SCRATCH_BASE macro. */ + + WRITE_SCRATCH_STRING (dword_bytes_needed, bytes_extra, data, array_offset); + WRITE_REG16 (GP_BLIT_MODE, blit_mode); + + array_offset += pitch; + } + + width -= section; + srcx += section; + dstx += section; + } +} + +/* +//---------------------------------------------------------------------------- +// MONOCHROME TEXT BLT +// +// This routine transfers contiguous monochrome text data to the screen. +// +// DSTX screen X position to render data +// DSTY screen Y position to render data +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +// *DATA pointer to bitmap data +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_text_blt(unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data) +#else +void gfx_text_blt(unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data) +#endif +{ + unsigned long dword_bytes_needed, bytes_extra; + long pitch, buffer_bytes, data_bytes; + + /* CALCULATE DATA SIZE */ + + pitch = (width + 7) >> 3; + data_bytes = (long)height * pitch; + + /* CHECK FOR SIMPLE CASE */ + /* This routine is designed to render a source copy text glyph. If destination */ + /* data is required or the source data will not fit, we will punt the operation */ + /* to the more versatile (and slow) mono bitmap routine. */ + + if (GFXbpp > 8) buffer_bytes = GFXbufferWidthPixels << 1; + else buffer_bytes = GFXbufferWidthPixels; + + if (GFXusesDstData || data_bytes > buffer_bytes) + { + gfx_mono_bitmap_to_screen_blt (0, 0, dstx, dsty, width, height, data, (short)pitch); + return; + } + + /* SET THE SCRATCHPAD BASE */ + + SET_SCRATCH_BASE (GFXbb0Base); + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + + dword_bytes_needed = data_bytes & ~3l; + bytes_extra = data_bytes & 3l; + + GFX_WAIT_PENDING; + WRITE_REG16(GP_HEIGHT, height); + WRITE_REG16 (GP_WIDTH, width); + WRITE_REG16 (GP_DST_XCOOR, dstx); + WRITE_REG16 (GP_DST_YCOOR, dsty); + WRITE_REG16 (GP_SRC_XCOOR, 0); + + /* WRITE ALL DATA TO THE BLT BUFFERS */ + /* The WRITE_SCRATCH_STRING macro assumes that the data begins at the */ + /* scratchpad offset set by the SET_SCRATCH_BASE macro. */ + + GFX_WAIT_PIPELINE; + + WRITE_SCRATCH_STRING (dword_bytes_needed, bytes_extra, data, 0); + WRITE_REG16 (GP_BLIT_MODE, BM_READ_SRC_BB0 | BM_SOURCE_TEXT); +} + +/* +//---------------------------------------------------------------------------- +// BRESENHAM LINE +// +// This routine draws a vector using the specified Bresenham parameters. +// Currently this file does not support a routine that accepts the two +// endpoints of a vector and calculates the Bresenham parameters. If it +// ever does, this routine is still required for vectors that have been +// clipped. +// +// X screen X position to start vector +// Y screen Y position to start vector +// LENGTH length of the vector, in pixels +// INITERR Bresenham initial error term +// AXIALERR Bresenham axial error term +// DIAGERR Bresenham diagonal error term +// FLAGS VM_YMAJOR, VM_MAJOR_INC, VM_MINOR_INC +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu1_bresenham_line(unsigned short x, unsigned short y, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags) +#else +void gfx_bresenham_line(unsigned short x, unsigned short y, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags) +#endif +{ + unsigned short vector_mode = flags; + if (GFXusesDstData) vector_mode |= VM_READ_DST_FB; + + /* CHECK NULL LENGTH */ + + if (!length) return; + + /* LOAD THE REGISTERS FOR THE VECTOR */ + + GFX_WAIT_PENDING; + WRITE_REG16(GP_DST_XCOOR, x); + WRITE_REG16(GP_DST_YCOOR, y); + WRITE_REG16(GP_VECTOR_LENGTH, length); + WRITE_REG16(GP_INIT_ERROR, initerr); + WRITE_REG16(GP_AXIAL_ERROR, axialerr); + WRITE_REG16(GP_DIAG_ERROR, diagerr); + WRITE_REG16(GP_VECTOR_MODE, vector_mode); +} + +/*--------------------------------------------------------------------------- + * GFX_WAIT_UNTIL_IDLE + * + * This routine waits until the graphics engine is idle. This is required + * before allowing direct access to the frame buffer. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu1_wait_until_idle(void) +#else +void gfx_wait_until_idle(void) +#endif +{ + GFX_WAIT_BUSY; +} + +/*--------------------------------------------------------------------------- + * GFX_TEST_BLT_PENDING + * + * This routine returns 1 if a BLT is pending, meaning that a call to + * perform a rendering operation would stall. Otherwise it returns 0. + * It is used by Darwin during random testing to only start a BLT + * operation when it knows the Durango routines won't spin on graphics + * (so Darwin can continue to do frame buffer reads and writes). + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +int gu1_test_blt_pending(void) +#else +int gfx_test_blt_pending(void) +#endif +{ + if(READ_REG16(GP_BLIT_STATUS) & BS_BLIT_PENDING) return(1); + else return(0); +} + +/*--------------------------------------------------------------------------- + * BLT BUFFERS!!!!! + *--------------------------------------------------------------------------- + */ + +/* THE BOOT CODE MUST SET THE BLT BUFFER BASES USING THE "CPU_WRITE" */ +/* INSTRUCTION TO ONE OF THE FOLLOWING VALUES: */ + +#define BB0_BASE_2K 0x800 +#define BB1_BASE_2K 0xB30 +#define BB0_BASE_3K 0x400 +#define BB1_BASE_3K 0x930 + +/*--------------------------------------------------------------------------- + * gu1_detect_blt_buffer_base + * + * This detection is hidden from the driver by being called from the + * "gfx_set_bpp" routine. + * + * This is fairly ugly for the following reasons: + * + * - It is the boot code that must set the BLT buffer bases to the + * appropriate values and load the scratchpad tags. + * - The old drivers would also set the base address values to what they + * knew they should be for the 2K or 3K scratchpad configuration. + * - Unfortunately, to set the base addresses requires the use of the + * CPU_WRITE instruction, an instruction specific to GX. + * - Using the CPU_WRITE instruction requires the use of assembly to + * produce the appropriate op codes. + * - Assembly is something that is avoided in Durango because it is not + * platform independent. Some compilers do not support inline assembly. + * - Therefore Durango cannot use the CPU_WRITE instruction. + * - Therefore drivers using Durango must rely on the boot code to set + * the appropriate values. Durango uses this routine to check where + * the base addresses have been set. + * - Unfortunately, it is not as simple as using IO to check for 2K or 3K + * scratchpad size. In VSA1, even though the boot code may set it for + * 3K, SoftVGA comes along and resets it to 2K for it's use in text + * redraws. It used to be that the display driver would set it back + * to 3K. + * - So, the Durango code was changed to just always use 2K. + * - But, the XpressROM code sets it for 3K, and the newer versions of + * SoftVGA do not interfere with that, so then Durango needs to use + * the 3K values to work properly. + * - Therefore, Durango does somewhat of a kludge by writing to directly + * to the scratchpad at both the 2K and 3K locations, then performing + * a unobtrusive BLT that loads data into BB0 (the graphics engine + * always knows the true base). After the BLT, Durango looks to see + * which location changed to know where the base address is. + * - This is a relatively simple way to allow Durango to work on old + * and new platforms without using theCPU_WRITE instructions. + * + * To summarize, the BLT buffers are one of the most painful aspects of + * the GX graphics unit design, and have been removed from future designs + * (the graphics unit has its own dedicated RAM). Durango has tried to + * hide the BLT buffer use from the drivers. + *--------------------------------------------------------------------------- + */ +void gu1_detect_blt_buffer_base(void) +{ + /* ASSUME 2K */ + + GFXbb0Base = BB0_BASE_2K; + GFXbb1Base = BB1_BASE_2K; + + /* CHECK IF SCRATCHPAD IS SET TO 3K OR 4K */ + /* Boot code should still set 3K values for 4K. */ + + if (gfx_gxm_config_read(GXM_CONFIG_GCR) & 0x08) + { + /* WRITE DATA TO 3K LOCATION */ + + GFX_WAIT_BUSY; + WRITE_SCRATCH32(BB0_BASE_3K, 0xFEEDFACE); + + /* HAVE THE GRAPHICS UNIT STORE SOMETHING IN BB0 */ + + WRITE_REG32(GP_DST_XCOOR, 0x00000000); /* AT (0,0) */ + WRITE_REG32(GP_WIDTH, 0x00010004); /* 4x1 BLT */ + WRITE_REG16(GP_RASTER_MODE, 0x00AA); /* KEEP DST */ + WRITE_REG16(GP_BLIT_MODE, BM_READ_DST_FB0); /* STORE IN BB0 */ + + /* CHECK 3K LOCATION */ + /* Breaks if data happened to be 0xFEEDFACE - unlikely. */ + + GFX_WAIT_BUSY; + if (READ_SCRATCH32(BB0_BASE_3K) != 0xFEEDFACE) + { + GFXbb0Base = BB0_BASE_3K; + GFXbb1Base = BB1_BASE_3K; + } + } +} + +/* END OF FILE */ + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/rndr_gu2.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/rndr_gu2.c 2005-12-14 11:29:58.000000000 -0700 @@ -0,0 +1,2116 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * $Workfile: rndr_gu2.c $ + * + * This file contains routines to program the 2D acceleration hardware for + * the second generation graphics unit. + * + * Basic rendering routines (common to all Geode processors): + * gfx_set_bpp + * gfx_set_solid_pattern + * gfx_set_mono_pattern + * gfx_set_color_pattern + * gfx_set_solid_source + * gfx_set_mono_source + * gfx_set_raster_operation + * gfx_pattern_fill + * gfx_color_pattern_fill + * gfx_screen_to_screen_blt + * gfx_screen_to_screen_xblt + * gfx_color_bitmap_to_screen_blt + * gfx_color_bitmap_to_screen_xblt + * gfx_mono_bitmap_to_screen_blt + * gfx_bresenham_line + * gfx_wait_until_idle + * + * Extended rendering routines for second generation functionality: + * gfx2_set_source_stride + * gfx2_set_destination_stride + * gfx2_set_pattern_origins + * gfx2_set_source_transparency + * gfx2_set_alpha_mode + * gfx2_set_alpha_value + * gfx2_pattern_fill + * gfx2_color_pattern_fill + * gfx2_screen_to_screen_blt + * gfx2_mono_expand_blt + * gfx2_color_bitmap_to_screen_blt + * gfx2_mono_bitmap_to_screen_blt + * gfx2_bresenham_line + * gfx2_sync_to_vblank + * */ + + +#define GU2_WAIT_PENDING while(READ_GP32(MGP_BLT_STATUS) & MGP_BS_BLT_PENDING) +#define GU2_WAIT_BUSY while(READ_GP32(MGP_BLT_STATUS) & MGP_BS_BLT_BUSY) +#define GU2_WAIT_HALF_EMPTY while(!(READ_GP32(MGP_BLT_STATUS) & MGP_BS_HALF_EMPTY)) + +/* PATTERN SWIZZLES */ + +#define WORD_SWIZZLE(x) (((x) << 16) | ((x) >> 16)) +#define BYTE_SWIZZLE(x) (((x) << 24) | ((x) >> 24) | (((x) << 8) & 0x00FF0000) | (((x) >> 8) & 0x0000FF00)) + +/* GLOBAL VARIABLES USED BY THE RENDERING ROUTINES */ + +unsigned long gu2_bpp; +unsigned long gu2_pitch = 1280; +unsigned long gu2_src_pitch = 1280; +unsigned long gu2_dst_pitch = 1280; +unsigned long gu2_xshift = 1; +unsigned long gu2_pattern_origin = 0; +unsigned long gu2_rop32; +unsigned long gu2_alpha32 = 0; +unsigned long gu2_alpha_value = 0; +unsigned long gu2_alpha_mode = 0; +unsigned long gu2_alpha_active = 0; +unsigned short gu2_alpha_blt_mode = 0; +unsigned short gu2_alpha_vec_mode = 0; +unsigned short gu2_blt_mode = 0; +unsigned short gu2_vector_mode = 0; +unsigned short gu2_bm_throttle = 0; +unsigned short gu2_vm_throttle = 0; +int gu2_current_line = 0; + +/*--------------------------------------------------------------------------- + * GFX_RESET_PITCH (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine resets all pitches in the graphics engine to one value. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu2_reset_pitch(unsigned short pitch) +#else +void gfx_reset_pitch(unsigned short pitch) +#endif +{ + gu2_pitch = pitch; + gu2_dst_pitch = pitch; + gu2_src_pitch = pitch; +} + +/*--------------------------------------------------------------------------- + * GFX_SET_BPP + * + * This routine sets the bits per pixel value in the graphics engine. + * It is also stored in the static variable "gu2_bpp" to use in the future + * calls to the rendering routines. That variable contains the hardware + * specific value to load into the MGP_RASTER_MODE register. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu2_set_bpp(unsigned short bpp) +#else +void gfx_set_bpp(unsigned short bpp) +#endif +{ + GFXbpp = bpp; + + /* COVERT TO BPP/FORMAT VALUE */ + /* Save in global to combine with ROP later. */ + /* Could write register here and then use byte access for */ + /* the ROP, but would need to set other 24 bits to make */ + /* sure all are set to their appropriate values. */ + + switch(bpp) + { + case 8: gu2_bpp = MGP_RM_BPPFMT_332; gu2_xshift = 0; break; + case 12: gu2_bpp = MGP_RM_BPPFMT_4444; gu2_xshift = 1; break; + case 15: gu2_bpp = MGP_RM_BPPFMT_1555; gu2_xshift = 1; break; + case 16: gu2_bpp = MGP_RM_BPPFMT_565; gu2_xshift = 1; break; + case 32: gu2_bpp = MGP_RM_BPPFMT_8888; gu2_xshift = 2; break; + } + + /* SET INITIAL ROP BASED ONLY ON BPP */ + /* Needs to be set before loading any pattern or source colors. */ + /* We must wait for BUSY because these bits are not pipelined */ + /* in the hardware. */ + + GU2_WAIT_BUSY; + WRITE_GP32(MGP_RASTER_MODE, gu2_bpp); +} + +/* +//--------------------------------------------------------------------------- +// GFX_SET_SOLID_SOURCE +// +// This routine is used to specify a solid source color. For the Xfree96 +// display driver, the source color is used to specify a planemask and the +// ROP is adjusted accordingly. +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_set_solid_source(unsigned long color) +#else +void gfx_set_solid_source(unsigned long color) +#endif +{ + /* CLEAR TRANSPARENCY FLAG */ + + GFXsourceFlags = 0; + + /* WRITE REGISTERS TO SPECIFY SOURCE COLOR */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_SRC_COLOR_FG, color); +} + +/* +//--------------------------------------------------------------------------- +// GFX_SET_MONO_SOURCE +// +// This routine is used to specify the monochrome source colors. +// It must be called *after* loading any pattern data (those routines +// clear the source flags). +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_set_mono_source(unsigned long bgcolor, unsigned long fgcolor, + unsigned short transparent) +#else +void gfx_set_mono_source(unsigned long bgcolor, unsigned long fgcolor, + unsigned short transparent) +#endif +{ + /* SET TRANSPARENCY FLAG */ + + GFXsourceFlags = transparent ? MGP_RM_SRC_TRANS : 0; + + /* WRITE COLOR VALUES */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_SRC_COLOR_FG, fgcolor); + WRITE_GP32(MGP_SRC_COLOR_BG, bgcolor); +} + +/* +//--------------------------------------------------------------------------- +// GFX_SET_SOLID_PATTERN +// +// This routine is used to specify a solid pattern color. It is called +// before performing solid rectangle fills or more complicated BLTs that +// use a solid pattern color. +// +// The driver should always call "gfx_load_raster_operation" after a call +// to this routine to make sure that the pattern flags are set appropriately. +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_set_solid_pattern(unsigned long color) +#else +void gfx_set_solid_pattern(unsigned long color) +#endif +{ + /* CLEAR TRANSPARENCY FLAG */ + + GFXsourceFlags = 0; + + /* SET PATTERN FLAGS */ + + GFXpatternFlags = 0; + + /* POLL UNTIL ABLE TO WRITE THE PATTERN COLOR */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_RASTER_MODE, gu2_bpp); + WRITE_GP32(MGP_PAT_COLOR_0, color); +} + +/* +//--------------------------------------------------------------------------- +// GFX_SET_MONO_PATTERN +// +// This routine is used to specify a monochrome pattern. +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, unsigned char transparent) +#else +void gfx_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, unsigned char transparent) +#endif +{ + /* CLEAR TRANSPARENCY FLAG */ + + GFXsourceFlags = 0; + + /* SET PATTERN FLAGS */ + + if (transparent) + GFXpatternFlags = MGP_RM_PAT_MONO | MGP_RM_PAT_TRANS; + else GFXpatternFlags = MGP_RM_PAT_MONO; + + /* POLL UNTIL ABLE TO WRITE THE PATTERN COLOR */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_RASTER_MODE, gu2_bpp | GFXpatternFlags); + WRITE_GP32(MGP_PAT_COLOR_0, bgcolor); + WRITE_GP32(MGP_PAT_COLOR_1, fgcolor); + WRITE_GP32(MGP_PAT_DATA_0, data0); + WRITE_GP32(MGP_PAT_DATA_1, data1); +} + +/* +//--------------------------------------------------------------------------- +// GFX_SET_COLOR_PATTERN +// +// This routine is used to specify a color pattern. +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_set_color_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1,unsigned long data2,unsigned long data3, unsigned char transparent) +#else +void gfx_set_color_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, unsigned long data2,unsigned long data3,unsigned char transparent) +#endif +{ + /* REMOVE */ +} + +/* +//--------------------------------------------------------------------------- +// GFX_LOAD_COLOR_PATTERN_LINE +// +// This routine is used to load a single line of a 8x8 color pattern. +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_load_color_pattern_line (short y, unsigned long *pattern_8x8) + +#else +void gfx_load_color_pattern_line (short y, unsigned long *pattern_8x8) +#endif +{ + unsigned long temp1, temp2, temp3, temp4; + + /* CLEAR TRANSPARENCY FLAG */ + + GFXsourceFlags = 0; + + /* SET PATTERN FLAGS */ + + GFXpatternFlags = MGP_RM_PAT_COLOR; + + /* OVERRIDE THE RASTER MODE REGISTER */ + /* If the pattern format is set to anything but color */ + /* before loading the registers, some of the data will */ + /* be duplicated according to the current mode. */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_RASTER_MODE, (gu2_rop32 & ~MGP_RM_PAT_FLAGS) | MGP_RM_PAT_COLOR); + + /* LOAD THE PATTERN DATA */ + /* This routine is designed to work in tandem with gfx_pattern_fill. */ + /* It is used for cases when multiple BLTs with color pattern data */ + /* are desired on the same line. It would be inefficient to */ + /* repeatedly call gfx_color_pattern_fill for each single-line BLT. */ + /* So, we will simply replicate the pattern data across all available */ + /* lines such that the pattern y origin plays no part in the BLT. */ + + /* 8 BPP */ + + if (gu2_xshift == 0) + { + pattern_8x8 += (y & 7) << 1; + temp1 = BYTE_SWIZZLE(pattern_8x8[0]); + temp2 = BYTE_SWIZZLE(pattern_8x8[1]); + WRITE_GP32 (MGP_PAT_DATA_1, temp1); + WRITE_GP32 (MGP_PAT_DATA_0, temp2); + WRITE_GP32 (MGP_PAT_COLOR_1, temp1); + WRITE_GP32 (MGP_PAT_COLOR_0, temp2); + + GU2_WAIT_BUSY; + WRITE_GP32 (MGP_PAT_COLOR_3, temp1); + WRITE_GP32 (MGP_PAT_COLOR_2, temp2); + WRITE_GP32 (MGP_PAT_COLOR_5, temp1); + WRITE_GP32 (MGP_PAT_COLOR_4, temp2); + } + else if (gu2_xshift == 1) + { + pattern_8x8 += (y & 7) << 2; + temp1 = WORD_SWIZZLE(pattern_8x8[0]); + temp2 = WORD_SWIZZLE(pattern_8x8[1]); + temp3 = WORD_SWIZZLE(pattern_8x8[2]); + temp4 = WORD_SWIZZLE(pattern_8x8[3]); + + WRITE_GP32 (MGP_PAT_COLOR_1, temp1); + WRITE_GP32 (MGP_PAT_COLOR_0, temp2); + WRITE_GP32 (MGP_PAT_DATA_1, temp3); + WRITE_GP32 (MGP_PAT_DATA_0, temp4); + + GU2_WAIT_BUSY; + WRITE_GP32 (MGP_PAT_COLOR_5, temp1); + WRITE_GP32 (MGP_PAT_COLOR_4, temp2); + WRITE_GP32 (MGP_PAT_COLOR_3, temp3); + WRITE_GP32 (MGP_PAT_COLOR_2, temp4); + } + else + { + pattern_8x8 += (y & 7) << 3; + + WRITE_GP32(MGP_PAT_COLOR_1, pattern_8x8[4]); + WRITE_GP32(MGP_PAT_COLOR_0, pattern_8x8[5]); + WRITE_GP32(MGP_PAT_DATA_1, pattern_8x8[6]); + WRITE_GP32(MGP_PAT_DATA_0, pattern_8x8[7]); + + GU2_WAIT_BUSY; + WRITE_GP32(MGP_PAT_COLOR_5, pattern_8x8[0]); + WRITE_GP32(MGP_PAT_COLOR_4, pattern_8x8[1]); + WRITE_GP32(MGP_PAT_COLOR_3, pattern_8x8[2]); + WRITE_GP32(MGP_PAT_COLOR_2, pattern_8x8[3]); + } +} + +/* +//--------------------------------------------------------------------------- +// GFX_SET_RASTER_OPERATION +// +// This routine loads the specified raster operation. It sets the pattern +// flags appropriately. +//--------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_set_raster_operation(unsigned char rop) +#else +void gfx_set_raster_operation(unsigned char rop) +#endif +{ + gu2_blt_mode = 0; + + /* DISABLE ALPHA BLENDING */ + + gu2_alpha_active = 0; + + /* GENERATE 32-BIT VERSION OF ROP WITH PATTERN FLAGS */ + + gu2_rop32 = (unsigned long) rop | GFXpatternFlags | gu2_bpp; + + /* CHECK IF SOURCE FLAGS SHOULD BE MERGED */ + + if ((rop & 0x33) ^ ((rop >> 2) & 0x33)) + gu2_rop32 |= GFXsourceFlags; + else + gu2_blt_mode = 0x40; + + /* SET FLAG INDICATING ROP REQUIRES DESTINATION DATA */ + /* True if even bits (0:2:4:6) do not equal the corresponding */ + /* even bits (1:3:5:7). */ + + if ((rop & 0x55) ^ ((rop >> 1) & 0x55)) + { + gu2_blt_mode |= MGP_BM_DST_REQ; + gu2_vector_mode = MGP_VM_DST_REQ; + } + else + { + gu2_vector_mode = 0; + } +} + +/* +//---------------------------------------------------------------------------- +// GFX_PATTERN_FILL +// +// This routine is used to fill a rectangular region. The pattern must +// be previously loaded using one of GFX_load_*_pattern routines. Also, the +// raster operation must be previously specified using the +// "GFX_load_raster_operation" routine. +// +// X screen X position (left) +// Y screen Y position (top) +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height) +#else +void gfx_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height) +#endif +{ + unsigned long offset = 0, size; + size = (((unsigned long) width) << 16) | height; + + /* CALCULATE STARTING OFFSET */ + + offset = (unsigned long) y * gu2_pitch + + (((unsigned long) x) << gu2_xshift); + + /* CHECK IF PATTERN ORIGINS NEED TO BE SET */ + + if (GFXpatternFlags) + { + /* COMBINE X AND Y PATTERN ORIGINS WITH OFFSET */ + + offset |= ((unsigned long) (x & 7)) << 26; + offset |= ((unsigned long) (y & 7)) << 29; + } + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Put off poll for as long as possible (do most calculations first). */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32); + WRITE_GP32(MGP_DST_OFFSET, offset); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_pitch); + WRITE_GP32(MGP_BLT_MODE, gu2_blt_mode); +} + +/* +//---------------------------------------------------------------------------- +// GFX_COLOR_PATTERN_FILL +// +// This routine is used to render a rectangle using the current raster +// operation and the specified color pattern. It allows an 8x8 color +// pattern to be rendered without multiple calls to the gfx_set_color_pattern +// and gfx_pattern_fill routines. +// +// X screen X position (left) +// Y screen Y position (top) +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +// *PATTERN pointer to 8x8 color pattern data +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_color_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height, unsigned long *pattern) +#else +void gfx_color_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height, unsigned long *pattern) +#endif +{ + /* CALL GFX2 ROUTINE TO AVOID DUPLICATION OF CODE */ + + unsigned long offset = (unsigned long) y * gu2_pitch + + (((unsigned long) x) << gu2_xshift); + unsigned long origin = gu2_pattern_origin; + unsigned long pitch = gu2_dst_pitch; + gfx2_set_pattern_origin(x, y); + gfx2_set_destination_stride((unsigned short) gu2_pitch); + gfx2_color_pattern_fill(offset, width, height, pattern); + + /* RESTORE GFX2 VALUES */ + + gu2_pattern_origin = origin; + gu2_dst_pitch = pitch; +} + +/* +//---------------------------------------------------------------------------- +// SCREEN TO SCREEN BLT +// +// This routine should be used to perform a screen to screen BLT when the +// ROP does not require destination data. +// +// SRCX screen X position to copy from +// SRCY screen Y position to copy from +// DSTX screen X position to copy to +// DSTY screen Y position to copy to +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_screen_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height) +#else +void gfx_screen_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height) +#endif +{ + unsigned long srcoffset, dstoffset, size; + unsigned short blt_mode; + size = (((unsigned long) width) << 16) | height; + + /* CALCULATE THE DIRECTION OF THE BLT */ + + blt_mode = (gu2_blt_mode & ~MGP_BM_SRC_TYPE_MASK) | MGP_BM_SRC_FB; + if (dstx > srcx) + { + blt_mode |= MGP_BM_NEG_XDIR; + srcx += width - 1; + dstx += width - 1; + } + if (dsty > srcy) + { + blt_mode |= MGP_BM_NEG_YDIR; + srcy += height - 1; + dsty += height - 1; + } + + /* CALCULATE STARTING OFFSETS */ + + srcoffset = (unsigned long) srcy * gu2_pitch + + (((unsigned long) srcx) << gu2_xshift); + dstoffset = ((unsigned long) dsty * gu2_pitch + + (((unsigned long) dstx) << gu2_xshift)) & 0xFFFFFF; + + /* MERGE PATTERN INFORMATION */ + /* This must be done after the x and y coordinates have been updated, */ + /* as the x and y pattern origins correspond to the first ROPed pixel. */ + + if (GFXpatternFlags) + { + /* COMBINE X AND Y PATTERN ORIGINS WITH OFFSET */ + + dstoffset |= ((unsigned long) (dstx & 7)) << 26; + dstoffset |= ((unsigned long) (dsty & 7)) << 29; + } + + /* TURN INTO BYTE ADDRESS IF NEGATIVE X DIRECTION */ + /* This is a quirk of the hardware. */ + + if (blt_mode & MGP_BM_NEG_XDIR) + { + srcoffset += (1 << gu2_xshift) - 1; + dstoffset += (1 << gu2_xshift) - 1; + } + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Put off poll for as long as possible (do most calculations first). */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32 | GFXsourceFlags); + WRITE_GP32(MGP_SRC_OFFSET, srcoffset); + WRITE_GP32(MGP_DST_OFFSET, dstoffset); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_pitch | (gu2_pitch << 16)); + WRITE_GP16(MGP_BLT_MODE, blt_mode); +} + +/* +//---------------------------------------------------------------------------- +// SCREEN TO SCREEN TRANSPARENT BLT +// +// This routine should be used to perform a screen to screen BLT when a +// specified color should by transparent. The only supported ROP is SRCCOPY. +// +// SRCX screen X position to copy from +// SRCY screen Y position to copy from +// DSTX screen X position to copy to +// DSTY screen Y position to copy to +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +// COLOR transparent color +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_screen_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned long color) +#else +void gfx_screen_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned long color) +#endif +{ + unsigned long rop32; + + /* SAVE ORIGINAL RASTER MODE SETTINGS */ + + rop32 = gu2_rop32; + + /* WRITE REGISTERS TO SPECIFY COLOR TRANSPARENCY */ + /* Match GU1 implementation that only allows SRCCOPY for the ROP. */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_SRC_COLOR_FG, color); + WRITE_GP32(MGP_SRC_COLOR_BG, 0xFFFFFFFF); + + /* SET GLOBAL RASTER SETTINGS */ + /* This is needed, as the screen-to-screen BLT */ + /* routine will overwrite the raster mode register. */ + + gu2_rop32 = gu2_bpp | MGP_RM_SRC_TRANS | 0xCC; + + /* CALL NORMAL SCREEN TO SCREEN BLT ROUTINE */ + + gfx_screen_to_screen_blt(srcx, srcy, dstx, dsty, width, height); + + /* RESTORE GLOBAL RASTER SETTINGS */ + + gu2_rop32 = rop32; +} + +/* +//---------------------------------------------------------------------------- +// COLOR BITMAP TO SCREEN BLT +// +// This routine transfers color bitmap data to the screen. +// +// SRCX X offset within source bitmap +// SRCY Y offset within source bitmap +// DSTX screen X position to render data +// DSTY screen Y position to render data +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +// *DATA pointer to bitmap data +// PITCH pitch of bitmap data (bytes between scanlines) +// +// Transparency is handled by another routine. +//---------------------------------------------------------------------------- +*/ + +#if GFX_2DACCEL_DYNAMIC +void gu2_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch) +#else +void gfx_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch) +#endif +{ + unsigned long dstoffset, srcoffset, size, bytes; + unsigned long offset, temp_offset; + unsigned long dword_bytes, bytes_extra; + unsigned short blt_mode; + + blt_mode = (gu2_blt_mode & ~MGP_BM_SRC_TYPE_MASK) | MGP_BM_SRC_FB; + size = (((unsigned long) width) << 16) | 1; + + /* CALCULATE STARTING OFFSETS */ + + offset = (unsigned long) srcy * pitch + ((unsigned long)srcx << gu2_xshift); + + dstoffset = (unsigned long) dsty * gu2_pitch + + (((unsigned long) dstx) << gu2_xshift); + + /* CHECK IF PATTERN ORIGINS NEED TO BE SET */ + + if (GFXpatternFlags) + { + /* COMBINE X AND Y PATTERN ORIGINS WITH OFFSET */ + + dstoffset |= ((unsigned long) (dstx & 7)) << 26; + dstoffset |= ((unsigned long) (dsty & 7)) << 29; + } + + bytes = width << gu2_xshift; + dword_bytes = bytes & ~0x3L; + bytes_extra = bytes & 0x3L; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Put off poll for as long as possible (do most calculations first). */ + /* The source offset is always 0 since we allow misaligned dword reads. */ + /* We must wait for BLT busy because the GP may be executing a screen */ + /* to screen BLT from the scratchpad area. */ + + GU2_WAIT_BUSY; + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32 | GFXsourceFlags); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_pitch); + + /* WRITE DATA ONE LINE AT A TIME */ + /* For speed reasons, data is written to an offscreen scratch area and then */ + /* BLTed using a screen to screen BLT. This is similar to the GX1 BLT buffers, but */ + /* slightly more efficient in that we can queue up data while the GP is rendering */ + /* a line. */ + + while (height--) + { + temp_offset = offset; + srcoffset = gfx_gx2_scratch_base; + if (gu2_current_line) + srcoffset += 8192; + + GU2_WAIT_PENDING; + WRITE_GP32 (MGP_SRC_OFFSET, srcoffset); + WRITE_GP32 (MGP_DST_OFFSET, dstoffset); + dstoffset += gu2_pitch; + dstoffset += 0x20000000; + + WRITE_FRAME_BUFFER_STRING32 (srcoffset, dword_bytes, data, temp_offset); + if (bytes_extra) + { + temp_offset += dword_bytes; + srcoffset += dword_bytes; + WRITE_FRAME_BUFFER_STRING8 (srcoffset, bytes_extra, data, temp_offset); + } + WRITE_GP16 (MGP_BLT_MODE, blt_mode); + offset += pitch; + gu2_current_line = 1 - gu2_current_line; + } +} + +/* +//---------------------------------------------------------------------------- +// COLOR BITMAP TO SCREEN TRANSPARENT BLT +// +// This routine transfers color bitmap data to the screen with transparency. +// The transparent color is specified. The only supported ROP is SRCCOPY, +// meaning that transparency cannot be applied if the ROP requires +// destination data (this is a hardware restriction). +// +// SRCX X offset within source bitmap +// SRCY Y offset within source bitmap +// DSTX screen X position to render data +// DSTY screen Y position to render data +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +// *DATA pointer to bitmap data +// PITCH pitch of bitmap data (bytes between scanlines) +// COLOR transparent color +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_color_bitmap_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch, + unsigned long color) +#else +void gfx_color_bitmap_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch, + unsigned long color) +#endif +{ + unsigned long rop32; + + /* SAVE EXISTING RASTER MODE SETTINGS */ + + rop32 = gu2_rop32; + + /* WRITE REGISTERS TO SPECIFY COLOR TRANSPARENCY */ + /* Match GU1 implementation that only allows SRCCOPY for the ROP. */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_SRC_COLOR_FG, color); + WRITE_GP32(MGP_SRC_COLOR_BG, 0xFFFFFFFF); + + /* SET GLOBAL RASTER SETTINGS */ + /* This is needed, as the screen-to-screen BLT */ + /* routine will overwrite the raster mode register. */ + + gu2_rop32 = gu2_bpp | MGP_RM_SRC_TRANS | 0xCC; + + /* CALL NORMAL COLOR BITMAP TO SCREEN BLT ROUTINE */ + + gfx_color_bitmap_to_screen_blt(srcx, srcy, dstx, dsty, width, height, + data, pitch); + + /* RESTORE RASTER SETTINGS */ + + gu2_rop32 = rop32; +} + +/* +//---------------------------------------------------------------------------- +// MONOCHROME BITMAP TO SCREEN BLT +// +// This routine transfers monochrome bitmap data to the screen. +// +// SRCX X offset within source bitmap +// SRCY Y offset within source bitmap +// DSTX screen X position to render data +// DSTY screen Y position to render data +// WIDTH width of rectangle, in pixels +// HEIGHT height of rectangle, in scanlines +// *DATA pointer to bitmap data +// PITCH pitch of bitmap data (bytes between scanlines) +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, short pitch) +#else +void gfx_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, short pitch) +#endif +{ + unsigned long dstoffset, size, bytes; + unsigned long offset, temp_offset, temp1 = 0, temp2 = 0; + unsigned long i, j = 0, fifo_lines, dwords_extra, bytes_extra; + unsigned long shift = 0; + + size = (((unsigned long) width) << 16) | height; + + /* CALCULATE STARTING OFFSETS */ + + offset = (unsigned long) srcy * pitch + ((unsigned long)srcx >> 3); + + dstoffset = (unsigned long) dsty * gu2_pitch + + (((unsigned long) dstx) << gu2_xshift); + + /* CHECK IF PATTERN ORIGINS NEED TO BE SET */ + + if (GFXpatternFlags) + { + /* COMBINE X AND Y PATTERN ORIGINS WITH OFFSET */ + + dstoffset |= ((unsigned long) (dstx & 7)) << 26; + dstoffset |= ((unsigned long) (dsty & 7)) << 29; + } + + bytes = ((srcx & 7) + width + 7) >> 3; + fifo_lines = bytes >> 5; + dwords_extra = (bytes & 0x0000001Cl) >> 2; + bytes_extra = bytes & 0x00000003l; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Put off poll for as long as possible (do most calculations first). */ + /* The source offset is always 0 since we allow misaligned dword reads. */ + /* Need to wait for busy instead of pending, since hardware clears */ + /* the host data FIFO at the beginning of a BLT. */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32 | GFXsourceFlags); + WRITE_GP32(MGP_SRC_OFFSET, ((unsigned long) srcx & 7) << 26); + WRITE_GP32(MGP_DST_OFFSET, dstoffset); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_pitch); + WRITE_GP16(MGP_BLT_MODE, (gu2_blt_mode & ~MGP_BM_SRC_TYPE_MASK) | MGP_BM_SRC_HOST | MGP_BM_SRC_MONO); + + /* WAIT FOR BLT TO BE LATCHED */ + + GU2_WAIT_PENDING; + + /* WRITE ALL OF THE DATA TO THE HOST SOURCE REGISTER */ + + while (height--) + { + temp_offset = offset; + + /* WRITE ALL FULL FIFO LINES */ + + for (i = 0; i < fifo_lines; i++) + { + GU2_WAIT_HALF_EMPTY; + WRITE_GPREG_STRING32 (MGP_HST_SOURCE, 8, j, data, temp_offset, temp1); + temp_offset += 32; + } + + /* WRITE ALL FULL DWORDS */ + + GU2_WAIT_HALF_EMPTY; + if (dwords_extra) + { + WRITE_GPREG_STRING32 (MGP_HST_SOURCE, dwords_extra, i, data, temp_offset, temp1); + temp_offset += (dwords_extra << 2); + } + + /* WRITE REMAINING BYTES */ + + shift = 0; + if (bytes_extra) + WRITE_GPREG_STRING8 (MGP_HST_SOURCE, bytes_extra, shift, i, data, temp_offset, temp1, temp2); + + offset += pitch; + } +} + +/*--------------------------------------------------------------------------- + * GFX_TEXT_BLT + * + * This routine is similar to the gfx_mono_bitmap_to_screen_blt routine + * but assumes that source data is byte-packed. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu2_text_blt(unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data) +#else +void gfx_text_blt(unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data) +#endif +{ + unsigned long size, bytes; + unsigned long dstoffset, temp1 = 0, temp2 = 0, temp_offset = 0; + unsigned long i, j = 0, fifo_lines, dwords_extra, bytes_extra; + unsigned long shift; + + size = (((unsigned long) width) << 16) | height; + + dstoffset = (unsigned long) dsty * gu2_pitch + + (((unsigned long) dstx) << gu2_xshift); + + /* CHECK IF PATTERN ORIGINS NEED TO BE SET */ + + if (GFXpatternFlags) + { + /* COMBINE X AND Y PATTERN ORIGINS WITH OFFSET */ + + dstoffset |= ((unsigned long) (dstx & 7)) << 26; + dstoffset |= ((unsigned long) (dsty & 7)) << 29; + } + + /* CALCULATE STARTING OFFSETS */ + + bytes = ((width + 7) >> 3) * height; + fifo_lines = bytes >> 5; + dwords_extra = (bytes & 0x0000001Cl) >> 2; + bytes_extra = bytes & 0x00000003l; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32 | GFXsourceFlags); + WRITE_GP32(MGP_SRC_OFFSET, 0); + WRITE_GP32(MGP_DST_OFFSET, dstoffset); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_pitch); + WRITE_GP16(MGP_BLT_MODE, (gu2_blt_mode & ~MGP_BM_SRC_TYPE_MASK) | MGP_BM_SRC_HOST | + MGP_BM_SRC_BP_MONO); + + /* WAIT FOR BLT TO BE LATCHED */ + + GU2_WAIT_PENDING; + + /* WRITE ALL FULL FIFO LINES */ + + for (i = 0; i < fifo_lines; i++) + { + GU2_WAIT_HALF_EMPTY; + WRITE_GPREG_STRING32 (MGP_HST_SOURCE, 8, j, data, temp_offset, temp1); + temp_offset += 32; + } + + /* WRITE ALL FULL DWORDS */ + + if (dwords_extra || bytes_extra) + { + GU2_WAIT_HALF_EMPTY; + if (dwords_extra) + { + WRITE_GPREG_STRING32 (MGP_HST_SOURCE, dwords_extra, i, data, temp_offset, temp1); + temp_offset += (dwords_extra << 2); + } + if (bytes_extra) + { + shift = 0; + WRITE_GPREG_STRING8 (MGP_HST_SOURCE, bytes_extra, shift, i, data, temp_offset, temp1, temp2); + } + } +} + +/* +//---------------------------------------------------------------------------- +// BRESENHAM LINE +// +// This routine draws a vector using the specified Bresenham parameters. +// Currently this file does not support a routine that accepts the two +// endpoints of a vector and calculates the Bresenham parameters. If it +// ever does, this routine is still required for vectors that have been +// clipped. +// +// X screen X position to start vector +// Y screen Y position to start vector +// LENGTH length of the vector, in pixels +// INITERR Bresenham initial error term +// AXIALERR Bresenham axial error term +// DIAGERR Bresenham diagonal error term +// FLAGS VM_YMAJOR, VM_MAJOR_INC, VM_MINOR_INC +//---------------------------------------------------------------------------- +*/ +#if GFX_2DACCEL_DYNAMIC +void gu2_bresenham_line(unsigned short x, unsigned short y, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags) +#else +void gfx_bresenham_line(unsigned short x, unsigned short y, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags) +#endif +{ + unsigned long offset; + unsigned long data1 = (((unsigned long) axialerr) << 16) | diagerr; + unsigned long data2 = (((unsigned long) length) << 16) | initerr; + unsigned short vector_mode = gu2_vector_mode | flags; + + /* CALCULATE STARTING OFFSET */ + + offset = (unsigned long) y * gu2_pitch + + (((unsigned long) x) << gu2_xshift); + + /* CHECK NULL LENGTH */ + + if (!length) return; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Put off poll for as long as possible (do most calculations first). */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32); + WRITE_GP32(MGP_DST_OFFSET, offset); + WRITE_GP32(MGP_VEC_ERR, data1); + WRITE_GP32(MGP_VEC_LEN, data2); + WRITE_GP32(MGP_STRIDE, gu2_pitch); + WRITE_GP32(MGP_VECTOR_MODE, vector_mode); +} + +/*--------------------------------------------------------------------------- + * GFX_WAIT_UNTIL_IDLE + * + * This routine waits until the graphics engine is idle. This is required + * before allowing direct access to the frame buffer. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu2_wait_until_idle(void) +#else +void gfx_wait_until_idle(void) +#endif +{ + while(READ_GP32(MGP_BLT_STATUS) & MGP_BS_BLT_BUSY); +} + +/*--------------------------------------------------------------------------- + * GFX_TEST_BLT_PENDING + * + * This routine returns 1 if a BLT is pending, meaning that a call to + * perform a rendering operation would stall. Otherwise it returns 0. + * It is used by Darwin during random testing to only start a BLT + * operation when it knows the Durango routines won't spin on graphics + * (so Darwin can continue to do frame buffer reads and writes). + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +int gu2_test_blt_pending(void) +#else +int gfx_test_blt_pending(void) +#endif +{ + if (READ_GP32(MGP_BLT_STATUS) & MGP_BS_BLT_PENDING) return(1); + return(0); +} + +/*--------------------------------------------------------------------------- + * NEW ROUTINES FOR REDCLOUD + *--------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------- + * GFX2_SET_SOURCE_STRIDE + * + * This routine sets the stride to be used in successive screen to screen + * BLTs (used by gfx2_screen_to_screen_blt and gfx2_mono_expand_blt). + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_set_source_stride (unsigned short stride) +#else +void gfx2_set_source_stride (unsigned short stride) +#endif +{ + /* SAVE STRIDE TO BE USED LATER */ + + gu2_src_pitch = (unsigned long) stride; +} + +/*--------------------------------------------------------------------------- + * GFX2_SET_DESTINATION_STRIDE + * + * This routine sets the stride used when rendering to the screen. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_set_destination_stride(unsigned short stride) +#else +void gfx2_set_destination_stride(unsigned short stride) +#endif +{ + /* SAVE STRIDE TO BE USED LATER */ + + gu2_dst_pitch = (unsigned long) stride; +} + +/*--------------------------------------------------------------------------- + * GFX2_SET_PATTERN_ORIGIN + * + * This routine sets the origin within an 8x8 pattern. It is needed if + * using a monochrome or color pattern (not used for a solid pattern). + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_set_pattern_origin(int x, int y) +#else +void gfx2_set_pattern_origin(int x, int y) +#endif +{ + /* STORE IN FORMAT THAT CAN BE COMBINED WITH THE DESTINATION OFFSET */ + + gu2_pattern_origin = (((unsigned long) (x & 7)) << 26) | + (((unsigned long) (y & 7)) << 29); +} + +/*--------------------------------------------------------------------------- + * GFX2_SET_SOURCE_TRANSPARENCY + * + * This routine sets the source transparency color and mask to be used + * in future rendering operations. If both the color and mask are set + * to zero (normally completely transparent), those values indicate that + * transparency should be disabled. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_set_source_transparency(unsigned long color, unsigned long mask) +#else +void gfx2_set_source_transparency(unsigned long color, unsigned long mask) +#endif +{ + /* WRITE REGISTERS TO SPECIFY COLOR TRANSPARENCY */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_SRC_COLOR_FG, color); + WRITE_GP32(MGP_SRC_COLOR_BG, mask); + + /* SET TRANSPARENCY FLAG */ + + GFXsourceFlags = (color || mask) ? MGP_RM_SRC_TRANS : 0; +} + +/*--------------------------------------------------------------------------- + * GFX2_SET_ALPHA_MODE + * + * This routine sets the alpha blending mode to be used in successive + * rendering operations. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_set_alpha_mode(int mode) +#else +void gfx2_set_alpha_mode(int mode) +#endif +{ + /* SAVE ALPHA MODE FOR LATER */ + + gu2_alpha_mode = mode; +} + +/*--------------------------------------------------------------------------- + * GFX2_SET_ALPHA_VALUE + * + * This routine sets the alpha value to be used with certain alpha blending + * modes (ALPHA_MODE_BLEND). + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_set_alpha_value(unsigned char value) +#else +void gfx2_set_alpha_value(unsigned char value) +#endif +{ + /* SAVE ALPHA VALUE TO BE USED LATER */ + + gu2_alpha_value = (unsigned long)value; + + /* SET GLOBAL FLAG */ + /* gfx2_* routines will use this flag to program alpha values */ + /* appropriately. Normal gfx_* routines will always write */ + /* the current ROP settings. In this way, the alpha mode */ + /* affects only second generation routines. */ + + gu2_alpha_active = 1; + + switch (gu2_alpha_mode) + { + case ALPHA_MODE_BLEND: + + /* GENERATE 32-BIT VERSION OF RASTER MODE REGISTER */ + /* Pattern data is not involved in the operation. */ + + gu2_alpha32 = gu2_alpha_value | gu2_bpp; + + /* HANDLE SPECIAL CASES FOR ENDPOINTS */ + /* The 8-bit hardware alpha value is always */ + /* interpreted as a fraction. Consequently, there */ + /* is no way to use values of 255 or 0 to exclude */ + /* one of the inputs. */ + + switch (gu2_alpha_value) + { + /* DESTINATION ONLY */ + /* Operation is alpha * A, where A is destination */ + /* and alpha is 1. */ + + case 0: + + gu2_alpha32 |= MGP_RM_SELECT_ALPHA_1 | + MGP_RM_ALPHA_TIMES_A | + MGP_RM_ALPHA_TO_RGB | + MGP_RM_DEST_FROM_CHAN_A; + break; + + /* SOURCE ONLY */ + /* Operation is alpha * A, where A is source and */ + /* alpha is 1. */ + + case 255: + + gu2_alpha32 |= MGP_RM_SELECT_ALPHA_1 | + MGP_RM_ALPHA_TO_RGB | + MGP_RM_ALPHA_TIMES_A; + break; + + /* DEFAULT */ + /* Operation is alpha * A + (1 - alpha) * B; */ + /* A is source, B is destination and alpha is the */ + /* programmed 8-bit value. */ + + default: + + gu2_alpha32 |= MGP_RM_SELECT_ALPHA_R | + MGP_RM_ALPHA_TO_RGB | + MGP_RM_ALPHA_A_PLUS_BETA_B; + + } + + /* CHECK IF SOURCE INFORMATION SHOULD BE MERGED */ + /* Alpha value of 0 indicates destination only. */ + + if (gu2_alpha_value != 0) + gu2_alpha32 |= GFXsourceFlags; + + /* SET FLAG FOR DESTINATION DATA IF NECESSARY */ + /* Alpha value of 255 indicates no destination */ + + if (gu2_alpha_value != 255) + { + gu2_alpha_blt_mode = MGP_BM_DST_REQ; + gu2_alpha_vec_mode = MGP_VM_DST_REQ; + } + + break; + } +} + +/*--------------------------------------------------------------------------- + * GFX2_PATTERN_FILL + * + * This routine is similar to the gfx_pattern_fill routine, but allows the + * use of an arbitrary destination stride. The rendering position is + * also specified as an offset instead of an (x,y) position. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_pattern_fill(unsigned long dstoffset, unsigned short width, unsigned short height) +#else +void gfx2_pattern_fill(unsigned long dstoffset, unsigned short width, unsigned short height) +#endif +{ + unsigned long size; + + size = (((unsigned long) width) << 16) | height; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Put off poll for as long as possible (do most calculations first). */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32); + WRITE_GP32(MGP_DST_OFFSET, dstoffset | gu2_pattern_origin); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_dst_pitch); + WRITE_GP32(MGP_BLT_MODE, gu2_blt_mode | gu2_bm_throttle); + gu2_bm_throttle = 0; + gu2_vm_throttle = 0; +} + +/*--------------------------------------------------------------------------- + * GFX2_COLOR_PATTERN_FILL + * + * This routine is used to render a rectangle using the current raster + * operation and the specified color pattern. It allows an 8x8 color + * pattern to be rendered without multiple calls to the gfx_set_color_pattern + * and gfx_pattern_fill routines. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_color_pattern_fill(unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned long *pattern) +#else +void gfx2_color_pattern_fill(unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned long *pattern) +#endif +{ + int pass; + unsigned long lines, size, patxorigin, patoffset; + + /* ONLY USE HW PATTERN ORIGIN FOR THE X DIRECTION */ + /* Y direction handled by referencing proper location in pattern data. */ + + patxorigin = (gu2_pattern_origin) & 0x1C000000; + + /* OVERRIDE PATTERN FLAGS IN ROP TO FORCE COLOR PATTERN */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_RASTER_MODE, (gu2_rop32 & ~MGP_RM_PAT_FLAGS) | MGP_RM_PAT_COLOR); + + /* ATTEMPT TO OPTIMIZE */ + /* If possible, we can perform the pattern fill in only a few passes */ + /* This is performed by multiplying the pitch by an appropriate amount. */ + /* Consequently, if the multiplied pitch exceeds 16 bits, this */ + /* optimization is impossible. */ + + if ((gu2_dst_pitch << (gu2_xshift + 1)) <= 0xFFFF) + { + /* HANDLE VARIOUS COLOR DEPTHS DIFFERENTLY */ + + switch (gu2_xshift) + { + case 0: /* 8 BPP */ + + /* TWO PASSES FOR 8 BPP */ + /* Render every other line per pass by doubling the pitch. */ + + patoffset = (gu2_pattern_origin >> 28) & 0x0E; + for (pass = 0; pass < 2; pass++) + { + /* CAN WRITE SOME PATTERN REGISTERS WHILE "PENDING" */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_DST_OFFSET, dstoffset | patxorigin); + lines = (height + 1 - pass) >> 1; + if (!lines) break; + size = (((unsigned long) width) << 16) | lines; + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_dst_pitch << 1); + WRITE_GP32(MGP_PAT_DATA_1, BYTE_SWIZZLE (pattern[patoffset])); + WRITE_GP32(MGP_PAT_DATA_0, BYTE_SWIZZLE (pattern[patoffset+1])); + patoffset = (patoffset + 4) & 0x0E; + WRITE_GP32(MGP_PAT_COLOR_1, BYTE_SWIZZLE (pattern[patoffset])); + WRITE_GP32(MGP_PAT_COLOR_0, BYTE_SWIZZLE (pattern[patoffset+1])); + patoffset = (patoffset + 4) & 0x0E; + + /* NEED TO WAIT UNTIL IDLE FOR COLORS 2 THROUGH 5 */ + /* Those registers are not pipelined. */ + + GU2_WAIT_BUSY; + WRITE_GP32(MGP_PAT_COLOR_3, BYTE_SWIZZLE (pattern[patoffset])); + WRITE_GP32(MGP_PAT_COLOR_2, BYTE_SWIZZLE (pattern[patoffset+1])); + patoffset = (patoffset + 4) & 0x0E; + WRITE_GP32(MGP_PAT_COLOR_5, BYTE_SWIZZLE (pattern[patoffset])); + WRITE_GP32(MGP_PAT_COLOR_4, BYTE_SWIZZLE (pattern[patoffset+1])); + WRITE_GP16(MGP_BLT_MODE, gu2_blt_mode | gu2_bm_throttle); + gu2_bm_throttle = 0; + gu2_vm_throttle = 0; + + /* ADJUST FOR NEXT PASS */ + + dstoffset += gu2_dst_pitch; + patoffset = (patoffset + 6) & 0x0E; + } + break; + + case 1: /* 12, 15, OR 16 BPP */ + + /* FOUR PASSES FOR 16 BPP */ + /* Render every 4th line per pass by quadrupling the pitch. */ + + patoffset = (gu2_pattern_origin >> 27) & 0x1C; + for (pass = 0; pass < 4; pass++) + { + /* CAN WRITE SOME PATTERN REGISTERS WHILE "PENDING" */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_DST_OFFSET, dstoffset | patxorigin); + lines = (height + 3 - pass) >> 2; + if (!lines) break; + size = (((unsigned long) width) << 16) | lines; + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_dst_pitch << 2); + WRITE_GP32(MGP_PAT_COLOR_1, WORD_SWIZZLE (pattern[patoffset])); + WRITE_GP32(MGP_PAT_COLOR_0, WORD_SWIZZLE (pattern[patoffset+1])); + WRITE_GP32(MGP_PAT_DATA_1, WORD_SWIZZLE (pattern[patoffset+2])); + WRITE_GP32(MGP_PAT_DATA_0, WORD_SWIZZLE (pattern[patoffset+3])); + patoffset = (patoffset + 16) & 0x1C; + + /* NEED TO WAIT UNTIL IDLE FOR COLORS 2 THROUGH 5 */ + /* Those registers are not pipelined. */ + + GU2_WAIT_BUSY; + WRITE_GP32(MGP_PAT_COLOR_5, WORD_SWIZZLE (pattern[patoffset])); + WRITE_GP32(MGP_PAT_COLOR_4, WORD_SWIZZLE (pattern[patoffset+1])); + WRITE_GP32(MGP_PAT_COLOR_3, WORD_SWIZZLE (pattern[patoffset+2])); + WRITE_GP32(MGP_PAT_COLOR_2, WORD_SWIZZLE (pattern[patoffset+3])); + WRITE_GP16(MGP_BLT_MODE, gu2_blt_mode | gu2_bm_throttle); + gu2_bm_throttle = 0; + gu2_vm_throttle = 0; + + /* ADJUST FOR NEXT PASS */ + + dstoffset += gu2_dst_pitch; + patoffset = (patoffset + 20) & 0x1C; + } + break; + + case 2: /* 32 BPP */ + + /* EIGHT PASSES FOR 32 BPP */ + /* Render every 8th line per pass by setting pitch * 8. */ + + patoffset = (gu2_pattern_origin >> 26) & 0x38; + for (pass = 0; pass < 8; pass++) + { + /* CAN WRITE SOME PATTERN REGISTERS WHILE "PENDING" */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_DST_OFFSET, dstoffset | patxorigin); + lines = (height + 7 - pass) >> 3; + if (!lines) break; + size = (((unsigned long) width) << 16) | lines; + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_dst_pitch << 3); + WRITE_GP32(MGP_PAT_COLOR_1, pattern[patoffset+4]); + WRITE_GP32(MGP_PAT_COLOR_0, pattern[patoffset+5]); + WRITE_GP32(MGP_PAT_DATA_1, pattern[patoffset+6]); + WRITE_GP32(MGP_PAT_DATA_0, pattern[patoffset+7]); + + /* NEED TO WAIT UNTIL IDLE FOR COLORS 2 THROUGH 5 */ + /* Those registers are not pipelined. */ + + GU2_WAIT_BUSY; + WRITE_GP32(MGP_PAT_COLOR_5, pattern[patoffset]); + WRITE_GP32(MGP_PAT_COLOR_4, pattern[patoffset+1]); + WRITE_GP32(MGP_PAT_COLOR_3, pattern[patoffset+2]); + WRITE_GP32(MGP_PAT_COLOR_2, pattern[patoffset+3]); + WRITE_GP16(MGP_BLT_MODE, gu2_blt_mode | gu2_bm_throttle); + gu2_bm_throttle = 0; + gu2_vm_throttle = 0; + + /* ADJUST FOR NEXT PASS */ + + dstoffset += gu2_dst_pitch; + patoffset = (patoffset + 8) & 0x38; + } + break; + } + } + + else + { + WRITE_GP32 (MGP_STRIDE, gu2_dst_pitch); + + switch (gu2_xshift) + { + case 0: /* 8 BPP - 4 LINES PER PASS */ + + patoffset = (gu2_pattern_origin >> 28) & 0x0E; + while (height) + { + lines = height > 4 ? 4 : height; + + /* CAN WRITE SOME REGISTERS WHILE PENDING */ + + WRITE_GP32(MGP_DST_OFFSET, dstoffset | patxorigin); + WRITE_GP32(MGP_WID_HEIGHT, (((unsigned long) width) << 16) | lines); + WRITE_GP32(MGP_PAT_DATA_1, BYTE_SWIZZLE (pattern[patoffset])); + WRITE_GP32(MGP_PAT_DATA_0, BYTE_SWIZZLE (pattern[patoffset + 1])); + patoffset = (patoffset + 2) & 0x0E; + WRITE_GP32(MGP_PAT_COLOR_1, BYTE_SWIZZLE (pattern[patoffset])); + WRITE_GP32(MGP_PAT_COLOR_0, BYTE_SWIZZLE (pattern[patoffset + 1])); + patoffset = (patoffset + 2) & 0x0E; + + /* NEED TO WAIT UNTIL IDLE FOR COLORS 2 THROUGH 5 */ + /* Those registers are not pipelined. */ + + GU2_WAIT_BUSY; + WRITE_GP32(MGP_PAT_COLOR_3, BYTE_SWIZZLE (pattern[patoffset])); + WRITE_GP32(MGP_PAT_COLOR_2, BYTE_SWIZZLE (pattern[patoffset + 1])); + patoffset = (patoffset + 2) & 0x0E; + WRITE_GP32(MGP_PAT_COLOR_5, BYTE_SWIZZLE (pattern[patoffset])); + WRITE_GP32(MGP_PAT_COLOR_4, BYTE_SWIZZLE (pattern[patoffset + 1])); + patoffset = (patoffset + 2) & 0x0E; + WRITE_GP16(MGP_BLT_MODE, gu2_blt_mode | gu2_bm_throttle); + + /* ADJUST FOR NEXT PASS */ + + dstoffset += gu2_dst_pitch << 2; + height -= (unsigned short)lines; + } + break; + + case 1: /* 12, 15 AND 16 BPP - 2 LINES PER PASS */ + + patoffset = (gu2_pattern_origin >> 27) & 0x1C; + while (height) + { + lines = height > 2 ? 2 : height; + + /* CAN WRITE SOME REGISTERS WHILE PENDING */ + + WRITE_GP32(MGP_DST_OFFSET, dstoffset | patxorigin); + WRITE_GP32(MGP_WID_HEIGHT, (((unsigned long) width) << 16) | lines); + WRITE_GP32(MGP_PAT_COLOR_1, WORD_SWIZZLE (pattern[patoffset])); + WRITE_GP32(MGP_PAT_COLOR_0, WORD_SWIZZLE (pattern[patoffset + 1])); + WRITE_GP32(MGP_PAT_DATA_1, WORD_SWIZZLE (pattern[patoffset + 2])); + WRITE_GP32(MGP_PAT_DATA_0, WORD_SWIZZLE (pattern[patoffset + 3])); + patoffset = (patoffset + 4) & 0x1C; + + /* NEED TO WAIT UNTIL IDLE FOR COLORS 2 THROUGH 5 */ + /* Those registers are not pipelined. */ + + GU2_WAIT_BUSY; + WRITE_GP32(MGP_PAT_COLOR_5, WORD_SWIZZLE (pattern[patoffset])); + WRITE_GP32(MGP_PAT_COLOR_4, WORD_SWIZZLE (pattern[patoffset + 1])); + WRITE_GP32(MGP_PAT_COLOR_3, WORD_SWIZZLE (pattern[patoffset + 2])); + WRITE_GP32(MGP_PAT_COLOR_2, WORD_SWIZZLE (pattern[patoffset + 3])); + patoffset = (patoffset + 4) & 0x1C; + WRITE_GP16(MGP_BLT_MODE, gu2_blt_mode | gu2_bm_throttle); + + /* ADJUST FOR NEXT PASS */ + + dstoffset += gu2_dst_pitch << 1; + height -= (unsigned short)lines; + } + break; + + case 2: /* 32 BPP - 1 LINE PER PASS */ + + patoffset = (gu2_pattern_origin >> 26) & 0x38; + while (height) + { + /* CAN WRITE SOME REGISTERS WHILE PENDING */ + + WRITE_GP32(MGP_DST_OFFSET, dstoffset | patxorigin); + WRITE_GP32(MGP_WID_HEIGHT, (((unsigned long) width) << 16) | 1l); + WRITE_GP32(MGP_PAT_COLOR_1, pattern[patoffset + 4]); + WRITE_GP32(MGP_PAT_COLOR_0, pattern[patoffset + 5]); + WRITE_GP32(MGP_PAT_DATA_1, pattern[patoffset + 6]); + WRITE_GP32(MGP_PAT_DATA_0, pattern[patoffset + 7]); + + /* NEED TO WAIT UNTIL IDLE FOR COLORS 2 THROUGH 5 */ + /* Those registers are not pipelined. */ + + GU2_WAIT_BUSY; + WRITE_GP32(MGP_PAT_COLOR_5, pattern[patoffset]); + WRITE_GP32(MGP_PAT_COLOR_4, pattern[patoffset + 1]); + WRITE_GP32(MGP_PAT_COLOR_3, pattern[patoffset + 2]); + WRITE_GP32(MGP_PAT_COLOR_2, pattern[patoffset + 3]); + patoffset = (patoffset + 8) & 0x38; + WRITE_GP16(MGP_BLT_MODE, gu2_blt_mode | gu2_bm_throttle); + + /* ADJUST FOR NEXT PASS */ + + dstoffset += gu2_dst_pitch ; + height--; + } + break; + } + + } + +} + +/*--------------------------------------------------------------------------- + * GFX2_SCREEN_TO_SCREEN_BLT + * + * This routine is similar to the gfx_screen_to_screen_blt routine but + * allows the use of arbitrary source and destination strides and alpha + * blending. It also allows the use of an arbitrary ROP with transparency. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_screen_to_screen_blt(unsigned long srcoffset, unsigned long dstoffset, + unsigned short width, unsigned short height, int flags) +#else +void gfx2_screen_to_screen_blt(unsigned long srcoffset, unsigned long dstoffset, + unsigned short width, unsigned short height, int flags) +#endif +{ + unsigned long size, xbytes; + unsigned short blt_mode; + size = (((unsigned long) width) << 16) | height; + + /* USE ALPHA SETTINGS, IF REQUESTED */ + + if (gu2_alpha_active) + blt_mode = gu2_alpha_blt_mode | MGP_BM_SRC_FB; + + else + blt_mode = (gu2_blt_mode & ~MGP_BM_SRC_TYPE_MASK) | MGP_BM_SRC_FB; + + + /* CALCULATE THE DIRECTION OF THE BLT */ + /* Using offsets, so flags from the calling routine are needed. */ + + if (flags & 1) + { + xbytes = (width - 1) << gu2_xshift; + srcoffset += xbytes; + dstoffset += xbytes; + blt_mode |= MGP_BM_NEG_XDIR; + } + if (flags & 2) + { + srcoffset += (height - 1) * gu2_src_pitch; + dstoffset += (height - 1) * gu2_dst_pitch; + blt_mode |= MGP_BM_NEG_YDIR; + } + + /* TURN INTO BYTE ADDRESS IF NEGATIVE X DIRECTION */ + /* This is a quirk of the hardware. */ + + if (blt_mode & MGP_BM_NEG_XDIR) + { + srcoffset += (1 << gu2_xshift) - 1; + dstoffset += (1 << gu2_xshift) - 1; + } + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Put off poll for as long as possible (do most calculations first). */ + + GU2_WAIT_PENDING; + + if (gu2_alpha_active) + { + WRITE_GP32(MGP_RASTER_MODE, gu2_alpha32); + } + else + { + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32 | GFXsourceFlags); + } + + WRITE_GP32(MGP_SRC_OFFSET, srcoffset); + WRITE_GP32(MGP_DST_OFFSET, dstoffset | gu2_pattern_origin); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_dst_pitch | (gu2_src_pitch << 16)); + WRITE_GP16(MGP_BLT_MODE, blt_mode | gu2_bm_throttle); + gu2_bm_throttle = 0; + gu2_vm_throttle = 0; +} + +/*--------------------------------------------------------------------------- + * GFX2_MONO_EXPAND_BLT + * + * This routine is similar to the gfx2_screen_to_screen_blt routine but + * expands monochrome data stored in graphics memory. + * WARNING: This routine assumes that the regions in graphics memory + * will not overlap, and therefore does not check the BLT direction. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_mono_expand_blt(unsigned long srcbase, unsigned short srcx, unsigned short srcy, + unsigned long dstoffset, unsigned short width, unsigned short height, + int byte_packed) +#else +void gfx2_mono_expand_blt(unsigned long srcbase, unsigned short srcx, unsigned short srcy, + unsigned long dstoffset, unsigned short width, unsigned short height, + int byte_packed) +#endif +{ + unsigned long size, srcoffset; + unsigned short blt_mode; + + size = (((unsigned long) width) << 16) | height; + + /* CALCULATE SOURCE OFFSET */ + + srcoffset = srcbase + (unsigned long) srcy * gu2_src_pitch; + srcoffset += srcx >> 3; + srcoffset |= ((unsigned long) srcx & 7) << 26; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Put off poll for as long as possible (do most calculations first). */ + + GU2_WAIT_PENDING; + + if (gu2_alpha_active) + { + blt_mode = gu2_alpha_blt_mode; + + WRITE_GP32(MGP_RASTER_MODE, gu2_alpha32); + } + else + { + blt_mode = (gu2_blt_mode & ~MGP_BM_SRC_TYPE_MASK); + + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32 | GFXsourceFlags); + } + + if (byte_packed) blt_mode |= MGP_BM_SRC_FB | MGP_BM_SRC_BP_MONO | gu2_bm_throttle; + else blt_mode |= MGP_BM_SRC_FB | MGP_BM_SRC_MONO | gu2_bm_throttle; + + WRITE_GP32(MGP_SRC_OFFSET, srcoffset); + WRITE_GP32(MGP_DST_OFFSET, dstoffset | gu2_pattern_origin); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_dst_pitch | (gu2_src_pitch << 16)); + WRITE_GP16(MGP_BLT_MODE, blt_mode); + gu2_bm_throttle = 0; + gu2_vm_throttle = 0; +} + +/*--------------------------------------------------------------------------- + * GFX2_COLOR_BITMAP_TO_SCREEN_BLT + * + * This routine is similar to the gfx_color_bitmap_to_screen_blt routine + * but allows the use of an arbitrary destination stride and alpha blending. + * It also allows the use of an arbitrary ROP with transparency. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned long dstoffset, unsigned short width, + unsigned short height, unsigned char *data, short pitch) +#else +void gfx2_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned long dstoffset, unsigned short width, + unsigned short height, unsigned char *data, short pitch) +#endif +{ + unsigned long size, bytes; + unsigned long offset, temp_offset; + unsigned long srcoffset, dword_bytes, bytes_extra; + unsigned short blt_mode; + + size = (((unsigned long) width) << 16) | 1; + + /* CALCULATE STARTING OFFSETS */ + + offset = (unsigned long) srcy * pitch + ((unsigned long)srcx << gu2_xshift); + + dstoffset |= gu2_pattern_origin; + + bytes = width << gu2_xshift; + dword_bytes = bytes & ~0x3L; + bytes_extra = bytes & 0x3L; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Put off poll for as long as possible (do most calculations first). */ + /* The source offset is always 0 since we allow misaligned dword reads. */ + /* We must wait for BLT busy because the GP may be executing a screen */ + /* to screen BLT from the scratchpad area. */ + + GU2_WAIT_BUSY; + + if (gu2_alpha_active) + { + blt_mode = gu2_alpha_blt_mode; + + WRITE_GP32(MGP_RASTER_MODE, gu2_alpha32); + } + else + { + blt_mode = (gu2_blt_mode & ~MGP_BM_SRC_TYPE_MASK); + + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32 | GFXsourceFlags); + } + blt_mode |= MGP_BM_SRC_FB | gu2_bm_throttle; + gu2_bm_throttle = 0; + gu2_vm_throttle = 0; + + WRITE_GP32(MGP_WID_HEIGHT, size); + + /* WRITE DATA ONE LINE AT A TIME */ + /* For speed reasons, data is written to an offscreen scratch area and then */ + /* BLTed using a screen to screen BLT. This is similar to the GX1 BLT buffers, but */ + /* slightly more efficient in that we can queue up data while the GP is rendering */ + /* a line. */ + + while (height--) + { + temp_offset = offset; + srcoffset = gfx_gx2_scratch_base; + if (gu2_current_line) + srcoffset += 8192; + + GU2_WAIT_PENDING; + WRITE_GP32 (MGP_SRC_OFFSET, srcoffset); + WRITE_GP32 (MGP_DST_OFFSET, dstoffset); + dstoffset += gu2_dst_pitch; + dstoffset += 0x20000000; + + WRITE_FRAME_BUFFER_STRING32 (srcoffset, dword_bytes, data, temp_offset); + if (bytes_extra) + { + temp_offset += dword_bytes; + srcoffset += dword_bytes; + WRITE_FRAME_BUFFER_STRING8 (srcoffset, bytes_extra, data, temp_offset); + } + WRITE_GP16 (MGP_BLT_MODE, blt_mode); + offset += pitch; + gu2_current_line = 1 - gu2_current_line; + } +} + +/*--------------------------------------------------------------------------- + * GFX2_TEXT_BLT + * + * This routine is similar to the gfx2_mono_bitmap_to_screen_blt routine + * but assumes that source data is byte-packed. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_text_blt(unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned char *data) +#else +void gfx2_text_blt(unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned char *data) +#endif +{ + unsigned long size, bytes; + unsigned long temp1 = 0, temp2 = 0, temp_offset = 0; + unsigned long i, j = 0, fifo_lines, dwords_extra, bytes_extra; + unsigned long shift; + unsigned short blt_mode; + + size = (((unsigned long) width) << 16) | height; + + /* CALCULATE STARTING OFFSETS */ + + bytes = ((width + 7) >> 3) * height; + fifo_lines = bytes >> 5; + dwords_extra = (bytes & 0x0000001Cl) >> 2; + bytes_extra = bytes & 0x00000003l; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + + GU2_WAIT_PENDING; + + if (gu2_alpha_active) + { + blt_mode = gu2_alpha_blt_mode; + + WRITE_GP32(MGP_RASTER_MODE, gu2_alpha32); + } + else + { + blt_mode = (gu2_blt_mode & ~MGP_BM_SRC_TYPE_MASK); + + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32 | GFXsourceFlags); + } + + WRITE_GP32(MGP_SRC_OFFSET, 0); + WRITE_GP32(MGP_DST_OFFSET, dstoffset | gu2_pattern_origin); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_dst_pitch); + WRITE_GP16(MGP_BLT_MODE, blt_mode | MGP_BM_SRC_HOST | + MGP_BM_SRC_BP_MONO | gu2_bm_throttle); + gu2_bm_throttle = 0; + gu2_vm_throttle = 0; + + /* WAIT FOR BLT TO BE LATCHED */ + + GU2_WAIT_PENDING; + + /* WRITE ALL FULL FIFO LINES */ + + for (i = 0; i < fifo_lines; i++) + { + GU2_WAIT_HALF_EMPTY; + WRITE_GPREG_STRING32 (MGP_HST_SOURCE, 8, j, data, temp_offset, temp1); + temp_offset += 32; + } + + /* WRITE ALL FULL DWORDS */ + + if (dwords_extra || bytes_extra) + { + GU2_WAIT_HALF_EMPTY; + if (dwords_extra) + { + WRITE_GPREG_STRING32 (MGP_HST_SOURCE, dwords_extra, i, data, temp_offset, temp1); + temp_offset += (dwords_extra << 2); + } + if (bytes_extra) + { + shift = 0; + WRITE_GPREG_STRING8 (MGP_HST_SOURCE, bytes_extra, shift, i, data, temp_offset, temp1, temp2); + } + } +} + +/*--------------------------------------------------------------------------- + * GFX2_MONO_BITMAP_TO_SCREEN_BLT + * + * This routine is similar to the gfx_mono_bitmap_to_screen_blt routine + * but allows the use of an arbitrary destination stride and alpha blending. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned long dstoffset, unsigned short width, + unsigned short height, unsigned char *data, short pitch) +#else +void gfx2_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned long dstoffset, unsigned short width, + unsigned short height, unsigned char *data, short pitch) +#endif +{ + unsigned long size, bytes; + unsigned long offset, temp_offset, temp1 = 0, temp2 = 0; + unsigned long i, j = 0, fifo_lines, dwords_extra, bytes_extra; + unsigned long shift = 0; + unsigned short blt_mode; + + size = (((unsigned long) width) << 16) | height; + + /* CALCULATE STARTING OFFSETS */ + + offset = (unsigned long) srcy * pitch + ((unsigned long)srcx >> 3); + + bytes = ((srcx & 7) + width + 7) >> 3; + fifo_lines = bytes >> 5; + dwords_extra = (bytes & 0x0000001Cl) >> 2; + bytes_extra = bytes & 0x00000003l; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + + GU2_WAIT_PENDING; + + if (gu2_alpha_active) + { + blt_mode = gu2_alpha_blt_mode; + + WRITE_GP32(MGP_RASTER_MODE, gu2_alpha32); + } + else + { + blt_mode = (gu2_blt_mode & ~MGP_BM_SRC_TYPE_MASK); + + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32 | GFXsourceFlags); + } + + WRITE_GP32(MGP_SRC_OFFSET, ((unsigned long) srcx & 7) << 26); + WRITE_GP32(MGP_DST_OFFSET, dstoffset | gu2_pattern_origin); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_dst_pitch); + WRITE_GP16(MGP_BLT_MODE, blt_mode | MGP_BM_SRC_HOST | + MGP_BM_SRC_MONO | gu2_bm_throttle); + gu2_bm_throttle = 0; + gu2_vm_throttle = 0; + + /* WAIT FOR BLT TO BE LATCHED */ + + GU2_WAIT_PENDING; + + /* WRITE ALL OF THE DATA TO THE HOST SOURCE REGISTER */ + + while (height--) + { + temp_offset = offset; + + /* WRITE ALL FULL FIFO LINES */ + + for (i = 0; i < fifo_lines; i++) + { + GU2_WAIT_HALF_EMPTY; + WRITE_GPREG_STRING32 (MGP_HST_SOURCE, 8, j, data, temp_offset, temp1); + temp_offset += 32; + } + + /* WRITE ALL FULL DWORDS */ + + GU2_WAIT_HALF_EMPTY; + if (dwords_extra) + WRITE_GPREG_STRING32 (MGP_HST_SOURCE, dwords_extra, i, data, temp_offset, temp1); + temp_offset += (dwords_extra << 2); + + /* WRITE REMAINING BYTES */ + + shift = 0; + if (bytes_extra) + WRITE_GPREG_STRING8 (MGP_HST_SOURCE, bytes_extra, shift, i, data, temp_offset, temp1, temp2); + + offset += pitch; + } +} + +/*--------------------------------------------------------------------------- + * GFX2_BRESENHAM_LINE + * + * This routine is similar to the gfx_bresenam_line routine but allows + * the use of an arbitrary destination stride. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_bresenham_line(unsigned long dstoffset, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags) +#else +void gfx2_bresenham_line(unsigned long dstoffset, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags) +#endif +{ + unsigned long vector_mode = gu2_vector_mode | flags; + unsigned long data1 = (((unsigned long) axialerr) << 16) | diagerr; + unsigned long data2 = (((unsigned long) length) << 16) | initerr; + + /* CHECK NULL LENGTH */ + + if (!length) return; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Put off poll for as long as possible (do most calculations first). */ + + GU2_WAIT_PENDING; + + if (gu2_alpha_active) + { + vector_mode = gu2_alpha_vec_mode | flags; + + WRITE_GP32(MGP_RASTER_MODE, gu2_alpha32); + } + else + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32); + + + WRITE_GP32(MGP_DST_OFFSET, dstoffset | gu2_pattern_origin); + WRITE_GP32(MGP_VEC_ERR, data1); + WRITE_GP32(MGP_VEC_LEN, data2); + WRITE_GP32(MGP_STRIDE, gu2_dst_pitch); + WRITE_GP32(MGP_VECTOR_MODE, vector_mode | gu2_vm_throttle); + gu2_bm_throttle = 0; + gu2_vm_throttle = 0; +} + +/*--------------------------------------------------------------------------- + * GFX2_SYNC_TO_VBLANK + * + * This routine sets a flag to synchronize the next rendering routine to + * VBLANK. The flag is cleared by the rendering routine. + *--------------------------------------------------------------------------- + */ +#if GFX_2DACCEL_DYNAMIC +void gu22_sync_to_vblank(void) +#else +void gfx2_sync_to_vblank(void) +#endif +{ + /* SET FLAGS TO THROTTLE NEXT RENDERING ROUTINE */ + + gu2_bm_throttle = MGP_BM_THROTTLE; + gu2_vm_throttle = MGP_VM_THROTTLE; +} + +/* END OF FILE */ + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/release.txt 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/release.txt 2004-04-05 16:09:22.000000000 -0600 @@ -0,0 +1,630 @@ +Durango Release Notes +Version 2.57.00 +Win98/WinXP/DOS/Linux +April 5, 2003 + +----------------------------------------------------------------------------- +PRODUCT INFORMATION +----------------------------------------------------------------------------- +Durango is a graphics/video software support package designed to assist in the +development of display drivers and embedded applications. The core of this +package is source code that performs most of the graphics related +functionality for the National Semiconductor ® Geode family of products. +Development time for new software is reduced by using these routines to access +the hardware. + +----------------------------------------------------------------------------- +INSTALLATION INSTRUCTIONS +----------------------------------------------------------------------------- +Download the file to a directory. Modify and include the file durango.c +according to the needs of the application. + +----------------------------------------------------------------------------- +REVISION HISTORY +----------------------------------------------------------------------------- + +04/05/04 Version 2.57.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Fixed the PLL setting for 1280x1024@70Hz and 1152x864@70Hz. + +============================================================================= + +03/30/04 Version 2.56.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Updated the GX2 render code such that BLTs that involve source will work + correctly even if source is not involved in the ROP. + +============================================================================= + +03/26/04 Version 2.55.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Filled in all missing refresh rates in the mode table for Redcloud and Castle. +* Added a new routine gfx_is_panel_mode_supported. +* Added new routines gfx_set_graphics_palette and gfx_set_graphics_palette_entry + to support using the video palette to gamma correct graphics data. + +============================================================================= + +03/11/04 Version 2.54.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Updated the video palette routines to clear the bypass both bit before + updating the palette. + +============================================================================= + +03/02/04 Version 2.53.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Added 1152x864@60, 85, 90 and 100Hz to the mode table. + +============================================================================= + +02/07/04 Version 2.52.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Updated Durango to support Castle, including a 48MHz dotref. +* Added 90 and 100Hz modes for Redcloud. +* Updated the PLL table to remove any pre-divides by 2. + +============================================================================= + +10/24/03 Version 2.51.08 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Removed GX2 1.0 support from the PLL routines, gfx_set_clock_frequency and + gfx_get_clock_frequency. +* Fixed a bug in gfx_set_clock_frequency, wherein the last three PLL values in + Durango's PLL table could never be set. + +============================================================================= + +09/22/03 Version 2.51.07 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Changed gfx_set_video_palette and gfx_set_video_palette_entry such that calling + one of these routines will also configure the video hardware to route video + data through the DF palette RAM. +* Added a new routine, gfx_set_video_palette_bypass to toggle the 'Bypass Both' + functionality of the SC1200 and GX2 palette RAMs. + +============================================================================= + +09/02/03 Version 2.51.06 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Added new routine gfx_get_max_video_width for SC1200 and CS5530. This routine + calculates the maximum theoretical video width based on the current display + mode and video clock. + +============================================================================= + +08/07/03 Version 2.51.05 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Fixed gfx_get_core_freq for SCx2xx when the fast PCI frequency is not 33MHz. +* Fixed gfx_get_compression_pitch to mask correct bits. +* Changed CS5530 and SCx2xx code to always enable video in the display + controller. +* Modified GX2 PLL code to only update the PLL when the value has not already + been programmed. + +============================================================================= + +06/17/03 Version 2.51.04 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Fixed code to set default gamma RAM for SCx2xx. + +============================================================================= + +06/02/03 Version 2.51.03 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Fixed gfx_get_cursor_position for GX2 to support large display resolutions. +* Added default gamma RAM table for SCx2xx and GX2 to correct CSC hardware. + +============================================================================= + +03/20/03 Version 2.51.02 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Changed all preprocessor statements to conform to K and R standard. +* Added support for 56Hz modes to all Durango routines. +* Added missing header file to gfx_priv.h + +============================================================================= + +03/13/03 Version 2.51.01 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Updated file headers to NSC standard headers. +* Added routine definitions for private and local routines. +* Minor fixes for compilation without warnings. +* Fixed panel timings for 640x480 panels and 1024x768 panels. + +============================================================================= + +02/05/03 Version 2.49.02 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Fixed GX2 left clipping for 4:2:0 video. + +============================================================================= + +01/29/03 Version 2.49.01 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Removed unused variable in CS5530 video code. +* Changed max supported pixel clock for SCx2xx to 157.5 MHz. + +============================================================================= + +01/10/03 Version 2.49.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Added extra wait loop when polling for CRC completion. +* Removed code that sets the pitch offsets for 4:2:0 video within + gfx_set_video_size. +* Fixed panning code to work with any display pitch. +* Added code to clear the PLL bypass bit when setting the dot PLL. +* Fixed panning code so cursor never disappears when panning. +* Changed GX2 delay loops to do a volatile register read to prevent + the entire delay loop from being discarded by a compiler. + +============================================================================= + +11/19/02 Version 2.47.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Updated gfx2_* routines to use a signed stride. +* SW workaround for issue #134.8 - Strange horizontal lines appearing while + drawing lines. +* Implemented gfx_set_video_left_crop for CS5530 +* Updated sub carrier reset values for NTSC and PAL. + +============================================================================= + +08/29/02 Version 2.45.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Modified gfx_set_cursor_position to use cursor position when panning and not adjust + using hotspots. +* Added new routine gfx_get_refreshrate_from_mode. +* Added gfx_text_blt routine. +* Added gfx_get_tv_display_mode_frequency routine. +* Added gfx_get_frequency_from_refreshrate routine. +* Added gfx_set_video_cursor_enable routine. +* Fixed Linux compilation warnings. +* Updated modeset code to clear panning variables. +* Added panel timings for 1600x1200 desktops. +* Removed wait for VBlank when panning using cursor routines. + +============================================================================= + +07/12/02 Version 2.43.03 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Modified gfx_get_display_mode to support 56 Hz modes. +* Added support for 8K pitch when setting a true color mode above 1024x768 +* Added a byte-packed option to gfx2_mono_expand_blt +* Fix for Carmel D2 alpha blending issue. +* Added typecasts for proper compilation. +* Fixed CS5535 MBIU address. +* Added new GX2 routine, gfx2_text_blt +* Added MSR implementations for Linux. +* Further optimized default GX1 string macros. +* Added new routine, gfx_set_panel_present to allow panning without adjusting panel timings. +* Added assembly macros for 32-bit Windows applications. + +============================================================================= + +03/21/02 Version 2.41.02 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Optimized GX2 Bitmap-to-screen BLTs by using a 2-line offscreen scratch area. +* Fixed a bug in GX2 monochrome bitmap BLTs. +* Fixed gfx_get_clock_frequency for GX2 2.0 +* Added 56 Hz support to gfx_get_clock_frequency +* Changed gfx_set_compression_size to subtract header size +* Changed gfx_get_compression_size to add header size + +============================================================================= + +03/04/02 Version 2.39.01 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Added support for CS5535 MSRs. +* Fixed a bug in monochrome bitmap BLTs. +* Added support for 32-bit CRC mechanism in GX2 2.0. +* First official GX2 release. +* Added support for new Dot PLL mechanism in GX2 2.0 +* Added support for Carmel D1.1 and D2. + +============================================================================= + +01/24/02 Version 2.37.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* Changed gfx_get_clock_frequency, gfx_get_cursor_offset and gfx_get_display_offset + to be outside the GFX_READ_ROUTINES flag. +* Modified the modeset code to set higher FIFO priority levels for high bandwidth + modes. +* Init code no longer returns Redcloud ID when no chip detected. +* Added fix for Redcloud 1.x rev ID +* New GX2 PLL settings - updates to the 14 MHz table and a new 48 MHz table. +* Optimized all bitmap-to-screen routines. Optimizations include new macros that + allow correct operation in a 16-bit environment. +* 3K cache is now assumed to be the default scratchpad configuration. +* gfx_get_frame_buffer_size for GX2 no longer uses a VGA register. This allows + correct operation even with an external VGA card present in the system. +* Added support for 1152x864 desktop resolution on a flat panel. +* Added 24BPP support for large display modes. +* Modified gfx_set_video_scale such that an identity scale is now default. +* Modifed flat panel modeset code to dynamically determine the size of the mode table. +* Added support for Carmel Rev D2. + +============================================================================= + +10/22/01 Version 2.35.01 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- + +* New release notes format. +* Added fix for SC1200 issue #813 (TVOut field indication is reversed. +* Added check for invalid values in video upscale. +* Fixed compilation warnings and run-time errors under DOS. +* Added new macros for word I/O. +* Optimized VSAII MSR code to used DWORD I/O. +* Fixed SoftVG base PCI base addresses. +* Several fixes to Redcloud API found during bringup. +* Modified Durango to support 4-pixel video alignment for Redcloud. +* Added the functions gfx_test_vip_overflow, gfx_get_vip_line, + gfx_set_decoder_luminance_filter, gfx_set_tv_YV_delya and + gfx_set_tv_field_status_invert. +* Added support for Carmel D1 revision ID. +* Moved gfx_get_vip_base and gfx_get_vbi_pitch outside of the + GXF_READ_ROUTINES flag. +* Minor fixes to saa7114.c and gfx_set_tv-enable. +* Added don't care option in gfx_set_vip_base. +* Added fix for SC1200 issue #1121 (VIP FIFO bus request threshold bit + is inverted. + +============================================================================= + +07/31/01 Version 2.33.02 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Completed implementation of vertical downscaling support for GX2. +* Added a method to lock the display controller timings. +* Added support for SC1200 Rev C. +* Small modifications to gfx_set_video_format. +* Removed unused and unimplemented I2C functions. +* Changes to prevent errors and compiler warnings in DOS. +* Updated headers to include both BSD and GPL licenses. + +============================================================================= + +06/08/01 Version 2.31.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Added new routines to manipulate vertical video downscaling on GX2. +* Minor fixes to the function gfx_read_window_crc. +* Implemented all init routines for GX2 except gfx_get_core_freq. +* Added support for 27MHz reference frequency to the GX2 PLL. +* Added new function gfx_get_softvga_active. +* Minor changes to the function sc1200_reset_video. +* Fixed some minor compiler warnings. + +============================================================================= + +04/25/01 Version 2.29.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Disabled all CSC when setting an RGB video format. +* Modified sc1200_set_video_size to add 2 to the window height. +* Modified code to support the accelerator and cursor in pixel and line double modes. +* Modified gfx_get_core_freq to be a dynamic API routine. +* Added the function gfx_read_window_crc for GX2. +* Added init routine gfx_get_graphics_register_base for GX2. +* Added new macros to access the scratchpad RAM to support Win2K and WinME. +* Added mew macros to access the GP registers for GX2. + +============================================================================= + +04/06/01 Version 2.27.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Added new TV read functions: + gfx_get_tv_enable, gfx_get_tv_output, gfx_get_tv_display_mode, + gfx_get_tv_mode_count, gfx_is_tv_display_mode_supported +* Added new function gfx_set_display_bpp. +* Added new function gfx_get_frame_buffer_line_size. +* Modified gfx_set_vbi_base to accept pure physical addresses instead of offsets. +* Implemented video and display controller routines for GX2. +* Modified some initialization routines to be dynamic. +* Created new API extension for GX2 MSR accesses. +* Added new icon routines for GX2. +* Modified gfx_set_tv_display to preserve current bpp. +* Minor modifications to gfx_set_tv_format, gfx_set_video_palette and + gfx_set_video_palette entry. +* Added support for 1152x864@75Hz + +============================================================================= + +03/12/01 Version 2.25.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Adapted new revision format system. +* Synchronized with NSTA Durango. Updated support for all SC1200 features. +* Added support for 640x400 as well as emulated VGA modes. +* Added new routines to access single palette color entries. +* Added new routine to return the maximum supported pixel clock. +* Added new routine gfx_set_crt_enable to manipulate the CRT display logic. +* Added new rendering routine gfx_color_pattern_fill. +* Added 4:2:0 and RGB video format support for CS5530 and SC1200. +* Modified code to allow operation under DOS. + +============================================================================= + +07/21/00 Version 2.04 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Verified Xfree86 driver version 1.1.4 under Linux, and ce v2.3. +* Merged sc1200 changes. +* Added routines to support the query of current display mode. +* Added functions gfx_enable_softvga, dfx_disable_softvga. +* Added code optimization in rendering loops to use 32 bit writes where possible. +* Added gfx_is_mode_supported to query if given mode supported by the h/w. +* Added Flat panel support, realy testing with panel done only for 800x600. +* Removed subtraction of 16 from gfx_set_compression_size. +* Added version.h file to reflect the version of the durango used. + +============================================================================= + +03/03/00 Version 2.01 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Verified Xfree86 driver version 1.1 under FreeBSD and Linux. +* Added automatic detection of BLT buffer bases in "gfx_set_bpp" routine. +* Fixed improper setting of VGA attrubute controller index register. +* Moved "gfx_get_display_bpp" to always be included. +* Moved "gfx_get_hactive" and "gfx_get_vactive" to always be included. +* Clipped video source size if off bottom or right side. +* Properly adjusted video offset if clipped on the top side. +* Added "gfx_get_video_line_size" and "gfx_get_video_xclip" routines. + +============================================================================= + +02/21/00 Version 2.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Added gfx_vga.c. +* Added write to GP_BLIT_STATUS in "gfx_set_bpp" routine. +* Verified alpha blending on SC1200. +* Removed "gfx_set_blt_buffers" routine. + +============================================================================= + +02/09/00 Version 1.20 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Verified display modes and graphics rendering on SC1200. +* Updated PLL table for SC1200 to set modes. +* DURANGO.C FILE CHANGE!: Modifed and added compiler definitions. +* Split gfx_disp.c file into gu1_disp.c and gu2_disp.c +* Split gfx_rndr.c file into gu1_rndr.c and gu2_rndr.c +* Split gfx_vid.c file into vid_5530.c, vid_1400.c, and vid_1200.c +* Split gfx_vip.c file into vip_1400.c and vip_1200.c +* Split gfx_tv.c file into geode_tv.c and fs451_tv.c +* Split gfx_i2c.c file into acc_i2c.c and gpio_i2c.c. +* Split gfx_dcdr.c file to saa7114.c +* Added GFX_READ_ROUTINES compiler definition. +* Moved routines from gfx_read.c (no longer exists) to other files. +* Abstracted display controller access in the video overlay routines. +* Added routines to control display compression hardware. + +============================================================================= + +01/28/00 Version 1.13 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Passes randomly generated rendering tests in Darwin for GXLV. +* Fixed bug for large bitmap to screen BLTs (greater than 64K). +* Fixed bug for pattern fills using solid source data for plane masks. + +============================================================================= + +01/14/00 Version 1.12 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Added proper use of hotspot to gfx_set_cursor_position. +* Fixed buffer size to handle all frame buffer start address alignments. +* Added initial version of gfx_tv.c. + +============================================================================= + +01/07/00 Version 1.11 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Fixed bug with transparent BLTs (loading transparent color into BB1). +* Added definition of gfx_color_bitmap_to_screen_blt to gfx_rtns.h. +* Added gfx_color_bitmap_to_screen_xblt (transparent bitmap to screen). + +============================================================================= + +12/21/99 Version 1.10 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Added additional video decoder routines to gfx_dcdr.c. +* Added VBI routines to gfx_vip.c. +* Added alpha blending routines for SC1200 to gfx_vid.c + +============================================================================= + +10/01/99 Version 1.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Added video port, video decoder, I2C, and hardware query rouines. +* New files: gfx_vip.c, gfx_dcdr.c, gfx_i2c.c, gfx_read.c. + +============================================================================= + +08/27/99 Version 0.05 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* INTERFACE CHANGE: Changed "gfx_csptr[]" to "gfx_vidptr" and "gfx_vipptr". +* Added "gfx_get_vid_register_base" and "gfx_get_vip_register_base". +* Added initial PLL table for SC1400. +* Verified mode set and video overlay routines work correctly on SC1400. +* Updated initilization routines. +* Added update of graphics engine in "gfx_set_display_pitch". + +============================================================================= + +08/20/99 Version 0.04 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* INTERFACE CHANGE: "gfx_load_*" routines changed to "gfx_set_*" for naming + consistency. The "gfx_text_glyph" routine was removed. +* Added video overlay routines. +* Added gfx_vid.c file. + +============================================================================= + +08/16/99 Version 0.03 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* INTERFACE CHANGE: Access to CS5530 now through separate pointer. Project + must declare and map the gfx_csptr[GFX_CSPTR_SIZE] variable. +* Added durango.c file as template for main source file. +* Added gfx_init.c file. + +============================================================================= + +08/04/99 Version 0.02 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Additional modes in gfx_mode.h file. +* Separated register definitions from gfx_defs.h into gfx_regs.h. + +============================================================================= + +07/30/99 Version 0.01 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +* Initial release. +----------------------------------------------------------------------------- + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/vga_gu1.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/vga_gu1.c 2005-12-14 11:29:07.000000000 -0700 @@ -0,0 +1,599 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to set modes using the VGA registers. + * Since this file is for the first generation graphics unit, it interfaces + * to SoftVGA registers. It works for both VSA1 and VSA2. + * */ + + + + +/* SoftVGA Extended CRTC register indices and bit definitions */ + +#define CRTC_EXTENDED_REGISTER_LOCK 0x30 +#define CRTC_MODE_SWITCH_CONTROL 0x3F + +/* BIT DEFINITIONS */ + +#define CRTC_BIT_16BPP 0x01 +#define CRTC_BIT_555 0x02 + +/* LOCAL ROUTINE DEFINITIONS */ + +int gu1_detect_vsa2(void); + +/*---------------------------------*/ +/* MODE TABLES FOR VGA REGISTERS */ +/*---------------------------------*/ + +/* FOR SoftVGA, the CRTC_EXTENDED_ADDRESS_CONTROL (0x43) is always equal to + * 0x03 for a packed linear frame buffer organization. The + * CRTC_EXTENDED_DAC_CONTROL (0x4B) is always equal to 0x03 to work with + * older versions of VSA1 (that needed to specify 8 or 16 bit bus to an + * external RAMDAC. This is not used in VSA2. The clock frequency is + * specified in register 0x4D if clock control (0x4C) is set to 0x80. + * Higher resolutions (1280x1024) use the CRTC_EXTENDED_VERTICAL_TIMING + * register (index 0x41). + */ + +gfx_vga_struct gfx_vga_modes[] = +{ +/*------------------------------------------------------------------------------*/ + { 640, 480, 60, /* 640x480 */ + 25, /* 25 MHz clock = 60 Hz refresh rate */ + 0xE3, /* miscOutput register */ + { 0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0x0B, 0x3E, /* standard CRTC */ + 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xEA, 0x0C, 0xDF, 0x50, 0x00, 0xE7, 0x04, 0xE3, 0xFF }, + { 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, /* extended CRTC */ + 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00 } }, +/*------------------------------------------------------------------------------*/ + { 640, 480, 72, /* 640x480 */ + 29, /* 29 MHz clock = 72 Hz refresh rate */ + 0xE3, /* miscOutput register */ + { 0x63, 0x4f, 0x50, 0x86, 0x55, 0x99, 0x06, 0x3e, /* standard CRTC */ + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe9, 0x0c, 0xdf, 0x00, 0x00, 0xe7, 0x00, 0xe3, 0xff }, + { 0x6D, 0x00, 0x00, 0x03, 0x00, 0x01, 0x01, 0x00, /* extended CRTC */ + 0x00, 0x00, 0x01, 0x08, 0x80, 0x1F, 0x00, 0x4B } }, +/*------------------------------------------------------------------------------*/ + { 640, 480, 75, /* 640x480 */ + 31, /* 31.5 MHz clock = 75 Hz refresh rate */ + 0xE3, /* miscOutput register */ + { 0x64, 0x4F, 0x4F, 0x88, 0x54, 0x9B, 0xF2, 0x1F, /* standard CRTC */ + 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xE1, 0x04, 0xDF, 0x50, 0x00, 0xDF, 0xF3, 0xE3, 0xFF }, + { 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, /* extended CRTC */ + 0x00, 0x00, 0x00, 0x03, 0x80, 0x1F, 0x00, 0x00 } }, +/*------------------------------------------------------------------------------*/ + { 800, 600, 60, /* 800x600 */ + 40, /* 40 MHz clock = 60 Hz refresh rate */ + 0x23, /* miscOutput register */ + { 0x7F, 0x63, 0x64, 0x82, 0x6B, 0x1B, 0x72, 0xF0, /* standard CRTC */ + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x59, 0x0D, 0x57, 0x64, 0x00, 0x57, 0x73, 0xE3, 0xFF }, + { 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, /* extended CRTC */ + 0x00, 0x00, 0x00, 0x03, 0x80, 0x28, 0x00, 0x00 } }, +/*------------------------------------------------------------------------------*/ + { 800, 600, 72, /* 800x600 */ + 47, /* 47 MHz clock = 72 Hz refresh rate */ + 0x2B, /* miscOutput register */ + { 0x7D, 0x63, 0x63, 0x81, 0x6D, 0x1B, 0x98, 0xF0, /* standard CRTC */ + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x7D, 0x03, 0x57, 0x00, 0x00, 0x57, 0x9A, 0xE3, 0xFF }, + { 0x6F, 0x00, 0x00, 0x03, 0x00, 0x01, 0x01, 0x00, /* extended CRTC */ + 0x00, 0x00, 0x01, 0x08, 0x80, 0x32, 0x00, 0x4B } }, +/*------------------------------------------------------------------------------*/ + { 800, 600, 75, /* 800x600 */ + 49, /* 49.5 MHz clock = 75 Hz refresh rate */ + 0x23, /* miscOutput register */ + { 0x7F, 0x63, 0x63, 0x83, 0x68, 0x11, 0x6F, 0xF0, /* standard CRTC */ + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x59, 0x1C, 0x57, 0x64, 0x00, 0x57, 0x70, 0xE3, 0xFF }, + { 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, /* extended CRTC */ + 0x00, 0x00, 0x00, 0x03, 0x80, 0x31, 0x00, 0x00 } }, +/*------------------------------------------------------------------------------*/ + { 1024, 768, 60, /* 1024x768 */ + 65, /* 65 MHz clock = 60 Hz refresh rate */ + 0xE3, /* miscOutput register */ + { 0xA3, 0x7F, 0x80, 0x86, 0x85, 0x96, 0x24, 0xF5, /* standard CRTC */ + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x0A, 0xFF, 0x80, 0x00, 0xFF, 0x25, 0xE3, 0xFF }, + { 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, /* extended CRTC */ + 0x00, 0x00, 0x00, 0x03, 0x80, 0x41, 0x00, 0x00 } }, +/*------------------------------------------------------------------------------*/ + { 1024, 768, 70, /* 1024x768 */ + 76, /* 76 MHz clock = 70 Hz refresh rate */ + 0x2B, /* miscOutput register */ + { 0xA1, 0x7F, 0x7F, 0x85, 0x85, 0x95, 0x24, 0xF5, /* standard CRTC */ + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x09, 0xFF, 0x00, 0x00, 0xFF, 0x26, 0xE3, 0xFF }, + { 0x62, 0x00, 0x00, 0x03, 0x00, 0x01, 0x01, 0x00, /* extended CRTC */ + 0x00, 0x00, 0x01, 0x02, 0x80, 0x4B, 0x00, 0x4B } }, +/*------------------------------------------------------------------------------*/ + { 1024, 768, 75, /* 1024x768 */ + 79, /* 79 MHz clock = 75 Hz refresh rate */ + 0xE3, /* miscOutput register */ + { 0x9F, 0x7F, 0x7F, 0x83, 0x84, 0x8F, 0x1E, 0xF5, /* standard CRTC */ + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x04, 0xFF, 0x80, 0x00, 0xFF, 0x1F, 0xE3, 0xFF }, + { 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, /* extended CRTC */ + 0x00, 0x00, 0x00, 0x03, 0x80, 0x4F, 0x00, 0x00 } }, +/*------------------------------------------------------------------------------*/ + { 1280, 1024, 60, /* 1280x1024 */ + 108, /* 108 MHz clock = 60 Hz refresh rate */ + 0x23, /* miscOutput register */ + { 0xCF, 0x9F, 0xA0, 0x92, 0xAA, 0x19, 0x28, 0x52, /* standard CRTC */ + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x04, 0xFF, 0xA0, 0x00, 0x00, 0x29, 0xE3, 0xFF }, + { 0x00, 0x51, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, /* extended CRTC */ + 0x00, 0x00, 0x00, 0x03, 0x80, 0x6C, 0x00, 0x00 } }, +/*------------------------------------------------------------------------------*/ + { 1280, 1024, 75, /* 1280x1024 */ + 135, /* 135 MHz clock = 75 Hz refresh rate */ + 0x23, /* miscOutput register */ + { 0xCE, 0x9F, 0x9F, 0x92, 0xA4, 0x15, 0x28, 0x52, /* standard CRTC */ + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x04, 0xFF, 0xA0, 0x00, 0x00, 0x29, 0xE3, 0xFF }, + { 0x00, 0x51, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, /* extended CRTC */ + 0x00, 0x00, 0x00, 0x03, 0x80, 0x87, 0x00, 0x00 } }, +/*------------------------------------------------------------------------------*/ + { 1280, 1024, 85, /* 1280x1024 */ + 159, /* 159 MHz clock = 85 Hz refresh rate */ + 0x2B, /* miscOutput register */ + { 0xD3, 0x9F, 0xA0, 0x98, 0xA8, 0x9C, 0x2E, 0x5A, /* standard CRTC */ + 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x04, 0xFF, 0x00, 0x00, 0xFF, 0x30, 0xE3, 0xFF }, + { 0x6B, 0x41, 0x00, 0x03, 0x00, 0x01, 0x00, 0x00, /* extended CRTC */ + 0x00, 0x00, 0x01, 0x00, 0x80, 0x9D, 0x00, 0x4B } }, + +/*------------------------------------------------------------------------------*/ +}; + +#define GFX_VGA_MODES sizeof(gfx_vga_modes)/sizeof(gfx_vga_struct) + +/*----------------------------------------------------------------------------- + * gfx_get_softvga_active + * + * This returns the active status of SoftVGA + *----------------------------------------------------------------------------- + */ +int gfx_get_softvga_active(void) +{ + unsigned short crtcindex, crtcdata; + + if(gu1_detect_vsa2()) + return(gfx_get_vsa2_softvga_enable()); + + crtcindex = (INB(0x3CC) & 0x01) ? 0x3D4 : 0x3B4; + crtcdata = crtcindex + 1; + + OUTB(crtcindex, CRTC_MODE_SWITCH_CONTROL); + return(INB(crtcdata) & 0x1); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_test_pci + * + * This routine looks for the VGA PCI header. It checks to see that bit 1 + * of the command register is writable to know that SoftVGA is trapping + * the PCI config cuscles. If SoftVGA is not emulating the header, the + * hardware will still respond with the proper device ID, etc. + * + * We need to know that SoftVGA is really there so that we can set the + * command register and have the proper effect (enable trapping of VGA). + * Otherwise, if we enable VGA via the PCI header, trapping really won't be + * enabled and the VGA register writes will go out to the external card. + *----------------------------------------------------------------------------- + */ +int gfx_vga_test_pci(void) +{ + int softvga = 1; + unsigned long value; + value = gfx_pci_config_read(0x80009400); + if ((value & 0x0000FFFF) != 0x1078) softvga = 0; + else + { + value = gfx_pci_config_read(0x80009404); + gfx_pci_config_write(0x80009404, value | 0x02); + if (!(gfx_pci_config_read(0x80009404) & 0x02)) softvga = 0; + gfx_pci_config_write(0x80009404, value); + } + return(softvga); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_get_pci_command + * + * This routine returns the value of the PCI command register. + *----------------------------------------------------------------------------- + */ +unsigned char gfx_vga_get_pci_command(void) +{ + unsigned long value; + value = gfx_pci_config_read(0x80009404); + return((unsigned char) value); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_set_pci_command + * + * This routine writes the value of the PCI command register. It is used + * to enable or disable SoftVGA. + * + * Bit 0: Enable VGA IO + * Bit 1: Enable VGA memory + *----------------------------------------------------------------------------- + */ +int gfx_vga_set_pci_command(unsigned char command) +{ + unsigned long value; + value = gfx_pci_config_read(0x80009404) & 0xFFFFFF00; + value |= (unsigned long) command; + gfx_pci_config_write(0x80009404, value); + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_seq_reset + * + * This routine enables or disables SoftVGA. It is used to make SoftVGA + * "be quiet" and not interfere with any of the direct hardware access from + * Durango. For VSA1, the sequencer is reset to stop text redraws. VSA2 may + * provide a better way to have SoftVGA sit in the background. + *----------------------------------------------------------------------------- + */ +int gfx_vga_seq_reset(int reset) +{ + OUTB(0x3C4, 0); + OUTB(0x3C5, (unsigned char) (reset ? 0x00 : 0x03)); + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_set_graphics_bits + * + * This routine sets the standard VGA sequencer, graphics controller, and + * attribute registers to appropriate values for a graphics mode (packed, + * 8 BPP or greater). This is also known as "VESA" modes. The timings for + * a particular mode are handled by the CRTC registers, which are set by + * the "gfx_vga_restore" routine. Most OSs that use VGA to set modes save + * and restore the standard VGA registers themselves, which is why these + * registers are not part of the save/restore paradigm. + *----------------------------------------------------------------------------- + */ +int gfx_vga_set_graphics_bits(void) +{ + /* SET GRAPHICS BIT IN GRAPHICS CONTROLLER REG 0x06 */ + + OUTB(0x3CE, 0x06); + OUTB(0x3CF, 0x01); + + /* SET GRAPHICS BIT IN ATTRIBUTE CONTROLLER REG 0x10 */ + + INB(0x3BA); /* Reset flip-flop */ + INB(0x3DA); + OUTB(0x3C0, 0x10); + OUTB(0x3C0, 0x01); + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_mode + * + * This routine searches the VGA mode table for a match of the specified + * mode and then fills in the VGA structure with the associated VGA register + * values. The "gfx_vga_restore" routine can then be called to actually + * set the mode. + *----------------------------------------------------------------------------- + */ +int gfx_vga_mode(gfx_vga_struct *vga, int xres, int yres, int bpp, int hz) +{ + unsigned int i; + unsigned short pitch; + for (i = 0; i < GFX_VGA_MODES; i++) + { + if ((gfx_vga_modes[i].xsize == xres) && + (gfx_vga_modes[i].ysize == yres) && + (gfx_vga_modes[i].hz == hz)) + { + /* COPY ENTIRE STRUCTURE FROM THE TABLE */ + + *vga = gfx_vga_modes[i]; + + /* SET PITCH TO 1K OR 2K */ + /* CRTC_EXTENDED_OFFSET index is 0x45, so offset = 0x05 */ + + pitch = (unsigned short) xres; + if (bpp > 8) pitch <<= 1; + if (pitch <= 1024) pitch = 1024 >> 3; + else pitch = 2048 >> 3; + vga->stdCRTCregs[0x13] = (unsigned char) pitch; + vga->extCRTCregs[0x05] = (unsigned char)((pitch >> 8) & 0x03); + + /* SET PROPER COLOR DEPTH VALUE */ + /* CRTC_EXTENDED_COLOR_CONTROL index is 0x46, so offset = 0x06 */ + + switch(bpp) + { + case 15: + vga->extCRTCregs[0x06] = CRTC_BIT_16BPP | CRTC_BIT_555; + break; + case 16: + vga->extCRTCregs[0x06] = CRTC_BIT_16BPP; + break; + default: + vga->extCRTCregs[0x06] = 0; + break; + } + return(GFX_STATUS_OK); + } + } + return(GFX_STATUS_UNSUPPORTED); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_pitch + * + * This routine updates the VGA regisers in the specified VGA structure for + * the specified pitch. It does not program the hardware. + *----------------------------------------------------------------------------- + */ +int gfx_vga_pitch(gfx_vga_struct *vga, unsigned short pitch) +{ + pitch >>= 3; + vga->stdCRTCregs[0x13] = (unsigned char) pitch; + vga->extCRTCregs[0x05] = (unsigned char)((pitch >> 8) & 0x03); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_save + * + * This routine saves the state of the VGA registers into the specified + * structure. Flags indicate what portions of the register state need to + * be saved. + *----------------------------------------------------------------------------- + */ +int gfx_vga_save(gfx_vga_struct *vga, int flags) +{ + int i; + unsigned short crtcindex, crtcdata; + crtcindex = (INB(0x3CC) & 0x01) ? 0x3D4 : 0x3B4; + crtcdata = crtcindex + 1; + + /* CHECK MISCELLANEOUS OUTPUT FLAG */ + + if (flags & GFX_VGA_FLAG_MISC_OUTPUT) + { + /* SAVE MISCCELLANEOUS OUTPUT REGISTER */ + + vga->miscOutput = INB(0x3CC); + } + + /* CHECK STANDARD CRTC FLAG */ + + if (flags & GFX_VGA_FLAG_STD_CRTC) + { + /* SAVE STANDARD CRTC REGISTERS */ + + for (i = 0; i < GFX_STD_CRTC_REGS; i++) + { + OUTB(crtcindex, (unsigned char) i); + vga->stdCRTCregs[i] = INB(crtcdata); + } + } + + /* CHECK EXTENDED CRTC FLAG */ + + if (flags & GFX_VGA_FLAG_EXT_CRTC) + { + /* SAVE EXTENDED CRTC REGISTERS */ + + for (i = 0; i < GFX_EXT_CRTC_REGS; i++) + { + OUTB(crtcindex, (unsigned char) (0x40+i)); + vga->extCRTCregs[i] = INB(crtcdata); + } + } + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_clear_extended + * + * This routine clears the extended SoftVGA register values to have SoftVGA + * behave like standard VGA. + *----------------------------------------------------------------------------- + */ +void gfx_vga_clear_extended(void) +{ + int i; + unsigned short crtcindex, crtcdata; + crtcindex = (INB(0x3CC) & 0x01) ? 0x3D4 : 0x3B4; + crtcdata = crtcindex + 1; + + OUTB(crtcindex, 0x30); + OUTB(crtcdata, 0x57); + OUTB(crtcdata, 0x4C); + for (i = 0x40; i <= 0x4F; i++) + { + OUTB(crtcindex, (unsigned char) i); + OUTB(crtcdata, 0); + } + OUTB(crtcindex, 0x30); + OUTB(crtcdata, 0x00); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_restore + * + * This routine restores the state of the VGA registers from the specified + * structure. Flags indicate what portions of the register state need to + * be saved. + *----------------------------------------------------------------------------- + */ +int gfx_vga_restore(gfx_vga_struct *vga, int flags) +{ + int i; + unsigned short crtcindex, crtcdata; + crtcindex = (INB(0x3CC) & 0x01) ? 0x3D4 : 0x3B4; + crtcdata = crtcindex + 1; + + /* CHECK MISCELLANEOUS OUTPUT FLAG */ + + if (flags & GFX_VGA_FLAG_MISC_OUTPUT) + { + /* RESTORE MISCELLANEOUS OUTPUT REGISTER VALUE */ + + OUTB(0x3C2, vga->miscOutput); + } + + /* CHECK STANDARD CRTC FLAG */ + + if (flags & GFX_VGA_FLAG_STD_CRTC) + { + /* UNLOCK STANDARD CRTC REGISTERS */ + + OUTB(crtcindex, 0x11); + OUTB(crtcdata, 0); + + /* RESTORE STANDARD CRTC REGISTERS */ + + for (i = 0; i < GFX_STD_CRTC_REGS; i++) + { + OUTB(crtcindex, (unsigned char) i); + OUTB(crtcdata, vga->stdCRTCregs[i]); + } + } + + /* CHECK EXTENDED CRTC FLAG */ + + if (flags & GFX_VGA_FLAG_EXT_CRTC) + { + /* UNLOCK EXTENDED CRTC REGISTERS */ + + OUTB(crtcindex, 0x30); + OUTB(crtcdata, 0x57); + OUTB(crtcdata, 0x4C); + + /* RESTORE EXTENDED CRTC REGISTERS */ + + for (i = 0; i < GFX_EXT_CRTC_REGS; i++) + { + OUTB(crtcindex, (unsigned char) (0x40+i)); + OUTB(crtcdata, vga->extCRTCregs[i]); + } + + /* LOCK EXTENDED CRTC REGISTERS */ + + OUTB(crtcindex, 0x30); + OUTB(crtcdata, 0x00); + + /* CHECK IF DIRECT FRAME BUFFER MODE (VESA MODE) */ + + if (vga->extCRTCregs[0x03] & 1) + { + /* SET BORDER COLOR TO BLACK */ + /* This really should be another thing saved/restored, but */ + /* Durango currently doesn't do the attr controller registers. */ + + INB(0x3BA); /* Reset flip-flop */ + INB(0x3DA); + OUTB(0x3C0, 0x11); + OUTB(0x3C0, 0x00); + } + } + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_mode_switch + * + * This routine programs the SoftVGA register to indicate that a mode switch + * is in progress. This results in a cleaner mode switch since SoftVGA will + * not validate the hardware with intermediate values. + *----------------------------------------------------------------------------- + */ +int gfx_vga_mode_switch(int active) +{ + unsigned short crtcindex, crtcdata; + crtcindex = (INB(0x3CC) & 0x01) ? 0x3D4 : 0x3B4; + crtcdata = crtcindex + 1; + + /* UNLOCK EXTENDED CRTC REGISTERS */ + + OUTB(crtcindex, CRTC_EXTENDED_REGISTER_LOCK); + OUTB(crtcdata, 0x57); + OUTB(crtcdata, 0x4C); + + /* SIGNAL THE BEGINNING OR END OF THE MODE SWITCH */ + /* SoftVGA will hold off validating the back end hardware. */ + + OUTB(crtcindex, CRTC_MODE_SWITCH_CONTROL); + active = active ? 1 : 0; + OUTB(crtcdata, (unsigned char) active); + + /* WAIT UNTIL SOFTVGA HAS VALIDATED MODE IF ENDING MODE SWITCH */ + /* This is for VSA1 only, where SoftVGA waits until the next */ + /* vertical blank to validate the hardware state. */ + + if ((!active) && (!(gu1_detect_vsa2()))) + { + OUTB(crtcindex, 0x33); + while(INB(crtcdata) & 0x80); + } + + /* LOCK EXTENDED CRTC REGISTERS */ + + OUTB(crtcindex, CRTC_EXTENDED_REGISTER_LOCK); + OUTB(crtcdata, 0x00); + return(0); +} + +/*----------------------------------------------------------------------------- + * gu1_detect_vsa2 + * + * This routine detects if VSA2 is present. The interface to SoftVGA + * changed slightly. + *----------------------------------------------------------------------------- + */ +int gu1_detect_vsa2(void) +{ + unsigned short crtcindex, crtcdata; + crtcindex = (INB(0x3CC) & 0x01) ? 0x3D4 : 0x3B4; + crtcdata = crtcindex + 1; + OUTB(crtcindex, 0x35); + if (INB(crtcdata) != 'C') return(0); + OUTB(crtcindex, 0x36); + if (INB(crtcdata) != 'X') return(0); + return(1); +} + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_init.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_init.c 2005-12-14 11:36:07.000000000 -0700 @@ -0,0 +1,747 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines typically used in driver initialization. + * + * Routines: + * + * gfx_pci_config_read + * gfx_cpu_config_read + * gfx_detect_cpu + * gfx_detect_video + * gfx_get_cpu_register_base + * gfx_get_frame_buffer_base + * gfx_get_frame_buffer_size + * gfx_get_vid_register_base + * gfx_get_vip_register_base + * */ + + + +/* CONSTANTS USED BY THE INITIALIZATION CODE */ + +#define PCI_CONFIG_ADDR 0x0CF8 +#define PCI_CONFIG_DATA 0x0CFC +#define PCI_VENDOR_DEVICE_GXM 0x00011078 +#define PCI_VENDOR_DEVICE_REDCLOUD 0x0028100B +#define REDCLOUD_VIDEO_PCI_VENDOR_DEVICE 0x0030100B +#define PCI_VENDOR_DEVICE_CASTLE 0x20801022 +#define CASTLE_VIDEO_PCI_VENDOR_DEVICE 0x20811022 + +#define GXM_CONFIG_GCR 0xB8 +#define GXM_CONFIG_CCR3 0xC3 +#define GXM_CONFIG_DIR0 0xFE +#define GXM_CONFIG_DIR1 0xFF + +/* STATIC VARIABLES FOR THIS FILE */ + +unsigned long gfx_cpu_version = 0; +unsigned long gfx_cpu_frequency = 0; +unsigned long gfx_vid_version = 0; +unsigned long gfx_gx1_scratch_base = 0; +unsigned long gfx_gx2_scratch_base = 0x7FC000; +unsigned long gfx_pci_speed_khz = 33300; +ChipType gfx_chip_revision = CHIP_NOT_DETECTED; + +ChipType gfx_detect_chip(void); + +/* INCLUDE SUPPORT FOR FIRST GENERATION, IF SPECIFIED. */ + +#if GFX_INIT_GU1 +#include "init_gu1.c" +#endif + +/* INCLUDE SUPPORT FOR SECOND GENERATION, IF SPECIFIED. */ + +#if GFX_INIT_GU2 +#include "init_gu2.c" +#endif + +/* INCLUDE SUPPORT FOR THIRD GENERATION, IF SPECIFIED. */ + +#if GFX_INIT_GU3 +#include "init_gu3.c" +#endif + +/* THE FOLLOWING ROUTINES ARE NEVER DYNAMIC */ +/* They are used to set the variables for future dynamic */ +/* function calls. */ + +/*----------------------------------------------------------------------------- + * gfx_detect_chip + * + * This routine returns the name and revision of the chip. This function is only + * relevant to the SC1200. + *----------------------------------------------------------------------------- + */ +ChipType gfx_detect_chip(void) +{ + unsigned char pid = INB(SC1200_CB_BASE_ADDR + SC1200_CB_PID); + unsigned char rev = INB(SC1200_CB_BASE_ADDR + SC1200_CB_REV); + unsigned short clk = INW(SC1200_CB_BASE_ADDR + SC1200_CB_CCFC); + + gfx_chip_revision = CHIP_NOT_DETECTED; + + if (pid == 0x4) + { + switch (rev) + { + case 0: + gfx_chip_revision = SC1200_REV_A; + break; + case 1: + gfx_chip_revision = SC1200_REV_B1_B2; + break; + case 2: + gfx_chip_revision = SC1200_REV_B3; + break; + case 3: + gfx_chip_revision = SC1200_REV_C1; + break; + case 4: + gfx_chip_revision = SC1200_REV_D1; + break; + case 5: + gfx_chip_revision = SC1200_REV_D1_1; + break; + case 6: + gfx_chip_revision = SC1200_REV_D2_MVD; + break; + } + if (rev > 0x6) + gfx_chip_revision = SC1200_FUTURE_REV; + } + else if (pid == 0x5) + { + if (rev == 0x6) + gfx_chip_revision = SC1200_REV_D2_MVE; + else if (rev > 0x6) + gfx_chip_revision = SC1200_FUTURE_REV; + } + + switch ((clk >> 8) & 3) + { + case 0: + default: gfx_pci_speed_khz = 33300; break; + case 1: gfx_pci_speed_khz = 48000; break; + case 2: gfx_pci_speed_khz = 66600; break; + } + + return(gfx_chip_revision); +} + +/*----------------------------------------------------------------------------- + * gfx_detect_cpu + * + * This routine returns the type and revison of the CPU. If a Geode + * processor is not present, the routine returns zero. + * + * The return value is as follows: + * bits[24:16] = minor version + * bits[15:8] = major version + * bits[7:0] = type (1 = GXm, 2 = SC1200, 3 = Redcloud) + * + * A return value of 0x00020501, for example, indicates GXm version 5.2. + *----------------------------------------------------------------------------- + */ +unsigned long gfx_detect_cpu(void) +{ + + unsigned long value = 0; + unsigned long version = 0; + + /* initialize core freq. to 0 */ + gfx_cpu_frequency = 0; + +#if GFX_INIT_GU1 + + value = gfx_pci_config_read(0x80000000); + + if (value == PCI_VENDOR_DEVICE_GXM) + { + unsigned char dir0 = gfx_gxm_config_read(GXM_CONFIG_DIR0) & 0xF0; + unsigned char dir1 = gfx_gxm_config_read(GXM_CONFIG_DIR1); + + if (dir0 == 0x40) + { + /* CHECK FOR GXLV (and GXm) (DIR1 = 0x30 THROUGH 0x82) */ + + if ((dir1 >= 0x30) && (dir1 <= 0x82)) + { + /* Major version is one less than what appears in DIR1 */ + if( (dir1&0xF0)<0x70){ + + version = GFX_CPU_GXLV | + + ((( ( (unsigned long) dir1 >> 4)-1 ) << 8) ) | /* major - 1 */ + + ((((unsigned long) dir1 & 0x0F)) << 16); /* minor */ + } + else{ + version = GFX_CPU_GXLV | + ((((unsigned long) dir1 >> 4) ) << 8) | /* major */ + ((((unsigned long) dir1 & 0x0F)) << 16); /* minor */ + + } + /* Currently always CS5530 for video overlay. */ + +#if GFX_VIDEO_DYNAMIC + gfx_video_type = GFX_VIDEO_TYPE_CS5530; +#endif + + /* Currently always CS5530 GPIOs for I2C access. */ + +#if GFX_I2C_DYNAMIC + gfx_i2c_type = GFX_I2C_TYPE_GPIO; +#endif + +#if GFX_TV_DYNAMIC + gfx_tv_type = GFX_TV_TYPE_FS451; +#endif + } + } + else if (dir0 == 0xB0) + { + /* CHECK FOR SC1200 */ + + if ((dir1 == 0x70) || (dir1 == 0x81)) + { + version = GFX_CPU_SC1200 | + ((((unsigned long) dir1 >> 4) ) << 8) | /* major */ + ((((unsigned long) dir1 & 0x0F)) << 16); /* minor */ + + /* Detect SC1200 revision */ + + gfx_detect_chip(); + + /* SC1200 for video overlay and VIP. */ + +#if GFX_VIDEO_DYNAMIC + gfx_video_type = GFX_VIDEO_TYPE_SC1200; +#endif + +#if GFX_VIP_DYNAMIC + gfx_vip_type = GFX_VIP_TYPE_SC1200; +#endif + + /* Currently always SAA7114 decoder. */ + +#if GFX_DECODER_DYNAMIC + gfx_decoder_type = GFX_DECODER_TYPE_SAA7114; +#endif + + /* SC1200 for TV encoder */ + +#if GFX_TV_DYNAMIC + gfx_tv_type = GFX_TV_TYPE_SC1200; +#endif + + /* Currently always ACCESS.bus for I2C access. */ + +#if GFX_I2C_DYNAMIC + gfx_i2c_type = GFX_I2C_TYPE_ACCESS; +#endif + } + } + + if (version ) + { + /* ALWAYS FIRST GENERATION GRAPHICS UNIT */ + +#if GFX_DISPLAY_DYNAMIC + gfx_display_type = GFX_DISPLAY_TYPE_GU1; +#endif +#if GFX_2DACCEL_DYNAMIC + gfx_2daccel_type = GFX_2DACCEL_TYPE_GU1; +#endif +#if GFX_INIT_DYNAMIC + gfx_init_type = GFX_INIT_TYPE_GU1; +#endif + + /* READ THE CORE FREQUENCY */ + + gfx_cpu_frequency = gfx_get_core_freq(); + } + } + +#endif + +#if GFX_INIT_GU2 + + value = gfx_pci_config_read(0x80000800); + + if (value == PCI_VENDOR_DEVICE_REDCLOUD) + { + Q_WORD msr_value; + int valid, i; + + /* CHECK FOR SOFT VG */ + /* If SoftVG is not present, the base addresses for all devices */ + /* will not be allocated. Essentially, it is as if no Redcloud */ + /* video hardware is present. */ + + value = gfx_pci_config_read (0x80000900); + + if (value == REDCLOUD_VIDEO_PCI_VENDOR_DEVICE) + { + valid = 1; + + /* BAR0 - BAR3 HOLD THE PERIPHERAL BASE ADDRESSES */ + + for (i = 0; i < 4; i++) + { + value = gfx_pci_config_read (0x80000910 + (i << 2)); + if (value == 0x00000000 || value == 0xFFFFFFFF) + { + valid = 0; + break; + } + } + + if (valid) + { + /* REDCLOUD INTEGRATED VIDEO */ + +#if GFX_VIDEO_DYNAMIC + gfx_video_type = GFX_VIDEO_TYPE_REDCLOUD; +#endif + + /* CURRENTLY, ALWAYS GPIO FOR I2C ACCESS */ + +#if GFX_I2C_DYNAMIC + gfx_i2c_type = GFX_I2C_TYPE_GPIO; +#endif + + /* SECOND-GENERATION DISPLAY CONTROLLER */ + +#if GFX_DISPLAY_DYNAMIC + gfx_display_type = GFX_DISPLAY_TYPE_GU2; +#endif + + /* SECOND-GENERATION GRAPHICS UNIT */ + +#if GFX_2DACCEL_DYNAMIC + gfx_2daccel_type = GFX_2DACCEL_TYPE_GU2; +#endif + + /* SECOND-GENERATION INITIALIZATION */ + +#if GFX_INIT_DYNAMIC + gfx_init_type = GFX_INIT_TYPE_GU2; +#endif + + /* MBUS MSR ACCESSES */ + +#if GFX_MSR_DYNAMIC + gfx_msr_type = GFX_MSR_TYPE_REDCLOUD; +#endif + + /* CS5530 GPIO I2C */ + +#if GFX_I2C_DYNAMIC + gfx_i2c_type = GFX_I2C_TYPE_GPIO; +#endif + + /* READ VERSION */ + + gfx_msr_init(); + + gfx_msr_read (RC_ID_MCP, MCP_RC_REVID, &msr_value); + + /* SUBTRACT 1 FROM REV ID */ + /* REDCLOUD 1.X rev id is 1 less than the reported value */ + + if ((msr_value.low & 0xF0) == 0x10) + msr_value.low--; + + version = GFX_CPU_REDCLOUD | + ((msr_value.low & 0xF0) << 4) | /* MAJOR */ + ((msr_value.low & 0x0F) << 16); /* MINOR */ + + /* READ THE CORE FREQUENCY */ + + gfx_cpu_frequency = gfx_get_core_freq(); + + /* SET THE GP SCRATCH AREA */ + /* Color bitmap BLTs use the last 16K of frame buffer space */ + + gfx_gx2_scratch_base = gfx_get_frame_buffer_size() - 0x4000; + } + } + } + +#endif + +#if GFX_INIT_GU3 + + value = gfx_pci_config_read(0x80000800); + + if (value == PCI_VENDOR_DEVICE_CASTLE) + { + Q_WORD msr_value; + int valid, i; + + /* CHECK FOR SOFT VG */ + /* If SoftVG is not present, the base addresses for all devices */ + /* will not be allocated. Essentially, it is as if no Redcloud */ + /* video hardware is present. */ + + value = gfx_pci_config_read (0x80000900); + + if (value == CASTLE_VIDEO_PCI_VENDOR_DEVICE) + { + valid = 1; + + /* BAR0 - BAR3 HOLD THE PERIPHERAL BASE ADDRESSES */ + + for (i = 0; i < 4; i++) + { + value = gfx_pci_config_read (0x80000910 + (i << 2)); + if (value == 0x00000000 || value == 0xFFFFFFFF) + { + valid = 0; + break; + } + } + + if (valid) + { + /* REDCLOUD INTEGRATED VIDEO */ + +#if GFX_VIDEO_DYNAMIC + gfx_video_type = GFX_VIDEO_TYPE_CASTLE; +#endif + + /* CURRENTLY, ALWAYS GPIO FOR I2C ACCESS */ + +#if GFX_I2C_DYNAMIC + gfx_i2c_type = GFX_I2C_TYPE_GPIO; +#endif + + /* THIRD-GENERATION DISPLAY CONTROLLER */ + +#if GFX_DISPLAY_DYNAMIC + gfx_display_type = GFX_DISPLAY_TYPE_GU3; +#endif + + /* SECOND-GENERATION GRAPHICS UNIT */ + +#if GFX_2DACCEL_DYNAMIC + gfx_2daccel_type = GFX_2DACCEL_TYPE_GU2; +#endif + + /* THIRD-GENERATION INITIALIZATION */ + +#if GFX_INIT_DYNAMIC + gfx_init_type = GFX_INIT_TYPE_GU3; +#endif + + /* MBUS MSR ACCESSES */ + +#if GFX_MSR_DYNAMIC + gfx_msr_type = GFX_MSR_TYPE_REDCLOUD; +#endif + + /* READ VERSION */ + + gfx_msr_init(); + + gfx_msr_read (RC_ID_MCP, MCP_RC_REVID, &msr_value); + + version = GFX_CPU_CASTLE | + ((msr_value.low & 0xF0) << 4) | /* MAJOR */ + ((msr_value.low & 0x0F) << 16); /* MINOR */ + + /* READ THE CORE FREQUENCY */ + + gfx_cpu_frequency = gfx_get_core_freq(); + + /* SET THE GP SCRATCH AREA */ + /* Color bitmap BLTs use the last 16K of frame buffer space */ + + gfx_gx2_scratch_base = gfx_get_frame_buffer_size() - 0x4000; + + /* CAP AT 16MB */ + + if (gfx_gx2_scratch_base > 0xFFC000) + gfx_gx2_scratch_base = 0xFFC000; + } + } + } + +#endif + + if (!version) + { + /* ALWAYS SECOND GENERATION IF SIMULATING */ + /* For now, that is. This could change. */ + +#if GFX_DISPLAY_DYNAMIC + gfx_display_type = GFX_DISPLAY_TYPE_GU2; +#endif +#if GFX_2DACCEL_DYNAMIC + gfx_2daccel_type = GFX_2DACCEL_TYPE_GU2; +#endif +#if GFX_INIT_DYNAMIC + gfx_init_type = GFX_INIT_TYPE_GU2; +#endif +#if GFX_MSR_DYNAMIC + gfx_msr_type = GFX_MSR_TYPE_REDCLOUD; +#endif +#if GFX_VIDEO_DYNAMIC + gfx_video_type = GFX_VIDEO_TYPE_REDCLOUD; +#endif +#if GFX_I2C_DYNAMIC + gfx_i2c_type = GFX_I2C_TYPE_GPIO; +#endif + } + gfx_cpu_version = version; + + return(version); +} + +/*----------------------------------------------------------------------------- + * gfx_detect_video + * + * This routine returns the type of the video hardware. + * + * The return value is as follows: + * bits[7:0] = type (1 = CS5530, 2 = SC1200, 3 = Redcloud) + * + * Currently this routine does not actually detect any hardware, and bases + * the video hardware entirely on the detected CPU. + *----------------------------------------------------------------------------- + */ +unsigned long gfx_detect_video(void) +{ + unsigned long version = 0; + if ((gfx_cpu_version & 0xFF) == GFX_CPU_GXLV) + version = GFX_VID_CS5530; + else if ((gfx_cpu_version & 0xFF) == GFX_CPU_SC1200) + version = GFX_VID_SC1200; + else if ((gfx_cpu_version & 0xFF) == GFX_CPU_REDCLOUD) + version = GFX_VID_REDCLOUD; + else if ((gfx_cpu_version & 0xFF) == GFX_CPU_CASTLE) + version = GFX_VID_CASTLE; + gfx_vid_version = version; + return(version); +} + +/*----------------------------------------------------------------------------- + * gfx_pci_config_read + * + * This routine reads a 32-bit value from the specified location in PCI + * configuration space. + *----------------------------------------------------------------------------- + */ +unsigned long gfx_pci_config_read(unsigned long address) +{ + unsigned long value = 0xFFFFFFFF; + OUTD(PCI_CONFIG_ADDR, address); + value = IND(PCI_CONFIG_DATA); + return(value); +} + +/*----------------------------------------------------------------------------- + * gfx_pci_config_write + * + * This routine writes a 32-bit value to the specified location in PCI + * configuration space. + *----------------------------------------------------------------------------- + */ +void gfx_pci_config_write(unsigned long address, unsigned long data) +{ + OUTD(PCI_CONFIG_ADDR, address); + OUTD(PCI_CONFIG_DATA, data); + return; +} + +/* WRAPPERS IF DYNAMIC SELECTION */ +/* Extra layer to call either first or second generation routines. */ + +#if GFX_INIT_DYNAMIC + +/*----------------------------------------------------------------------------- + * gfx_get_core_freq + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_core_freq(void) +{ + unsigned long freq = 0; +#if GFX_INIT_GU1 + if (gfx_init_type & GFX_INIT_TYPE_GU1) + freq = gu1_get_core_freq(); +#endif +#if GFX_INIT_GU2 + if (gfx_init_type & GFX_INIT_TYPE_GU2) + freq = gu2_get_core_freq(); +#endif +#if GFX_INIT_GU3 + if (gfx_init_type & GFX_INIT_TYPE_GU3) + freq = gu3_get_core_freq(); +#endif + return freq; +} + +/*----------------------------------------------------------------------------- + * gfx_get_cpu_register_base + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_cpu_register_base(void) +{ + unsigned long base = 0; + +#if GFX_INIT_GU1 + if (gfx_init_type & GFX_INIT_TYPE_GU1) + base = gu1_get_cpu_register_base (); +#endif +#if GFX_INIT_GU2 + if (gfx_init_type & GFX_INIT_TYPE_GU2) + base = gu2_get_cpu_register_base (); +#endif +#if GFX_INIT_GU3 + if (gfx_init_type & GFX_INIT_TYPE_GU3) + base = gu3_get_cpu_register_base (); +#endif + + return(base); +} + +/*----------------------------------------------------------------------------- + * gfx_get_graphics_register_base + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_graphics_register_base(void) +{ + unsigned long base = 0; + +#if GFX_INIT_GU2 + if (gfx_init_type & GFX_INIT_TYPE_GU2) + base = gu2_get_graphics_register_base (); +#endif +#if GFX_INIT_GU3 + if (gfx_init_type & GFX_INIT_TYPE_GU3) + base = gu3_get_graphics_register_base (); +#endif + + return(base); +} + +/*----------------------------------------------------------------------------- + * gfx_get_frame_buffer_base + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_frame_buffer_base(void) +{ + unsigned long base = 0; + +#if GFX_INIT_GU1 + if (gfx_init_type & GFX_INIT_TYPE_GU1) + base = gu1_get_frame_buffer_base (); +#endif +#if GFX_INIT_GU2 + if (gfx_init_type & GFX_INIT_TYPE_GU2) + base = gu2_get_frame_buffer_base (); +#endif +#if GFX_INIT_GU3 + if (gfx_init_type & GFX_INIT_TYPE_GU3) + base = gu3_get_frame_buffer_base (); +#endif + + return(base); +} + +/*----------------------------------------------------------------------------- + * gfx_get_frame_buffer_size + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_frame_buffer_size(void) +{ + unsigned long size = 0; + +#if GFX_INIT_GU1 + if (gfx_init_type & GFX_INIT_TYPE_GU1) + size = gu1_get_frame_buffer_size(); +#endif +#if GFX_INIT_GU2 + if (gfx_init_type & GFX_INIT_TYPE_GU2) + size = gu2_get_frame_buffer_size(); +#endif +#if GFX_INIT_GU3 + if (gfx_init_type & GFX_INIT_TYPE_GU3) + size = gu3_get_frame_buffer_size(); +#endif + + return size; +} + +/*----------------------------------------------------------------------------- + * gfx_get_vid_register_base + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_vid_register_base(void) +{ + unsigned long base = 0; + +#if GFX_INIT_GU1 + if (gfx_init_type & GFX_INIT_TYPE_GU1) + base = gu1_get_vid_register_base (); +#endif +#if GFX_INIT_GU2 + if (gfx_init_type & GFX_INIT_TYPE_GU2) + base = gu2_get_vid_register_base (); +#endif +#if GFX_INIT_GU3 + if (gfx_init_type & GFX_INIT_TYPE_GU3) + base = gu3_get_vid_register_base (); +#endif + + return(base); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vip_register_base + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_vip_register_base(void) +{ + unsigned long base = 0; + +#if GFX_INIT_GU1 + if (gfx_init_type & GFX_INIT_TYPE_GU1) + base = gu1_get_vip_register_base (); +#endif + + return(base); +} + +#endif + +/* END OF FILE */ + + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/i2c_gpio.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/i2c_gpio.c 2005-12-14 11:30:55.000000000 -0700 @@ -0,0 +1,646 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to write to and read from the I2C bus using + * the GPIO pins of the CS5530. + * */ + + +/* STATIC VARIABLES TO STORE WHAT GPIO PINS TO USE */ + +int gpio_clock = 0; +int gpio_data = 0; + +static int g_initialized = 0; + +#define I2CWRITE 0x00 /* Write address */ +#define I2CREAD 0x01 /* Read address */ + +#define I2CACK 0x00 /* Ack value */ +#define I2CNACK 0x01 /* Not - ack value */ + +#define CS5530_ID (0x80000000 | (0x00<<16) | (0x12<<11) | (0<<8) | 0x00) +#define CS5530_GPIO (0x80000000 | (0x00<<16) | (0x12<<11) | (0<<8) | 0x90) +#define SDA 0x0800 +#define SCL 0x0400 +#define SDADIR 0x0008 +#define SCLDIR 0x0004 + +int I2C_init(void); +void I2C_cleanup(void); + +int I2C_Read(unsigned char address, unsigned int reg, unsigned long *p_value, unsigned int bytes); +int I2C_Write(unsigned char address, unsigned int reg, unsigned long value, unsigned int bytes); +int I2CAL_init(void); +void I2CAL_cleanup(void); + +void I2CAL_output_clock(int state); +void I2CAL_output_data(int state); +unsigned char I2CAL_input_data(void); + +void I2CAL_set_data_for_input(void); +void I2CAL_set_data_for_output(void); + +void SendI2CStart(void); +void SendI2CData(unsigned char inData); + +unsigned char ReceiveI2CAck(void); +void SendI2CStop(void); +void SendI2CNack(void); +void SendI2CAck (void); +unsigned char ReceiveI2CData(void); + + +/* ### ADD ### ANY LOCAL ROUTINE DEFINITIONS SPECIFIC TO GPIO */ + +/*--------------------------------------------------------------------------- + * gfx_i2c_reset + * + * This routine resets the I2C bus. + *--------------------------------------------------------------------------- + */ + +#if GFX_I2C_DYNAMIC +int gpio_i2c_reset(unsigned char busnum, short adr, char freq) +#else +int gfx_i2c_reset(unsigned char busnum, short adr, char freq) +#endif +{ + /* ### ADD ### Any code needed to reset the state of the GPIOs. */ + return GFX_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_select_gpio + * + * This routine selects which GPIO pins to use. + *--------------------------------------------------------------------------- + */ +#if GFX_I2C_DYNAMIC +int gpio_i2c_select_gpio(int clock, int data) +#else +int gfx_i2c_select_gpio(int clock, int data) +#endif +{ + gpio_clock = clock; + gpio_data = data; + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_write + * + * This routine writes data to the specified I2C address. + *--------------------------------------------------------------------------- + */ +#if GFX_I2C_DYNAMIC +int gpio_i2c_write(unsigned char busnum, unsigned char address, unsigned char reg, + unsigned char bytes, unsigned char * value) +#else +int gfx_i2c_write(unsigned char busnum, unsigned char address, unsigned char reg, + unsigned char bytes, unsigned char * value) +#endif +{ + /* ### ADD ### CODE TO WRITE BYTE TO I2B BUS */ + + int restart_count = 0; + + + while (restart_count++ < 5) + { + /* set the access pointer register. */ + /* The address is shifted left by one to make room for Read/Write bit */ + SendI2CStart(); + SendI2CData((char)((address << 1) | I2CWRITE)); + if (!ReceiveI2CAck()) + { + SendI2CStop(); + gfx_delay_milliseconds(10); + continue; + } + SendI2CData((unsigned char)reg); + if (!ReceiveI2CAck()) + { + SendI2CStop(); + gfx_delay_milliseconds(10); + continue; + } + + /* write the first byte */ + SendI2CData(*value); + if (!ReceiveI2CAck()) + { + SendI2CStop(); + gfx_delay_milliseconds(10); + continue; + } + + + /* write the second byte. */ + if (bytes == 2) + { + SendI2CData(*(value+1)); + if (!ReceiveI2CAck()) + { + SendI2CStop(); + gfx_delay_milliseconds(10); + continue; + } + } + + + /* done. */ + SendI2CStop(); + + return 0; + } + + return(0); + +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_read + * + * This routine reads data from the specified I2C address. + *--------------------------------------------------------------------------- + */ +#if GFX_I2C_DYNAMIC +int gpio_i2c_read(unsigned char busnum, unsigned char address, unsigned char reg, + unsigned char bytes, unsigned char *p_value) +#else +int gfx_i2c_read(unsigned char busnum, unsigned char address, unsigned char reg, + unsigned char bytes, unsigned char *p_value) +#endif +{ + /* ### ADD ### CODE TO WRITE BYTE TO I2B BUS */ + /* For now return clock and data pins */ + + int restart_count = 0; + + + if (!p_value) + return(1); + + while (restart_count++ < 5) + { + /* set the access pointer register. */ + /* The address is shifted left by one to make room for Read/Write bit */ + SendI2CStart(); + SendI2CData((char)((address << 1) | I2CWRITE)); + if (!ReceiveI2CAck()) + { + SendI2CStop(); + gfx_delay_milliseconds(10); + continue; + } + SendI2CData((unsigned char)(reg & 0xFF)); + SendI2CNack(); + + /* read the first data byte. */ + SendI2CStart(); + SendI2CData((char)((address << 1) | I2CREAD)); + if (!ReceiveI2CAck()) + { + SendI2CStop(); + gfx_delay_milliseconds(10); + continue; + } + *p_value = ReceiveI2CData(); + + + /* read the second byte. */ + if (bytes == 2) + { + SendI2CAck(); + *(p_value+1) = ReceiveI2CData(); + } + + + /* done. */ + SendI2CNack(); + SendI2CStop(); + + + return 0; + } + + return(1); +} + +/* Added i2c/gpio code to test fs451 chip. */ + +/* +//---------------------------------------------------------------------- +// +// void SendI2CStart(void) +// +// Sends an I2C start signal on the bus. +// +//---------------------------------------------------------------------- +*/ +void SendI2CStart(void) +{ + I2CAL_output_data(1); + I2CAL_output_clock(1); + I2CAL_output_data(0); + I2CAL_output_clock(0); +} + +/* +//---------------------------------------------------------------------- +// +// void SendI2CStop(void) +// +// Sends an I2C stop signal on the bus. +// +//---------------------------------------------------------------------- +*/ +void SendI2CStop(void) +{ + I2CAL_output_data(0); + I2CAL_output_clock(1); + I2CAL_output_data(1); +} + +/* +//---------------------------------------------------------------------- +// +// void SendI2CAck(void) +// +// Sends the Ack signal on the I2C bus. +// +//---------------------------------------------------------------------- +*/ +void SendI2CAck(void) +{ + I2CAL_output_data(0); + I2CAL_output_clock(1); + I2CAL_output_clock(0); +} + +/* +//---------------------------------------------------------------------- +// +// void SendI2CNack(void) +// +// Sends the Nt-Ack signal on the I2C bus. +// +//---------------------------------------------------------------------- +*/ +void SendI2CNack(void) +{ + I2CAL_output_data(1); + I2CAL_output_clock(1); + I2CAL_output_clock(0); +} + +/* +//---------------------------------------------------------------------- +// +// UInt8 SendI2CData( UInt8 inData ) +// +// Sends a byte of data on the I2C bus and returns the TRUE if the slave ACK'd +// the data. +// +// Input: inData - the byte of data to send +// Output: (return) - TRUE (1) if ACK was received, FALSE (0) if not +// +//---------------------------------------------------------------------- +*/ +void SendI2CData(unsigned char inData) +{ + unsigned char bit; + + /* Send all 8 bits of data byte, MSB to LSB */ + for (bit = 0x80; bit != 0; bit >>= 1) + { + if (inData & bit) + I2CAL_output_data(1); + else + I2CAL_output_data(0); + + I2CAL_output_clock(1); + I2CAL_output_clock(0); + } +} + +/* +//---------------------------------------------------------------------- +// +// UInt8 ReceiveI2CAck( ) +// +// Receives the Ack (or Nack) from the slave. +// +// Output: (return) - TRUE (1) if ACK was received, FALSE (0) if not +// +//---------------------------------------------------------------------- +*/ +unsigned char ReceiveI2CAck(void) +{ + unsigned char bit; + + /* Test for Ack/Nack */ + I2CAL_set_data_for_input(); + I2CAL_output_data(1); + I2CAL_output_clock(1); + bit = I2CAL_input_data(); + I2CAL_output_clock(0); + I2CAL_set_data_for_output(); + return !bit; +} + +/* +//---------------------------------------------------------------------- +// +// unsigned char ReceiveI2CData(void) +// +// Receives a byte of data from the I2C bus. +// +// Output: (return) - The data byte recehved from the bus +// +//---------------------------------------------------------------------- +*/ +unsigned char ReceiveI2CData(void) +{ + unsigned char data = 0; + unsigned char x; + + /* make sure the data line is released */ + I2CAL_set_data_for_input(); + I2CAL_output_data(1); + + /* shift in the data */ + for (x=0; x<8; x++) + { + /* shift the data left */ + I2CAL_output_clock(1); + data <<= 1; + data |= I2CAL_input_data(); + I2CAL_output_clock(0); + } + + I2CAL_set_data_for_output(); + I2CAL_output_data(1); + return data; +} + + +/* +//---------------------------------------------------------------------- +// +// void I2C_init(void) +// +// This routine initializes the I2C interface. Clients of the I2C.c +// will call this routine before calling any other routine in the I2C.c +// +//---------------------------------------------------------------------- +*/ + +#if GFX_I2C_DYNAMIC +int gpio_i2c_init(void) +#else +int gfx_i2c_init(void) +#endif +{ + int errc; + + /* init I2CAL */ + errc = I2CAL_init(); + if (errc) + return errc; + + /* set the clock and data lines to the proper states */ + I2CAL_output_clock(1); + I2CAL_output_data(1); + I2CAL_set_data_for_output(); + + SendI2CStart(); + SendI2CStop(); + SendI2CStop(); + + g_initialized = 1; + + return 0; +} + +/* +//---------------------------------------------------------------------- +// +// void I2C_cleanup(void) +// +// This routine disables the I2C interface. Clients of the I2C.c will not +// call any other I2C routine after calling this routine. +// +//---------------------------------------------------------------------- +*/ + +#if GFX_I2C_DYNAMIC +void gpio_i2c_cleanup(void) +#else +void gfx_i2c_cleanup(void) +#endif + +{ + if (g_initialized) + { + + /* set the clock and data lines to a harmless state */ + I2CAL_output_clock(1); + I2CAL_output_data(1); + + g_initialized = 0; + } + + I2CAL_cleanup(); +} + + + +int I2CAL_init(void) +{ + unsigned long l_reg; + unsigned short reg; + + /* initialize the i2c port. */ + l_reg = gfx_pci_config_read(CS5530_GPIO); + + if (l_reg != 0x01001078) + return 1; + + l_reg = gfx_pci_config_read(CS5530_GPIO); + reg = (unsigned short) l_reg; + + /* both outputs, both high. */ + reg |= (SDADIR | SCLDIR | SDA | SCL); + l_reg = reg; + gfx_pci_config_write(CS5530_GPIO, l_reg); + + g_initialized = 1; + + return 0; +} + +void I2CAL_cleanup(void) +{ + if (g_initialized) + { + + g_initialized = 0; + } +} + + +/* +//-------------------------------------------------------------------------------- +// +// set the I2C clock line state +// +//-------------------------------------------------------------------------------- +*/ +void I2CAL_output_clock(int inState) +{ + unsigned short reg; + unsigned long value; + + value = gfx_pci_config_read(CS5530_GPIO); + reg = (unsigned short)value; + + if (inState) + { /* write a 1. */ + reg |= SCL; + } + else + { /* write a 0. */ + reg &= ~SCL; + } + + value = reg; + gfx_pci_config_write(CS5530_GPIO, value); + + /* hold it for a minimum of 4.7us */ + gfx_delay_microseconds(5); +} + +/* +//-------------------------------------------------------------------------------- +// +// set the I2C data line state +// +//-------------------------------------------------------------------------------- +*/ +void I2CAL_output_data(int inState) +{ + unsigned short reg; + unsigned long value; + + value = gfx_pci_config_read(CS5530_GPIO); + reg = (unsigned short)value; + + if (inState) + { /* write a 1. */ + reg |= SDA; + } + else + { + /* write a 0. */ + reg &= ~SDA; + } + value = reg; + gfx_pci_config_write(CS5530_GPIO, value); + + /* 250 ns setup time */ + gfx_delay_microseconds(1); +} + +/* +//-------------------------------------------------------------------------------- +// +// read the state of the data line +// +//-------------------------------------------------------------------------------- +*/ +unsigned char I2CAL_input_data(void) +{ + unsigned short reg; + unsigned long value; + + value = gfx_pci_config_read(CS5530_GPIO); + reg = (unsigned short)value; + + if (reg & SDA) + return 1; + else + return 0; +} + +/* +//-------------------------------------------------------------------------------- +// +// set the I2C data for input mode +// +//-------------------------------------------------------------------------------- +*/ +void I2CAL_set_data_for_input(void) +{ + unsigned short reg; + unsigned long value; + + value = gfx_pci_config_read(CS5530_GPIO); + reg = (unsigned short)value; + + reg &= ~SDADIR; + + value = reg; + + gfx_pci_config_write(CS5530_GPIO, value); +} + +/* +//-------------------------------------------------------------------------------- +// +// set the I2C data for output mode +// +//-------------------------------------------------------------------------------- +*/ +void I2CAL_set_data_for_output(void) +{ + unsigned short reg; + unsigned long value; + + value = gfx_pci_config_read(CS5530_GPIO); + reg = (unsigned short)value; + reg |= SDADIR; + value = reg; + + gfx_pci_config_write(CS5530_GPIO, value); + +} + + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/history.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/history.h 2005-12-14 11:31:13.000000000 -0700 @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +/* Version is in the format of MMmmpp + * where in MM is the Major version, mm is the minor version + * and pp is the patch number (0 - 99) +*/ + +#define DURANGO_VERSION 30003 + +#if 0 + +This file contains specific revision info SINCE THE LAST RELEASE. It is not meant to +be a comprehensive record of all additions. + +#endif +/* END OF FILE */ + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_mode.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_mode.h 2005-12-14 11:35:57.000000000 -0700 @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This header file contains the mode tables. It is used by the "gfx_disp.c" + * file to set a display mode. + * */ + + +#ifndef _gfx_mode_h +#define _gfx_mode_h + +/* MODE FLAGS (BITWISE-OR) */ + +#define GFX_MODE_8BPP 0x00000001 +#define GFX_MODE_12BPP 0x00000002 +#define GFX_MODE_15BPP 0x00000004 +#define GFX_MODE_16BPP 0x00000008 +#define GFX_MODE_24BPP 0x00000010 +#define GFX_MODE_56HZ 0x00000020 +#define GFX_MODE_60HZ 0x00000040 +#define GFX_MODE_70HZ 0x00000080 +#define GFX_MODE_72HZ 0x00000100 +#define GFX_MODE_75HZ 0x00000200 +#define GFX_MODE_85HZ 0x00000400 +#define GFX_MODE_90HZ 0x00000800 +#define GFX_MODE_100HZ 0x00001000 +#define GFX_MODE_NEG_HSYNC 0x00002000 +#define GFX_MODE_NEG_VSYNC 0x00004000 +#define GFX_MODE_PIXEL_DOUBLE 0x00008000 +#define GFX_MODE_LINE_DOUBLE 0x00010000 +#define GFX_MODE_TV_NTSC 0x00020000 +#define GFX_MODE_TV_PAL 0x00040000 +#define GFX_MODE_EXCLUDE_PLL 0x00080000 +#define GFX_MODE_LOCK_TIMING 0x10000000 + + +/* STRUCTURE DEFINITION */ + +typedef struct tagDISPLAYMODE +{ + /* DISPLAY MODE FLAGS */ + /* Specify valid color depths and the refresh rate. */ + + unsigned long flags; + + /* TIMINGS */ + + unsigned short hactive; + unsigned short hblankstart; + unsigned short hsyncstart; + unsigned short hsyncend; + unsigned short hblankend; + unsigned short htotal; + + unsigned short vactive; + unsigned short vblankstart; + unsigned short vsyncstart; + unsigned short vsyncend; + unsigned short vblankend; + unsigned short vtotal; + + /* CLOCK FREQUENCY */ + + unsigned long frequency; + +} DISPLAYMODE; + + +/* For Fixed timings */ +typedef struct tagFIXEDTIMINGS +{ + /* DISPLAY MODE FLAGS */ + /* Specify valid color depths and the refresh rate. */ + + int panelresx; + int panelresy; + unsigned short xres; + unsigned short yres; + + /* TIMINGS */ + + unsigned short hactive; + unsigned short hblankstart; + unsigned short hsyncstart; + unsigned short hsyncend; + unsigned short hblankend; + unsigned short htotal; + + unsigned short vactive; + unsigned short vblankstart; + unsigned short vsyncstart; + unsigned short vsyncend; + unsigned short vblankend; + unsigned short vtotal; + + /* CLOCK FREQUENCY */ + + unsigned long frequency; + +} FIXEDTIMINGS; + +#endif /* !_gfx_mode_h */ + +/* END OF FILE */ + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_priv.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_priv.h 2005-12-14 11:35:37.000000000 -0700 @@ -0,0 +1,940 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This header file contains the prototypes for local and private routines. + * */ + + +/*---------------------------------*/ +/* FIRST GENERATION INITIALIZATION */ +/*---------------------------------*/ + +#if GFX_INIT_GU1 + +/* PRIVATE ROUTINES */ + +unsigned char gfx_gxm_config_read(unsigned char index); + +/* DYNAMIC ROUTINES */ + +#if GFX_INIT_DYNAMIC +unsigned long gu1_get_core_freq(void); +unsigned long gu1_get_cpu_register_base(void); +unsigned long gu1_get_graphics_register_base(void); +unsigned long gu1_get_frame_buffer_base(void); +unsigned long gu1_get_frame_buffer_size(void); +unsigned long gu1_get_vid_register_base(void); +unsigned long gu1_get_vip_register_base(void); +#endif + +#endif + +/*----------------------------------*/ +/* SECOND GENERATION INITIALIZATION */ +/*----------------------------------*/ + +#if GFX_INIT_GU2 + +/* DYNAMIC ROUTINES */ + +#if GFX_INIT_DYNAMIC +unsigned long gu2_get_core_freq(void); +unsigned long gu2_get_cpu_register_base(void); +unsigned long gu2_get_graphics_register_base(void); +unsigned long gu2_get_frame_buffer_base(void); +unsigned long gu2_get_frame_buffer_size(void); +unsigned long gu2_get_vid_register_base(void); +unsigned long gu2_get_vip_register_base(void); +#endif + +#endif + +/*----------------------------------*/ +/* MSR ROUTINES */ +/*----------------------------------*/ + +#if GFX_MSR_REDCLOUD + +/* PRIVATE ROUTINES */ + +void redcloud_build_mbus_tree(void); +int redcloud_init_msr_devices(MSR aDev[], unsigned int array_size); +DEV_STATUS redcloud_find_msr_device (MSR *pDev); + +/* DYNAMIC ROUTINES */ + +#if GFX_MSR_DYNAMIC +int redcloud_msr_init (void); +DEV_STATUS redcloud_id_msr_device (MSR *pDev, unsigned long address); +DEV_STATUS redcloud_get_msr_dev_address (unsigned int device, unsigned long *address); +DEV_STATUS redcloud_get_glink_id_at_address(unsigned int *device, unsigned long address); +DEV_STATUS redcloud_msr_read (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue); +DEV_STATUS redcloud_msr_write (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue); +#endif + +#endif + +void gfx_set_display_video_enable(int enable); +void gfx_set_display_video_size(unsigned short width, unsigned short height); +void gfx_set_display_video_offset(unsigned long offset); +unsigned long gfx_get_display_video_offset(void); +unsigned long gfx_get_display_video_size(void); + +/*----------------------------------*/ +/* FIRST GENERATION DISPLAY */ +/*----------------------------------*/ + +#if GFX_DISPLAY_GU1 + +/* PRIVATE ROUTINES */ + +void gu1_enable_compression(void); +void gu1_disable_compression(void); +void gu1_delay_approximate (unsigned long milliseconds); +void gu1_delay_precise (unsigned long milliseconds); + +/* DYNAMIC ROUTINES */ + +#if GFX_DISPLAY_DYNAMIC +void gu1_set_display_video_enable(int enable); +void gu1_set_display_video_size(unsigned short width, unsigned short height); +void gu1_set_display_video_offset(unsigned long offset); +unsigned long gu1_get_display_video_offset(void); +unsigned long gu1_get_display_video_size(void); +int gu1_set_display_bpp (unsigned short bpp); +int gu1_is_display_mode_supported(int xres, int yres, int bpp, int hz); +int gu1_set_display_mode(int xres, int yres, int bpp, int hz); +int gu1_set_display_timings(unsigned short bpp, unsigned short flags, + unsigned short hactive, unsigned short hblank_start, + unsigned short hsync_start, unsigned short hsync_end, + unsigned short hblank_end, unsigned short htotal, + unsigned short vactive, unsigned short vblank_start, + unsigned short vsync_start, unsigned short vsync_end, + unsigned short vblank_end, unsigned short vtotal, + unsigned long frequency); +int gu1_set_vtotal(unsigned short vtotal); +void gu1_set_display_pitch(unsigned short pitch); +void gu1_set_display_offset(unsigned long offset); +int gu1_set_display_palette_entry(unsigned long index, unsigned long palette); +int gu1_set_display_palette(unsigned long *palette); +void gu1_video_shutdown(void); +void gu1_set_cursor_enable(int enable); +void gu1_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor); +void gu1_set_cursor_position(unsigned long memoffset, + unsigned short xpos, unsigned short ypos, + unsigned short xhotspot, unsigned short yhotspot); +void gu1_set_cursor_shape32(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask); +int gu1_set_compression_enable(int enable); +int gu1_set_compression_offset(unsigned long offset); +int gu1_set_compression_pitch(unsigned short pitch); +int gu1_set_compression_size(unsigned short size); +void gu1_set_display_priority_high(int enable); +int gu1_test_timing_active(void); +int gu1_test_vertical_active(void); +int gu1_wait_vertical_blank(void); +void gu1_delay_milliseconds(unsigned long milliseconds); +void gu1_delay_microseconds(unsigned long microseconds); +void gu1_enable_panning(int x, int y); +int gu1_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp); +int gu1_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp); +void gu1_reset_timing_lock(void); +int gu1_get_display_details(unsigned int mode, int *xres, int *yres, int *hz); +unsigned short gu1_get_display_pitch(void); +unsigned long gu1_get_max_supported_pixel_clock (void); +int gu1_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency); +int gu1_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency); +int gu1_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency); +int gu1_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency); +int gu1_get_display_mode_count(void); +int gu1_get_display_mode(int *xres, int *yres, int *bpp, int *hz); +unsigned long gu1_get_frame_buffer_line_size (void); +unsigned short gu1_get_hactive(void); +unsigned short gu1_get_hblank_start(void); +unsigned short gu1_get_hsync_start(void); +unsigned short gu1_get_hsync_end(void); +unsigned short gu1_get_hblank_end(void); +unsigned short gu1_get_htotal(void); +unsigned short gu1_get_vactive(void); +unsigned short gu1_get_vline(void); +unsigned short gu1_get_vblank_start(void); +unsigned short gu1_get_vsync_start(void); +unsigned short gu1_get_vsync_end(void); +unsigned short gu1_get_vblank_end(void); +unsigned short gu1_get_vtotal(void); +unsigned short gu1_get_display_bpp(void); +unsigned long gu1_get_display_offset(void); +int gu1_get_display_palette_entry(unsigned long index, unsigned long *palette); +void gu1_get_display_palette(unsigned long *palette); +unsigned long gu1_get_cursor_enable(void); +unsigned long gu1_get_cursor_offset(void); +unsigned long gu1_get_cursor_position(void); +unsigned long gu1_get_cursor_clip(void); +unsigned long gu1_get_cursor_color(int color); +unsigned long gu1_get_icon_enable(void); +unsigned long gu1_get_icon_offset (void); +unsigned long gu1_get_icon_position (void); +unsigned long gu1_get_icon_color (int color); +int gu1_get_compression_enable(void); +unsigned long gu1_get_compression_offset(void); +unsigned short gu1_get_compression_pitch(void); +unsigned short gu1_get_compression_size(void); +int gu1_get_display_priority_high(void); +int gu1_get_valid_bit(int line); +#endif + +#endif + +void gfx_set_display_video_format(unsigned long format); +void gfx_set_display_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, + unsigned long voffset); +void gfx_set_display_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch); +void gfx_set_display_video_downscale (unsigned short srch, unsigned short dsth); +void gfx_set_display_video_vertical_downscale_enable(int enable); +void gfx_get_display_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset); +void gfx_get_display_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch); +unsigned long gfx_get_display_video_downscale_delta(void); +int gfx_get_display_video_downscale_enable(void); + +/*----------------------------------*/ +/* SECOND GENERATION DISPLAY */ +/*----------------------------------*/ + +#if GFX_DISPLAY_GU2 + +/* PRIVATE ROUTINES */ + +void gu2_enable_compression(void); +void gu2_disable_compression(void); + +/* DYNAMIC ROUTINES */ + +#if GFX_DISPLAY_DYNAMIC +void gu2_get_display_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset); +void gu2_get_display_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch); +unsigned long gu2_get_display_video_downscale_delta(void); +int gu2_get_display_video_downscale_enable(void); +void gu2_set_display_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, + unsigned long voffset); +void gu2_set_display_video_format(unsigned long format); +void gu2_set_display_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch); +void gu2_set_display_video_downscale (unsigned short srch, unsigned short dsth); +void gu2_set_display_video_vertical_downscale_enable(int enable); +void gu2_set_display_video_enable(int enable); +void gu2_set_display_video_size(unsigned short width, unsigned short height); +void gu2_set_display_video_offset(unsigned long offset); +unsigned long gu2_get_display_video_offset(void); +unsigned long gu2_get_display_video_size(void); +int gu2_set_display_bpp (unsigned short bpp); +int gu2_is_display_mode_supported(int xres, int yres, int bpp, int hz); +int gu2_set_display_mode(int xres, int yres, int bpp, int hz); +int gu2_set_display_timings(unsigned short bpp, unsigned short flags, + unsigned short hactive, unsigned short hblank_start, + unsigned short hsync_start, unsigned short hsync_end, + unsigned short hblank_end, unsigned short htotal, + unsigned short vactive, unsigned short vblank_start, + unsigned short vsync_start, unsigned short vsync_end, + unsigned short vblank_end, unsigned short vtotal, + unsigned long frequency); +int gu2_set_vtotal(unsigned short vtotal); +void gu2_set_display_pitch(unsigned short pitch); +void gu2_set_display_offset(unsigned long offset); +int gu2_set_display_palette_entry(unsigned long index, unsigned long palette); +int gu2_set_display_palette(unsigned long *palette); +void gu2_set_cursor_enable(int enable); +void gu2_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor); +void gu2_set_cursor_position(unsigned long memoffset, + unsigned short xpos, unsigned short ypos, + unsigned short xhotspot, unsigned short yhotspot); +void gu2_set_cursor_shape32(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask); +void gu2_set_cursor_shape64(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask); +void gu2_set_icon_enable (int enable); +void gu2_set_icon_colors (unsigned long color0, unsigned long color1, unsigned long color2); +void gu2_set_icon_position (unsigned long memoffset, unsigned short xpos); +void gu2_set_icon_shape64 (unsigned long memoffset, unsigned long *andmask, + unsigned long *xormask, unsigned int lines); +int gu2_set_compression_enable(int enable); +int gu2_set_compression_offset(unsigned long offset); +int gu2_set_compression_pitch(unsigned short pitch); +int gu2_set_compression_size(unsigned short size); +void gu2_set_display_priority_high(int enable); +int gu2_test_timing_active(void); +int gu2_test_vertical_active(void); +int gu2_wait_vertical_blank(void); +void gu2_delay_milliseconds(unsigned long milliseconds); +void gu2_delay_microseconds(unsigned long microseconds); +void gu2_enable_panning(int x, int y); +int gu2_is_panel_mode_supported(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp); +int gu2_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp); +int gu2_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp); +void gu2_reset_timing_lock(void); +int gu2_get_display_details(unsigned int mode, int *xres, int *yres, int *hz); +unsigned short gu2_get_display_pitch(void); +unsigned long gu2_get_max_supported_pixel_clock (void); +int gu2_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency); +int gu2_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency); +int gu2_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency); +int gu2_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency); +int gu2_get_display_mode_count(void); +int gu2_get_display_mode(int *xres, int *yres, int *bpp, int *hz); +unsigned long gu2_get_frame_buffer_line_size (void); +unsigned short gu2_get_hactive(void); +unsigned short gu2_get_hblank_start(void); +unsigned short gu2_get_hsync_start(void); +unsigned short gu2_get_hsync_end(void); +unsigned short gu2_get_hblank_end(void); +unsigned short gu2_get_htotal(void); +unsigned short gu2_get_vactive(void); +unsigned short gu2_get_vline(void); +unsigned short gu2_get_vblank_start(void); +unsigned short gu2_get_vsync_start(void); +unsigned short gu2_get_vsync_end(void); +unsigned short gu2_get_vblank_end(void); +unsigned short gu2_get_vtotal(void); +unsigned short gu2_get_display_bpp(void); +unsigned long gu2_get_display_offset(void); +int gu2_get_display_palette_entry(unsigned long index, unsigned long *palette); +void gu2_get_display_palette(unsigned long *palette); +unsigned long gu2_get_cursor_enable(void); +unsigned long gu2_get_cursor_offset(void); +unsigned long gu2_get_cursor_position(void); +unsigned long gu2_get_cursor_clip(void); +unsigned long gu2_get_cursor_color(int color); +unsigned long gu2_get_icon_enable(void); +unsigned long gu2_get_icon_offset (void); +unsigned long gu2_get_icon_position (void); +unsigned long gu2_get_icon_color (int color); +int gu2_get_compression_enable(void); +unsigned long gu2_get_compression_offset(void); +unsigned short gu2_get_compression_pitch(void); +unsigned short gu2_get_compression_size(void); +int gu2_get_valid_bit(int line); +#endif + +#endif + +/*----------------------------------*/ +/* FIRST GENERATION 2D ACCELERATION */ +/*----------------------------------*/ + +#if GFX_2DACCEL_GU1 + +/* PRIVATE ROUTINES */ + +void gu1_solid_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height, unsigned long color); +void gu1_detect_blt_buffer_base(void); + +/* DYNAMIC ROUTINES */ + +#if GFX_2DACCEL_DYNAMIC +void gu1_set_bpp(unsigned short bpp); +void gu1_set_solid_pattern(unsigned long color); +void gu1_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, unsigned char transparency); +void gu1_set_color_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1,unsigned long data2,unsigned long data3, unsigned char transparency); +void gu1_load_color_pattern_line (short y, unsigned long *pattern_8x8); +void gu1_set_solid_source(unsigned long color); +void gu1_set_mono_source(unsigned long bgcolor, unsigned long fgcolor, + unsigned short transparent); +void gu1_set_pattern_flags(unsigned short flags); +void gu1_set_raster_operation(unsigned char rop); +void gu1_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height); +void gu1_color_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height, unsigned long *pattern); +void gu1_screen_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height); +void gu1_screen_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned long color); +void gu1_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch); +void gu1_color_bitmap_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch, + unsigned long color); +void gu1_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, short pitch); +void gu1_text_blt(unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data); +void gu1_bresenham_line(unsigned short x, unsigned short y, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags); +void gu1_wait_until_idle(void); +int gu1_test_blt_pending(void); +#endif + +#endif + +/*-----------------------------------*/ +/* SECOND GENERATION 2D ACCELERATION */ +/*-----------------------------------*/ + +#if GFX_2DACCEL_GU2 + +/* DYNAMIC ROUTINES */ + +#if GFX_2DACCEL_DYNAMIC +void gfx_reset_pitch(unsigned short pitch); +void gu2_reset_pitch(unsigned short pitch); +void gu2_set_bpp(unsigned short bpp); +void gu2_set_solid_pattern(unsigned long color); +void gu2_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, unsigned char transparency); +void gu2_set_color_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1,unsigned long data2,unsigned long data3, unsigned char transparency); +void gu2_load_color_pattern_line (short y, unsigned long *pattern_8x8); +void gu2_set_solid_source(unsigned long color); +void gu2_set_mono_source(unsigned long bgcolor, unsigned long fgcolor, + unsigned short transparent); +void gu2_set_pattern_flags(unsigned short flags); +void gu2_set_raster_operation(unsigned char rop); +void gu2_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height); +void gu2_color_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height, unsigned long *pattern); +void gu2_screen_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height); +void gu2_screen_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned long color); +void gu2_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch); +void gu2_color_bitmap_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch, + unsigned long color); +void gu2_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, short pitch); +void gu2_text_blt(unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data); +void gu2_bresenham_line(unsigned short x, unsigned short y, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags); +void gu2_wait_until_idle(void); +int gu2_test_blt_pending(void); + +void gu22_set_source_stride(unsigned short stride); +void gu22_set_destination_stride(unsigned short stride); +void gu22_set_pattern_origin(int x, int y); +void gu22_set_source_transparency(unsigned long color, unsigned long mask); +void gu22_set_alpha_mode(int mode); +void gu22_set_alpha_value(unsigned char value); +void gu22_pattern_fill(unsigned long dstoffset, unsigned short width, + unsigned short height); +void gu22_color_pattern_fill(unsigned long dstoffset, unsigned short width, + unsigned short height, unsigned long *pattern); +void gu22_screen_to_screen_blt(unsigned long srcoffset, unsigned long dstoffset, + unsigned short width, unsigned short height, int flags); +void gu22_mono_expand_blt(unsigned long srcbase, unsigned short srcx, + unsigned short srcy, unsigned long dstoffset, unsigned short width, + unsigned short height, int byte_packed); +void gu22_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned char *data, short pitch); +void gu22_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned char *data, short pitch); +void gu22_text_blt (unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned char *data); +void gu22_bresenham_line(unsigned long dstoffset, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags); +void gu22_sync_to_vblank(void); +#endif + +#endif + +void gfx_reset_video(void); +int gfx_set_display_control(int sync_polarities); +int gfx_set_screen_enable(int enable); + +/*-----------------------*/ +/* CS5530 VIDEO ROUTINES */ +/*-----------------------*/ + +#if GFX_VIDEO_CS5530 + +/* PRIVATE ROUTINES */ + +/* DYNAMIC ROUTINES */ + +#if GFX_VIDEO_DYNAMIC +void cs5530_reset_video(void); +int cs5530_set_display_control(int sync_polarities); +void cs5530_set_clock_frequency(unsigned long frequency); +unsigned long cs5530_get_clock_frequency(void); +int cs5530_set_crt_enable(int enable); +int cs5530_get_sync_polarities(void); +int cs5530_get_vsa2_softvga_enable(void); +int cs5530_set_video_enable(int enable); +int cs5530_set_video_format(unsigned long format); +int cs5530_set_video_size(unsigned short width, unsigned short height); +int cs5530_set_video_offset(unsigned long offset); +int cs5530_set_video_window(short x, short y, unsigned short w, unsigned short h); +int cs5530_set_video_left_crop(unsigned short x); +int cs5530_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth); +int cs5530_set_video_color_key(unsigned long key, unsigned long mask, + int bluescreen); +int cs5530_set_video_filter(int xfilter, int yfilter); +int cs5530_set_video_palette(unsigned long *palette); +int cs5530_set_video_palette_entry (unsigned long index, unsigned long color); +int cs5530_disable_softvga(void); +int cs5530_enable_softvga(void); +unsigned long cs5530_get_max_video_width(void); + +/* READ ROUTINES IN GFX_VID.C */ + +int cs5530_get_video_enable(void); +int cs5530_get_video_format(void); +unsigned long cs5530_get_video_src_size(void); +unsigned long cs5530_get_video_line_size(void); +unsigned long cs5530_get_video_xclip(void); +unsigned long cs5530_get_video_offset(void); +unsigned long cs5530_get_video_upscale(void); +unsigned long cs5530_get_video_scale(void); +unsigned long cs5530_get_video_dst_size(void); +unsigned long cs5530_get_video_position(void); +unsigned long cs5530_get_video_color_key(void); +unsigned long cs5530_get_video_color_key_mask(void); +int cs5530_get_video_palette_entry(unsigned long index, unsigned long *palette); +int cs5530_get_video_color_key_src(void); +int cs5530_get_video_filter(void); +unsigned long cs5530_read_crc(void); +#endif +#endif + +/*-----------------------*/ +/* SC1200 VIDEO ROUTINES */ +/*-----------------------*/ + +#if GFX_VIDEO_SC1200 + +/* PRIVATE ROUTINES */ + +/* DYNAMIC ROUTINES */ + +#if GFX_VIDEO_DYNAMIC +void sc1200_reset_video(void); +int sc1200_set_display_control(int sync_polarities); +int sc1200_set_screen_enable(int enable); +void sc1200_set_clock_frequency(unsigned long frequency); +unsigned long sc1200_get_clock_frequency(void); +int sc1200_set_crt_enable(int enable); +int sc1200_get_sync_polarities(void); +int sc1200_get_vsa2_softvga_enable(void); +int sc1200_set_video_enable(int enable); +int sc1200_set_video_format(unsigned long format); +int sc1200_set_video_size(unsigned short width, unsigned short height); +int sc1200_set_video_offset(unsigned long offset); +int sc1200_set_video_window(short x, short y, unsigned short w, unsigned short h); +int sc1200_set_video_left_crop(unsigned short x); +int sc1200_set_video_upscale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth); +int sc1200_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth); +int sc1200_set_video_downscale_config(unsigned short type, unsigned short m); +int sc1200_set_video_color_key(unsigned long key, unsigned long mask, + int bluescreen); +int sc1200_set_video_filter(int xfilter, int yfilter); +int sc1200_set_video_palette(unsigned long *palette); +int sc1200_set_video_palette_bypass (int enable); +int sc1200_set_video_palette_entry (unsigned long index, unsigned long color); +int sc1200_set_video_downscale_coefficients(unsigned short coef1, unsigned short coef2, + unsigned short coef3, unsigned short coef4) ; +int sc1200_set_video_downscale_enable(int enable); +int sc1200_set_video_source(VideoSourceType source); +int sc1200_set_vbi_source(VbiSourceType source); +int sc1200_set_vbi_lines(unsigned long even, unsigned long odd); +int sc1200_set_vbi_total(unsigned long even, unsigned long odd); +int sc1200_set_video_interlaced(int enable); +int sc1200_set_color_space_YUV(int enable); +int sc1200_set_vertical_scaler_offset(char offset); +int sc1200_set_top_line_in_odd(int enable); +int sc1200_set_genlock_delay(unsigned long delay); +int sc1200_set_genlock_enable(int flags); +int sc1200_set_video_cursor(unsigned long key, unsigned long mask, unsigned short select_color2, + unsigned long color1, unsigned long color2); +int sc1200_set_video_request(short x, short y); + +int sc1200_select_alpha_region(int region); +int sc1200_set_alpha_enable(int enable); +int sc1200_set_alpha_window(short x, short y, + unsigned short width, unsigned short height); +int sc1200_set_alpha_value(unsigned char alpha, char delta); +int sc1200_set_alpha_priority(int priority); +int sc1200_set_alpha_color(unsigned long color); +int sc1200_set_alpha_color_enable(int enable); +int sc1200_set_no_ck_outside_alpha(int enable); +int sc1200_disable_softvga(void); +int sc1200_enable_softvga(void); +int sc1200_set_macrovision_enable(int enable); +unsigned long sc1200_get_max_video_width(void); + +/* READ ROUTINES IN GFX_VID.C */ + +int sc1200_get_video_enable(void); +int sc1200_get_video_format(void); +unsigned long sc1200_get_video_src_size(void); +unsigned long sc1200_get_video_line_size(void); +unsigned long sc1200_get_video_xclip(void); +unsigned long sc1200_get_video_offset(void); +unsigned long sc1200_get_video_upscale(void); +unsigned long sc1200_get_video_scale(void); +int sc1200_get_video_downscale_config(unsigned short *type, unsigned short *m); +void sc1200_get_video_downscale_coefficients(unsigned short *coef1, unsigned short *coef2, + unsigned short *coef3, unsigned short *coef4); +void sc1200_get_video_downscale_enable(int *enable); +unsigned long sc1200_get_video_dst_size(void); +unsigned long sc1200_get_video_position(void); +unsigned long sc1200_get_video_color_key(void); +unsigned long sc1200_get_video_color_key_mask(void); +int sc1200_get_video_palette_entry(unsigned long index, unsigned long *palette); +int sc1200_get_video_color_key_src(void); +int sc1200_get_video_filter(void); +int sc1200_get_video_request(short *x, short *y); +int sc1200_get_video_source(VideoSourceType *source); +int sc1200_get_vbi_source(VbiSourceType *source); +unsigned long sc1200_get_vbi_lines(int odd); +unsigned long sc1200_get_vbi_total(int odd); +int sc1200_get_video_interlaced(void); +int sc1200_get_color_space_YUV(void); +int sc1200_get_vertical_scaler_offset(char *offset); +unsigned long sc1200_get_genlock_delay(void); +int sc1200_get_genlock_enable(void); +int sc1200_get_video_cursor(unsigned long *key, unsigned long *mask, unsigned short *select_color2, + unsigned long *color1, unsigned short *color2); +unsigned long sc1200_read_crc(void); +int sc1200_get_macrovision_enable(void); + +void sc1200_get_alpha_enable(int *enable); +void sc1200_get_alpha_size(unsigned short *x, unsigned short *y, + unsigned short *width, unsigned short *height); +void sc1200_get_alpha_value(unsigned char *alpha, char *delta); +void sc1200_get_alpha_priority(int *priority); +void sc1200_get_alpha_color(unsigned long *color); +#endif +#endif + +/*-------------------------*/ +/* REDCLOUD VIDEO ROUTINES */ +/*-------------------------*/ + +#if GFX_VIDEO_REDCLOUD + +/* PRIVATE ROUTINES */ + +/* DYNAMIC ROUTINES */ + +#if GFX_VIDEO_DYNAMIC +void redcloud_reset_video(void); +int redcloud_set_display_control(int sync_polarities); +void redcloud_set_clock_frequency(unsigned long frequency); +unsigned long redcloud_get_clock_frequency(void); +int redcloud_set_crt_enable(int enable); +int redcloud_get_sync_polarities(void); +int redcloud_set_video_enable(int enable); +int redcloud_set_video_format(unsigned long format); +int redcloud_set_video_size(unsigned short width, unsigned short height); +int redcloud_set_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch); +int redcloud_set_video_offset(unsigned long offset); +int redcloud_set_video_yuv_offsets (unsigned long yoffset, unsigned long uoffset, + unsigned long voffset); +int redcloud_set_video_window(short x, short y, unsigned short w, unsigned short h); +int redcloud_set_video_left_crop(unsigned short x); +int redcloud_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth); +int redcloud_set_video_vertical_downscale(unsigned short srch, unsigned short dsth); +void redcloud_set_video_vertical_downscale_enable (int enable); +int redcloud_set_video_downscale_config(unsigned short type, unsigned short m); +int redcloud_set_video_color_key(unsigned long key, unsigned long mask, + int bluescreen); +int redcloud_set_video_filter(int xfilter, int yfilter); +int redcloud_set_video_palette(unsigned long *palette); +int redcloud_set_graphics_palette(unsigned long *palette); +int redcloud_set_video_palette_bypass (int enable); +int redcloud_set_video_palette_entry (unsigned long index, unsigned long color); +int redcloud_set_graphics_palette_entry (unsigned long index, unsigned long color); +int redcloud_set_video_downscale_coefficients(unsigned short coef1, unsigned short coef2, + unsigned short coef3, unsigned short coef4) ; +int redcloud_set_video_downscale_enable(int enable); +int redcloud_set_video_cursor(unsigned long key, unsigned long mask, unsigned short select_color2, + unsigned long color1, unsigned long color2); +int redcloud_set_video_cursor_enable (int enable); + +int redcloud_select_alpha_region(int region); +int redcloud_set_alpha_enable(int enable); +int redcloud_set_alpha_window(short x, short y, + unsigned short width, unsigned short height); +int redcloud_set_alpha_value(unsigned char alpha, char delta); +int redcloud_set_alpha_priority(int priority); +int redcloud_set_alpha_color(unsigned long color); +int redcloud_set_alpha_color_enable(int enable); +int redcloud_set_no_ck_outside_alpha(int enable); +int redcloud_set_video_request(short x, short y); + +/* READ ROUTINES IN GFX_VID.C */ + +int redcloud_get_video_enable(void); +int redcloud_get_video_format(void); +unsigned long redcloud_get_video_src_size(void); +unsigned long redcloud_get_video_line_size(void); +unsigned long redcloud_get_video_xclip(void); +unsigned long redcloud_get_video_offset(void); +void redcloud_get_video_yuv_offsets (unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset); +void redcloud_get_video_yuv_pitch (unsigned long *ypitch, unsigned long *uvpitch); +unsigned long redcloud_get_video_scale(void); +unsigned long redcloud_get_video_downscale_delta(void); +int redcloud_get_video_vertical_downscale_enable (void); +int redcloud_get_video_downscale_config(unsigned short *type, unsigned short *m); +void redcloud_get_video_downscale_coefficients(unsigned short *coef1, unsigned short *coef2, + unsigned short *coef3, unsigned short *coef4); +void redcloud_get_video_downscale_enable(int *enable); +unsigned long redcloud_get_video_dst_size(void); +unsigned long redcloud_get_video_position(void); +unsigned long redcloud_get_video_color_key(void); +unsigned long redcloud_get_video_color_key_mask(void); +int redcloud_get_video_palette_entry(unsigned long index, unsigned long *palette); +int redcloud_get_video_color_key_src(void); +int redcloud_get_video_filter(void); +int redcloud_get_video_cursor(unsigned long *key, unsigned long *mask, unsigned short *select_color2, + unsigned long *color1, unsigned short *color2); +unsigned long redcloud_read_crc(void); +unsigned long redcloud_read_crc32(void); +unsigned long redcloud_read_window_crc(int source, unsigned short x, unsigned short y, + unsigned short width, unsigned short height, int crc32); + +void redcloud_get_alpha_enable(int *enable); +void redcloud_get_alpha_size(unsigned short *x, unsigned short *y, + unsigned short *width, unsigned short *height); +void redcloud_get_alpha_value(unsigned char *alpha, char *delta); +void redcloud_get_alpha_priority(int *priority); +void redcloud_get_alpha_color(unsigned long *color); +int redcloud_get_video_request(short *x, short *y); +#endif +#endif + +/*--------------*/ +/* VIP ROUTINES */ +/*--------------*/ + +#if GFX_VIP_SC1200 + +/* DYNAMIC ROUTINES */ + +#if GFX_VIP_DYNAMIC +int sc1200_set_vip_enable(int enable); +int sc1200_set_vip_capture_run_mode(int mode); +int sc1200_set_vip_base(unsigned long even, unsigned long odd); +int sc1200_set_vip_pitch(unsigned long pitch); +int sc1200_set_vip_mode(int mode); +int sc1200_set_vbi_enable(int enable); +int sc1200_set_vbi_mode(int mode); +int sc1200_set_vbi_base(unsigned long even, unsigned long odd); +int sc1200_set_vbi_pitch(unsigned long pitch); +int sc1200_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines); +int sc1200_set_vbi_interrupt(int enable); +int sc1200_set_vip_bus_request_threshold_high(int enable); +int sc1200_set_vip_last_line(int last_line); +int sc1200_test_vip_odd_field(void); +int sc1200_test_vip_bases_updated(void); +int sc1200_test_vip_fifo_overflow(void); +int sc1200_get_vip_line(void); +int sc1200_get_vip_enable(void); +unsigned long sc1200_get_vip_base(int odd); +unsigned long sc1200_get_vip_pitch(void); +int sc1200_get_vip_mode(void); +int sc1200_get_vbi_enable(void); +int sc1200_get_vbi_mode(void); +unsigned long sc1200_get_vbi_base(int odd); +unsigned long sc1200_get_vbi_pitch(void); +unsigned long sc1200_get_vbi_direct(int odd); +int sc1200_get_vbi_interrupt(void); +int sc1200_get_vip_bus_request_threshold_high(void); +#endif +#endif + +/* DECODER ROUTINES */ + +#if GFX_DECODER_SAA7114 + +/* PRIVATE ROUTINES */ + +int saa7114_write_reg(unsigned char reg, unsigned char val); +int saa7114_read_reg(unsigned char reg, unsigned char * val); + +/* DYNAMIC ROUTINES */ + +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_defaults(void); +int saa7114_set_decoder_analog_input(unsigned char input); +int saa7114_set_decoder_brightness(unsigned char brightness); +int saa7114_set_decoder_contrast(unsigned char contrast); +int saa7114_set_decoder_hue(char hue); +int saa7114_set_decoder_saturation(unsigned char saturation); +int saa7114_set_decoder_input_offset(unsigned short x, unsigned short y); +int saa7114_set_decoder_input_size(unsigned short width, unsigned short height); +int saa7114_set_decoder_output_size(unsigned short width, unsigned short height); +int saa7114_set_decoder_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth); +int saa7114_set_decoder_vbi_format(int start, int end, int format); +int saa7114_set_decoder_vbi_enable(int enable); +int saa7114_set_decoder_vbi_upscale(void); +int saa7114_set_decoder_TV_standard(TVStandardType TVStandard); +int saa7114_set_decoder_luminance_filter(unsigned char lufi); +int saa7114_decoder_software_reset(void); +int saa7114_decoder_detect_macrovision(void); +int saa7114_decoder_detect_video(void); +unsigned char saa7114_get_decoder_brightness(void); +unsigned char saa7114_get_decoder_contrast(void); +char saa7114_get_decoder_hue(void); +unsigned char saa7114_get_decoder_saturation(void); +unsigned long saa7114_get_decoder_input_offset(void); +unsigned long saa7114_get_decoder_input_size(void); +unsigned long saa7114_get_decoder_output_size(void); +int saa7114_get_decoder_vbi_format(int line); +#endif +#endif + +/* ACCESS I2C ROUTINES */ + +#if GFX_I2C_ACCESS + +#if GFX_I2C_DYNAMIC +int acc_i2c_reset(unsigned char busnum, short adr, char freq); +int acc_i2c_write(unsigned char busnum, unsigned char chipadr, unsigned char subadr, + unsigned char bytes, unsigned char * data); +int acc_i2c_read(unsigned char busnum, unsigned char chipadr, unsigned char subadr, + unsigned char bytes, unsigned char * data); +int acc_i2c_select_gpio(int clock, int data); +int acc_i2c_init(void); +void acc_i2c_cleanup(void); +#endif +#endif + +/* GPIO I2C ROUTINES */ + +#if GFX_I2C_GPIO + +#if GFX_I2C_DYNAMIC +int gpio_i2c_reset(unsigned char busnum, short adr, char freq); +int gpio_i2c_write(unsigned char busnum, unsigned char chipadr, unsigned char subadr, + unsigned char bytes, unsigned char * data); +int gpio_i2c_read(unsigned char busnum, unsigned char chipadr, unsigned char subadr, + unsigned char bytes, unsigned char * data); +int gpio_i2c_select_gpio(int clock, int data); +int gpio_i2c_init(void); +void gpio_i2c_cleanup(void); +#endif +#endif + +/* TV ROUTINES */ + +#if GFX_TV_SC1200 + +#if GFX_TV_DYNAMIC +int sc1200_set_tv_format(TVStandardType format, GfxOnTVType resolution); +int sc1200_set_tv_output(int output); +int sc1200_set_tv_enable(int enable); +int sc1200_set_tv_flicker_filter(int ff); +int sc1200_set_tv_sub_carrier_reset(int screset); +int sc1200_set_tv_vphase(int vphase); +int sc1200_set_tv_YC_delay(int delay); +int sc1200_set_tvenc_reset_interval(int interval); +int sc1200_set_tv_cc_enable(int enable); +int sc1200_set_tv_cc_data(unsigned char data1, unsigned char data2); +int sc1200_set_tv_display(int width, int height); +int sc1200_test_tvout_odd_field(void); +int sc1200_test_tvenc_odd_field(void); +int sc1200_set_tv_field_status_invert(int enable); +int sc1200_get_tv_vphase(void); +int sc1200_get_tv_enable(unsigned int *p_on); +int sc1200_get_tv_output(void); +int sc1200_get_tv_mode_count(TVStandardType format); +int sc1200_get_tv_display_mode (int *width, int *height, int *bpp, int *hz); +int sc1200_get_tv_display_mode_frequency (unsigned short width, unsigned short height, TVStandardType format, int *frequency); +int sc1200_is_tv_display_mode_supported (unsigned short width, unsigned short height, TVStandardType format); +unsigned char cc_add_parity_bit(unsigned char data); + +#endif +#endif + + +/* FS450 ROUTINES */ + +#if GFX_TV_FS451 + +#if GFX_TV_DYNAMIC +int fs450_set_tv_format(TVStandardType format, GfxOnTVType resolution); +int fs450_set_tv_output(int output); +int fs450_set_tv_enable(int enable); +int fs450_get_tv_standard(unsigned long *p_standard); +int fs450_get_available_tv_standards(unsigned long *p_standards); +int fs450_set_tv_standard(unsigned long standard); +int fs450_get_tv_vga_mode(unsigned long *p_vga_mode); +int fs450_get_available_tv_vga_modes(unsigned long *p_vga_modes); +int fs450_set_tv_vga_mode(unsigned long vga_mode); +int fs450_get_tvout_mode(unsigned long *p_tvout_mode); +int fs450_set_tvout_mode(unsigned long tvout_mode); +int fs450_get_sharpness(int *p_sharpness); +int fs450_set_sharpness(int sharpness); +int fs450_get_flicker_filter(int *p_flicker); +int fs450_set_flicker_filter(int flicker); +int fs450_get_overscan(int *p_x, int *p_y); +int fs450_set_overscan(int x, int y); +int fs450_get_position(int *p_x, int *p_y); +int fs450_set_position(int x, int y); +int fs450_get_color(int *p_color); +int fs450_set_color(int color); +int fs450_get_brightness(int *p_brightness); +int fs450_set_brightness(int brightness); +int fs450_get_contrast(int *p_contrast); +int fs450_set_contrast(int constrast); +int fs450_get_yc_filter(unsigned int *p_yc_filter); +int fs450_set_yc_filter(unsigned int yc_filter); +int fs450_get_aps_trigger_bits(unsigned int *p_trigger_bits); +int fs450_set_aps_trigger_bits(unsigned int trigger_bits); +#endif +#endif --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/saa7114.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/saa7114.c 2005-12-14 11:29:42.000000000 -0700 @@ -0,0 +1,817 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to control the Philips SAA7114 video decoder. + * */ + + +/*---------------------------*/ +/* TABLE OF DEFAULT VALUES */ +/*---------------------------*/ + +typedef struct tagGFX_SAA7114_INIT +{ + unsigned char index; + unsigned char value; +} GFX_SAA7114_INIT; + +/* Task A is for VBI raw data and task B is for video */ + +GFX_SAA7114_INIT gfx_saa7114_init_values[] = { + { 0x01, 0x08 }, { 0x02, 0xC0 }, { 0x03, 0x00 }, { 0x04, 0x90 }, + { 0x05, 0x90 }, { 0x06, 0xEB }, { 0x07, 0xE0 }, { 0x08, 0x88 }, + { 0x09, 0x40 }, { 0x0A, 0x80 }, { 0x0B, 0x44 }, { 0x0C, 0x40 }, + { 0x0D, 0x00 }, { 0x0E, 0x89 }, { 0x0F, 0x2E }, { 0x10, 0x0E }, + { 0x11, 0x00 }, { 0x12, 0x05 }, { 0x13, 0x00 }, { 0x14, 0x08 }, + { 0x15, 0x11 }, { 0x16, 0xFE }, { 0x17, 0x00 }, { 0x18, 0x40 }, + { 0x19, 0x80 }, { 0x30, 0xBC }, { 0x31, 0xDF }, { 0x32, 0x02 }, + { 0x34, 0xCD }, { 0x35, 0xCC }, { 0x36, 0x3A }, { 0x38, 0x03 }, + { 0x39, 0x10 }, { 0x3A, 0x00 }, { 0x40, 0x00 }, { 0x41, 0xFF }, + { 0x42, 0xFF }, { 0x43, 0xFF }, { 0x44, 0xFF }, { 0x45, 0xFF }, + { 0x46, 0xFF }, { 0x47, 0xFF }, { 0x48, 0xFF }, { 0x49, 0xFF }, + { 0x4A, 0xFF }, { 0x4B, 0xFF }, { 0x4C, 0xFF }, { 0x4D, 0xFF }, + { 0x4E, 0xFF }, { 0x4F, 0xFF }, { 0x50, 0xFF }, { 0x51, 0xFF }, + { 0x52, 0xFF }, { 0x53, 0xFF }, { 0x54, 0xFF }, { 0x55, 0xFF }, + { 0x56, 0xFF }, { 0x57, 0xFF }, { 0x58, 0x00 }, { 0x59, 0x47 }, + { 0x5A, 0x06 }, { 0x5B, 0x43 }, { 0x5D, 0x3E }, { 0x5E, 0x00 }, + { 0x80, 0x30 }, { 0x83, 0x00 }, { 0x84, 0x60 }, { 0x85, 0x00 }, + { 0x86, 0xE5 }, { 0x87, 0x01 }, { 0x88, 0xF8 }, + + /* VBI task */ + + { 0x90, 0x01 }, { 0x91, 0xC8 }, { 0x92, 0x08 }, { 0x93, 0x84 }, + { 0x94, 0x10 }, { 0x95, 0x00 }, { 0x96, 0xD0 }, { 0x97, 0x02 }, + { 0x98, 0x05 }, { 0x99, 0x00 }, { 0x9A, 0x0B }, { 0x9B, 0x00 }, + { 0x9C, 0xA0 }, { 0x9D, 0x05 }, { 0x9E, 0x0B }, { 0x9F, 0x00 }, + { 0xA0, 0x01 }, { 0xA1, 0x00 }, { 0xA2, 0x00 }, { 0xA4, 0x80 }, + { 0xA5, 0x40 }, { 0xA6, 0x40 }, { 0xA8, 0x00 }, { 0xA9, 0x02 }, + { 0xAA, 0x00 }, { 0xAC, 0x00 }, { 0xAD, 0x01 }, { 0xAE, 0x00 }, + { 0xB0, 0x00 }, { 0xB1, 0x04 }, { 0xB2, 0x00 }, { 0xB3, 0x04 }, + { 0xB4, 0x00 }, { 0xB8, 0x00 }, { 0xB9, 0x00 }, { 0xBA, 0x00 }, + { 0xBB, 0x00 }, { 0xBC, 0x00 }, { 0xBD, 0x00 }, { 0xBE, 0x00 }, + { 0xBF, 0x00 }, + + /* Video task */ + + { 0xC0, 0x80 }, { 0xC1, 0x08 }, { 0xC2, 0x00 }, { 0xC3, 0x80 }, + { 0xC4, 0x10 }, { 0xC5, 0x00 }, { 0xC6, 0xD0 }, { 0xC7, 0x02 }, + { 0xC8, 0x11 }, { 0xC9, 0x00 }, { 0xCA, 0xF1 }, { 0xCB, 0x00 }, + { 0xCC, 0xD0 }, { 0xCD, 0x02 }, { 0xCE, 0xF1 }, { 0xCF, 0x00 }, + { 0xD0, 0x01 }, { 0xD1, 0x00 }, { 0xD2, 0x00 }, { 0xD4, 0x80 }, + { 0xD5, 0x40 }, { 0xD6, 0x40 }, { 0xD8, 0x00 }, { 0xD9, 0x04 }, + { 0xDA, 0x00 }, { 0xDC, 0x00 }, { 0xDD, 0x02 }, { 0xDE, 0x00 }, + { 0xE0, 0x00 }, { 0xE1, 0x04 }, { 0xE2, 0x00 }, { 0xE3, 0x04 }, + { 0xE4, 0x00 }, { 0xE8, 0x00 }, { 0xE9, 0x00 }, { 0xEA, 0x00 }, + { 0xEB, 0x00 }, { 0xEC, 0x00 }, { 0xED, 0x00 }, { 0xEE, 0x00 }, + { 0xEF, 0x00 }, +}; + +#define GFX_NUM_SAA7114_INIT_VALUES sizeof(gfx_saa7114_init_values)/sizeof(GFX_SAA7114_INIT) + +/*-----------------------------------------------------*/ +/* TABLE OF FIR PREFILTER RECOMMENDED VALUES */ +/*-----------------------------------------------------*/ + +int optimize_for_aliasing = 0; + +typedef struct tagGFX_SAA7114_FIR_PREFILTER +{ + unsigned char prescaler; + unsigned char acl_low; + unsigned char prefilter_low; + unsigned char acl_high; + unsigned char prefilter_high; +} GFX_SAA7114_FIR_PREFILTER; + +GFX_SAA7114_FIR_PREFILTER gfx_saa7114_fir_values[] = { + { 0x01, 0x00, 0x00, 0x00, 0x00 }, { 0x02, 0x02, 0x5A, 0x01, 0x51 }, + { 0x03, 0x04, 0xAB, 0x03, 0xA2 }, { 0x04, 0x07, 0xA3, 0x04, 0xAB }, + { 0x05, 0x08, 0xAC, 0x07, 0xA3 }, { 0x06, 0x08, 0xFC, 0x07, 0xF3 }, + { 0x07, 0x08, 0xFC, 0x07, 0xF3 }, { 0x08, 0x0F, 0xF4, 0x08, 0xFC }, + { 0x09, 0x0F, 0xF4, 0x08, 0xFC }, { 0x0A, 0x10, 0xFD, 0x08, 0xFC }, + { 0x0B, 0x10, 0xFD, 0x08, 0xFC }, { 0x0C, 0x10, 0xFD, 0x08, 0xFC }, + { 0x0D, 0x10, 0xFD, 0x10, 0xFD }, { 0x0E, 0x10, 0xFD, 0x10, 0xFD }, + { 0x0F, 0x1F, 0xF5, 0x10, 0xFD }, { 0x10, 0x20, 0xFE, 0x10, 0xFD }, + { 0x11, 0x20, 0xFE, 0x10, 0xFD }, { 0x12, 0x20, 0xFE, 0x10, 0xFD }, + { 0x13, 0x20, 0xFE, 0x20, 0xFE }, { 0x14, 0x20, 0xFE, 0x20, 0xFE }, + { 0x15, 0x20, 0xFE, 0x20, 0xFE }, { 0x16, 0x20, 0xFE, 0x20, 0xFE }, + { 0x17, 0x20, 0xFE, 0x20, 0xFE }, { 0x18, 0x20, 0xFE, 0x20, 0xFE }, + { 0x19, 0x20, 0xFE, 0x20, 0xFE }, { 0x1A, 0x20, 0xFE, 0x20, 0xFE }, + { 0x1B, 0x20, 0xFE, 0x20, 0xFE }, { 0x1C, 0x20, 0xFE, 0x20, 0xFE }, + { 0x1D, 0x20, 0xFE, 0x20, 0xFE }, { 0x1E, 0x20, 0xFE, 0x20, 0xFE }, + { 0x1F, 0x20, 0xFE, 0x20, 0xFE }, { 0x20, 0x3F, 0xFF, 0x20, 0xFE }, + { 0x21, 0x3F, 0xFF, 0x20, 0xFE }, { 0x22, 0x3F, 0xFF, 0x20, 0xFE }, + { 0x23, 0x3F, 0xFF, 0x20, 0xFF } +}; + +int saa7114_write_reg(unsigned char reg, unsigned char val) +{ + return gfx_i2c_write(2, SAA7114_CHIPADDR, reg, 1, &val); +} + +int saa7114_read_reg(unsigned char reg, unsigned char * val) +{ + return gfx_i2c_read(2, SAA7114_CHIPADDR, reg, 1, val); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_vbi_upscale + * + * This routine configures the video decoder task A to upscale raw VBI data + * horizontally to match a different system clock. + * The upscale is from 13.5 MHz (SAA7114) to 14.318 MHz (Bt835). + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_vbi_upscale(void) +#else +int gfx_set_decoder_vbi_upscale(void) +#endif +{ + /* Set horizontal output length to 1528 (720 * 2 * 14.318 / 13.5) */ + saa7114_write_reg(SAA7114_TASK_A_HORZ_OUTPUT_LO, 0xF8); + saa7114_write_reg(SAA7114_TASK_A_HORZ_OUTPUT_HI, 0x05); + + /* Set horizontal luminance scaling increment to 484 (1024 * 13.5 / 28.636) */ + saa7114_write_reg(SAA7114_TASK_A_HSCALE_LUMA_LO, 0xE4); + saa7114_write_reg(SAA7114_TASK_A_HSCALE_LUMA_HI, 0x01); + + /* Set horizontal chrominance scaling increment to 242 */ + saa7114_write_reg(SAA7114_TASK_A_HSCALE_CHROMA_LO, 0xF2); + saa7114_write_reg(SAA7114_TASK_A_HSCALE_CHROMA_HI, 0x00); + + return GFX_STATUS_OK; +} + +/*----------------------------------------------------------------------------- + * gfx_decoder_software_reset + * + * This routine performs a software reset of the decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_decoder_software_reset(void) +#else +int gfx_decoder_software_reset(void) +#endif +{ + saa7114_write_reg(0x88, 0xC0); + /* I2C-bus latency should be sufficient for resetting the internal state machine. */ + /* gfx_delay_milliseconds(10); */ + saa7114_write_reg(0x88, 0xF0); + return GFX_STATUS_OK; +} + +/*----------------------------------------------------------------------------- + * gfx_decoder_detect_macrovision + * + * This routine detects if macrovision exists in the input of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_decoder_detect_macrovision(void) +#else +int gfx_decoder_detect_macrovision(void) +#endif +{ + unsigned char macrovision = 0xff; + saa7114_read_reg(SAA7114_STATUS, ¯ovision); + return ((macrovision & 0x02) >> 1); +} + +/*----------------------------------------------------------------------------- + * gfx_decoder_detect_video + * + * This routine detects if video exists in the input of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_decoder_detect_video(void) +#else +int gfx_decoder_detect_video(void) +#endif +{ + unsigned char video = 0xff; + saa7114_read_reg(SAA7114_STATUS, &video); + return !((video & 0x40) >> 6); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_defaults + * + * This routine is called to set the initial register values of the + * video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_defaults(void) +#else +int gfx_set_decoder_defaults(void) +#endif +{ + unsigned int i; + + /* LOOP THROUGH INDEX/DATA PAIRS IN THE TABLE */ + + for (i = 0; i < GFX_NUM_SAA7114_INIT_VALUES; i++) + { + saa7114_write_reg(gfx_saa7114_init_values[i].index, + gfx_saa7114_init_values[i].value); + } + + gfx_decoder_software_reset(); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_analog_input + * + * This routine sets the analog input of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_analog_input(unsigned char input) +#else +int gfx_set_decoder_analog_input(unsigned char input) +#endif +{ + saa7114_write_reg(SAA7114_ANALOG_INPUT_CTRL1, input); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_brightness + * + * This routine sets the brightness of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_brightness(unsigned char brightness) +#else +int gfx_set_decoder_brightness(unsigned char brightness) +#endif +{ + saa7114_write_reg(SAA7114_BRIGHTNESS, brightness); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_contrast + * + * This routine sets the contrast of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_contrast(unsigned char contrast) +#else +int gfx_set_decoder_contrast(unsigned char contrast) +#endif +{ + saa7114_write_reg(SAA7114_CONTRAST, (unsigned char) (contrast >> 1)); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_hue + * + * This routine sets the hue control of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_hue(char hue) +#else +int gfx_set_decoder_hue(char hue) +#endif +{ + saa7114_write_reg(SAA7114_HUE, (unsigned char) hue); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_saturation + * + * This routine sets the saturation adjustment of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_saturation(unsigned char saturation) +#else +int gfx_set_decoder_saturation(unsigned char saturation) +#endif +{ + saa7114_write_reg(SAA7114_SATURATION, (unsigned char) (saturation >> 1)); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_input_offset + * + * This routine sets the size of the decoder input window. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_input_offset(unsigned short x, unsigned short y) +#else +int gfx_set_decoder_input_offset(unsigned short x, unsigned short y) +#endif +{ + /* SET THE INPUT WINDOW OFFSET */ + + saa7114_write_reg(SAA7114_HORZ_OFFSET_LO, (unsigned char) (x & 0x00FF)); + saa7114_write_reg(SAA7114_HORZ_OFFSET_HI, (unsigned char) (x >> 8)); + saa7114_write_reg(SAA7114_VERT_OFFSET_LO, (unsigned char) (y & 0x00FF)); + saa7114_write_reg(SAA7114_VERT_OFFSET_HI, (unsigned char) (y >> 8)); + + gfx_decoder_software_reset(); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_input_size + * + * This routine sets the size of the decoder input window. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_input_size(unsigned short width, unsigned short height) +#else +int gfx_set_decoder_input_size(unsigned short width, unsigned short height) +#endif +{ + /* DIVIDE HEIGHT BY TWO FOR INTERLACING */ + + height = (height + 1) >> 1; + + /* SET THE INPUT WINDOW SIZE */ + + saa7114_write_reg(SAA7114_HORZ_INPUT_LO, (unsigned char) (width & 0x00FF)); + saa7114_write_reg(SAA7114_HORZ_INPUT_HI, (unsigned char) (width >> 8)); + saa7114_write_reg(SAA7114_VERT_INPUT_LO, (unsigned char) (height & 0x00FF)); + saa7114_write_reg(SAA7114_VERT_INPUT_HI, (unsigned char) (height >> 8)); + + gfx_decoder_software_reset(); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_output_size + * + * This routine sets the size of the decoder output window. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_output_size(unsigned short width, unsigned short height) +#else +int gfx_set_decoder_output_size(unsigned short width, unsigned short height) +#endif +{ + /* ROUND WIDTH UP TO EVEN NUMBER TO PREVENT DECODER BECOMING STUCK */ + + width = ((width + 1) >> 1) << 1; + + /* DIVIDE HEIGHT BY TWO FOR INTERLACING */ + + height = (height + 1) >> 1; + + /* SET THE OUTPUT WINDOW SIZE */ + + saa7114_write_reg(SAA7114_HORZ_OUTPUT_LO, (unsigned char) (width & 0x00FF)); + saa7114_write_reg(SAA7114_HORZ_OUTPUT_HI, (unsigned char) (width >> 8)); + saa7114_write_reg(SAA7114_VERT_OUTPUT_LO, (unsigned char) (height & 0x00FF)); + saa7114_write_reg(SAA7114_VERT_OUTPUT_HI, (unsigned char) (height >> 8)); + + gfx_decoder_software_reset(); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_scale + * + * This routine sets the scaling of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +#else +int gfx_set_decoder_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +#endif +{ + unsigned char prescale = 0; + int scale = 0; + + /* SET THE HORIZONTAL PRESCALE */ + /* Downscale from 1 to 1/63 source size. */ + + if (dstw) prescale = (unsigned char) (srcw/dstw); + if (!prescale) prescale = 1; + if (prescale > 63) return(1); + saa7114_write_reg(SAA7114_HORZ_PRESCALER, prescale); + + /* USE FIR PREFILTER FUNCTIONALITY (OPTIMISATION) */ + + if ( prescale < 36 ) { + if (optimize_for_aliasing) { + saa7114_write_reg(SAA7114_HORZ_ACL, + gfx_saa7114_fir_values[prescale-1].acl_low ); + saa7114_write_reg(SAA7114_HORZ_FIR_PREFILTER, + gfx_saa7114_fir_values[prescale-1].prefilter_low ); + } else { + saa7114_write_reg(SAA7114_HORZ_ACL, + gfx_saa7114_fir_values[prescale-1].acl_high ); + saa7114_write_reg(SAA7114_HORZ_FIR_PREFILTER, + gfx_saa7114_fir_values[prescale-1].prefilter_high ); + } + } else { + /* SAME SETTINGS FOR RATIO 1/35 DOWNTO 1/63 */ + if (optimize_for_aliasing) { + saa7114_write_reg(SAA7114_HORZ_ACL, + gfx_saa7114_fir_values[34].acl_low ); + saa7114_write_reg(SAA7114_HORZ_FIR_PREFILTER, + gfx_saa7114_fir_values[34].prefilter_low ); + } else { + saa7114_write_reg(SAA7114_HORZ_ACL, + gfx_saa7114_fir_values[34].acl_high ); + saa7114_write_reg(SAA7114_HORZ_FIR_PREFILTER, + gfx_saa7114_fir_values[34].prefilter_high ); + } + } + + /* SET THE HORIZONTAL SCALING */ + + if (!dstw) return(1); + scale = ( (1024 * srcw * 1000) / (dstw * prescale) ) / 1000; + if ((scale > 8191) || (scale < 300)) return(1); + saa7114_write_reg(SAA7114_HSCALE_LUMA_LO, (unsigned char) (scale & 0x00FF)); + saa7114_write_reg(SAA7114_HSCALE_LUMA_HI, (unsigned char) (scale >> 8)); + scale >>= 1; + saa7114_write_reg(SAA7114_HSCALE_CHROMA_LO, (unsigned char) (scale & 0x00FF)); + saa7114_write_reg(SAA7114_HSCALE_CHROMA_HI, (unsigned char) (scale >> 8)); + + /* SET THE VERTICAL SCALING (INTERPOLATION MODE) */ + + if (!dsth) return(1); + + /* ROUND DESTINATION HEIGHT UP TO EVEN NUMBER TO PREVENT DECODER BECOMING STUCK */ + + dsth = ((dsth + 1) >> 1) << 1; + + scale = (int)((1024 * srch) / dsth); + saa7114_write_reg(SAA7114_VSCALE_LUMA_LO, (unsigned char) (scale & 0x00FF)); + saa7114_write_reg(SAA7114_VSCALE_LUMA_HI, (unsigned char) (scale >> 8)); + saa7114_write_reg(SAA7114_VSCALE_CHROMA_LO, (unsigned char) (scale & 0x00FF)); + saa7114_write_reg(SAA7114_VSCALE_CHROMA_HI, (unsigned char) (scale >> 8)); + + if (dsth >= (srch >> 1)) + { + /* USE INTERPOLATION MODE FOR SCALE FACTOR ABOVE 0.5 */ + + saa7114_write_reg(SAA7114_VSCALE_CONTROL, 0x00); + + /* SET VERTICAL PHASE REGISTER FOR CORRECT SCALED INTERLACED OUTPUT (OPTIMISATION) */ + /* THE OPTIMISATION IS BASED ON OFIDC = 0 (REG 90h[6] = 0 ) */ + saa7114_write_reg(SAA7114_VSCALE_CHROMA_OFFS0, SAA7114_VSCALE_PHO ); + saa7114_write_reg(SAA7114_VSCALE_CHROMA_OFFS1, SAA7114_VSCALE_PHO ); + saa7114_write_reg(SAA7114_VSCALE_CHROMA_OFFS2, (unsigned char)(SAA7114_VSCALE_PHO+scale/64-16) ); + saa7114_write_reg(SAA7114_VSCALE_CHROMA_OFFS3, (unsigned char)(SAA7114_VSCALE_PHO+scale/64-16) ); + + saa7114_write_reg(SAA7114_VSCALE_LUMINA_OFFS0, SAA7114_VSCALE_PHO ); + saa7114_write_reg(SAA7114_VSCALE_LUMINA_OFFS1, SAA7114_VSCALE_PHO ); + saa7114_write_reg(SAA7114_VSCALE_LUMINA_OFFS2, (unsigned char)(SAA7114_VSCALE_PHO+scale/64-16) ); + saa7114_write_reg(SAA7114_VSCALE_LUMINA_OFFS3, (unsigned char)(SAA7114_VSCALE_PHO+scale/64-16) ); + + /* RESTORE CONTRAST AND SATURATION FOR INTERPOLATION MODE */ + + saa7114_write_reg(SAA7114_FILTER_CONTRAST, (unsigned char) 0x40); + saa7114_write_reg(SAA7114_FILTER_SATURATION, (unsigned char) 0x40); + } + else + { + /* USE ACCUMULATION MODE FOR DOWNSCALING BY MORE THAN 2x */ + + saa7114_write_reg(SAA7114_VSCALE_CONTROL, 0x01); + + /* SET VERTICAL PHASE OFFSETS OFF (OPTIMISATION) */ + saa7114_write_reg(SAA7114_VSCALE_CHROMA_OFFS0, 0x00 ); + saa7114_write_reg(SAA7114_VSCALE_CHROMA_OFFS1, 0x00 ); + saa7114_write_reg(SAA7114_VSCALE_CHROMA_OFFS2, 0x00 ); + saa7114_write_reg(SAA7114_VSCALE_CHROMA_OFFS3, 0x00 ); + + saa7114_write_reg(SAA7114_VSCALE_LUMINA_OFFS0, 0x00 ); + saa7114_write_reg(SAA7114_VSCALE_LUMINA_OFFS1, 0x00 ); + saa7114_write_reg(SAA7114_VSCALE_LUMINA_OFFS2, 0x00 ); + saa7114_write_reg(SAA7114_VSCALE_LUMINA_OFFS3, 0x00 ); + + /* ADJUST CONTRAST AND SATURATION FOR ACCUMULATION MODE */ + + if (srch) scale = (64 * dsth) / srch; + saa7114_write_reg(SAA7114_FILTER_CONTRAST, (unsigned char) scale); + saa7114_write_reg(SAA7114_FILTER_SATURATION, (unsigned char) scale); + } + + gfx_decoder_software_reset(); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_vbi_format + * + * This routine programs the decoder to produce the specified format of VBI + * data for the specified lines. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_vbi_format(int start, int end, int format) +#else +int gfx_set_decoder_vbi_format(int start, int end, int format) +#endif +{ + int i; + unsigned char data; + + for (i = start; i <= end; i++) + { + switch (format) + { + case VBI_FORMAT_VIDEO: data = 0xFF; break; /* Active video */ + case VBI_FORMAT_RAW: data = 0x77; break; /* Raw VBI data */ + case VBI_FORMAT_CC: data = 0x55; break; /* US CC */ + case VBI_FORMAT_NABTS: data = 0xCC; break; /* US NABTS */ + default: + return GFX_STATUS_BAD_PARAMETER; + } + saa7114_write_reg((unsigned char)(0x3F + i), data); + } + return GFX_STATUS_OK; +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_vbi_enable + * + * This routine enables or disables VBI transfer in the decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_vbi_enable(int enable) +#else +int gfx_set_decoder_vbi_enable(int enable) +#endif +{ + unsigned char data; + saa7114_read_reg(SAA7114_IPORT_CONTROL, &data); + if (enable) data |= 0x80; + else data &= ~0x80; + saa7114_write_reg(SAA7114_IPORT_CONTROL, data); + return GFX_STATUS_OK; +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_TV_standard + * + * This routine configures the decoder for the required TV standard. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_TV_standard(TVStandardType TVStandard) +#else +int gfx_set_decoder_TV_standard(TVStandardType TVStandard) +#endif +{ + switch (TVStandard) { + case TV_STANDARD_NTSC: + saa7114_write_reg(0x0E, 0x89); + saa7114_write_reg(0x5A, 0x06); + break; + case TV_STANDARD_PAL: + saa7114_write_reg(0x0E, 0x81); + saa7114_write_reg(0x5A, 0x03); + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + gfx_decoder_software_reset(); + return GFX_STATUS_OK; +} + +/*----------------------------------------------------------------------------- + * gfx_set_decoder_luminance_filter + * + * This routine sets the hue control of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_set_decoder_luminance_filter(unsigned char lufi) +#else +int gfx_set_decoder_luminance_filter(unsigned char lufi) +#endif +{ + unsigned char data; + saa7114_read_reg(SAA7114_LUMINANCE_CONTROL, &data); + saa7114_write_reg(SAA7114_LUMINANCE_CONTROL, (unsigned char)((data & ~0x0F) | (lufi & 0x0F))); + return(0); +} + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +#if GFX_READ_ROUTINES + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_brightness + * + * This routine returns the current brightness of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +unsigned char saa7114_get_decoder_brightness(void) +#else +unsigned char gfx_get_decoder_brightness(void) +#endif +{ + unsigned char brightness = 0; + saa7114_read_reg(SAA7114_BRIGHTNESS, &brightness); + return(brightness); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_contrast + * + * This routine returns the current contrast of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +unsigned char saa7114_get_decoder_contrast(void) +#else +unsigned char gfx_get_decoder_contrast(void) +#endif +{ + unsigned char contrast = 0; + saa7114_read_reg(SAA7114_CONTRAST, &contrast); + contrast <<= 1; + return(contrast); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_hue + * + * This routine returns the current hue of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +char saa7114_get_decoder_hue(void) +#else +char gfx_get_decoder_hue(void) +#endif +{ + unsigned char hue = 0; + saa7114_read_reg(SAA7114_HUE, &hue); + return((char)hue); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_saturation + * + * This routine returns the current saturation of the video decoder. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +unsigned char saa7114_get_decoder_saturation(void) +#else +unsigned char gfx_get_decoder_saturation(void) +#endif +{ + unsigned char saturation = 0; + saa7114_read_reg(SAA7114_SATURATION, &saturation); + saturation <<= 1; + return(saturation); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_input_offset + * + * This routine returns the offset into the input window. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +unsigned long saa7114_get_decoder_input_offset(void) +#else +unsigned long gfx_get_decoder_input_offset(void) +#endif +{ + unsigned long value = 0; + unsigned char data; + saa7114_read_reg(SAA7114_HORZ_OFFSET_LO, &data); + value = (unsigned long) data; + saa7114_read_reg(SAA7114_HORZ_OFFSET_HI, &data); + value |= ((unsigned long) data) << 8; + saa7114_read_reg(SAA7114_VERT_OFFSET_LO, &data); + value |= ((unsigned long) data) << 16; + saa7114_read_reg(SAA7114_VERT_OFFSET_HI, &data); + value |= ((unsigned long) data) << 24; + return(value); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_input_size + * + * This routine returns the current size of the input window + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +unsigned long saa7114_get_decoder_input_size(void) +#else +unsigned long gfx_get_decoder_input_size(void) +#endif +{ + unsigned long value = 0; + unsigned char data; + saa7114_read_reg(SAA7114_HORZ_INPUT_LO, &data); + value = (unsigned long) data; + saa7114_read_reg(SAA7114_HORZ_INPUT_HI, &data); + value |= ((unsigned long) data) << 8; + saa7114_read_reg(SAA7114_VERT_INPUT_LO, &data); + value |= ((unsigned long) data) << 17; + saa7114_read_reg(SAA7114_VERT_INPUT_HI, &data); + value |= ((unsigned long) data) << 25; + return(value); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_output_size + * + * This routine returns the current size of the output window. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +unsigned long saa7114_get_decoder_output_size(void) +#else +unsigned long gfx_get_decoder_output_size(void) +#endif +{ + unsigned long value = 0; + unsigned char data; + saa7114_read_reg(SAA7114_HORZ_OUTPUT_LO, &data); + value = (unsigned long) data; + saa7114_read_reg(SAA7114_HORZ_OUTPUT_HI, &data); + value |= ((unsigned long) data) << 8; + saa7114_read_reg(SAA7114_VERT_OUTPUT_LO, &data); + value |= ((unsigned long) data) << 17; + saa7114_read_reg(SAA7114_VERT_OUTPUT_HI, &data); + value |= ((unsigned long) data) << 25; + return(value); +} + +/*----------------------------------------------------------------------------- + * gfx_get_decoder_vbi_format + * + * This routine returns the current format of VBI data for the specified line. + *----------------------------------------------------------------------------- + */ +#if GFX_DECODER_DYNAMIC +int saa7114_get_decoder_vbi_format(int line) +#else +int gfx_get_decoder_vbi_format(int line) +#endif +{ + unsigned char format = 0, data; + saa7114_read_reg((unsigned char)(0x3F + line), &data); + switch (data) + { + case 0xFF: format = VBI_FORMAT_VIDEO; break; /* Active video */ + case 0x77: format = VBI_FORMAT_RAW; break; /* Raw VBI data */ + case 0x55: format = VBI_FORMAT_CC; break; /* US CC */ + case 0xCC: format = VBI_FORMAT_NABTS; break; /* US NABTS */ + } + return(format); +} + +#endif /* GFX_READ_ROUTINES */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_regs.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_regs.h 2005-12-14 11:35:27.000000000 -0700 @@ -0,0 +1,1634 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This header file contains the graphics register definitions. + * */ + + +/*----------------------------------*/ +/* FIRST GENERATION GRAPHICS UNIT */ +/*----------------------------------*/ + +#define GP_DST_XCOOR 0x8100 /* x destination origin */ +#define GP_DST_YCOOR 0x8102 /* y destination origin */ +#define GP_WIDTH 0x8104 /* pixel width */ +#define GP_HEIGHT 0x8106 /* pixel height */ +#define GP_SRC_XCOOR 0x8108 /* x source origin */ +#define GP_SRC_YCOOR 0x810A /* y source origin */ + +#define GP_VECTOR_LENGTH 0x8104 /* vector length */ +#define GP_INIT_ERROR 0x8106 /* vector initial error */ +#define GP_AXIAL_ERROR 0x8108 /* axial error increment */ +#define GP_DIAG_ERROR 0x810A /* diagonal error increment */ + +#define GP_SRC_COLOR_0 0x810C /* source color 0 */ +#define GP_SRC_COLOR_1 0x810E /* source color 1 */ +#define GP_PAT_COLOR_0 0x8110 /* pattern color 0 */ +#define GP_PAT_COLOR_1 0x8112 /* pattern color 1 */ +#define GP_PAT_COLOR_2 0x8114 /* pattern color 2 */ +#define GP_PAT_COLOR_3 0x8116 /* pattern color 3 */ +#define GP_PAT_DATA_0 0x8120 /* bits 31:0 of pattern */ +#define GP_PAT_DATA_1 0x8124 /* bits 63:32 of pattern */ +#define GP_PAT_DATA_2 0x8128 /* bits 95:64 of pattern */ +#define GP_PAT_DATA_3 0x812C /* bits 127:96 of pattern */ + +#define GP_VGA_WRITE 0x8140 /* VGA write path control */ +#define GP_VGA_READ 0x8144 /* VGA read path control */ + +#define GP_RASTER_MODE 0x8200 /* raster operation */ +#define GP_VECTOR_MODE 0x8204 /* vector mode register */ +#define GP_BLIT_MODE 0x8208 /* blit mode register */ +#define GP_BLIT_STATUS 0x820C /* blit status register */ + +#define GP_VGA_BASE 0x8210 /* VGA memory offset (x64K) */ +#define GP_VGA_LATCH 0x8214 /* VGA display latch */ + +/* "GP_VECTOR_MODE" BIT DEFINITIONS */ + +#define VM_X_MAJOR 0x0000 /* X major vector */ +#define VM_Y_MAJOR 0x0001 /* Y major vector */ +#define VM_MAJOR_INC 0x0002 /* positive major axis step */ +#define VM_MINOR_INC 0x0004 /* positive minor axis step */ +#define VM_READ_DST_FB 0x0008 /* read destination data */ + +/* "GP_RASTER_MODE" BIT DEFINITIONS */ + +#define RM_PAT_DISABLE 0x0000 /* pattern is disabled */ +#define RM_PAT_MONO 0x0100 /* 1BPP pattern expansion */ +#define RM_PAT_DITHER 0x0200 /* 2BPP pattern expansion */ +#define RM_PAT_COLOR 0x0300 /* 8BPP or 16BPP pattern */ +#define RM_PAT_MASK 0x0300 /* mask for pattern mode */ +#define RM_PAT_TRANSPARENT 0x0400 /* transparent 1BPP pattern */ +#define RM_SRC_TRANSPARENT 0x0800 /* transparent 1BPP source */ + +/* "GP_BLIT_STATUS" BIT DEFINITIONS */ + +#define BS_BLIT_BUSY 0x0001 /* blit engine is busy */ +#define BS_PIPELINE_BUSY 0x0002 /* graphics pipeline is busy*/ +#define BS_BLIT_PENDING 0x0004 /* blit pending */ +#define BC_FLUSH 0x0080 /* flush pipeline requests */ +#define BC_8BPP 0x0000 /* 8BPP mode */ +#define BC_16BPP 0x0100 /* 16BPP mode */ +#define BC_FB_WIDTH_1024 0x0000 /* framebuffer width = 1024 */ +#define BC_FB_WIDTH_2048 0x0200 /* framebuffer width = 2048 */ +#define BC_FB_WIDTH_4096 0x0400 /* framebuffer width = 4096 */ + +/* "GP_BLIT_MODE" BIT DEFINITIONS */ + +#define BM_READ_SRC_NONE 0x0000 /* source foreground color */ +#define BM_READ_SRC_FB 0x0001 /* read source from FB */ +#define BM_READ_SRC_BB0 0x0002 /* read source from BB0 */ +#define BM_READ_SRC_BB1 0x0003 /* read source from BB1 */ +#define BM_READ_SRC_MASK 0x0003 /* read source mask */ + +#define BM_READ_DST_NONE 0x0000 /* no destination data */ +#define BM_READ_DST_BB0 0x0008 /* destination from BB0 */ +#define BM_READ_DST_BB1 0x000C /* destination from BB1 */ +#define BM_READ_DST_FB0 0x0010 /* dest from FB (store BB0) */ +#define BM_READ_DST_FB1 0x0014 /* dest from FB (store BB1) */ +#define BM_READ_DST_MASK 0x001C /* read destination mask */ + +#define BM_WRITE_FB 0x0000 /* write to framebuffer */ +#define BM_WRITE_MEM 0x0020 /* write to memory */ +#define BM_WRITE_MASK 0x0020 /* write mask */ + +#define BM_SOURCE_COLOR 0x0000 /* source is 8BPP or 16BPP */ +#define BM_SOURCE_EXPAND 0x0040 /* source is 1BPP */ +#define BM_SOURCE_TEXT 0x00C0 /* source is 1BPP text */ +#define BM_SOURCE_MASK 0x00C0 /* source mask */ + +#define BM_REVERSE_Y 0x0100 /* reverse Y direction */ + +/*---------------------------------------*/ +/* FIRST GENERATION DISPLAY CONTROLLER */ +/*---------------------------------------*/ + +#define DC_UNLOCK 0x8300 /* lock register */ +#define DC_GENERAL_CFG 0x8304 /* config registers... */ +#define DC_TIMING_CFG 0x8308 +#define DC_OUTPUT_CFG 0x830C + +#define DC_FB_ST_OFFSET 0x8310 /* framebuffer start offset */ +#define DC_CB_ST_OFFSET 0x8314 /* compression start offset */ +#define DC_CURS_ST_OFFSET 0x8318 /* cursor start offset */ +#define DC_ICON_ST_OFFSET 0x831C /* icon start offset */ +#define DC_VID_ST_OFFSET 0x8320 /* video start offset */ +#define DC_LINE_DELTA 0x8324 /* fb and cb skip counts */ +#define DC_BUF_SIZE 0x8328 /* fb and cb line size */ + +#define DC_H_TIMING_1 0x8330 /* horizontal timing... */ +#define DC_H_TIMING_2 0x8334 +#define DC_H_TIMING_3 0x8338 +#define DC_FP_H_TIMING 0x833C + +#define DC_V_TIMING_1 0x8340 /* vertical timing... */ +#define DC_V_TIMING_2 0x8344 +#define DC_V_TIMING_3 0x8348 +#define DC_FP_V_TIMING 0x834C + +#define DC_CURSOR_X 0x8350 /* cursor x position */ +#define DC_ICON_X 0x8354 /* HACK - 1.3 definition */ +#define DC_V_LINE_CNT 0x8354 /* vertical line counter */ +#define DC_CURSOR_Y 0x8358 /* cursor y position */ +#define DC_ICON_Y 0x835C /* HACK - 1.3 definition */ +#define DC_SS_LINE_CMP 0x835C /* line compare value */ +#define DC_CURSOR_COLOR 0x8360 /* cursor colors */ +#define DC_ICON_COLOR 0x8364 /* icon colors */ +#define DC_BORDER_COLOR 0x8368 /* border color */ +#define DC_PAL_ADDRESS 0x8370 /* palette address */ +#define DC_PAL_DATA 0x8374 /* palette data */ +#define DC_DFIFO_DIAG 0x8378 /* display FIFO diagnostic */ +#define DC_CFIFO_DIAG 0x837C /* compression FIF0 diagnostic */ + +/* PALETTE LOCATIONS */ + +#define PAL_CURSOR_COLOR_0 0x100 +#define PAL_CURSOR_COLOR_1 0x101 +#define PAL_ICON_COLOR_0 0x102 +#define PAL_ICON_COLOR_1 0x103 +#define PAL_OVERSCAN_COLOR 0x104 + +/* UNLOCK VALUE */ + +#define DC_UNLOCK_VALUE 0x00004758 /* used to unlock DC regs */ + +/* "DC_GENERAL_CFG" BIT DEFINITIONS */ + +#define DC_GCFG_DFLE 0x00000001 /* display FIFO load enable */ +#define DC_GCFG_CURE 0x00000002 /* cursor enable */ +#define DC_GCFG_VCLK_DIV 0x00000004 /* vid clock divisor */ +#define DC_GCFG_PLNO 0x00000004 /* planar offset LSB */ +#define DC_GCFG_PPC 0x00000008 /* pixel pan compatibility */ +#define DC_GCFG_CMPE 0x00000010 /* compression enable */ +#define DC_GCFG_DECE 0x00000020 /* decompression enable */ +#define DC_GCFG_DCLK_MASK 0x000000C0 /* dotclock multiplier */ +#define DC_GCFG_DCLK_POS 6 /* dotclock multiplier */ +#define DC_GCFG_DFHPSL_MASK 0x00000F00 /* FIFO high-priority start */ +#define DC_GCFG_DFHPSL_POS 8 /* FIFO high-priority start */ +#define DC_GCFG_DFHPEL_MASK 0x0000F000 /* FIFO high-priority end */ +#define DC_GCFG_DFHPEL_POS 12 /* FIFO high-priority end */ +#define DC_GCFG_CIM_MASK 0x00030000 /* compressor insert mode */ +#define DC_GCFG_CIM_POS 16 /* compressor insert mode */ +#define DC_GCFG_FDTY 0x00040000 /* frame dirty mode */ +#define DC_GCFG_RTPM 0x00080000 /* real-time perf. monitor */ +#define DC_GCFG_DAC_RS_MASK 0x00700000 /* DAC register selects */ +#define DC_GCFG_DAC_RS_POS 20 /* DAC register selects */ +#define DC_GCFG_CKWR 0x00800000 /* clock write */ +#define DC_GCFG_LDBL 0x01000000 /* line double */ +#define DC_GCFG_DIAG 0x02000000 /* FIFO diagnostic mode */ +#define DC_GCFG_CH4S 0x04000000 /* sparse refresh mode */ +#define DC_GCFG_SSLC 0x08000000 /* enable line compare */ +#define DC_GCFG_VIDE 0x10000000 /* video enable */ +#define DC_GCFG_DFCK 0x20000000 /* divide flat-panel clock - rev 2.3 down */ +#define DC_GCFG_VRDY 0x20000000 /* video port speed - rev 2.4 up */ +#define DC_GCFG_DPCK 0x40000000 /* divide pixel clock */ +#define DC_GCFG_DDCK 0x80000000 /* divide dot clock */ + +/* "DC_TIMING_CFG" BIT DEFINITIONS */ + +#define DC_TCFG_FPPE 0x00000001 /* flat-panel power enable */ +#define DC_TCFG_HSYE 0x00000002 /* horizontal sync enable */ +#define DC_TCFG_VSYE 0x00000004 /* vertical sync enable */ +#define DC_TCFG_BLKE 0x00000008 /* blank enable */ +#define DC_TCFG_DDCK 0x00000010 /* DDC clock */ +#define DC_TCFG_TGEN 0x00000020 /* timing generator enable */ +#define DC_TCFG_VIEN 0x00000040 /* vertical interrupt enable*/ +#define DC_TCFG_BLNK 0x00000080 /* blink enable */ +#define DC_TCFG_CHSP 0x00000100 /* horizontal sync polarity */ +#define DC_TCFG_CVSP 0x00000200 /* vertical sync polarity */ +#define DC_TCFG_FHSP 0x00000400 /* panel horz sync polarity */ +#define DC_TCFG_FVSP 0x00000800 /* panel vert sync polarity */ +#define DC_TCFG_FCEN 0x00001000 /* flat-panel centering */ +#define DC_TCFG_CDCE 0x00002000 /* HACK - 1.3 definition */ +#define DC_TCFG_PLNR 0x00002000 /* planar mode enable */ +#define DC_TCFG_INTL 0x00004000 /* interlace scan */ +#define DC_TCFG_PXDB 0x00008000 /* pixel double */ +#define DC_TCFG_BKRT 0x00010000 /* blink rate */ +#define DC_TCFG_PSD_MASK 0x000E0000 /* power sequence delay */ +#define DC_TCFG_PSD_POS 17 /* power sequence delay */ +#define DC_TCFG_DDCI 0x08000000 /* DDC input (RO) */ +#define DC_TCFG_SENS 0x10000000 /* monitor sense (RO) */ +#define DC_TCFG_DNA 0x20000000 /* display not active (RO) */ +#define DC_TCFG_VNA 0x40000000 /* vertical not active (RO) */ +#define DC_TCFG_VINT 0x80000000 /* vertical interrupt (RO) */ + +/* "DC_OUTPUT_CFG" BIT DEFINITIONS */ + +#define DC_OCFG_8BPP 0x00000001 /* 8/16 bpp select */ +#define DC_OCFG_555 0x00000002 /* 16 bpp format */ +#define DC_OCFG_PCKE 0x00000004 /* PCLK enable */ +#define DC_OCFG_FRME 0x00000008 /* frame rate mod enable */ +#define DC_OCFG_DITE 0x00000010 /* dither enable */ +#define DC_OCFG_2PXE 0x00000020 /* 2 pixel enable */ +#define DC_OCFG_2XCK 0x00000040 /* 2 x pixel clock */ +#define DC_OCFG_2IND 0x00000080 /* 2 index enable */ +#define DC_OCFG_34ADD 0x00000100 /* 3- or 4-bit add */ +#define DC_OCFG_FRMS 0x00000200 /* frame rate mod select */ +#define DC_OCFG_CKSL 0x00000400 /* clock select */ +#define DC_OCFG_PRMP 0x00000800 /* palette re-map */ +#define DC_OCFG_PDEL 0x00001000 /* panel data enable low */ +#define DC_OCFG_PDEH 0x00002000 /* panel data enable high */ +#define DC_OCFG_CFRW 0x00004000 /* comp line buffer r/w sel */ +#define DC_OCFG_DIAG 0x00008000 /* comp line buffer diag */ + +#define MC_MEM_CNTRL1 0x00008400 +#define MC_DR_ADD 0x00008418 +#define MC_DR_ACC 0x0000841C + +/* MC_MEM_CNTRL1 BIT DEFINITIONS */ + +#define MC_XBUSARB 0x00000008 /* 0 = GP priority < CPU priority */ + /* 1 = GP priority = CPU priority */ + /* GXm databook V2.0 is wrong ! */ +/*----------*/ +/* CS5530 */ +/*----------*/ + +/* CS5530 REGISTER DEFINITIONS */ + +#define CS5530_VIDEO_CONFIG 0x0000 +#define CS5530_DISPLAY_CONFIG 0x0004 +#define CS5530_VIDEO_X_POS 0x0008 +#define CS5530_VIDEO_Y_POS 0x000C +#define CS5530_VIDEO_SCALE 0x0010 +#define CS5530_VIDEO_COLOR_KEY 0x0014 +#define CS5530_VIDEO_COLOR_MASK 0x0018 +#define CS5530_PALETTE_ADDRESS 0x001C +#define CS5530_PALETTE_DATA 0x0020 +#define CS5530_DOT_CLK_CONFIG 0x0024 +#define CS5530_CRCSIG_TFT_TV 0x0028 + +/* "CS5530_VIDEO_CONFIG" BIT DEFINITIONS */ + +#define CS5530_VCFG_VID_EN 0x00000001 +#define CS5530_VCFG_VID_REG_UPDATE 0x00000002 +#define CS5530_VCFG_VID_INP_FORMAT 0x0000000C +#define CS5530_VCFG_8_BIT_4_2_0 0x00000004 +#define CS5530_VCFG_16_BIT_4_2_0 0x00000008 +#define CS5530_VCFG_GV_SEL 0x00000010 +#define CS5530_VCFG_CSC_BYPASS 0x00000020 +#define CS5530_VCFG_X_FILTER_EN 0x00000040 +#define CS5530_VCFG_Y_FILTER_EN 0x00000080 +#define CS5530_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 +#define CS5530_VCFG_INIT_READ_MASK 0x01FF0000 +#define CS5530_VCFG_EARLY_VID_RDY 0x02000000 +#define CS5530_VCFG_LINE_SIZE_UPPER 0x08000000 +#define CS5530_VCFG_4_2_0_MODE 0x10000000 +#define CS5530_VCFG_16_BIT_EN 0x20000000 +#define CS5530_VCFG_HIGH_SPD_INT 0x40000000 + +/* "CS5530_DISPLAY_CONFIG" BIT DEFINITIONS */ + +#define CS5530_DCFG_DIS_EN 0x00000001 +#define CS5530_DCFG_HSYNC_EN 0x00000002 +#define CS5530_DCFG_VSYNC_EN 0x00000004 +#define CS5530_DCFG_DAC_BL_EN 0x00000008 +#define CS5530_DCFG_DAC_PWDNX 0x00000020 +#define CS5530_DCFG_FP_PWR_EN 0x00000040 +#define CS5530_DCFG_FP_DATA_EN 0x00000080 +#define CS5530_DCFG_CRT_HSYNC_POL 0x00000100 +#define CS5530_DCFG_CRT_VSYNC_POL 0x00000200 +#define CS5530_DCFG_FP_HSYNC_POL 0x00000400 +#define CS5530_DCFG_FP_VSYNC_POL 0x00000800 +#define CS5530_DCFG_XGA_FP 0x00001000 +#define CS5530_DCFG_FP_DITH_EN 0x00002000 +#define CS5530_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 +#define CS5530_DCFG_CRT_SYNC_SKW_INIT 0x00010000 +#define CS5530_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 +#define CS5530_DCFG_PWR_SEQ_DLY_INIT 0x00080000 +#define CS5530_DCFG_VG_CK 0x00100000 +#define CS5530_DCFG_GV_PAL_BYP 0x00200000 +#define CS5530_DCFG_DDC_SCL 0x00400000 +#define CS5530_DCFG_DDC_SDA 0x00800000 +#define CS5530_DCFG_DDC_OE 0x01000000 +#define CS5530_DCFG_16_BIT_EN 0x02000000 + + +/*----------*/ +/* SC1200 */ +/*----------*/ + +/* SC1200 VIDEO REGISTER DEFINITIONS */ + +#define SC1200_VIDEO_CONFIG 0x000 +#define SC1200_DISPLAY_CONFIG 0x004 +#define SC1200_VIDEO_X_POS 0x008 +#define SC1200_VIDEO_Y_POS 0x00C +#define SC1200_VIDEO_UPSCALE 0x010 +#define SC1200_VIDEO_COLOR_KEY 0x014 +#define SC1200_VIDEO_COLOR_MASK 0x018 +#define SC1200_PALETTE_ADDRESS 0x01C +#define SC1200_PALETTE_DATA 0x020 +#define SC1200_VID_MISC 0x028 +#define SC1200_VID_CLOCK_SELECT 0x02C +#define SC1200_VIDEO_DOWNSCALER_CONTROL 0x03C +#define SC1200_VIDEO_DOWNSCALER_COEFFICIENTS 0x40 +#define SC1200_VID_CRC 0x044 +#define SC1200_DEVICE_ID 0x048 +#define SC1200_VID_ALPHA_CONTROL 0x04C +#define SC1200_CURSOR_COLOR_KEY 0x050 +#define SC1200_CURSOR_COLOR_MASK 0x054 +#define SC1200_CURSOR_COLOR_1 0x058 +#define SC1200_CURSOR_COLOR_2 0x05C +#define SC1200_ALPHA_XPOS_1 0x060 +#define SC1200_ALPHA_YPOS_1 0x064 +#define SC1200_ALPHA_COLOR_1 0x068 +#define SC1200_ALPHA_CONTROL_1 0x06C +#define SC1200_ALPHA_XPOS_2 0x070 +#define SC1200_ALPHA_YPOS_2 0x074 +#define SC1200_ALPHA_COLOR_2 0x078 +#define SC1200_ALPHA_CONTROL_2 0x07C +#define SC1200_ALPHA_XPOS_3 0x080 +#define SC1200_ALPHA_YPOS_3 0x084 +#define SC1200_ALPHA_COLOR_3 0x088 +#define SC1200_ALPHA_CONTROL_3 0x08C +#define SC1200_VIDEO_REQUEST 0x090 +#define SC1200_ALPHA_WATCH 0x094 +#define SC1200_VIDEO_DISPLAY_MODE 0x400 +#define SC1200_VIDEO_ODD_VBI_LINE_ENABLE 0x40C +#define SC1200_VIDEO_EVEN_VBI_LINE_ENABLE 0x410 +#define SC1200_VIDEO_VBI_HORIZ_CONTROL 0x414 +#define SC1200_VIDEO_ODD_VBI_TOTAL_COUNT 0x418 +#define SC1200_VIDEO_EVEN_VBI_TOTAL_COUNT 0x41C +#define SC1200_GENLOCK 0x420 +#define SC1200_GENLOCK_DELAY 0x424 +#define SC1200_TVOUT_HORZ_TIM 0x800 +#define SC1200_TVOUT_HORZ_SYNC 0x804 +#define SC1200_TVOUT_VERT_SYNC 0x808 +#define SC1200_TVOUT_LINE_END 0x80C +#define SC1200_TVOUT_VERT_DOWNSCALE 0x810 /* REV. A & B */ +#define SC1200_TVOUT_HORZ_PRE_ENCODER_SCALE 0x810 /* REV. C */ +#define SC1200_TVOUT_HORZ_SCALING 0x814 +#define SC1200_TVOUT_DEBUG 0x818 +#define SC1200_TVENC_TIM_CTRL_1 0xC00 +#define SC1200_TVENC_TIM_CTRL_2 0xC04 +#define SC1200_TVENC_TIM_CTRL_3 0xC08 +#define SC1200_TVENC_SUB_FREQ 0xC0C +#define SC1200_TVENC_DISP_POS 0xC10 +#define SC1200_TVENC_DISP_SIZE 0xC14 +#define SC1200_TVENC_CC_DATA 0xC18 +#define SC1200_TVENC_EDS_DATA 0xC1C +#define SC1200_TVENC_CGMS_DATA 0xC20 +#define SC1200_TVENC_WSS_DATA 0xC24 +#define SC1200_TVENC_CC_CONTROL 0xC28 +#define SC1200_TVENC_DAC_CONTROL 0xC2C +#define SC1200_TVENC_MV_CONTROL 0xC30 + +/* "SC1200_VIDEO_CONFIG" BIT DEFINITIONS */ + +#define SC1200_VCFG_VID_EN 0x00000001 +#define SC1200_VCFG_VID_INP_FORMAT 0x0000000C +#define SC1200_VCFG_UYVY_FORMAT 0x00000000 +#define SC1200_VCFG_Y2YU_FORMAT 0x00000004 +#define SC1200_VCFG_YUYV_FORMAT 0x00000008 +#define SC1200_VCFG_YVYU_FORMAT 0x0000000C +#define SC1200_VCFG_X_FILTER_EN 0x00000040 +#define SC1200_VCFG_Y_FILTER_EN 0x00000080 +#define SC1200_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 +#define SC1200_VCFG_INIT_READ_MASK 0x01FF0000 +#define SC1200_VCFG_LINE_SIZE_UPPER 0x08000000 +#define SC1200_VCFG_4_2_0_MODE 0x10000000 + +/* "SC1200_DISPLAY_CONFIG" BIT DEFINITIONS */ + +#define SC1200_DCFG_DIS_EN 0x00000001 +#define SC1200_DCFG_HSYNC_EN 0x00000002 +#define SC1200_DCFG_VSYNC_EN 0x00000004 +#define SC1200_DCFG_DAC_BL_EN 0x00000008 +#define SC1200_DCFG_FP_PWR_EN 0x00000040 +#define SC1200_DCFG_FP_DATA_EN 0x00000080 +#define SC1200_DCFG_CRT_HSYNC_POL 0x00000100 +#define SC1200_DCFG_CRT_VSYNC_POL 0x00000200 +#define SC1200_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 +#define SC1200_DCFG_CRT_SYNC_SKW_INIT 0x00010000 +#define SC1200_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 +#define SC1200_DCFG_PWR_SEQ_DLY_INIT 0x00080000 +#define SC1200_DCFG_VG_CK 0x00100000 +#define SC1200_DCFG_GV_PAL_BYP 0x00200000 +#define SC1200_DCFG_DDC_SCL 0x00400000 +#define SC1200_DCFG_DDC_SDA 0x00800000 +#define SC1200_DCFG_DDC_OE 0x01000000 + +/* "SC1200_VID_MISC" BIT DEFINITIONS */ + +#define SC1200_GAMMA_BYPASS_BOTH 0x00000001 +#define SC1200_DAC_POWER_DOWN 0x00000400 +#define SC1200_ANALOG_POWER_DOWN 0x00000800 +#define SC1200_PLL_POWER_NORMAL 0x00001000 + +/* "SC1200_VIDEO_DOWNSCALER_CONTROL" BIT DEFINITIONS */ + +#define SC1200_VIDEO_DOWNSCALE_ENABLE 0x00000001 +#define SC1200_VIDEO_DOWNSCALE_FACTOR_POS 1 +#define SC1200_VIDEO_DOWNSCALE_FACTOR_MASK 0x0000001E +#define SC1200_VIDEO_DOWNSCALE_TYPE_A 0x00000000 +#define SC1200_VIDEO_DOWNSCALE_TYPE_B 0x00000040 +#define SC1200_VIDEO_DOWNSCALE_TYPE_MASK 0x00000040 + +/* "SC1200_VIDEO_DOWNSCALER_COEFFICIENTS" BIT DEFINITIONS */ + +#define SC1200_VIDEO_DOWNSCALER_COEF1_POS 0 +#define SC1200_VIDEO_DOWNSCALER_COEF2_POS 8 +#define SC1200_VIDEO_DOWNSCALER_COEF3_POS 16 +#define SC1200_VIDEO_DOWNSCALER_COEF4_POS 24 +#define SC1200_VIDEO_DOWNSCALER_COEF_MASK 0xF + +/* VIDEO DE-INTERLACING AND ALPHA CONTROL (REGISTER 0x4C) */ + +#define SC1200_VERTICAL_SCALER_SHIFT_MASK 0x00000007 +#define SC1200_VERTICAL_SCALER_SHIFT_INIT 0x00000004 +#define SC1200_VERTICAL_SCALER_SHIFT_EN 0x00000010 +#define SC1200_TOP_LINE_IN_ODD 0x00000040 +#define SC1200_NO_CK_OUTSIDE_ALPHA 0x00000100 +#define SC1200_VIDEO_IS_INTERLACED 0x00000200 +#define SC1200_CSC_VIDEO_YUV_TO_RGB 0x00000400 +#define SC1200_CSC_GFX_RGB_TO_YUV 0x00000800 +#define SC1200_VIDEO_INPUT_IS_RGB 0x00002000 +#define SC1200_VIDEO_LINE_OFFSET_ODD 0x00001000 +#define SC1200_ALPHA1_PRIORITY_POS 16 +#define SC1200_ALPHA1_PRIORITY_MASK 0x00030000 +#define SC1200_ALPHA2_PRIORITY_POS 18 +#define SC1200_ALPHA2_PRIORITY_MASK 0x000C0000 +#define SC1200_ALPHA3_PRIORITY_POS 20 +#define SC1200_ALPHA3_PRIORITY_MASK 0x00300000 + +/* VIDEO CURSOR COLOR KEY DEFINITIONS (REGISTER 0x50) */ + +#define SC1200_CURSOR_COLOR_KEY_OFFSET_POS 24 +#define SC1200_CURSOR_COLOR_BITS 23 +#define SC1200_COLOR_MASK 0x00FFFFFF /* 24 significant bits */ + +/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */ + +#define SC1200_ALPHA_COLOR_ENABLE 0x01000000 + +/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */ + +#define SC1200_ACTRL_WIN_ENABLE 0x00010000 +#define SC1200_ACTRL_LOAD_ALPHA 0x00020000 + +/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */ + +#define SC1200_VIDEO_Y_REQUEST_POS 0 +#define SC1200_VIDEO_X_REQUEST_POS 16 +#define SC1200_VIDEO_REQUEST_MASK 0x00000FFF + +/* VIDEO DISPLAY MODE (REGISTER 0x400) */ + +#define SC1200_VIDEO_SOURCE_MASK 0x00000003 +#define SC1200_VIDEO_SOURCE_GX1 0x00000000 +#define SC1200_VIDEO_SOURCE_DVIP 0x00000002 +#define SC1200_VBI_SOURCE_MASK 0x00000004 +#define SC1200_VBI_SOURCE_DVIP 0x00000000 +#define SC1200_VBI_SOURCE_GX1 0x00000004 + +/* ODD/EVEN VBI LINE ENABLE (REGISTERS 0x40C, 0x410) */ + +#define SC1200_VIDEO_VBI_LINE_ENABLE_MASK 0x00FFFFFC +#define SC1200_VIDEO_ALL_ACTIVE_IS_VBI 0x01000000 +#define SC1200_VIDEO_VBI_LINE_OFFSET_POS 25 +#define SC1200_VIDEO_VBI_LINE_OFFSET_MASK 0x3E000000 + +/* ODD/EVEN VBI TOTAL COUNT (REGISTERS 0x418, 0x41C) */ + +#define SC1200_VIDEO_VBI_TOTAL_COUNT_MASK 0x000FFFFF + +/* GENLOCK BIT DEFINITIONS */ + +#define SC1200_GENLOCK_SINGLE_ENABLE 0x00000001 +#define SC1200_GENLOCK_FIELD_SYNC_ENABLE 0x00000001 +#define SC1200_GENLOCK_CONTINUOUS_ENABLE 0x00000002 +#define SC1200_GENLOCK_GX_VSYNC_FALLING_EDGE 0x00000004 +#define SC1200_GENLOCK_VIP_VSYNC_FALLING_EDGE 0x00000008 +#define SC1200_GENLOCK_TIMEOUT_ENABLE 0x00000010 +#define SC1200_GENLOCK_TVENC_RESET_EVEN_FIELD 0x00000020 +#define SC1200_GENLOCK_TVENC_RESET_BEFORE_DELAY 0x00000040 +#define SC1200_GENLOCK_TVENC_RESET_ENABLE 0x00000080 +#define SC1200_GENLOCK_SYNC_TO_TVENC 0x00000100 +#define SC1200_GENLOCK_DELAY_MASK 0x001FFFFF + +/* TVOUT HORIZONTAL PRE ENCODER SCALE BIT DEFINITIONS */ + +#define SC1200_TVOUT_YC_DELAY_MASK 0x00C00000 +#define SC1200_TVOUT_YC_DELAY_NONE 0x00000000 +#define SC1200_TVOUT_Y_DELAY_ONE_PIXEL 0x00400000 +#define SC1200_TVOUT_C_DELAY_ONE_PIXEL 0x00800000 +#define SC1200_TVOUT_C_DELAY_TWO_PIXELS 0x00C00000 + +/* TVOUT HORIZONTAL SCALING/CONTROL BIT DEFINITIONS */ + +#define SC1200_TVOUT_FLICKER_FILTER_MASK 0x60000000 +#define SC1200_TVOUT_FLICKER_FILTER_FOURTH_HALF_FOURTH 0x00000000 +#define SC1200_TVOUT_FLICKER_FILTER_HALF_ONE_HALF 0x20000000 +#define SC1200_TVOUT_FLICKER_FILTER_DISABLED 0x40000000 +#define SC1200_TVENC_EXTERNAL_RESET_INTERVAL_MASK 0x0F000000 +#define SC1200_TVENC_EXTERNAL_RESET_EVERY_ODD_FIELD 0x00000000 +#define SC1200_TVENC_EXTERNAL_RESET_EVERY_EVEN_FIELD 0x02000000 +#define SC1200_TVENC_EXTERNAL_RESET_NEXT_ODD_FIELD 0x05000000 +#define SC1200_TVENC_EXTERNAL_RESET_NEXT_EVEN_FIELD 0x07000000 +#define SC1200_TVENC_EXTERNAL_RESET_EVERY_FIELD 0x0E000000 +#define SC1200_TVENC_EXTERNAL_RESET_EVERY_X_ODD_FIELDS 0x08000000 +#define SC1200_TVENC_EXTERNAL_RESET_EVERY_X_EVEN_FIELDS 0x0A000000 + +/* TVOUT DEBUG BIT DEFINITIONS */ + +#define SC1200_TVOUT_FIELD_STATUS_EVEN 0x00000040 +#define SC1200_TVOUT_FIELD_STATUS_TV 0x00000080 +#define SC1200_TVOUT_CRT_VSYNC_STATUS_TRAILING 0x00000100 +#define SC1200_TVOUT_FIELD_STATUS_INVERT 0x00000200 +#define SC1200_TVOUT_CONVERTER_INTERPOLATION 0x00000400 + +/* TVENC TIMING/CONTROL 1 BIT DEFINITIONS (REGISTER 0xC00) */ + +#define SC1200_TVENC_VPHASE_MASK 0x001FF800 +#define SC1200_TVENC_VPHASE_POS 11 +#define SC1200_TVENC_SUB_CARRIER_RESET_MASK 0x30000000 +#define SC1200_TVENC_SUB_CARRIER_RESET_NEVER 0x00000000 +#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_TWO_LINES 0x10000000 +#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_TWO_FRAMES 0x20000000 +#define SC1200_TVENC_SUB_CARRIER_RESET_EVERY_FOUR_FRAMES 0x30000000 +#define SC1200_TVENC_VIDEO_TIMING_ENABLE 0x80000000 + +/* TVENC TIMING/CONTROL 2 BIT DEFINITIONS (REGISTER 0xC04) */ + +#define SC1200_TVENC_OUTPUT_YCBCR 0x40000000 +#define SC1200_TVENC_CFS_MASK 0x00030000 +#define SC1200_TVENC_CFS_BYPASS 0x00000000 +#define SC1200_TVENC_CFS_CVBS 0x00020000 +#define SC1200_TVENC_CFS_SVIDEO 0x00030000 + +/* TVENC TIMING/CONTROL 3 BIT DEFINITIONS (REGISTER 0xC08) */ + +#define SC1200_TVENC_CS 0x00000001 +#define SC1200_TVENC_SYNCMODE_MASK 0x00000006 +#define SC1200_TVENC_SYNC_ON_GREEN 0x00000002 +#define SC1200_TVENC_SYNC_ON_CVBS 0x00000004 +#define SC1200_TVENC_CM 0x00000008 + +/* TVENC DAC CONTROL BIT DEFINITIONS (REGISTER 0xC2C) */ +#define SC1200_TVENC_TRIM_MASK 0x00000007 +#define SC1200_TVENC_POWER_DOWN 0x00000020 + +/* TVENC MV CONTROL BIT DEFINITIONS (REGISTER 0xC30) */ +#define SC1200_TVENC_MV_ENABLE 0xBE + +/* SC1200 VIP REGISTER DEFINITIONS */ + +#define SC1200_VIP_CONFIG 0x00000000 +#define SC1200_VIP_CONTROL 0x00000004 +#define SC1200_VIP_STATUS 0x00000008 +#define SC1200_VIP_CURRENT_LINE 0x00000010 +#define SC1200_VIP_LINE_TARGET 0x00000014 +#define SC1200_ODD_DIRECT_VBI_LINE_ENABLE 0x00000018 +#define SC1200_EVEN_DIRECT_VBI_LINE_ENABLE 0x0000001C +#define SC1200_VIP_ODD_BASE 0x00000020 +#define SC1200_VIP_EVEN_BASE 0x00000024 +#define SC1200_VIP_PITCH 0x00000028 +#define SC1200_VBI_ODD_BASE 0x00000040 +#define SC1200_VBI_EVEN_BASE 0x00000044 +#define SC1200_VBI_PITCH 0x00000048 + +/* "SC1200_VIP_CONFIG" BIT DEFINITIONS */ + +#define SC1200_VIP_MODE_MASK 0x00000003 +#define SC1200_VIP_MODE_C 0x00000002 +#define SC1200_VBI_ANCILLARY_TO_MEMORY 0x000C0000 +#define SC1200_VBI_TASK_A_TO_MEMORY 0x00140000 +#define SC1200_VBI_TASK_B_TO_MEMORY 0x00240000 +#define SC1200_VIP_BUS_REQUEST_THRESHOLD 0x00400000 + +/* "SC1200_VIP_CONTROL" BIT DEFINITIONS */ + +#define SC1200_CAPTURE_RUN_MODE_MASK 0x00000003 +#define SC1200_CAPTURE_RUN_MODE_STOP_LINE 0x00000000 +#define SC1200_CAPTURE_RUN_MODE_STOP_FIELD 0x00000001 +#define SC1200_CAPTURE_RUN_MODE_START 0x00000003 +#define SC1200_VIP_DATA_CAPTURE_EN 0x00000100 +#define SC1200_VIP_VBI_CAPTURE_EN 0x00000200 +#define SC1200_VIP_VBI_FIELD_INTERRUPT_EN 0x00010000 + +/* "SC1200_VIP_STATUS" BIT DEFINITIONS */ + +#define SC1200_VIP_CURRENT_FIELD_ODD 0x01000000 +#define SC1200_VIP_BASE_NOT_UPDATED 0x00200000 +#define SC1200_VIP_FIFO_OVERFLOW 0x00100000 +#define SC1200_VIP_CLEAR_LINE_INT 0x00020000 +#define SC1200_VIP_CLEAR_FIELD_INT 0x00010000 +#define SC1200_VBI_DATA_CAPTURE_ACTIVE 0x00000200 +#define SC1200_VIDEO_DATA_CAPTURE_ACTIVE 0x00000100 + +/* "SC1200_VIP_CURRENT_LINE" BIT DEFINITIONS */ + +#define SC1200_VIP_CURRENT_LINE_MASK 0x000003FF + +/* "SC1200_VIP_LINE_TARGET" BIT DEFINITIONS */ + +#define SC1200_VIP_LAST_LINE_MASK 0x03FF0000 + +/* "SC1200_VIP_PITCH" BIT DEFINITION */ + +#define SC1200_VIP_PITCH_MASK 0x0000FFFC + +/* "SC1200_VBI_PITCH" BIT DEFINITION */ + +#define SC1200_VBI_PITCH_MASK 0x0000FFFC + +/* SC1200 DIRECT VBI LINE ENABLE BIT DEFINITION */ + +#define SC1200_DIRECT_VBI_LINE_ENABLE_MASK 0x00FFFFFF + +/* SC1200 CONFIGURATION BLOCK */ + +#define SC1200_CB_BASE_ADDR 0x9000 +#define SC1200_CB_WDTO 0x0000 +#define SC1200_CB_WDCNFG 0x0002 +#define SC1200_CB_WDSTS 0x0004 +#define SC1200_CB_TMVALUE 0x0008 +#define SC1200_CB_TMCNFG 0x000D +#define SC1200_CB_CCFC 0x001E +#define SC1200_CB_PMR 0x0030 +#define SC1200_CB_MCR 0x0034 +#define SC1200_CB_INTSEL 0x0038 +#define SC1200_CB_PID 0x003C +#define SC1200_CB_REV 0x003D + +/* SC1200 HIGH RESOLUTION TIMER CONFIGURATION REGISTER BITS */ + +#define SC1200_TMCLKSEL_27MHZ 0x2 + +/*---------------------------------*/ +/* PHILIPS SAA7114 VIDEO DECODER */ +/*---------------------------------*/ + +#define SAA7114_CHIPADDR 0x42 + +/* VIDEO DECODER REGISTER DEFINITIONS */ + +#define SAA7114_ANALOG_INPUT_CTRL1 0x02 +#define SAA7114_LUMINANCE_CONTROL 0x09 +#define SAA7114_BRIGHTNESS 0x0A +#define SAA7114_CONTRAST 0x0B +#define SAA7114_SATURATION 0x0C +#define SAA7114_HUE 0x0D +#define SAA7114_STATUS 0x1F +#define SAA7114_IPORT_CONTROL 0x86 + +/* TASK A REGISTER DEFINITIONS */ + +#define SAA7114_TASK_A_HORZ_OUTPUT_LO 0x9C +#define SAA7114_TASK_A_HORZ_OUTPUT_HI 0x9D +#define SAA7114_TASK_A_HSCALE_LUMA_LO 0xA8 +#define SAA7114_TASK_A_HSCALE_LUMA_HI 0xA9 +#define SAA7114_TASK_A_HSCALE_CHROMA_LO 0xAC +#define SAA7114_TASK_A_HSCALE_CHROMA_HI 0xAD + +/* TASK B REGISTER DEFINITIONS */ + +#define SAA7114_HORZ_OFFSET_LO 0xC4 +#define SAA7114_HORZ_OFFSET_HI 0xC5 +#define SAA7114_HORZ_INPUT_LO 0xC6 +#define SAA7114_HORZ_INPUT_HI 0xC7 +#define SAA7114_VERT_OFFSET_LO 0xC8 +#define SAA7114_VERT_OFFSET_HI 0xC9 +#define SAA7114_VERT_INPUT_LO 0xCA +#define SAA7114_VERT_INPUT_HI 0xCB +#define SAA7114_HORZ_OUTPUT_LO 0xCC +#define SAA7114_HORZ_OUTPUT_HI 0xCD +#define SAA7114_VERT_OUTPUT_LO 0xCE +#define SAA7114_VERT_OUTPUT_HI 0xCF +#define SAA7114_HORZ_PRESCALER 0xD0 +#define SAA7114_HORZ_ACL 0xD1 +#define SAA7114_HORZ_FIR_PREFILTER 0xD2 +#define SAA7114_FILTER_CONTRAST 0xD5 +#define SAA7114_FILTER_SATURATION 0xD6 +#define SAA7114_HSCALE_LUMA_LO 0xD8 +#define SAA7114_HSCALE_LUMA_HI 0xD9 +#define SAA7114_HSCALE_CHROMA_LO 0xDC +#define SAA7114_HSCALE_CHROMA_HI 0xDD +#define SAA7114_VSCALE_LUMA_LO 0xE0 +#define SAA7114_VSCALE_LUMA_HI 0xE1 +#define SAA7114_VSCALE_CHROMA_LO 0xE2 +#define SAA7114_VSCALE_CHROMA_HI 0xE3 +#define SAA7114_VSCALE_CONTROL 0xE4 +#define SAA7114_VSCALE_CHROMA_OFFS0 0xE8 +#define SAA7114_VSCALE_CHROMA_OFFS1 0xE9 +#define SAA7114_VSCALE_CHROMA_OFFS2 0xEA +#define SAA7114_VSCALE_CHROMA_OFFS3 0xEB +#define SAA7114_VSCALE_LUMINA_OFFS0 0xEC +#define SAA7114_VSCALE_LUMINA_OFFS1 0xED +#define SAA7114_VSCALE_LUMINA_OFFS2 0xEE +#define SAA7114_VSCALE_LUMINA_OFFS3 0xEF + + +/* Still need to determine PHO value (common phase offset) */ +#define SAA7114_VSCALE_PHO 0x00 + + +/*----------------------------------------------*/ +/* SECOND GENERATION GRAPHICS UNIT (REDCLOUD) */ +/*----------------------------------------------*/ + +#define MGP_DST_OFFSET 0x0000 /* dst address */ +#define MGP_SRC_OFFSET 0x0004 /* src address */ +#define MGP_VEC_ERR 0x0004 /* vector diag/axial errors */ +#define MGP_STRIDE 0x0008 /* src and dst strides */ +#define MGP_WID_HEIGHT 0x000C /* width and height of BLT */ +#define MGP_VEC_LEN 0x000C /* vector length/init error */ +#define MGP_SRC_COLOR_FG 0x0010 /* src mono data fgcolor */ +#define MGP_SRC_COLOR_BG 0x0014 /* src mono data bkcolor */ +#define MGP_PAT_COLOR_0 0x0018 /* pattern color 0 */ +#define MGP_PAT_COLOR_1 0x001C /* pattern color 1 */ +#define MGP_PAT_COLOR_2 0x0020 /* pattern color 2 */ +#define MGP_PAT_COLOR_3 0x0024 /* pattern color 3 */ +#define MGP_PAT_COLOR_4 0x0028 /* pattern color 4 */ +#define MGP_PAT_COLOR_5 0x002C /* pattern color 5 */ +#define MGP_PAT_DATA_0 0x0030 /* pattern data 0 */ +#define MGP_PAT_DATA_1 0x0034 /* pattern data 1 */ +#define MGP_RASTER_MODE 0x0038 /* raster operation */ +#define MGP_VECTOR_MODE 0x003C /* render vector */ +#define MGP_BLT_MODE 0x0040 /* render BLT */ +#define MGP_BLT_STATUS 0x0044 /* BLT status register */ +#define MGP_RESET 0x0044 /* reset register (write) */ +#define MGP_HST_SOURCE 0x0048 /* host src data (bitmap) */ +#define MGP_BASE_OFFSET 0x004C /* base render offset */ + +/* MGP_RASTER_MODE DEFINITIONS */ + +#define MGP_RM_BPPFMT_332 0x00000000 /* 8 BPP, 3:3:2 */ +#define MGP_RM_BPPFMT_4444 0x40000000 /* 16 BPP, 4:4:4:4 */ +#define MGP_RM_BPPFMT_1555 0x50000000 /* 16 BPP, 1:5:5:5 */ +#define MGP_RM_BPPFMT_565 0x60000000 /* 16 BPP, 5:6:5 */ +#define MGP_RM_BPPFMT_8888 0x80000000 /* 32 BPP, 8:8:8:8 */ +#define MGP_RM_ALPHA_EN_MASK 0x00C00000 /* Alpha enable */ +#define MGP_RM_ALPHA_TO_RGB 0x00400000 /* Alpha applies to RGB */ +#define MGP_RM_ALPHA_TO_ALPHA 0x00800000 /* Alpha applies to alpha */ +#define MGP_RM_ALPHA_OP_MASK 0x00300000 /* Alpha operation */ +#define MGP_RM_ALPHA_TIMES_A 0x00000000 /* Alpha * A */ +#define MGP_RM_BETA_TIMES_B 0x00100000 /* (1-alpha) * B */ +#define MGP_RM_A_PLUS_BETA_B 0x00200000 /* A + (1-alpha) * B */ +#define MGP_RM_ALPHA_A_PLUS_BETA_B 0x00300000 /* alpha * A + (1 - alpha)B */ +#define MGP_RM_ALPHA_SELECT 0x000E0000 /* Alpha Select */ +#define MGP_RM_SELECT_ALPHA_A 0x00000000 /* Alpha from channel A */ +#define MGP_RM_SELECT_ALPHA_B 0x00020000 /* Alpha from channel B */ +#define MGP_RM_SELECT_ALPHA_R 0x00040000 /* Registered alpha */ +#define MGP_RM_SELECT_ALPHA_1 0x00060000 /* Constant 1 */ +#define MGP_RM_SELECT_ALPHA_CHAN_A 0x00080000 /* RGB Values from A */ +#define MGP_RM_SELECT_ALPHA_CHAN_B 0x000A0000 /* RGB Values from B */ +#define MGP_RM_DEST_FROM_CHAN_A 0x00010000 /* Alpha channel select */ +#define MGP_RM_PAT_FLAGS 0x00000700 /* pattern related bits */ +#define MGP_RM_PAT_MONO 0x00000100 /* monochrome pattern */ +#define MGP_RM_PAT_COLOR 0x00000200 /* color pattern */ +#define MGP_RM_PAT_TRANS 0x00000400 /* pattern transparency */ +#define MGP_RM_SRC_TRANS 0x00000800 /* source transparency */ + +/* MGP_VECTOR_MODE DEFINITIONS */ + +#define MGP_VM_DST_REQ 0x00000008 /* dst data required */ +#define MGP_VM_THROTTLE 0x00000010 /* sync to VBLANK */ + +/* MGP_BLT_MODE DEFINITIONS */ + +#define MGP_BM_SRC_FB 0x00000001 /* src = frame buffer */ +#define MGP_BM_SRC_HOST 0x00000002 /* src = host register */ +#define MGP_BM_DST_REQ 0x00000004 /* dst data required */ +#define MGP_BM_SRC_MONO 0x00000040 /* monochrome source data */ +#define MGP_BM_SRC_BP_MONO 0x00000080 /* Byte-packed monochrome */ +#define MGP_BM_SRC_TYPE_MASK 0x000000C0 /* Mask for all source fmts */ +#define MGP_BM_NEG_YDIR 0x00000100 /* negative Y direction */ +#define MGP_BM_NEG_XDIR 0x00000200 /* negative X direction */ +#define MGP_BM_THROTTLE 0x00000400 /* sync to VBLANK */ + +/* MGP_BLT_STATUS DEFINITIONS */ + +#define MGP_BS_BLT_BUSY 0x00000001 /* GP is not idle */ +#define MGP_BS_BLT_PENDING 0x00000004 /* second BLT is pending */ +#define MGP_BS_HALF_EMPTY 0x00000008 /* src FIFO half empty */ + +/* ALPHA BLENDING MODES */ + +#define ALPHA_MODE_BLEND 0x00000000 + +/*---------------------------------------------------*/ +/* SECOND GENERATION DISPLAY CONTROLLER (REDCLOUD) */ +/*---------------------------------------------------*/ + +#define MDC_UNLOCK 0x00000000 /* Unlock register */ +#define MDC_GENERAL_CFG 0x00000004 /* Config registers */ +#define MDC_DISPLAY_CFG 0x00000008 +#define MDC_GFX_SCL 0x0000000C /* Graphics scaling */ + +#define MDC_FB_ST_OFFSET 0x00000010 /* Frame buffer start offset */ +#define MDC_CB_ST_OFFSET 0x00000014 /* Compression start offset */ +#define MDC_CURS_ST_OFFSET 0x00000018 /* Cursor buffer start offset */ +#define MDC_ICON_ST_OFFSET 0x0000001C /* Icon buffer start offset */ +#define MDC_VID_Y_ST_OFFSET 0x00000020 /* Video Y Buffer start offset */ +#define MDC_VID_U_ST_OFFSET 0x00000024 /* Video U Buffer start offset */ +#define MDC_VID_V_ST_OFFSET 0x00000028 /* Video V Buffer start offset */ +#define MDC_LINE_SIZE 0x00000030 /* Video, CB, and FB line sizes */ +#define MDC_GFX_PITCH 0x00000034 /* FB and DB skip counts */ +#define MDC_VID_YUV_PITCH 0x00000038 /* Y, U and V buffer skip counts */ + +#define MDC_H_ACTIVE_TIMING 0x00000040 /* Horizontal timings */ +#define MDC_H_BLANK_TIMING 0x00000044 +#define MDC_H_SYNC_TIMING 0x00000048 +#define MDC_V_ACTIVE_TIMING 0x00000050 /* Vertical Timings */ +#define MDC_V_BLANK_TIMING 0x00000054 +#define MDC_V_SYNC_TIMING 0x00000058 + +#define MDC_CURSOR_X 0x00000060 /* Cursor X position */ +#define MDC_CURSOR_Y 0x00000064 /* Cursor Y Position */ +#define MDC_ICON_X 0x00000068 /* Icon X Position */ +#define MDC_LINE_CNT_STATUS 0x0000006C /* Icon Y Position */ + +#define MDC_PAL_ADDRESS 0x00000070 /* Palette Address */ +#define MDC_PAL_DATA 0x00000074 /* Palette Data */ +#define MDC_DFIFO_DIAG 0x00000078 /* Display FIFO diagnostic */ +#define MDC_CFIFO_DIAG 0x0000007C /* Compression FIFO diagnostic */ + +#define MDC_VID_DS_DELTA 0x00000080 /* Vertical Downscaling fraction */ + +#define MDC_PHY_MEM_OFFSET 0x00000084 /* VG Base Address Register */ +#define MDC_DV_CTL 0x00000088 /* Dirty-Valid Control Register */ +#define MDC_DV_ACC 0x0000008C /* Dirty-Valid RAM Access */ + +/* UNLOCK VALUE */ + +#define MDC_UNLOCK_VALUE 0x00004758 /* used to unlock DC regs */ + +/* VG MBUS DEVICE SMI MSR FIELDS */ + +#define MDC_VG_BL_MASK 0x00000001 +#define MDC_MISC_MASK 0x00000002 +#define MDC_ISR0_MASK 0x00000004 +#define MDC_VGA_BL_MASK 0x00000008 +#define MDC_CRTCIO_MSK 0x00000010 +#define MDC_VG_BLANK_SMI 0x00000001 +#define MDC_MISC_SMI 0x00000002 +#define MDC_ISR0_SMI 0x00000004 +#define MDC_VGA_BLANK_SMI 0x00000008 +#define MDC_CRTCIO_SMI 0x00000010 + +/* MDC_GENERAL_CFG BIT FIELDS */ + +#define MDC_GCFG_DBUG 0x80000000 +#define MDC_GCFG_DBSL 0x40000000 +#define MDC_GCFG_CFRW 0x20000000 +#define MDC_GCFG_DIAG 0x10000000 +#define MDC_GCFG_GXRFS4 0x08000000 +#define MDC_GCFG_SGFR 0x04000000 +#define MDC_GCFG_SGRE 0x02000000 +#define MDC_GCFG_SIGE 0x01000000 +#define MDC_GCFG_YUVM 0x00100000 +#define MDC_GCFG_VDSE 0x00080000 +#define MDC_GCFG_VGAFT 0x00040000 +#define MDC_GCFG_FDTY 0x00020000 +#define MDC_GCFG_STFM 0x00010000 +#define MDC_GCFG_DFHPEL_MASK 0x0000F000 +#define MDC_GCFG_DFHPSL_MASK 0x00000F00 +#define MDC_GCFG_VGAE 0x00000080 +#define MDC_GCFG_DECE 0x00000040 +#define MDC_GCFG_CMPE 0x00000020 +#define MDC_GCFG_VIDE 0x00000008 +#define MDC_GCFG_ICNE 0x00000004 +#define MDC_GCFG_CURE 0x00000002 +#define MDC_GCFG_DFLE 0x00000001 + +/* MDC_DISPLAY_CFG BIT FIELDS */ + +#define MDC_DCFG_A20M 0x80000000 +#define MDC_DCFG_A18M 0x40000000 +#define MDC_DCFG_VISL 0x08000000 +#define MDC_DCFG_FRLK 0x04000000 +#define MDC_DCFG_PALB 0x02000000 +#define MDC_DCFG_PIX_PAN_MASK 0x00F00000 +#define MDC_DCFG_DCEN 0x00080000 +#define MDC_DCFG_16BPP_MODE_MASK 0x00000C00 +#define MDC_DCFG_16BPP 0x00000000 +#define MDC_DCFG_15BPP 0x00000400 +#define MDC_DCFG_12BPP 0x00000800 +#define MDC_DCFG_DISP_MODE_MASK 0x00000300 +#define MDC_DCFG_DISP_MODE_8BPP 0x00000000 +#define MDC_DCFG_DISP_MODE_16BPP 0x00000100 +#define MDC_DCFG_DISP_MODE_24BPP 0x00000200 +#define MDC_DCFG_SCLE 0x00000080 +#define MDC_DCFG_TRUP 0x00000040 +#define MDC_DCFG_VIEN 0x00000020 +#define MDC_DCFG_VDEN 0x00000010 +#define MDC_DCFG_GDEN 0x00000008 +#define MDC_DCFG_VCKE 0x00000004 +#define MDC_DCFG_PCKE 0x00000002 +#define MDC_DCFG_TGEN 0x00000001 + +/* MDC_LINE_CNT BIT FIELDS */ + +#define MDC_LNCNT_DNA 0x80000000 +#define MDC_LNCNT_VNA 0x40000000 +#define MDC_LNCNT_VSA 0x20000000 +#define MDC_LNCNT_VINT 0x10000000 +#define MDC_LNCNT_FLIP 0x08000000 +#define MDC_LNCNT_V_LINE_CNT 0x07FF0000 +#define MDC_LNCNT_VFLIP 0x00008000 +#define MDC_LNCNT_SIGC 0x00004000 +#define MDC_LNCNT_SS_LINE_CMP 0x000007FF + +/* MDC_FB_ST_OFFSET BIT FIELDS */ + +#define MDC_FB_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_CB_ST_OFFSET BIT FIELDS */ + +#define MDC_CB_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_CURS_ST_OFFSET BIT FIELDS */ + +#define MDC_CURS_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_ICON_ST_OFFSET BIT FIELDS */ + +#define MDC_ICON_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_VID_Y_ST_OFFSET BIT FIELDS */ + +#define MDC_VID_Y_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_VID_U_ST_OFFSET BIT FIELDS */ + +#define MDC_VID_U_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_VID_V_ST_OFFSET BIT FIELDS */ + +#define MDC_VID_V_ST_OFFSET_MASK 0x0FFFFFFF + +/* MDC_LINE_SIZE BIT FIELDS */ + +#define MDC_LINE_SIZE_VLS_MASK 0xFF000000 +#define MDC_LINE_SIZE_CBLS_MASK 0x007F0000 +#define MDC_LINE_SIZE_FBLS_MASK 0x000007FF + +/* MDC_GFX_PITCH BIT FIELDS */ + +#define MDC_GFX_PITCH_CBP_MASK 0xFFFF0000 +#define MDC_GFX_PITCH_FBP_MASK 0x0000FFFF + +/* MDC_VID_YUV_PITCH BIT FIELDS */ + +#define MDC_YUV_PITCH_UVP_MASK 0xFFFF0000 +#define MDC_YUV_PITCH_YBP_MASK 0x0000FFFF + +/* MDC_H_ACTIVE_TIMING BIT FIELDS */ + +#define MDC_HAT_HT_MASK 0x0FF80000 +#define MDC_HAT_HA_MASK 0x00000FF8 + +/* MDC_H_BLANK_TIMING BIT FIELDS */ + +#define MDC_HBT_HBE_MASK 0x0FF80000 +#define MDC_HBT_HBS_MASK 0x00000FF8 + +/* MDC_H_SYNC_TIMING BIT FIELDS */ + +#define MDC_HST_HSE_MASK 0x0FF80000 +#define MDC_HST_HSS_MASK 0x00000FF8 + +/* MDC_V_ACTIVE_TIMING BIT FIELDS */ + +#define MDC_VAT_VT_MASK 0x07FF0000 +#define MDC_VAT_VA_MASK 0x000007FF + +/* MDC_V_BLANK_TIMING BIT FIELDS */ + +#define MDC_VBT_VBE_MASK 0x07FF0000 +#define MDC_VBT_VBS_MASK 0x000007FF + +/* MDC_V_SYNC_TIMING BIT FIELDS */ + +#define MDC_VST_VSE_MASK 0x07FF0000 +#define MDC_VST_VSS_MASK 0x000007FF + +/* MDC_DV_CTL BIT DEFINITIONS */ + +#define MDC_DV_LINE_SIZE_MASK 0x00000C00 +#define MDC_DV_LINE_SIZE_1024 0x00000000 +#define MDC_DV_LINE_SIZE_2048 0x00000400 +#define MDC_DV_LINE_SIZE_4096 0x00000800 +#define MDC_DV_LINE_SIZE_8192 0x00000C00 + +/* VGA DEFINITIONS */ + +#define MDC_SEQUENCER_INDEX 0x03C4 +#define MDC_SEQUENCER_DATA 0x03C5 +#define MDC_SEQUENCER_RESET 0x00 +#define MDC_SEQUENCER_CLK_MODE 0x01 + +#define MDC_RESET_VGA_DISP_ENABLE 0x03 +#define MDC_CLK_MODE_SCREEN_OFF 0x20 + + +/*---------------------------------------------------*/ +/* REDCLOUD DISPLAY FILTER */ +/*---------------------------------------------------*/ + +/* RCDF VIDEO REGISTER DEFINITIONS */ + +#define RCDF_VIDEO_CONFIG 0x000 +#define RCDF_DISPLAY_CONFIG 0x008 +#define RCDF_VIDEO_X_POS 0x010 +#define RCDF_VIDEO_Y_POS 0x018 +#define RCDF_VIDEO_SCALE 0x020 +#define RCDF_VIDEO_COLOR_KEY 0x028 +#define RCDF_VIDEO_COLOR_MASK 0x030 +#define RCDF_PALETTE_ADDRESS 0x038 +#define RCDF_PALETTE_DATA 0x040 +#define RCDF_VID_MISC 0x050 +#define RCDF_VID_CLOCK_SELECT 0x058 +#define RCDF_VIDEO_DOWNSCALER_CONTROL 0x078 +#define RCDF_VIDEO_DOWNSCALER_COEFFICIENTS 0x080 +#define RCDF_VID_CRC 0x088 +#define RCDF_VID_CRC32 0x090 +#define RCDF_VID_ALPHA_CONTROL 0x098 +#define RCDF_CURSOR_COLOR_KEY 0x0A0 +#define RCDF_CURSOR_COLOR_MASK 0x0A8 +#define RCDF_CURSOR_COLOR_1 0x0B0 +#define RCDF_CURSOR_COLOR_2 0x0B8 +#define RCDF_ALPHA_XPOS_1 0x0C0 +#define RCDF_ALPHA_YPOS_1 0x0C8 +#define RCDF_ALPHA_COLOR_1 0x0D0 +#define RCDF_ALPHA_CONTROL_1 0x0D8 +#define RCDF_ALPHA_XPOS_2 0x0E0 +#define RCDF_ALPHA_YPOS_2 0x0E8 +#define RCDF_ALPHA_COLOR_2 0x0F0 +#define RCDF_ALPHA_CONTROL_2 0x0F8 +#define RCDF_ALPHA_XPOS_3 0x100 +#define RCDF_ALPHA_YPOS_3 0x108 +#define RCDF_ALPHA_COLOR_3 0x110 +#define RCDF_ALPHA_CONTROL_3 0x118 +#define RCDF_VIDEO_REQUEST 0x120 +#define RCDF_ALPHA_WATCH 0x128 +#define RCDF_VIDEO_TEST_MODE 0x210 +#define RCDF_POWER_MANAGEMENT 0x410 + +/* DISPLAY FILTER POWER MANAGEMENT DEFINITIONS */ + +#define RCDF_PM_PANEL_POWER_ON 0x01000000 + +/* DISPLAY FILTER MSRS */ + +#define RCDF_MBD_MSR_DIAG_DF 0x2010 +#define RCDF_DIAG_32BIT_CRC 0x80000000 + +/* "RCDF_VIDEO_CONFIG" BIT DEFINITIONS */ + +#define RCDF_VCFG_VID_EN 0x00000001 +#define RCDF_VCFG_VID_INP_FORMAT 0x0000000C +#define RCDF_VCFG_X_FILTER_EN 0x00000040 +#define RCDF_VCFG_Y_FILTER_EN 0x00000080 +#define RCDF_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 +#define RCDF_VCFG_INIT_READ_MASK 0x01FF0000 +#define RCDF_VCFG_LINE_SIZE_UPPER 0x08000000 +#define RCDF_VCFG_4_2_0_MODE 0x10000000 +#define RCDF_VCFG_UYVY_FORMAT 0x00000000 +#define RCDF_VCFG_Y2YU_FORMAT 0x00000004 +#define RCDF_VCFG_YUYV_FORMAT 0x00000008 +#define RCDF_VCFG_YVYU_FORMAT 0x0000000C + +/* "RCDF_DISPLAY_CONFIG" BIT DEFINITIONS */ + +#define RCDF_DCFG_DIS_EN 0x00000001 +#define RCDF_DCFG_HSYNC_EN 0x00000002 +#define RCDF_DCFG_VSYNC_EN 0x00000004 +#define RCDF_DCFG_DAC_BL_EN 0x00000008 +#define RCDF_DCFG_FP_PWR_EN 0x00000040 +#define RCDF_DCFG_FP_DATA_EN 0x00000080 +#define RCDF_DCFG_CRT_HSYNC_POL 0x00000100 +#define RCDF_DCFG_CRT_VSYNC_POL 0x00000200 +#define RCDF_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 +#define RCDF_DCFG_CRT_SYNC_SKW_INIT 0x00010000 +#define RCDF_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 +#define RCDF_DCFG_PWR_SEQ_DLY_INIT 0x00080000 +#define RCDF_DCFG_VG_CK 0x00100000 +#define RCDF_DCFG_GV_PAL_BYP 0x00200000 +#define RCDF_DAC_VREF 0x04000000 +#define RCDF_FP_ON_STATUS 0x08000000 + +/* "RCDF_VID_MISC" BIT DEFINITIONS */ + +#define RCDF_GAMMA_BYPASS_BOTH 0x00000001 +#define RCDF_DAC_POWER_DOWN 0x00000400 +#define RCDF_ANALOG_POWER_DOWN 0x00000800 + +/* "RCDF_VIDEO_DOWNSCALER_CONTROL" BIT DEFINITIONS */ + +#define RCDF_VIDEO_DOWNSCALE_ENABLE 0x00000001 +#define RCDF_VIDEO_DOWNSCALE_FACTOR_POS 1 +#define RCDF_VIDEO_DOWNSCALE_FACTOR_MASK 0x0000001E +#define RCDF_VIDEO_DOWNSCALE_TYPE_A 0x00000000 +#define RCDF_VIDEO_DOWNSCALE_TYPE_B 0x00000040 +#define RCDF_VIDEO_DOWNSCALE_TYPE_MASK 0x00000040 + +/* "RCDF_VIDEO_DOWNSCALER_COEFFICIENTS" BIT DEFINITIONS */ + +#define RCDF_VIDEO_DOWNSCALER_COEF1_POS 0 +#define RCDF_VIDEO_DOWNSCALER_COEF2_POS 8 +#define RCDF_VIDEO_DOWNSCALER_COEF3_POS 16 +#define RCDF_VIDEO_DOWNSCALER_COEF4_POS 24 +#define RCDF_VIDEO_DOWNSCALER_COEF_MASK 0xF + +/* VIDEO DE-INTERLACING AND ALPHA CONTROL */ + +#define RCDF_NO_CK_OUTSIDE_ALPHA 0x00000100 +#define RCDF_CSC_VIDEO_YUV_TO_RGB 0x00000400 +#define RCDF_VIDEO_INPUT_IS_RGB 0x00002000 +#define RCDF_ALPHA1_PRIORITY_POS 16 +#define RCDF_ALPHA1_PRIORITY_MASK 0x00030000 +#define RCDF_ALPHA2_PRIORITY_POS 18 +#define RCDF_ALPHA2_PRIORITY_MASK 0x000C0000 +#define RCDF_ALPHA3_PRIORITY_POS 20 +#define RCDF_ALPHA3_PRIORITY_MASK 0x00300000 + +/* VIDEO CURSOR COLOR KEY DEFINITIONS */ + +#define RCDF_CURSOR_COLOR_KEY_ENABLE 0x20000000 +#define RCDF_CURSOR_COLOR_KEY_OFFSET_POS 24 +#define RCDF_CURSOR_COLOR_BITS 23 +#define RCDF_COLOR_MASK 0x00FFFFFF /* 24 significant bits */ + +/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */ + +#define RCDF_ALPHA_COLOR_ENABLE 0x01000000 + +/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */ + +#define RCDF_ACTRL_WIN_ENABLE 0x00010000 +#define RCDF_ACTRL_LOAD_ALPHA 0x00020000 + +/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */ + +#define RCDF_VIDEO_Y_REQUEST_POS 0 +#define RCDF_VIDEO_X_REQUEST_POS 16 +#define RCDF_VIDEO_REQUEST_MASK 0x000007FF + +/* GEODELINK DEVICE MSR REGISTER SUMMARY */ + +#define MBD_MSR_CAP 0x2000 /* Device Capabilities */ +#define MBD_MSR_CONFIG 0x2001 /* Device Master Configuration Register */ +#define MBD_MSR_SMI 0x2002 /* MBus Device SMI Register */ +#define MBD_MSR_ERROR 0x2003 /* MBus Device Error */ +#define MBD_MSR_PM 0x2004 /* MBus Device Power Management Register */ +#define MBD_MSR_DIAG 0x2005 /* Mbus Device Diagnostic Register */ + +/* DISPLAY FILTER MBD_MSR_DIAG DEFINITIONS */ + +#define RCDF_MBD_DIAG_SEL0 0x00007FFF /* Lower 32-bits of Diag Bus Select */ +#define RCDF_MBD_DIAG_EN0 0x00008000 /* Enable for lower 32-bits of diag bus */ +#define RCDF_MBD_DIAG_SEL1 0x7FFF0000 /* Upper 32-bits of Diag Bus Select */ +#define RCDF_MBD_DIAG_EN1 0x80000000 /* Enable for upper 32-bits of diag bus */ + +/* DISPLAY FILTER MBD_MSR_CONFIG DEFINITIONS */ + +#define RCDF_CONFIG_FMT_MASK 0x00000038 /* Output Format */ +#define RCDF_CONFIG_FMT_CRT 0x00000000 +#define RCDF_CONFIG_FMT_FP 0x00000008 + +/* MCP MSR DEFINITIONS */ + +#define MCP_CLKOFF 0x0010 +#define MCP_CLKACTIVE 0x0011 +#define MCP_CLKDISABLE 0x0012 +#define MCP_CLK4ACK 0x0013 +#define MCP_SYS_RSTPLL 0x0014 +#define MCP_DOTPLL 0x0015 +#define MCP_DBGCLKCTL 0x0016 +#define MCP_RC_REVID 0x0017 +#define MCP_SETM0CTL 0x0040 +#define MCP_SETN0CTL 0x0048 +#define MCP_CMPVAL0 0x0050 +#define MCP_CMPMASK0 0x0051 +#define MCP_REGA 0x0058 +#define MCP_REGB 0x0059 +#define MCP_REGAMASK 0x005A +#define MCP_REGAVAL 0x005B +#define MCP_REGBMASK 0x005C +#define MCP_REGBVAL 0x005D +#define MCP_FIFOCTL 0x005E +#define MCP_DIAGCTL 0x005F +#define MCP_H0CTL 0x0060 +#define MCP_XSTATE 0x0066 +#define MCP_YSTATE 0x0067 +#define MCP_ACTION0 0x0068 + +/* MCP_SYS_RSTPLL DEFINITIONS */ + +#define MCP_DOTPOSTDIV3 0x00000008 +#define MCP_DOTPREMULT2 0x00000004 +#define MCP_DOTPREDIV2 0x00000002 +#define MCP_DOTPLL_HALFPIX 0x01000000 + +/* MCP MBD_MSR_DIAG DEFINITIONS */ + +#define MCP_MBD_DIAG_SEL0 0x00000007 +#define MCP_MBD_DIAG_EN0 0x00008000 +#define MCP_MBD_DIAG_SEL1 0x00070000 +#define MCP_MBD_DIAG_EN1 0x80000000 + +/* MCP_DOTPLL DEFINITIONS */ + +#define MCP_DOTPLL_P 0x00000003 +#define MCP_DOTPLL_N 0x000001FC +#define MCP_DOTPLL_M 0x00001E00 +#define MCP_DOTPLL_LOCK 0x02000000 +#define MCP_DOTPLL_BYPASS 0x00008000 + + +/*---------------------------------------------------*/ +/* THIRD GENERATION DISPLAY CONTROLLER (CASTLE) */ +/*---------------------------------------------------*/ + +#define DC3_VG_SPARE_MSR 0x2011 + +#define DC3_UNLOCK 0x00000000 /* Unlock register */ +#define DC3_GENERAL_CFG 0x00000004 /* Config registers */ +#define DC3_DISPLAY_CFG 0x00000008 +#define DC3_ARB_CFG 0x0000000C + +#define DC3_FB_ST_OFFSET 0x00000010 /* Frame buffer start offset */ +#define DC3_CB_ST_OFFSET 0x00000014 /* Compression start offset */ +#define DC3_CURS_ST_OFFSET 0x00000018 /* Cursor buffer start offset */ +#define DC3_VID_Y_ST_OFFSET 0x00000020 /* Video Y Buffer start offset */ +#define DC3_VID_U_ST_OFFSET 0x00000024 /* Video U Buffer start offset */ +#define DC3_VID_V_ST_OFFSET 0x00000028 /* Video V Buffer start offset */ +#define DC3_LINE_SIZE 0x00000030 /* Video, CB, and FB line sizes */ +#define DC3_GFX_PITCH 0x00000034 /* FB and DB skip counts */ +#define DC3_VID_YUV_PITCH 0x00000038 /* Y, U and V buffer skip counts */ + +#define DC3_H_ACTIVE_TIMING 0x00000040 /* Horizontal timings */ +#define DC3_H_BLANK_TIMING 0x00000044 +#define DC3_H_SYNC_TIMING 0x00000048 +#define DC3_V_ACTIVE_TIMING 0x00000050 /* Vertical Timings */ +#define DC3_V_BLANK_TIMING 0x00000054 +#define DC3_V_SYNC_TIMING 0x00000058 + +#define DC3_CURSOR_X 0x00000060 /* Cursor X position */ +#define DC3_CURSOR_Y 0x00000064 /* Cursor Y Position */ +#define DC3_LINE_CNT_STATUS 0x0000006C /* Icon Y Position */ + +#define DC3_PAL_ADDRESS 0x00000070 /* Palette Address */ +#define DC3_PAL_DATA 0x00000074 /* Palette Data */ +#define DC3_DFIFO_DIAG 0x00000078 /* Display FIFO diagnostic */ +#define DC3_CFIFO_DIAG 0x0000007C /* Compression FIFO diagnostic */ + +#define DC3_VID_DS_DELTA 0x00000080 /* Vertical Downscaling fraction */ + +#define DC3_PHY_MEM_OFFSET 0x00000084 /* VG Base Address Register */ +#define DC3_DV_CTL 0x00000088 /* Dirty-Valid Control Register */ +#define DC3_DV_ACC 0x0000008C /* Dirty-Valid RAM Access */ + +#define DC3_GFX_SCALE 0x00000090 +#define DC3_IRQ_CTL 0x00000094 + +#define DC3_COLOR_KEY 0x000000B8 /* Graphics color key */ +#define DC3_COLOR_MASK 0x000000BC /* Graphics color key mask */ +#define DC3_COLOR_KEY_X 0x000000C0 /* Color Key X Region */ +#define DC3_COLOR_KEY_Y 0x000000C4 /* Color Key Y Region */ + +/* UNLOCK VALUE */ + +#define DC3_UNLOCK_VALUE 0x00004758 /* used to unlock DC regs */ + +/* VG SPARE MSR FIELDS */ + +#define VG_SPARE_DISABLE_CFIFO_HGO 0x00000800 +#define VG_SPARE_VFIFO_ARB_SELECT 0x00000400 +#define VG_SPARE_WM_LPEN_OVRD 0x00000200 +#define VG_SPARE_LOAD_WM_LPEN_MASK 0x00000100 +#define VG_SPARE_DISABLE_INIT_VID_PRI 0x00000080 +#define VG_SPARE_DISABLE_VFIFO_WM 0x00000040 +#define VG_SPARE_DISABLE_CWD_CHECK 0x00000020 +#define VG_SPARE_PIX8_PAN_FIX 0x00000010 +#define VG_SPARE_FIRST_REQ_MASK 0x00000020 + +/* VG MBUS DEVICE SMI MSR FIELDS */ + +#define DC3_VG_BL_MASK 0x00000001 +#define DC3_MISC_MASK 0x00000002 +#define DC3_ISR0_MASK 0x00000004 +#define DC3_VGA_BL_MASK 0x00000008 +#define DC3_CRTCIO_MSK 0x00000010 +#define DC3_VG_BLANK_SMI 0x00000001 +#define DC3_MISC_SMI 0x00000002 +#define DC3_ISR0_SMI 0x00000004 +#define DC3_VGA_BLANK_SMI 0x00000008 +#define DC3_CRTCIO_SMI 0x00000010 + +/* DC3_GENERAL_CFG BIT FIELDS */ + +#define DC3_GCFG_DBUG 0x80000000 +#define DC3_GCFG_DBSL 0x40000000 +#define DC3_GCFG_CFRW 0x20000000 +#define DC3_GCFG_DIAG 0x10000000 +#define DC3_GCFG_SGFR 0x04000000 +#define DC3_GCFG_SGRE 0x02000000 +#define DC3_GCFG_SIGE 0x01000000 +#define DC3_GCFG_YUVM 0x00100000 +#define DC3_GCFG_VDSE 0x00080000 +#define DC3_GCFG_VGAFT 0x00040000 +#define DC3_GCFG_FDTY 0x00020000 +#define DC3_GCFG_STFM 0x00010000 +#define DC3_GCFG_DFHPEL_MASK 0x0000F000 +#define DC3_GCFG_DFHPSL_MASK 0x00000F00 +#define DC3_GCFG_VGAE 0x00000080 +#define DC3_GCFG_DECE 0x00000040 +#define DC3_GCFG_CMPE 0x00000020 +#define DC3_GCFG_VIDE 0x00000008 +#define DC3_GCFG_CURE 0x00000002 +#define DC3_GCFG_DFLE 0x00000001 + +/* DC3_DISPLAY_CFG BIT FIELDS */ + +#define DC3_DCFG_VISL 0x08000000 +#define DC3_DCFG_FRLK 0x04000000 +#define DC3_DCFG_PALB 0x02000000 +#define DC3_DCFG_PIX_PAN_MASK 0x00F00000 +#define DC3_DCFG_DCEN 0x00080000 +#define DC3_DCFG_16BPP_MODE_MASK 0x00000C00 +#define DC3_DCFG_16BPP 0x00000000 +#define DC3_DCFG_15BPP 0x00000400 +#define DC3_DCFG_12BPP 0x00000800 +#define DC3_DCFG_DISP_MODE_MASK 0x00000300 +#define DC3_DCFG_DISP_MODE_8BPP 0x00000000 +#define DC3_DCFG_DISP_MODE_16BPP 0x00000100 +#define DC3_DCFG_DISP_MODE_24BPP 0x00000200 +#define DC3_DCFG_SCLE 0x00000080 +#define DC3_DCFG_TRUP 0x00000040 +#define DC3_DCFG_VIEN 0x00000020 +#define DC3_DCFG_VDEN 0x00000010 +#define DC3_DCFG_GDEN 0x00000008 +#define DC3_DCFG_VCKE 0x00000004 +#define DC3_DCFG_PCKE 0x00000002 +#define DC3_DCFG_TGEN 0x00000001 + +/* DC3_LINE_CNT BIT FIELDS */ + +#define DC3_LNCNT_DNA 0x80000000 +#define DC3_LNCNT_VNA 0x40000000 +#define DC3_LNCNT_VSA 0x20000000 +#define DC3_LNCNT_VINT 0x10000000 +#define DC3_LNCNT_FLIP 0x08000000 +#define DC3_LNCNT_V_LINE_CNT 0x07FF0000 +#define DC3_LNCNT_VFLIP 0x00008000 +#define DC3_LNCNT_SIGC 0x00004000 +#define DC3_LNCNT_SS_LINE_CMP 0x000007FF + +/* DC3_FB_ST_OFFSET BIT FIELDS */ + +#define DC3_FB_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_CB_ST_OFFSET BIT FIELDS */ + +#define DC3_CB_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_CURS_ST_OFFSET BIT FIELDS */ + +#define DC3_CURS_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_ICON_ST_OFFSET BIT FIELDS */ + +#define DC3_ICON_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_VID_Y_ST_OFFSET BIT FIELDS */ + +#define DC3_VID_Y_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_VID_U_ST_OFFSET BIT FIELDS */ + +#define DC3_VID_U_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_VID_V_ST_OFFSET BIT FIELDS */ + +#define DC3_VID_V_ST_OFFSET_MASK 0x0FFFFFFF + +/* DC3_LINE_SIZE BIT FIELDS */ + +#define DC3_LINE_SIZE_VLS_MASK 0x3FF00000 +#define DC3_LINE_SIZE_CBLS_MASK 0x0007F000 +#define DC3_LINE_SIZE_FBLS_MASK 0x000003FF +#define DC3_LINE_SIZE_CB_SHIFT 12 +#define DC3_LINE_SIZE_VB_SHIFT 20 + +/* DC3_GFX_PITCH BIT FIELDS */ + +#define DC3_GFX_PITCH_CBP_MASK 0xFFFF0000 +#define DC3_GFX_PITCH_FBP_MASK 0x0000FFFF + +/* DC3_VID_YUV_PITCH BIT FIELDS */ + +#define DC3_YUV_PITCH_UVP_MASK 0xFFFF0000 +#define DC3_YUV_PITCH_YBP_MASK 0x0000FFFF + +/* DC3_H_ACTIVE_TIMING BIT FIELDS */ + +#define DC3_HAT_HT_MASK 0x0FF80000 +#define DC3_HAT_HA_MASK 0x00000FF8 + +/* DC3_H_BLANK_TIMING BIT FIELDS */ + +#define DC3_HBT_HBE_MASK 0x0FF80000 +#define DC3_HBT_HBS_MASK 0x00000FF8 + +/* DC3_H_SYNC_TIMING BIT FIELDS */ + +#define DC3_HST_HSE_MASK 0x0FF80000 +#define DC3_HST_HSS_MASK 0x00000FF8 + +/* DC3_V_ACTIVE_TIMING BIT FIELDS */ + +#define DC3_VAT_VT_MASK 0x07FF0000 +#define DC3_VAT_VA_MASK 0x000007FF + +/* DC3_V_BLANK_TIMING BIT FIELDS */ + +#define DC3_VBT_VBE_MASK 0x07FF0000 +#define DC3_VBT_VBS_MASK 0x000007FF + +/* DC3_V_SYNC_TIMING BIT FIELDS */ + +#define DC3_VST_VSE_MASK 0x07FF0000 +#define DC3_VST_VSS_MASK 0x000007FF + +/* DC3_DV_CTL BIT DEFINITIONS */ + +#define DC3_DV_LINE_SIZE_MASK 0x00000C00 +#define DC3_DV_LINE_SIZE_1024 0x00000000 +#define DC3_DV_LINE_SIZE_2048 0x00000400 +#define DC3_DV_LINE_SIZE_4096 0x00000800 +#define DC3_DV_LINE_SIZE_8192 0x00000C00 + +#define DC3_CLR_KEY_DATA_MASK 0x00FFFFFF +#define DC3_CLR_KEY_ENABLE 0x01000000 +#define DC3_CLR_KEY_INVERT 0x02000000 + +/* VGA DEFINITIONS */ + +#define DC3_SEQUENCER_INDEX 0x03C4 +#define DC3_SEQUENCER_DATA 0x03C5 +#define DC3_SEQUENCER_RESET 0x00 +#define DC3_SEQUENCER_CLK_MODE 0x01 + +#define DC3_RESET_VGA_DISP_ENABLE 0x03 +#define DC3_CLK_MODE_SCREEN_OFF 0x20 + +/*---------------------------------------------------*/ +/* CASTLE DISPLAY FILTER */ +/*---------------------------------------------------*/ + +/* CASTLE VIDEO REGISTER DEFINITIONS */ + +#define CASTLE_VIDEO_CONFIG 0x000 +#define CASTLE_DISPLAY_CONFIG 0x008 +#define CASTLE_VIDEO_X_POS 0x010 +#define CASTLE_VIDEO_Y_POS 0x018 +#define CASTLE_VIDEO_SCALER 0x020 +#define CASTLE_VIDEO_COLOR_KEY 0x028 +#define CASTLE_VIDEO_COLOR_MASK 0x030 +#define CASTLE_PALETTE_ADDRESS 0x038 +#define CASTLE_PALETTE_DATA 0x040 +#define CASTLE_VID_MISC 0x050 +#define CASTLE_VIDEO_YSCALE 0x060 +#define CASTLE_VIDEO_XSCALE 0x068 +#define CASTLE_VIDEO_DOWNSCALER_CONTROL 0x078 +#define CASTLE_VID_CRC 0x088 +#define CASTLE_VID_CRC32 0x090 +#define CASTLE_VID_ALPHA_CONTROL 0x098 +#define CASTLE_CURSOR_COLOR_KEY 0x0A0 +#define CASTLE_CURSOR_COLOR_MASK 0x0A8 +#define CASTLE_CURSOR_COLOR_1 0x0B0 +#define CASTLE_CURSOR_COLOR_2 0x0B8 +#define CASTLE_ALPHA_XPOS_1 0x0C0 +#define CASTLE_ALPHA_YPOS_1 0x0C8 +#define CASTLE_ALPHA_COLOR_1 0x0D0 +#define CASTLE_ALPHA_CONTROL_1 0x0D8 +#define CASTLE_ALPHA_XPOS_2 0x0E0 +#define CASTLE_ALPHA_YPOS_2 0x0E8 +#define CASTLE_ALPHA_COLOR_2 0x0F0 +#define CASTLE_ALPHA_CONTROL_2 0x0F8 +#define CASTLE_ALPHA_XPOS_3 0x100 +#define CASTLE_ALPHA_YPOS_3 0x108 +#define CASTLE_ALPHA_COLOR_3 0x110 +#define CASTLE_ALPHA_CONTROL_3 0x118 +#define CASTLE_VIDEO_REQUEST 0x120 +#define CASTLE_ALPHA_WATCH 0x128 +#define CASTLE_VIDEO_TEST_MODE 0x210 +#define CASTLE_POWER_MANAGEMENT 0x410 +#define CASTLE_COEFFICIENT_BASE 0x1000 + +/* DISPLAY FILTER POWER MANAGEMENT DEFINITIONS */ + +#define CASTLE_PM_PANEL_POWER_ON 0x01000000 + +/* DISPLAY FILTER MSRS */ + +#define CASTLE_MBD_MSR_DIAG_DF 0x2010 +#define CASTLE_DIAG_32BIT_CRC 0x80000000 + +/* "CASTLE_VIDEO_CONFIG" BIT DEFINITIONS */ + +#define CASTLE_VCFG_VID_EN 0x00000001 +#define CASTLE_VCFG_VID_INP_FORMAT 0x0000000C +#define CASTLE_VCFG_SC_BYP 0x00000020 +#define CASTLE_VCFG_LINE_SIZE_LOWER_MASK 0x0000FF00 +#define CASTLE_VCFG_INIT_READ_MASK 0x01FF0000 +#define CASTLE_VCFG_LINE_SIZE_BIT9 0x04000000 +#define CASTLE_VCFG_LINE_SIZE_UPPER 0x08000000 +#define CASTLE_VCFG_4_2_0_MODE 0x10000000 +#define CASTLE_VCFG_UYVY_FORMAT 0x00000000 +#define CASTLE_VCFG_Y2YU_FORMAT 0x00000004 +#define CASTLE_VCFG_YUYV_FORMAT 0x00000008 +#define CASTLE_VCFG_YVYU_FORMAT 0x0000000C + +/* "CASTLE_DISPLAY_CONFIG" BIT DEFINITIONS */ + +#define CASTLE_DCFG_DIS_EN 0x00000001 +#define CASTLE_DCFG_HSYNC_EN 0x00000002 +#define CASTLE_DCFG_VSYNC_EN 0x00000004 +#define CASTLE_DCFG_DAC_BL_EN 0x00000008 +#define CASTLE_DCFG_CRT_HSYNC_POL 0x00000100 +#define CASTLE_DCFG_CRT_VSYNC_POL 0x00000200 +#define CASTLE_DCFG_CRT_SYNC_SKW_MASK 0x0001C000 +#define CASTLE_DCFG_CRT_SYNC_SKW_INIT 0x00010000 +#define CASTLE_DCFG_PWR_SEQ_DLY_MASK 0x000E0000 +#define CASTLE_DCFG_PWR_SEQ_DLY_INIT 0x00080000 +#define CASTLE_DCFG_VG_CK 0x00100000 +#define CASTLE_DCFG_GV_PAL_BYP 0x00200000 +#define CASTLE_DAC_VREF 0x04000000 + +/* "CASTLE_VID_MISC" BIT DEFINITIONS */ + +#define CASTLE_GAMMA_BYPASS_BOTH 0x00000001 +#define CASTLE_DAC_POWER_DOWN 0x00000400 +#define CASTLE_ANALOG_POWER_DOWN 0x00000800 + +/* VIDEO DE-INTERLACING AND ALPHA CONTROL */ + +#define CASTLE_NO_CK_OUTSIDE_ALPHA 0x00000100 +#define CASTLE_CSC_VIDEO_YUV_TO_RGB 0x00000400 +#define CASTLE_CSC_GRAPHICS_RGB_TO_YUV 0x00000800 +#define CASTLE_VIDEO_INPUT_IS_RGB 0x00002000 +#define CASTLE_ALPHA1_PRIORITY_POS 16 +#define CASTLE_ALPHA1_PRIORITY_MASK 0x00030000 +#define CASTLE_ALPHA2_PRIORITY_POS 18 +#define CASTLE_ALPHA2_PRIORITY_MASK 0x000C0000 +#define CASTLE_ALPHA3_PRIORITY_POS 20 +#define CASTLE_ALPHA3_PRIORITY_MASK 0x00300000 + +/* VIDEO CURSOR COLOR KEY DEFINITIONS */ + +#define CASTLE_CURSOR_COLOR_KEY_ENABLE 0x20000000 +#define CASTLE_CURSOR_COLOR_KEY_OFFSET_POS 24 +#define CASTLE_CURSOR_COLOR_BITS 23 +#define CASTLE_COLOR_MASK 0x00FFFFFF /* 24 significant bits */ + +/* ALPHA COLOR BIT DEFINITION (REGISTERS 0x68, 0x78, AND 0x88) */ + +#define CASTLE_ALPHA_COLOR_ENABLE 0x01000000 + +/* ALPHA CONTROL BIT DEFINITIONS (REGISTERS 0x6C, 0x7C, AND 0x8C) */ + +#define CASTLE_ACTRL_WIN_ENABLE 0x00010000 +#define CASTLE_ACTRL_LOAD_ALPHA 0x00020000 + +/* CASTLE_VIDEO_SCALER DEFINITIONS */ + +#define CASTLE_SCALE_128_PHASES 0x00002000 + +/* VIDEO REQUEST DEFINITIONS (REGISTER 0x90) */ + +#define CASTLE_VIDEO_Y_REQUEST_POS 0 +#define CASTLE_VIDEO_X_REQUEST_POS 16 +#define CASTLE_VIDEO_REQUEST_MASK 0x000007FF + +/* END OF FILE */ + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_rndr.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_rndr.c 2005-12-14 11:35:14.000000000 -0700 @@ -0,0 +1,633 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to program the 2D acceleration hardware: + * + * gfx_set_bpp + * gfx_set_solid_pattern + * gfx_set_mono_pattern + * gfx_set_color_pattern + * gfx_load_color_pattern_line + * gfx_set_solid_source + * gfx_set_mono_source + * gfx_set_raster_operation + * gfx_pattern_fill + * gfx_color_pattern_fill + * gfx_screen_to_screen_blt + * gfx_screen_to_screen_xblt + * gfx_color_bitmap_to_screen_blt + * gfx_color_bitmap_to_screen_xblt + * gfx_mono_bitmap_to_screen_blt + * gfx_bresenham_line + * gfx_wait_until_idle + * */ + + +/* STATIC VARIABLES */ + +unsigned short GFXbpp = 16; +unsigned short GFXbb0Base = 0x400; +unsigned short GFXbb1Base = 0x930; +unsigned short GFXbufferWidthPixels = 400; + +unsigned short GFXpatternFlags = 0; +unsigned short GFXsourceFlags = 0; +unsigned long GFXsavedColor = 0; +unsigned short GFXsavedRop = 0; +unsigned short GFXusesDstData = 0; + +/* INCLUDE SUPPORT FOR FIRST GENERATION, IF SPECIFIED. */ + +#if GFX_2DACCEL_GU1 +#include "rndr_gu1.c" +#endif + +/* INCLUDE SUPPORT FOR SECOND GENERATION, IF SPECIFIED. */ + +#if GFX_2DACCEL_GU2 +#include "rndr_gu2.c" +#endif + +/* WRAPPERS IF DYNAMIC SELECTION */ +/* Extra layer to call either first or second generation routines. */ + +#if GFX_2DACCEL_DYNAMIC + +/*--------------------------------------------------------------------------- + * gfx_reset_pitch (PRIVATE ROUTINE - NOT PART OF API) + *--------------------------------------------------------------------------- + */ +void gfx_reset_pitch(unsigned short pitch) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_reset_pitch(pitch); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_bpp + *--------------------------------------------------------------------------- + */ +void gfx_set_bpp(unsigned short bpp) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_set_bpp(bpp); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_set_bpp(bpp); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_solid_source + *--------------------------------------------------------------------------- + */ +void gfx_set_solid_source(unsigned long color) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_set_solid_source(color); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_set_solid_source(color); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_mono_source + *--------------------------------------------------------------------------- + */ +void gfx_set_mono_source(unsigned long bgcolor, unsigned long fgcolor, + unsigned short transparent) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_set_mono_source(bgcolor, fgcolor, transparent); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_set_mono_source(bgcolor, fgcolor, transparent); +#endif +} + +void gfx_set_pattern_flags(unsigned short flags) +{ + GFXpatternFlags |= flags; +} + +/*--------------------------------------------------------------------------- + * gfx_set_solid_pattern + *--------------------------------------------------------------------------- + */ +void gfx_set_solid_pattern(unsigned long color) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_set_solid_pattern(color); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_set_solid_pattern(color); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_mono_pattern + *--------------------------------------------------------------------------- + */ +void gfx_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, unsigned char transparent) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_set_mono_pattern(bgcolor, fgcolor, data0, data1, transparent); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_set_mono_pattern(bgcolor, fgcolor, data0, data1, transparent); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_color_pattern + *--------------------------------------------------------------------------- + */ +void gfx_set_color_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, + unsigned long data2, unsigned long data3, unsigned char transparent) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_set_color_pattern(bgcolor, fgcolor, data0, data1, data2, data3, transparent); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_set_color_pattern(bgcolor, fgcolor, data0, data1, data2, data3, transparent); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_load_color_pattern_line + *--------------------------------------------------------------------------- + */ +void gfx_load_color_pattern_line(short y, unsigned long *pattern_8x8) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_load_color_pattern_line(y, pattern_8x8); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_load_color_pattern_line(y, pattern_8x8); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_raster_operation + *--------------------------------------------------------------------------- + */ +void gfx_set_raster_operation(unsigned char rop) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_set_raster_operation(rop); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_set_raster_operation(rop); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_pattern_fill + *--------------------------------------------------------------------------- + */ +void gfx_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_pattern_fill(x, y, width, height); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_pattern_fill(x, y, width, height); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_color_pattern_fill + *--------------------------------------------------------------------------- + */ +void gfx_color_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height, unsigned long *pattern) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_color_pattern_fill(x, y, width, height, pattern); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_color_pattern_fill(x, y, width, height, pattern); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_screen_to_screen_blt + *--------------------------------------------------------------------------- + */ +void gfx_screen_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_screen_to_screen_blt(srcx, srcy, dstx, dsty, width, height); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_screen_to_screen_blt(srcx, srcy, dstx, dsty, width, height); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_screen_to_screen_xblt + *--------------------------------------------------------------------------- + */ +void gfx_screen_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned long color) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_screen_to_screen_xblt(srcx, srcy, dstx, dsty, width, height, color); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_screen_to_screen_xblt(srcx, srcy, dstx, dsty, width, height, color); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_color_bitmap_to_screen_blt + *--------------------------------------------------------------------------- + */ +void gfx_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_color_bitmap_to_screen_blt(srcx, srcy, dstx, dsty, width, height, + data, pitch); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_color_bitmap_to_screen_blt(srcx, srcy, dstx, dsty, width, height, + data, pitch); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_color_bitmap_to_screen_xblt + *--------------------------------------------------------------------------- + */ +void gfx_color_bitmap_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch, + unsigned long color) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_color_bitmap_to_screen_xblt(srcx, srcy, dstx, dsty, width, height, + data, pitch, color); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_color_bitmap_to_screen_xblt(srcx, srcy, dstx, dsty, width, height, + data, pitch, color); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_mono_bitmap_to_screen_blt + *--------------------------------------------------------------------------- + */ +void gfx_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, short pitch) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_mono_bitmap_to_screen_blt(srcx, srcy, dstx, dsty, width, height, + data, pitch); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_mono_bitmap_to_screen_blt(srcx, srcy, dstx, dsty, width, height, + data, pitch); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_text_blt + *--------------------------------------------------------------------------- + */ +void gfx_text_blt(unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data) + +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_text_blt (dstx, dsty, width, height, data); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_text_blt (dstx, dsty, width, height, data); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_bresenham_line + *--------------------------------------------------------------------------- + */ +void gfx_bresenham_line(unsigned short x, unsigned short y, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_bresenham_line(x, y, length, initerr, axialerr, diagerr, flags); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_bresenham_line(x, y, length, initerr, axialerr, diagerr, flags); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_wait_until_idle + *--------------------------------------------------------------------------- + */ +void gfx_wait_until_idle(void) +{ +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + gu1_wait_until_idle(); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu2_wait_until_idle(); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_test_blt_pending + *--------------------------------------------------------------------------- + */ +int gfx_test_blt_pending(void) +{ + int retval = 0; +#if GFX_2DACCEL_GU1 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU1) + retval = gu1_test_blt_pending(); +#endif +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + retval = gu2_test_blt_pending(); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * NEW ROUTINES FOR REDCLOUD + *--------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------- + * gfx2_set_source_stride + *--------------------------------------------------------------------------- + */ +void gfx2_set_source_stride(unsigned short stride) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_set_source_stride (stride); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_set_destination_stride + *--------------------------------------------------------------------------- + */ +void gfx2_set_destination_stride(unsigned short stride) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_set_destination_stride (stride); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_set_pattern_origin + *--------------------------------------------------------------------------- + */ +void gfx2_set_pattern_origin(int x, int y) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_set_pattern_origin (x, y); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_set_source_transparency + *--------------------------------------------------------------------------- + */ +void gfx2_set_source_transparency(unsigned long color, unsigned long mask) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_set_source_transparency (color, mask); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_set_alpha_mode + *--------------------------------------------------------------------------- + */ +void gfx2_set_alpha_mode(int mode) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_set_alpha_mode (mode); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_set_alpha_value + *--------------------------------------------------------------------------- + */ +void gfx2_set_alpha_value(unsigned char value) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_set_alpha_value (value); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_pattern_fill + *--------------------------------------------------------------------------- + */ +void gfx2_pattern_fill(unsigned long dstoffset, unsigned short width, + unsigned short height) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_pattern_fill (dstoffset, width, height); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_color_pattern_fill + *--------------------------------------------------------------------------- + */ +void gfx2_color_pattern_fill(unsigned long dstoffset, unsigned short width, + unsigned short height, unsigned long *pattern) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_color_pattern_fill (dstoffset, width, height, pattern); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_screen_to_screen_blt + *--------------------------------------------------------------------------- + */ +void gfx2_screen_to_screen_blt(unsigned long srcoffset, unsigned long dstoffset, + unsigned short width, unsigned short height, int flags) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_screen_to_screen_blt (srcoffset, dstoffset, width, height, flags); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_mono_expand_blt + *--------------------------------------------------------------------------- + */ +void gfx2_mono_expand_blt(unsigned long srcbase, unsigned short srcx, + unsigned short srcy, unsigned long dstoffset, unsigned short width, + unsigned short height, int byte_packed) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_mono_expand_blt (srcbase, srcx, srcy, dstoffset, width, height, byte_packed); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_color_bitmap_to_screen_blt + *--------------------------------------------------------------------------- + */ +void gfx2_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned char *data, short pitch) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_color_bitmap_to_screen_blt (srcx, srcy, dstoffset, width, height, data, pitch); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_text_blt + *--------------------------------------------------------------------------- + */ +void gfx2_text_blt (unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned char *data) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_text_blt (dstoffset, width, height, data); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_mono_bitmap_to_screen_blt + *--------------------------------------------------------------------------- + */ +void gfx2_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned char *data, short pitch) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_mono_bitmap_to_screen_blt (srcx, srcy, dstoffset, width, height, data, pitch); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_bresenham_line + *--------------------------------------------------------------------------- + */ +void gfx2_bresenham_line(unsigned long dstoffset, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_bresenham_line (dstoffset, length, initerr, axialerr, diagerr, flags); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx2_sync_to_vblank + *--------------------------------------------------------------------------- + */ +void gfx2_sync_to_vblank(void) +{ +#if GFX_2DACCEL_GU2 + if (gfx_2daccel_type & GFX_2DACCEL_TYPE_GU2) + gu22_sync_to_vblank(); +#endif +} + +#endif /* GFX_2DACCEL_DYNAMIC */ + +/* END OF FILE */ + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_i2c.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_i2c.c 2005-12-14 11:36:15.000000000 -0700 @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to write to and read from the I2C bus. + * */ + + +/* INCLUDE ROUTINES FOR ACCESS.BUS, IF SPECIFIED */ +/* This is for SC1200 systems. */ + +#if GFX_I2C_ACCESS +#include "i2c_acc.c" +#endif + +/* INCLUDE ROUTINES FOR CS5530 GPIOs, IF SPECIFIED */ +/* This is for GXLV systems that use GPIOs on the CS5530 for I2C. */ + +#if GFX_I2C_GPIO +#include "i2c_gpio.c" +#endif + +/* WRAPPERS IF DYNAMIC SELECTION */ +/* Extra layer to call either ACCESS.bus or GPIO routines. */ + +#if GFX_I2C_DYNAMIC + +/*--------------------------------------------------------------------------- + * gfx_i2c_reset + *--------------------------------------------------------------------------- + */ +int gfx_i2c_reset(unsigned char busnum, short adr, char freq) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_I2C_ACCESS + if (gfx_i2c_type & GFX_I2C_TYPE_ACCESS) + status = acc_i2c_reset(busnum, adr, freq); +#endif +#if GFX_I2C_GPIO + if (gfx_i2c_type & GFX_I2C_TYPE_GPIO) + status = gpio_i2c_reset(busnum, adr, freq); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_select_gpio + *--------------------------------------------------------------------------- + */ +int gfx_i2c_select_gpio(int clock, int data) +{ +#if GFX_I2C_ACCESS + if (gfx_i2c_type & GFX_I2C_TYPE_ACCESS) + acc_i2c_select_gpio(clock, data); +#endif +#if GFX_I2C_GPIO + if (gfx_i2c_type & GFX_I2C_TYPE_GPIO) + gpio_i2c_select_gpio(clock, data); +#endif + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_write + *--------------------------------------------------------------------------- + */ +int gfx_i2c_write(unsigned char busnum, unsigned char chipadr, unsigned char subadr, + unsigned char bytes, unsigned char * data) +{ + int status = -1; +#if GFX_I2C_ACCESS + if (gfx_i2c_type & GFX_I2C_TYPE_ACCESS) + status = acc_i2c_write(busnum, chipadr, subadr, bytes, data); +#endif +#if GFX_I2C_GPIO + if (gfx_i2c_type & GFX_I2C_TYPE_GPIO) + status = gpio_i2c_write(busnum, chipadr, subadr, bytes, data); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_read + *--------------------------------------------------------------------------- + */ +int gfx_i2c_read(unsigned char busnum, unsigned char chipadr, unsigned char subadr, + unsigned char bytes, unsigned char * data) +{ + int status = -1; +#if GFX_I2C_ACCESS + if (gfx_i2c_type & GFX_I2C_TYPE_ACCESS) + status = acc_i2c_read(busnum, chipadr, subadr, bytes, data); +#endif +#if GFX_I2C_GPIO + if (gfx_i2c_type & GFX_I2C_TYPE_GPIO) + status = gpio_i2c_read(busnum, chipadr, subadr, bytes, data); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_init + *--------------------------------------------------------------------------- + */ +int gfx_i2c_init(void) +{ + int status = -1; +#if GFX_I2C_ACCESS + if (gfx_i2c_type & GFX_I2C_TYPE_ACCESS) + status = acc_i2c_init(); +#endif +#if GFX_I2C_GPIO + if (gfx_i2c_type & GFX_I2C_TYPE_GPIO) + status = gpio_i2c_init(); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_i2c_cleanup + *--------------------------------------------------------------------------- + */ +void gfx_i2c_cleanup(void) +{ +#if GFX_I2C_ACCESS + if (gfx_i2c_type & GFX_I2C_TYPE_ACCESS) + acc_i2c_cleanup(); +#endif +#if GFX_I2C_GPIO + if (gfx_i2c_type & GFX_I2C_TYPE_GPIO) + gpio_i2c_cleanup(); +#endif +} + +#endif /* GFX_I2C_DYNAMIC */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_rtns.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_rtns.h 2005-12-14 11:35:03.000000000 -0700 @@ -0,0 +1,575 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This header file defines the Durango routines and variables used + * to access the memory mapped regions. + * */ + + +#ifndef _gfx_rtns_h +#define _gfx_rtns_h + +/* INCLUDE DURANGO DEFINITIONS */ +/* These definitions are placed in another file to allow their inclusion */ +/* in a user application. Such applications generally work through driver */ +/* shell routines that simply pass their parameters to Durango routines. */ +/* An external file provides an easy way to provide the definitions for these */ +/* parameters without the applications gaining any Durango visisbility. */ + +#include "gfx_type.h" + +/* COMPILER OPTION FOR C++ PROGRAMS */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* DURANGO MEMORY POINTERS */ + +extern unsigned char *gfx_virt_regptr; +extern unsigned char *gfx_virt_fbptr; +extern unsigned char *gfx_virt_vidptr; +extern unsigned char *gfx_virt_vipptr; +extern unsigned char *gfx_virt_spptr; +extern unsigned char *gfx_virt_gpptr; + +extern unsigned char *gfx_phys_regptr; +extern unsigned char *gfx_phys_fbptr; +extern unsigned char *gfx_phys_vidptr; +extern unsigned char *gfx_phys_vipptr; +extern unsigned char *gfx_phys_spptr; +extern unsigned char *gfx_phys_gpptr; + +/* DURANGO VARIBLES FOR RUNTIME SELECTION AND POSSIBLE VALUES */ + +extern int gfx_display_type; +#define GFX_DISPLAY_TYPE_GU1 0x0001 +#define GFX_DISPLAY_TYPE_GU2 0x0002 +#define GFX_DISPLAY_TYPE_GU3 0x0004 + +extern int gfx_init_type; +#define GFX_INIT_TYPE_GU1 0x0001 +#define GFX_INIT_TYPE_GU2 0x0002 +#define GFX_INIT_TYPE_GU3 0x0004 + +extern int gfx_msr_type; +#define GFX_MSR_TYPE_REDCLOUD 0x0001 + +extern int gfx_2daccel_type; +#define GFX_2DACCEL_TYPE_GU1 0x0001 +#define GFX_2DACCEL_TYPE_GU2 0x0002 + +extern int gfx_video_type; +#define GFX_VIDEO_TYPE_CS5530 0x0001 +#define GFX_VIDEO_TYPE_SC1200 0x0002 +#define GFX_VIDEO_TYPE_REDCLOUD 0x0004 +#define GFX_VIDEO_TYPE_CASTLE 0x0008 + +extern int gfx_vip_type; +#define GFX_VIP_TYPE_SC1200 0x0001 + +extern int gfx_decoder_type; +#define GFX_DECODER_TYPE_SAA7114 0x0001 + +extern int gfx_tv_type; +#define GFX_TV_TYPE_SC1200 0x0001 +#define GFX_TV_TYPE_FS451 0x0002 + +extern int gfx_i2c_type; +#define GFX_I2C_TYPE_ACCESS 0x0001 +#define GFX_I2C_TYPE_GPIO 0x0002 + +/* GLOBAL CPU INFORMATION */ + +extern unsigned long gfx_cpu_version; +extern unsigned long gfx_cpu_frequency; +extern unsigned long gfx_vid_version; +extern ChipType gfx_chip_revision; + +/* ROUTINES IN GFX_INIT.C */ + +unsigned long gfx_pci_config_read(unsigned long address); +void gfx_pci_config_write(unsigned long address, unsigned long data); +unsigned long gfx_get_core_freq(void); +unsigned long gfx_detect_cpu(void); +unsigned long gfx_detect_video(void); +unsigned long gfx_get_cpu_register_base(void); +unsigned long gfx_get_graphics_register_base(void); +unsigned long gfx_get_frame_buffer_base(void); +unsigned long gfx_get_frame_buffer_size(void); +unsigned long gfx_get_vid_register_base(void); +unsigned long gfx_get_vip_register_base(void); + +/* ROUTINES IN GFX_MSR.C */ + +int gfx_msr_init (void); +DEV_STATUS gfx_id_msr_device (MSR *pDev, unsigned long address); +DEV_STATUS gfx_get_msr_dev_address (unsigned int device, unsigned long *address); +DEV_STATUS gfx_get_glink_id_at_address(unsigned int *device, unsigned long address); +DEV_STATUS gfx_msr_read (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue); +DEV_STATUS gfx_msr_write (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue); + +/* ROUTINES IN GFX_DISP.C */ + +int gfx_set_display_bpp (unsigned short bpp); +int gfx_is_display_mode_supported(int xres, int yres, int bpp, int hz); +int gfx_set_display_mode(int xres, int yres, int bpp, int hz); +int gfx_set_display_timings(unsigned short bpp, unsigned short flags, + unsigned short hactive, unsigned short hblank_start, + unsigned short hsync_start, unsigned short hsync_end, + unsigned short hblank_end, unsigned short htotal, + unsigned short vactive, unsigned short vblank_start, + unsigned short vsync_start, unsigned short vsync_end, + unsigned short vblank_end, unsigned short vtotal, + unsigned long frequency); +int gfx_set_vtotal(unsigned short vtotal); +void gfx_set_display_pitch(unsigned short pitch); +void gfx_set_display_offset(unsigned long offset); +int gfx_set_display_palette_entry(unsigned long index, unsigned long palette); +int gfx_set_display_palette(unsigned long *palette); +void gfx_video_shutdown(void); +void gfx_set_clock_frequency(unsigned long frequency); +int gfx_set_crt_enable(int enable); +void gfx_set_cursor_enable(int enable); +void gfx_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor); +void gfx_set_cursor_position(unsigned long memoffset, + unsigned short xpos, unsigned short ypos, + unsigned short xhotspot, unsigned short yhotspot); +void gfx_set_cursor_shape32(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask); +void gfx_set_cursor_shape64(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask); +void gfx_set_icon_enable (int enable); +void gfx_set_icon_colors (unsigned long color0, unsigned long color1, unsigned long color2); +void gfx_set_icon_position (unsigned long memoffset, unsigned short xpos); +void gfx_set_icon_shape64 (unsigned long memoffset, unsigned long *andmask, + unsigned long *xormask, unsigned int lines); + +int gfx_set_compression_enable(int enable); +int gfx_set_compression_offset(unsigned long offset); +int gfx_set_compression_pitch(unsigned short pitch); +int gfx_set_compression_size(unsigned short size); +void gfx_set_display_priority_high(int enable); +int gfx_test_timing_active(void); +int gfx_test_vertical_active(void); +int gfx_wait_vertical_blank(void); +void gfx_delay_milliseconds(unsigned long milliseconds); +void gfx_delay_microseconds(unsigned long microseconds); +void gfx_enable_panning(int x, int y); +int gfx_is_panel_mode_supported(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp); +int gfx_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp); +int gfx_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp); +void gfx_reset_timing_lock(void); + +/* "READ" ROUTINES IN GFX_DISP.C */ + +int gfx_get_display_details(unsigned int mode, int *xres, int *yres, int *hz); +unsigned short gfx_get_display_pitch(void); +int gfx_get_vsa2_softvga_enable(void); +int gfx_get_sync_polarities(void); +unsigned long gfx_get_clock_frequency(void); +unsigned long gfx_get_max_supported_pixel_clock (void); +int gfx_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency); +int gfx_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency); +int gfx_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency); +int gfx_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency); +int gfx_get_display_mode_count(void); +int gfx_get_display_mode(int *xres, int *yres, int *bpp, int *hz); +unsigned long gfx_get_frame_buffer_line_size (void); +unsigned short gfx_get_hactive(void); +unsigned short gfx_get_hblank_start(void); +unsigned short gfx_get_hsync_start(void); +unsigned short gfx_get_hsync_end(void); +unsigned short gfx_get_hblank_end(void); +unsigned short gfx_get_htotal(void); +unsigned short gfx_get_vactive(void); +unsigned short gfx_get_vline(void); +unsigned short gfx_get_vblank_start(void); +unsigned short gfx_get_vsync_start(void); +unsigned short gfx_get_vsync_end(void); +unsigned short gfx_get_vblank_end(void); +unsigned short gfx_get_vtotal(void); +unsigned short gfx_get_display_bpp(void); +unsigned long gfx_get_display_offset(void); +int gfx_get_display_palette_entry(unsigned long index, unsigned long *palette); +void gfx_get_display_palette(unsigned long *palette); +unsigned long gfx_get_cursor_enable(void); +unsigned long gfx_get_cursor_offset(void); +unsigned long gfx_get_cursor_position(void); +unsigned long gfx_get_cursor_clip(void); +unsigned long gfx_get_cursor_color(int color); +unsigned long gfx_get_icon_enable(void); +unsigned long gfx_get_icon_offset (void); +unsigned long gfx_get_icon_position (void); +unsigned long gfx_get_icon_color (int color); +int gfx_get_compression_enable(void); +unsigned long gfx_get_compression_offset(void); +unsigned short gfx_get_compression_pitch(void); +unsigned short gfx_get_compression_size(void); +int gfx_get_display_priority_high(void); +int gfx_get_valid_bit(int line); + +/* ROUTINES IN GFX_RNDR.C */ + +void gfx_set_bpp(unsigned short bpp); +void gfx_set_solid_pattern(unsigned long color); +void gfx_set_mono_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1, unsigned char transparency); +void gfx_set_color_pattern(unsigned long bgcolor, unsigned long fgcolor, + unsigned long data0, unsigned long data1,unsigned long data2,unsigned long data3, unsigned char transparency); +void gfx_load_color_pattern_line (short y, unsigned long *pattern_8x8); +void gfx_set_solid_source(unsigned long color); +void gfx_set_mono_source(unsigned long bgcolor, unsigned long fgcolor, + unsigned short transparent); +void gfx_set_pattern_flags(unsigned short flags); +void gfx_set_raster_operation(unsigned char rop); +void gfx_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height); +void gfx_color_pattern_fill(unsigned short x, unsigned short y, + unsigned short width, unsigned short height, unsigned long *pattern); +void gfx_screen_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height); +void gfx_screen_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned long color); +void gfx_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch); +void gfx_color_bitmap_to_screen_xblt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, long pitch, + unsigned long color); +void gfx_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data, short pitch); +void gfx_text_blt(unsigned short dstx, unsigned short dsty, unsigned short width, + unsigned short height, unsigned char *data); +void gfx_bresenham_line(unsigned short x, unsigned short y, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags); +void gfx_wait_until_idle(void); +int gfx_test_blt_pending(void); + +/* SECOND GENERATION RENDERING ROUTINES */ + +void gfx2_set_source_stride(unsigned short stride); +void gfx2_set_destination_stride(unsigned short stride); +void gfx2_set_pattern_origin(int x, int y); +void gfx2_set_source_transparency(unsigned long color, unsigned long mask); +void gfx2_set_alpha_mode(int mode); +void gfx2_set_alpha_value(unsigned char value); +void gfx2_pattern_fill(unsigned long dstoffset, unsigned short width, + unsigned short height); +void gfx2_color_pattern_fill(unsigned long dstoffset, unsigned short width, + unsigned short height, unsigned long *pattern); +void gfx2_screen_to_screen_blt(unsigned long srcoffset, unsigned long dstoffset, + unsigned short width, unsigned short height, int flags); +void gfx2_mono_expand_blt(unsigned long srcbase, unsigned short srcx, + unsigned short srcy, unsigned long dstoffset, unsigned short width, + unsigned short height, int byte_packed); +void gfx2_color_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned char *data, short pitch); +void gfx2_mono_bitmap_to_screen_blt(unsigned short srcx, unsigned short srcy, + unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned char *data, short pitch); +void gfx2_text_blt (unsigned long dstoffset, unsigned short width, unsigned short height, + unsigned char *data); +void gfx2_bresenham_line(unsigned long dstoffset, + unsigned short length, unsigned short initerr, + unsigned short axialerr, unsigned short diagerr, + unsigned short flags); +void gfx2_sync_to_vblank(void); + +/* ROUTINES IN GFX_VID.C */ + +int gfx_set_video_enable(int enable); +int gfx_set_video_format(unsigned long format); +int gfx_set_video_size(unsigned short width, unsigned short height); +int gfx_set_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch); +int gfx_set_video_offset(unsigned long offset); +int gfx_set_video_yuv_offsets (unsigned long yoffset, unsigned long uoffset, + unsigned long voffset); +int gfx_set_video_window(short x, short y, unsigned short w, unsigned short h); +int gfx_set_video_left_crop(unsigned short x); +int gfx_set_video_upscale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth); +int gfx_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth); +int gfx_set_video_vertical_downscale(unsigned short srch, unsigned short dsth); +void gfx_set_video_vertical_downscale_enable (int enable); +int gfx_set_video_downscale_config(unsigned short type, unsigned short m); +int gfx_set_video_color_key(unsigned long key, unsigned long mask, + int bluescreen); +int gfx_set_video_filter(int xfilter, int yfilter); +int gfx_set_video_palette(unsigned long *palette); +int gfx_set_graphics_palette(unsigned long *palette); +int gfx_set_video_palette_bypass (int enable); +int gfx_set_video_palette_entry (unsigned long index, unsigned long color); +int gfx_set_graphics_palette_entry (unsigned long index, unsigned long color); +int gfx_set_video_downscale_coefficients(unsigned short coef1, unsigned short coef2, + unsigned short coef3, unsigned short coef4) ; +int gfx_set_video_downscale_enable(int enable); +int gfx_set_video_source(VideoSourceType source); +int gfx_set_vbi_source(VbiSourceType source); +int gfx_set_vbi_lines(unsigned long even, unsigned long odd); +int gfx_set_vbi_total(unsigned long even, unsigned long odd); +int gfx_set_video_interlaced(int enable); +int gfx_set_color_space_YUV(int enable); +int gfx_set_vertical_scaler_offset(char offset); +int gfx_set_top_line_in_odd(int enable); +int gfx_set_genlock_delay(unsigned long delay); +int gfx_set_genlock_enable(int flags); +int gfx_set_video_cursor(unsigned long key, unsigned long mask, unsigned short select_color2, + unsigned long color1, unsigned long color2); +int gfx_set_video_cursor_enable (int enable); +int gfx_set_video_request(short x, short y); + +int gfx_select_alpha_region(int region); +int gfx_set_alpha_enable(int enable); +int gfx_set_alpha_window(short x, short y, + unsigned short width, unsigned short height); +int gfx_set_alpha_value(unsigned char alpha, char delta); +int gfx_set_alpha_priority(int priority); +int gfx_set_alpha_color(unsigned long color); +int gfx_set_alpha_color_enable(int enable); +int gfx_set_no_ck_outside_alpha(int enable); +int gfx_disable_softvga(void); +int gfx_enable_softvga(void); +int gfx_set_macrovision_enable(int enable); +unsigned long gfx_get_max_video_width(void); + +/* READ ROUTINES IN GFX_VID.C */ + +int gfx_get_video_enable(void); +int gfx_get_video_format(void); +unsigned long gfx_get_video_src_size(void); +unsigned long gfx_get_video_line_size(void); +unsigned long gfx_get_video_xclip(void); +unsigned long gfx_get_video_offset(void); +void gfx_get_video_yuv_offsets (unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset); +void gfx_get_video_yuv_pitch (unsigned long *ypitch, unsigned long *uvpitch); +unsigned long gfx_get_video_upscale(void); +unsigned long gfx_get_video_scale(void); +unsigned long gfx_get_video_downscale_delta(void); +int gfx_get_video_vertical_downscale_enable (void); +int gfx_get_video_downscale_config(unsigned short *type, unsigned short *m); +void gfx_get_video_downscale_coefficients(unsigned short *coef1, unsigned short *coef2, + unsigned short *coef3, unsigned short *coef4); +void gfx_get_video_downscale_enable(int *enable); +unsigned long gfx_get_video_dst_size(void); +unsigned long gfx_get_video_position(void); +unsigned long gfx_get_video_color_key(void); +unsigned long gfx_get_video_color_key_mask(void); +int gfx_get_video_palette_entry(unsigned long index, unsigned long *palette); +int gfx_get_video_color_key_src(void); +int gfx_get_video_filter(void); +int gfx_get_video_request(short *x, short *y); +int gfx_get_video_source(VideoSourceType *source); +int gfx_get_vbi_source(VbiSourceType *source); +unsigned long gfx_get_vbi_lines(int odd); +unsigned long gfx_get_vbi_total(int odd); +int gfx_get_video_interlaced(void); +int gfx_get_color_space_YUV(void); +int gfx_get_vertical_scaler_offset(char *offset); +unsigned long gfx_get_genlock_delay(void); +int gfx_get_genlock_enable(void); +int gfx_get_video_cursor(unsigned long *key, unsigned long *mask, unsigned short *select_color2, + unsigned long *color1, unsigned short *color2); +unsigned long gfx_read_crc(void); +unsigned long gfx_read_crc32(void); +unsigned long gfx_read_window_crc(int source, unsigned short x, unsigned short y, + unsigned short width, unsigned short height, int crc32); +int gfx_get_macrovision_enable(void); + +void gfx_get_alpha_enable(int *enable); +void gfx_get_alpha_size(unsigned short *x, unsigned short *y, + unsigned short *width, unsigned short *height); +void gfx_get_alpha_value(unsigned char *alpha, char *delta); +void gfx_get_alpha_priority(int *priority); +void gfx_get_alpha_color(unsigned long *color); + +/* ROUTINES IN GFX_VIP.C */ + +int gfx_set_vip_enable(int enable); +int gfx_set_vip_capture_run_mode(int mode); +int gfx_set_vip_base(unsigned long even, unsigned long odd); +int gfx_set_vip_pitch(unsigned long pitch); +int gfx_set_vip_mode(int mode); +int gfx_set_vbi_enable(int enable); +int gfx_set_vbi_mode(int mode); +int gfx_set_vbi_base(unsigned long even, unsigned long odd); +int gfx_set_vbi_pitch(unsigned long pitch); +int gfx_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines); +int gfx_set_vbi_interrupt(int enable); +int gfx_set_vip_bus_request_threshold_high(int enable); +int gfx_set_vip_last_line(int last_line); +int gfx_test_vip_odd_field(void); +int gfx_test_vip_bases_updated(void); +int gfx_test_vip_fifo_overflow(void); +int gfx_get_vip_line(void); + +/* READ ROUTINES IN GFX_VIP.C */ + +int gfx_get_vip_enable(void); +unsigned long gfx_get_vip_base(int odd); +unsigned long gfx_get_vip_pitch(void); +int gfx_get_vip_mode(void); +int gfx_get_vbi_enable(void); +int gfx_get_vbi_mode(void); +unsigned long gfx_get_vbi_base(int odd); +unsigned long gfx_get_vbi_pitch(void); +unsigned long gfx_get_vbi_direct(int odd); +int gfx_get_vbi_interrupt(void); +int gfx_get_vip_bus_request_threshold_high(void); + +/* ROUTINES IN GFX_DCDR.C */ + +int gfx_set_decoder_defaults(void); +int gfx_set_decoder_analog_input(unsigned char input); +int gfx_set_decoder_brightness(unsigned char brightness); +int gfx_set_decoder_contrast(unsigned char contrast); +int gfx_set_decoder_hue(char hue); +int gfx_set_decoder_saturation(unsigned char saturation); +int gfx_set_decoder_input_offset(unsigned short x, unsigned short y); +int gfx_set_decoder_input_size(unsigned short width, unsigned short height); +int gfx_set_decoder_output_size(unsigned short width, unsigned short height); +int gfx_set_decoder_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth); +int gfx_set_decoder_vbi_format(int start, int end, int format); +int gfx_set_decoder_vbi_enable(int enable); +int gfx_set_decoder_vbi_upscale(void); +int gfx_set_decoder_TV_standard(TVStandardType TVStandard); +int gfx_set_decoder_luminance_filter(unsigned char lufi); +int gfx_decoder_software_reset(void); +int gfx_decoder_detect_macrovision(void); +int gfx_decoder_detect_video(void); + +/* READ ROUTINES IN GFX_DCDR.C */ + +unsigned char gfx_get_decoder_brightness(void); +unsigned char gfx_get_decoder_contrast(void); +char gfx_get_decoder_hue(void); +unsigned char gfx_get_decoder_saturation(void); +unsigned long gfx_get_decoder_input_offset(void); +unsigned long gfx_get_decoder_input_size(void); +unsigned long gfx_get_decoder_output_size(void); +int gfx_get_decoder_vbi_format(int line); + +/* ROUTINES IN GFX_I2C.C */ + +int gfx_i2c_reset(unsigned char busnum, short adr, char freq); +int gfx_i2c_write(unsigned char busnum, unsigned char chipadr, unsigned char subadr, + unsigned char bytes, unsigned char * data); +int gfx_i2c_read(unsigned char busnum, unsigned char chipadr, unsigned char subadr, + unsigned char bytes, unsigned char * data); +int gfx_i2c_select_gpio(int clock, int data); +int gfx_i2c_init(void); +void gfx_i2c_cleanup(void); + +/* ROUTINES IN GFX_TV.C */ + +int gfx_set_tv_format(TVStandardType format, GfxOnTVType resolution); +int gfx_set_tv_output(int output); +int gfx_set_tv_enable(int enable); +int gfx_set_tv_flicker_filter(int ff); +int gfx_set_tv_sub_carrier_reset(int screset); +int gfx_set_tv_vphase(int vphase); +int gfx_set_tv_YC_delay(int delay); +int gfx_set_tvenc_reset_interval(int interval); +int gfx_set_tv_cc_enable(int enable); +int gfx_set_tv_cc_data(unsigned char data1, unsigned char data2); +int gfx_set_tv_display(int width, int height); +int gfx_test_tvout_odd_field(void); +int gfx_test_tvenc_odd_field(void); +int gfx_set_tv_field_status_invert(int enable); +int gfx_get_tv_vphase(void); +int gfx_get_tv_enable(unsigned int *p_on); +int gfx_get_tv_output(void); +int gfx_get_tv_mode_count(TVStandardType format); +int gfx_get_tv_display_mode (int *width, int *height, int *bpp, int *hz); +int gfx_get_tv_display_mode_frequency (unsigned short width, unsigned short height, TVStandardType format, int *frequency); +int gfx_is_tv_display_mode_supported (unsigned short width, unsigned short height, TVStandardType format); + +int gfx_get_tv_standard(unsigned long *p_standard); +int gfx_get_available_tv_standards(unsigned long *p_standards); +int gfx_set_tv_standard(unsigned long standard); +int gfx_get_tv_vga_mode(unsigned long *p_vga_mode); +int gfx_get_available_tv_vga_modes(unsigned long *p_vga_modes); +int gfx_set_tv_vga_mode(unsigned long vga_mode); +int gfx_get_tvout_mode(unsigned long *p_tvout_mode); +int gfx_set_tvout_mode(unsigned long tvout_mode); +int gfx_get_sharpness(int *p_sharpness); +int gfx_set_sharpness(int sharpness); +int gfx_get_flicker_filter(int *p_flicker); +int gfx_set_flicker_filter(int flicker); +int gfx_get_overscan(int *p_x, int *p_y); +int gfx_set_overscan(int x, int y); +int gfx_get_position(int *p_x, int *p_y); +int gfx_set_position(int x, int y); +int gfx_get_color(int *p_color); +int gfx_set_color(int color); +int gfx_get_brightness(int *p_brightness); +int gfx_set_brightness(int brightness); +int gfx_get_contrast(int *p_contrast); +int gfx_set_contrast(int constrast); +int gfx_get_yc_filter(unsigned int *p_yc_filter); +int gfx_set_yc_filter(unsigned int yc_filter); +int gfx_get_aps_trigger_bits(unsigned int *p_trigger_bits); +int gfx_set_aps_trigger_bits(unsigned int trigger_bits); + +/* ROUTINES IN GFX_VGA.C */ + +int gfx_get_softvga_active(void); +int gfx_vga_test_pci(void); +unsigned char gfx_vga_get_pci_command(void); +int gfx_vga_set_pci_command(unsigned char command); +int gfx_vga_seq_reset(int reset); +int gfx_vga_set_graphics_bits(void); +int gfx_vga_mode(gfx_vga_struct *vga, int xres, int yres, int bpp, int hz); +int gfx_vga_pitch(gfx_vga_struct *vga, unsigned short pitch); +int gfx_vga_save(gfx_vga_struct *vga, int flags); +int gfx_vga_restore(gfx_vga_struct *vga, int flags); +int gfx_vga_mode_switch(int active); +void gfx_vga_clear_extended(void); + +/* CLOSE BRACKET FOR C++ COMPLILATION */ + +#ifdef __cplusplus +} +#endif + +#endif /* !_gfx_rtns_h */ + +/* END OF FILE */ + + + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_msr.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_msr.c 2005-12-14 11:35:49.000000000 -0700 @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to read machine-specific registers (MSRs) + * + * Routines: + * + * gfx_msr_init + * gfx_id_msr_device + * gfx_get_msr_dev_address + * gfx_get_glink_id_at_address + * gfx_msr_read + * gfx_msr_write + * */ + + +/* INCLUDE SUPPORT FOR REDCLOUD, IF SPECIFIED */ + +#if GFX_MSR_REDCLOUD +#include "msr_rdcl.c" +#endif + +/* EXTRA WRAPPERS FOR DYNAMIC SELECTION */ + +#if GFX_MSR_DYNAMIC + +/*----------------------------------------------------------------------------- + * gfx_msr_init + *----------------------------------------------------------------------------- + */ +int gfx_msr_init () +{ + int ret_value = 0; + +#if GFX_MSR_REDCLOUD + if (gfx_msr_type & GFX_MSR_TYPE_REDCLOUD) + ret_value = redcloud_msr_init(); +#endif + + return ret_value; +} + +/*----------------------------------------------------------------------------- + * gfx_id_msr_device + *----------------------------------------------------------------------------- + */ +DEV_STATUS gfx_id_msr_device (MSR *pDev, unsigned long address) +{ + DEV_STATUS ret_value = NOT_KNOWN; + +#if GFX_MSR_REDCLOUD + if (gfx_msr_type & GFX_MSR_TYPE_REDCLOUD) + ret_value = redcloud_id_msr_device(pDev, address); +#endif + + return ret_value; +} + +/*----------------------------------------------------------------------------- + * gfx_get_msr_dev_address + *----------------------------------------------------------------------------- + */ +DEV_STATUS gfx_get_msr_dev_address (unsigned int device, unsigned long *address) +{ + DEV_STATUS ret_value = NOT_KNOWN; + +#if GFX_MSR_REDCLOUD + if (gfx_msr_type & GFX_MSR_TYPE_REDCLOUD) + ret_value = redcloud_get_msr_dev_address (device, address); +#endif + + return ret_value; +} + +/*----------------------------------------------------------------------------- + * gfx_get_glink_id_at_address + *----------------------------------------------------------------------------- + */ +DEV_STATUS gfx_get_glink_id_at_address(unsigned int *device, unsigned long address) +{ + DEV_STATUS ret_value = NOT_KNOWN; + +#if GFX_MSR_REDCLOUD + if (gfx_msr_type & GFX_MSR_TYPE_REDCLOUD) + ret_value = redcloud_get_glink_id_at_address (device, address); +#endif + + return ret_value; +} + +/*----------------------------------------------------------------------------- + * gfx_msr_read + *----------------------------------------------------------------------------- + */ +DEV_STATUS gfx_msr_read (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue) +{ + DEV_STATUS ret_value = NOT_KNOWN; + +#if GFX_MSR_REDCLOUD + if (gfx_msr_type & GFX_MSR_TYPE_REDCLOUD) + ret_value = redcloud_msr_read (device, msrRegister, msrValue); +#endif + + return ret_value; +} + +/*----------------------------------------------------------------------------- + * gfx_msr_write + *----------------------------------------------------------------------------- + */ +DEV_STATUS gfx_msr_write (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue) +{ + DEV_STATUS ret_value = NOT_KNOWN; + +#if GFX_MSR_REDCLOUD + if (gfx_msr_type & GFX_MSR_TYPE_REDCLOUD) + ret_value = redcloud_msr_write(device, msrRegister, msrValue); +#endif + + return ret_value; +} + +#endif --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_vga.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_vga.c 2005-12-14 11:31:54.000000000 -0700 @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to interface to the VGA registers. Some + * operating systems require mode sets be done through VGA, rather than + * directly using the "gfx_set_display_mode" routine. + * */ + + +/* INCLUDE SUPPORT FOR FIRST GENERATION, IF SPECIFIED. */ + +#if GFX_VGA_GU1 +#include "vga_gu1.c" +#endif + +/* WRAPPERS IF DYNAMIC SELECTION */ +/* Extra layer to call either first or second generation routines. */ + +#if GFX_VGA_DYNAMIC + +#endif /* GFX_DISPLAY_DYNAMIC */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_vid.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_vid.c 2005-12-14 11:31:43.000000000 -0700 @@ -0,0 +1,2125 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * $Workfile: gfx_vid.c $ + * + * This file contains routines to control the video overlay window. + * + * Video overlay routines: + * + * gfx_set_clock_frequency + * gfx_set_crt_enable + * gfx_set_video_enable + * gfx_set_video_format + * gfx_set_video_size + * gfx_set_video_offset + * gfx_set_video_yuv_offsets + * gfx_set_video_yuv_pitch + * gfx_set_video_scale + * gfx_set_video_upscale + * gfx_set_video_downscale_config + * gfx_set_video_downscale_coefficients + * gfx_set_video_downscale_enable + * gfx_set_video_vertical_downscale + * gfx_set_video_vertical_downscale_enable + * gfx_set_video_window + * gfx_set_video_left_crop + * gfx_set_video_color_key + * gfx_set_video_filter + * gfx_set_video_palette + * gfx_set_video_request + * gfx_set_video_source + * gfx_set_vbi_source + * gfx_set_vbi_lines + * gfx_set_vbi_total + * gfx_set_video_interlaced + * gfx_set_color_space_YUV + * gfx_set_vertical_scaler_offset + * gfx_set_top_line_in_odd + * gfx_set_genlock_delay + * gfx_set_genlock_enable + * gfx_set_video_cursor + * gfx_set_video_cursor_enable + * + * Alpha blending routines (SC1200 ONLY): + * + * gfx_select_alpha_region + * gfx_set_alpha_enable + * gfx_set_alpha_window + * gfx_set_alpha_value + * gfx_set_alpha_priority + * gfx_set_alpha_color + * gfx_set_alpha_color_enable + * gfx_set_no_ck_outside_alpha + * gfx_test_tvout_odd_field + * + * And the following routines if GFX_READ_ROUTINES is set: + * + * gfx_get_sync_polarities + * gfx_get_video_enable + * gfx_get_video_format + * gfx_get_video_src_size + * gfx_get_video_line_size + * gfx_get_video_xclip + * gfx_get_video_offset + * gfx_get_video_yuv_offsets + * gfx_get_video_yuv_pitch + * gfx_get_video_scale + * gfx_get_video_upscale + * gfx_get_video_downscale_config + * gfx_get_video_downscale_coefficients + * gfx_get_video_downscale_enable + * gfx_get_video_downscale_delta + * gfx_get_video_vertical_downscale_enable + * gfx_get_video_dst_size + * gfx_get_video_position + * gfx_get_video_color_key + * gfx_get_video_color_key_mask + * gfx_get_video_color_key_src + * gfx_get_video_filter + * gfx_get_video_request + * gfx_get_video_source + * gfx_get_vbi_source + * gfx_get_vbi_lines + * gfx_get_vbi_total + * gfx_get_video_interlaced + * gfx_get_color_space_YUV + * gfx_get_vertical_scaler_offset + * gfx_get_genlock_delay + * gfx_get_genlock_enable + * gfx_get_video_cursor + * gfx_get_clock_frequency + * gfx_read_crc + * + * Alpha blending read routines (SC1200 ONLY): + * + * gfx_get_alpha_enable + * gfx_get_alpha_size + * gfx_get_alpha_value + * gfx_get_alpha_priority + * gfx_get_alpha_color + * */ + + +/* STATIC VARIABLES FOR VIDEO OVERLAY CONTROL */ +/* These are saved to allow these routines to do clipping. */ + +unsigned long gfx_vid_offset = 0; /* copy from last gfx_set_video_offset */ +unsigned long gfx_vid_uoffset = 0; /* copy from last gfx_set_video_yuv_offsets */ +unsigned long gfx_vid_voffset = 0; /* copy from last gfx_set_video_yuv_offsets */ +unsigned long gfx_vid_srcw = 300; /* copy from last gfx_set_video_scale */ +unsigned long gfx_vid_srch = 300; /* copy from last gfx_set_video_scale */ +unsigned long gfx_vid_dstw = 300; /* copy from last gfx_set_video_scale */ +unsigned long gfx_vid_dsth = 300; /* copy from last gfx_set_video_scale */ +short gfx_vid_xpos = 0; /* copy from last gfx_set_video_window */ +short gfx_vid_ypos = 0; /* copy from last gfx_set_video_window */ +unsigned short gfx_vid_width = 0; /* copy from last gfx_set_video_window */ +unsigned short gfx_vid_height = 0; /* copy from last gfx_set_video_window */ + +int gfx_alpha_select = 0; /* currently selected alpha region */ + +int gfx_set_screen_enable(int enable); /* forward declaration */ + +/* INCLUDE SUPPORT FOR CS5530, IF SPECIFIED. */ + +#if GFX_VIDEO_CS5530 +#include "vid_5530.c" +#endif + +/* INCLUDE SUPPORT FOR SC1200, IF SPECIFIED. */ + +#if GFX_VIDEO_SC1200 +#include "vid_1200.c" +#endif + +/* INLUDE SUPPORT FOR REDCLOUD, IF SPECIFIED. */ + +#if GFX_VIDEO_REDCLOUD +#include "vid_rdcl.c" +#endif + +/* INLUDE SUPPORT FOR CASTLE, IF SPECIFIED. */ + +#if GFX_VIDEO_CASTLE +#include "vid_cstl.c" +#endif + +/*--------------------------------------------------------------------------- + * gfx_select_alpha_region + * + * This routine selects which alpha region should be used for future + * updates. The SC1200, for example, has 3 alpha windows available, + * so valid parameter values are 0..2. + *--------------------------------------------------------------------------- + */ +int gfx_select_alpha_region(int region) +{ + if (region > 2) return(GFX_STATUS_BAD_PARAMETER); + + gfx_alpha_select = region; + return(GFX_STATUS_OK); +} + +/* WRAPPERS IF DYNAMIC SELECTION */ +/* Extra layer to call either CS5530 or SC1200 routines. */ + +#if GFX_VIDEO_DYNAMIC + +/*--------------------------------------------------------------------------- + * gfx_reset_video (PRIVATE ROUTINE: NOT PART OF DURANGO API) + * + * This routine is used to disable all components of video overlay before + * performing a mode switch. + *--------------------------------------------------------------------------- + */ +void gfx_reset_video(void) +{ +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + cs5530_reset_video(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + sc1200_reset_video(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + redcloud_reset_video(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + castle_reset_video(); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_control (PRIVATE ROUTINE: NOT PART OF DURANGO API) + * + * This routine is used to configure the display output during a modeset + *--------------------------------------------------------------------------- + */ +int gfx_set_display_control(int sync_polarities) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_display_control(sync_polarities); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_display_control(sync_polarities); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_display_control(sync_polarities); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_display_control(sync_polarities); +#endif + return (status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_clock_frequency + *----------------------------------------------------------------------------- + */ +void gfx_set_clock_frequency(unsigned long frequency) +{ +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + cs5530_set_clock_frequency(frequency); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + sc1200_set_clock_frequency(frequency); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + redcloud_set_clock_frequency(frequency); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + castle_set_clock_frequency(frequency); +#endif +} + +/*----------------------------------------------------------------------------- + * gfx_set_crt_enable + *----------------------------------------------------------------------------- + */ +int gfx_set_crt_enable(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_crt_enable(enable); +#endif +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_crt_enable(enable); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_crt_enable(enable); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_crt_enable(enable); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_enable + *----------------------------------------------------------------------------- + */ +int gfx_set_video_enable(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_video_enable(enable); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_enable(enable); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_enable(enable); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_enable(enable); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_screen_enable (PRIVATE ROUTINE: NOT PART OF DURANGO API) + * + * This routine enables or disables the graphics display logic of the video processor. + *--------------------------------------------------------------------------- + */ +int gfx_set_screen_enable(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_screen_enable(enable); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_format + *----------------------------------------------------------------------------- + */ +int gfx_set_video_format(unsigned long format) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_video_format(format); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_format(format); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_format(format); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_format(format); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_size + *----------------------------------------------------------------------------- + */ +int gfx_set_video_size(unsigned short width, unsigned short height) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_video_size(width, height); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_size(width, height); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_size(width, height); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_size(width, height); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_yuv_pitch + *----------------------------------------------------------------------------- + */ +int gfx_set_video_yuv_pitch(unsigned long ypitch, unsigned long uvpitch) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_yuv_pitch (ypitch, uvpitch); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_yuv_pitch (ypitch, uvpitch); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_offset + *----------------------------------------------------------------------------- + */ +int gfx_set_video_offset(unsigned long offset) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_video_offset(offset); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_offset(offset); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_offset(offset); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_offset(offset); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_yuv_offsets + *----------------------------------------------------------------------------- + */ +int gfx_set_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, + unsigned long voffset) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_yuv_offsets (yoffset, uoffset, voffset); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_yuv_offsets (yoffset, uoffset, voffset); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_scale + *--------------------------------------------------------------------------- + */ +int gfx_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_video_scale(srcw, srch, dstw, dsth); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_scale(srcw, srch, dstw, dsth); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_scale(srcw, srch, dstw, dsth); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_scale(srcw, srch, dstw, dsth); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_upscale + *--------------------------------------------------------------------------- + */ +int gfx_set_video_upscale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_upscale(srcw, srch, dstw, dsth); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_vertical_downscale + *--------------------------------------------------------------------------- + */ +int gfx_set_video_vertical_downscale(unsigned short srch, unsigned short dsth) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_vertical_downscale(srch, dsth); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_vertical_downscale_enable + *--------------------------------------------------------------------------- + */ +void gfx_set_video_vertical_downscale_enable(int enable) +{ +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + redcloud_set_video_vertical_downscale_enable(enable); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_downscale_config + *--------------------------------------------------------------------------- + */ +int gfx_set_video_downscale_config(unsigned short type, unsigned short m) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_downscale_config(type, m); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_downscale_config(type, m); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_downscale_coefficients + *--------------------------------------------------------------------------- + */ +int gfx_set_video_downscale_coefficients(unsigned short coef1, unsigned short coef2, + unsigned short coef3, unsigned short coef4) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_downscale_coefficients(coef1, coef2, coef3, coef4); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_downscale_coefficients(coef1, coef2, coef3, coef4); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_downscale_enable + *--------------------------------------------------------------------------- + */ +int gfx_set_video_downscale_enable(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_downscale_enable(enable); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_downscale_enable(enable); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_window + *--------------------------------------------------------------------------- + */ +int gfx_set_video_window(short x, short y, unsigned short w, unsigned short h) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_video_window(x, y, w, h); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_window(x, y, w, h); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_window(x, y, w, h); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_window(x, y, w, h); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_left_crop + *--------------------------------------------------------------------------- + */ +int gfx_set_video_left_crop(unsigned short x) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_left_crop(x); +#endif +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_video_left_crop(x); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_left_crop(x); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_left_crop(x); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_color_key + *--------------------------------------------------------------------------- + */ +int gfx_set_video_color_key(unsigned long key, unsigned long mask, + int graphics) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_video_color_key(key, mask, graphics); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_color_key(key, mask, graphics); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_color_key(key, mask, graphics); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_color_key(key, mask, graphics); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_filter + *--------------------------------------------------------------------------- + */ +int gfx_set_video_filter(int xfilter, int yfilter) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_video_filter(xfilter, yfilter); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_filter(xfilter, yfilter); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_filter(xfilter, yfilter); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette + *--------------------------------------------------------------------------- + */ +int gfx_set_video_palette(unsigned long *palette) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_video_palette(palette); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_palette(palette); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_palette(palette); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_palette(palette); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_graphics_palette + *--------------------------------------------------------------------------- + */ +int gfx_set_graphics_palette(unsigned long *palette) +{ + int status = GFX_STATUS_UNSUPPORTED; + +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_graphics_palette(palette); +#endif + + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette_entry + *--------------------------------------------------------------------------- + */ +int gfx_set_video_palette_entry(unsigned long index, unsigned long palette) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_set_video_palette_entry(index, palette); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_palette_entry(index, palette); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_palette_entry(index, palette); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_palette_entry(index, palette); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_graphics_palette_entry + *--------------------------------------------------------------------------- + */ +int gfx_set_graphics_palette_entry(unsigned long index, unsigned long palette) +{ + int status = GFX_STATUS_UNSUPPORTED; + +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_graphics_palette_entry(index, palette); +#endif + + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette_bypass + *--------------------------------------------------------------------------- + */ +int gfx_set_video_palette_bypass (int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; + +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_palette_bypass(enable); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_palette_bypass(enable); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_request + *--------------------------------------------------------------------------- + */ +int gfx_set_video_request(short x, short y) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_request(x, y); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_request(x, y); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_request(x, y); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_source + *--------------------------------------------------------------------------- + */ +int gfx_set_video_source(VideoSourceType source) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_source(source); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_vbi_source + *--------------------------------------------------------------------------- + */ +int gfx_set_vbi_source(VbiSourceType source) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_vbi_source(source); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_vbi_lines + *--------------------------------------------------------------------------- + */ +int gfx_set_vbi_lines(unsigned long even, unsigned long odd) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_vbi_lines(even, odd); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_vbi_total + *--------------------------------------------------------------------------- + */ +int gfx_set_vbi_total(unsigned long even, unsigned long odd) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_vbi_total(even, odd); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_interlaced + *--------------------------------------------------------------------------- + */ +int gfx_set_video_interlaced(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_interlaced(enable); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_color_space_YUV + *--------------------------------------------------------------------------- + */ +int gfx_set_color_space_YUV(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_color_space_YUV(enable); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_vertical_scaler_offset + *--------------------------------------------------------------------------- + */ +int gfx_set_vertical_scaler_offset(char offset) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_vertical_scaler_offset(offset); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_top_line_in_odd + *--------------------------------------------------------------------------- + */ +int gfx_set_top_line_in_odd(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_top_line_in_odd(enable); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_genlock_delay + *--------------------------------------------------------------------------- + */ +int gfx_set_genlock_delay(unsigned long delay) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_genlock_delay(delay); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_genlock_enable + *--------------------------------------------------------------------------- + */ +int gfx_set_genlock_enable(int flags) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_genlock_enable(flags); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_cursor + *--------------------------------------------------------------------------- + */ +int gfx_set_video_cursor(unsigned long key, unsigned long mask, unsigned short select_color2, + unsigned long color1, unsigned long color2) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_video_cursor(key, mask, select_color2, color1, color2); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_cursor(key, mask, select_color2, color1, color2); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_cursor(key, mask, select_color2, color1, color2); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_cursor_enable + *--------------------------------------------------------------------------- + */ +int gfx_set_video_cursor_enable (int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; + +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_video_cursor_enable (enable); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_video_cursor_enable (enable); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_enable + *--------------------------------------------------------------------------- + */ +int gfx_set_alpha_enable(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_alpha_enable(enable); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_alpha_enable(enable); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_alpha_enable(enable); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_window + *--------------------------------------------------------------------------- + */ +int gfx_set_alpha_window(short x, short y, + unsigned short width, unsigned short height) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_alpha_window(x, y, width, height); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_alpha_window(x, y, width, height); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_alpha_window(x, y, width, height); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_value + *--------------------------------------------------------------------------- + */ +int gfx_set_alpha_value(unsigned char alpha, char delta) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_alpha_value(alpha, delta); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_alpha_value(alpha, delta); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_alpha_value(alpha, delta); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_priority + *--------------------------------------------------------------------------- + */ +int gfx_set_alpha_priority(int priority) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_alpha_priority(priority); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_alpha_priority(priority); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_alpha_priority(priority); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_color + *--------------------------------------------------------------------------- + */ +int gfx_set_alpha_color(unsigned long color) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_alpha_color(color); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_alpha_color(color); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_alpha_color(color); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_color_enable + *--------------------------------------------------------------------------- + */ +int gfx_set_alpha_color_enable(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_alpha_color_enable(enable); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_alpha_color_enable(enable); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_alpha_color_enable(enable); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_no_ck_outside_alpha + *--------------------------------------------------------------------------- + */ +int gfx_set_no_ck_outside_alpha(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_no_ck_outside_alpha(enable); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_set_no_ck_outside_alpha(enable); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_set_no_ck_outside_alpha(enable); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_set_macrovision_enable + *--------------------------------------------------------------------------- + */ +int gfx_set_macrovision_enable(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_set_macrovision_enable(enable); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_disable_softvga + *--------------------------------------------------------------------------- + */ +int gfx_disable_softvga(void) +{ + int status = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_disable_softvga(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_disable_softvga(); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_enable_softvga + *--------------------------------------------------------------------------- + */ +int gfx_enable_softvga(void) +{ + int status = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_enable_softvga(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_enable_softvga(); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_get_clock_frequency + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_clock_frequency(void) +{ + unsigned long frequency = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + frequency = cs5530_get_clock_frequency(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + frequency = sc1200_get_clock_frequency(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + frequency = redcloud_get_clock_frequency(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + frequency = castle_get_clock_frequency(); +#endif + return(frequency); +} + +/*--------------------------------------------------------------------------- + * gfx_get_max_video_width + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_max_video_width(void) +{ + unsigned long width = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + width = cs5530_get_max_video_width(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + width = sc1200_get_max_video_width(); +#endif + return(width); +} + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +#if GFX_READ_ROUTINES + +/*--------------------------------------------------------------------------- + * gfx_get_vsa2_softvga_enable + *--------------------------------------------------------------------------- + */ +int gfx_get_vsa2_softvga_enable(void) +{ + int enable = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + enable = cs5530_get_vsa2_softvga_enable(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + enable = sc1200_get_vsa2_softvga_enable(); +#endif + return enable; + +} + +/*--------------------------------------------------------------------------- + * gfx_get_sync_polarities + *--------------------------------------------------------------------------- + */ +int gfx_get_sync_polarities(void) +{ + int polarities = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + polarities = cs5530_get_sync_polarities(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + polarities = sc1200_get_sync_polarities(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + polarities = redcloud_get_sync_polarities(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + polarities = castle_get_sync_polarities(); +#endif + return(polarities); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_palette_entry + *--------------------------------------------------------------------------- + */ +int gfx_get_video_palette_entry(unsigned long index, unsigned long *palette) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + status = cs5530_get_video_palette_entry (index, palette); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_get_video_palette_entry (index, palette); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_get_video_palette_entry (index, palette); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_get_video_palette_entry (index, palette); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_enable + *----------------------------------------------------------------------------- + */ +int gfx_get_video_enable(void) +{ + int enable = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + enable = cs5530_get_video_enable(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + enable = sc1200_get_video_enable(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + enable = redcloud_get_video_enable(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + enable = castle_get_video_enable(); +#endif + return(enable); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_format + *----------------------------------------------------------------------------- + */ +int gfx_get_video_format(void) +{ + int format = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + format = cs5530_get_video_format(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + format = sc1200_get_video_format(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + format = redcloud_get_video_format(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + format = castle_get_video_format(); +#endif + return(format); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_src_size + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_video_src_size(void) +{ + unsigned long size = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + size = cs5530_get_video_src_size(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + size = sc1200_get_video_src_size(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + size = redcloud_get_video_src_size(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + size = castle_get_video_src_size(); +#endif + return(size); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_line_size + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_video_line_size(void) +{ + unsigned long size = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + size = cs5530_get_video_line_size(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + size = sc1200_get_video_line_size(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + size = redcloud_get_video_line_size(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + size = castle_get_video_line_size(); +#endif + return(size); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_xclip + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_video_xclip(void) +{ + unsigned long size = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + size = cs5530_get_video_xclip(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + size = sc1200_get_video_xclip(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + size = redcloud_get_video_xclip(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + size = castle_get_video_xclip(); +#endif + return(size); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_offset + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_video_offset(void) +{ + unsigned long offset = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + offset = cs5530_get_video_offset(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + offset = sc1200_get_video_offset(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + offset = redcloud_get_video_offset(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + offset = castle_get_video_offset(); +#endif + return(offset); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_yuv_offsets + *----------------------------------------------------------------------------- + */ +void gfx_get_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset) +{ +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + redcloud_get_video_yuv_offsets(yoffset, uoffset, voffset); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + castle_get_video_yuv_offsets(yoffset, uoffset, voffset); +#endif +} +/*----------------------------------------------------------------------------- + * gfx_get_video_yuv_pitch + *----------------------------------------------------------------------------- + */ +void gfx_get_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch) +{ +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + redcloud_get_video_yuv_pitch (ypitch, uvpitch); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + castle_get_video_yuv_pitch (ypitch, uvpitch); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_upscale + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_video_upscale(void) +{ + unsigned long scale = 0; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + scale = sc1200_get_video_upscale(); +#endif + return(scale); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_scale + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_video_scale(void) +{ + unsigned long scale = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + scale = cs5530_get_video_scale(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + scale = sc1200_get_video_scale(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + scale = redcloud_get_video_scale(); +#endif + return(scale); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_downscale_delta + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_video_downscale_delta(void) +{ + unsigned long delta = 0; +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + delta = redcloud_get_video_downscale_delta(); +#endif + return(delta); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_vertical_downscale_enable + *--------------------------------------------------------------------------- + */ +int gfx_get_video_vertical_downscale_enable(void) +{ + int enable = 0; +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + enable = redcloud_get_video_vertical_downscale_enable(); +#endif + return(enable); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_downscale_config + *--------------------------------------------------------------------------- + */ +int gfx_get_video_downscale_config(unsigned short *type, unsigned short *m) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_get_video_downscale_config(type, m); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_get_video_downscale_config(type, m); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_downscale_coefficients + *--------------------------------------------------------------------------- + */ +void gfx_get_video_downscale_coefficients(unsigned short *coef1, unsigned short *coef2, + unsigned short *coef3, unsigned short *coef4) +{ +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + sc1200_get_video_downscale_coefficients(coef1, coef2, coef3, coef4); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + redcloud_get_video_downscale_coefficients(coef1, coef2, coef3, coef4); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_downscale_enable + *--------------------------------------------------------------------------- + */ +void gfx_get_video_downscale_enable(int *enable) +{ +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + sc1200_get_video_downscale_enable(enable); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + redcloud_get_video_downscale_enable(enable); +#endif +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_dst_size + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_video_dst_size(void) +{ + unsigned long size = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + size = cs5530_get_video_dst_size(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + size = sc1200_get_video_dst_size(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + size = redcloud_get_video_dst_size(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + size = castle_get_video_dst_size(); +#endif + return(size); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_position + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_video_position(void) +{ + unsigned long position = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + position = cs5530_get_video_position(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + position = sc1200_get_video_position(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + position = redcloud_get_video_position(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + position = castle_get_video_position(); +#endif + return(position); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_video_color_key(void) +{ + unsigned long key = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + key = cs5530_get_video_color_key(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + key = sc1200_get_video_color_key(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + key = redcloud_get_video_color_key(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + key = castle_get_video_color_key(); +#endif + return(key); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key_mask + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_video_color_key_mask(void) +{ + unsigned long mask = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + mask = cs5530_get_video_color_key_mask(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + mask = sc1200_get_video_color_key_mask(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + mask = redcloud_get_video_color_key_mask(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + mask = castle_get_video_color_key_mask(); +#endif + return(mask); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key_src + *--------------------------------------------------------------------------- + */ +int gfx_get_video_color_key_src(void) +{ + int src = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + src = cs5530_get_video_color_key_src(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + src = sc1200_get_video_color_key_src(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + src = redcloud_get_video_color_key_src(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + src = castle_get_video_color_key_src(); +#endif + return(src); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_filter + *--------------------------------------------------------------------------- + */ +int gfx_get_video_filter(void) +{ + int filter = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + filter = cs5530_get_video_filter(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + filter = sc1200_get_video_filter(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + filter = redcloud_get_video_filter(); +#endif + return(filter); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_request + *--------------------------------------------------------------------------- + */ +int gfx_get_video_request(short *x, short *y) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_get_video_request(x, y); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + status = redcloud_get_video_request(x, y); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + status = castle_get_video_request(x, y); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_source + *--------------------------------------------------------------------------- + */ +int gfx_get_video_source(VideoSourceType *source) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_get_video_source(source); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vbi_source + *--------------------------------------------------------------------------- + */ +int gfx_get_vbi_source(VbiSourceType *source) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_get_vbi_source(source); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vbi_lines + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_vbi_lines(int odd) +{ + unsigned long lines = (unsigned long)GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + lines = sc1200_get_vbi_lines(odd); +#endif + return(lines); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vbi_total + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_vbi_total(int odd) +{ + unsigned long total = (unsigned long)GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + total = sc1200_get_vbi_total(odd); +#endif + return(total); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_interlaced + *--------------------------------------------------------------------------- + */ +int gfx_get_video_interlaced(void) +{ + int interlaced = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + interlaced = sc1200_get_video_interlaced(); +#endif + return(interlaced); +} + +/*--------------------------------------------------------------------------- + * gfx_get_color_space_YUV + *--------------------------------------------------------------------------- + */ +int gfx_get_color_space_YUV(void) +{ + int color_space = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + color_space = sc1200_get_color_space_YUV(); +#endif + return(color_space); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vertical_scaler_offset + *--------------------------------------------------------------------------- + */ +int gfx_get_vertical_scaler_offset(char *offset) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + status = sc1200_get_vertical_scaler_offset(offset); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_get_genlock_delay + *--------------------------------------------------------------------------- + */ +unsigned long gfx_get_genlock_delay(void) +{ + unsigned long delay = (unsigned long)GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + delay = sc1200_get_genlock_delay(); +#endif + return(delay); +} + +/*--------------------------------------------------------------------------- + * gfx_get_genlock_enable + *--------------------------------------------------------------------------- + */ +int gfx_get_genlock_enable(void) +{ + int enable = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + enable = sc1200_get_genlock_enable(); +#endif + return(enable); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_cursor + *--------------------------------------------------------------------------- + */ +int gfx_get_video_cursor(unsigned long *key, unsigned long *mask, unsigned short *select_color2, + unsigned long *color1, unsigned short *color2) +{ + int enable = GFX_STATUS_UNSUPPORTED; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + enable = sc1200_get_video_cursor(key, mask, select_color2, color1, color2); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + enable = redcloud_get_video_cursor(key, mask, select_color2, color1, color2); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + enable = castle_get_video_cursor(key, mask, select_color2, color1, color2); +#endif + return(enable); +} + +/*--------------------------------------------------------------------------- + * gfx_read_crc + *--------------------------------------------------------------------------- + */ +unsigned long gfx_read_crc(void) +{ + unsigned long crc = 0; +#if GFX_VIDEO_CS5530 + if (gfx_video_type == GFX_VIDEO_TYPE_CS5530) + crc = cs5530_read_crc(); +#endif +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + crc = sc1200_read_crc(); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + crc = redcloud_read_crc(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + crc = castle_read_crc(); +#endif + return(crc); +} + +/*--------------------------------------------------------------------------- + * gfx_read_crc32 + *--------------------------------------------------------------------------- + */ +unsigned long gfx_read_crc32(void) +{ + unsigned long crc = 0; +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + crc = redcloud_read_crc32(); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + crc = castle_read_crc32(); +#endif + return(crc); +} + +/*--------------------------------------------------------------------------- + * gfx_read_window_crc + *--------------------------------------------------------------------------- + */ +unsigned long gfx_read_window_crc(int source, unsigned short x, unsigned short y, + unsigned short width, unsigned short height, int crc32) +{ + unsigned long crc = 0; +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + crc = redcloud_read_window_crc(source, x, y, width, height, crc32); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + crc = castle_read_window_crc(source, x, y, width, height, crc32); +#endif + return(crc); +} + +/*----------------------------------------------------------------------------- + * gfx_get_macrovision_enable + *----------------------------------------------------------------------------- + */ +int gfx_get_macrovision_enable(void) +{ + int enable = 0; +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + enable = sc1200_get_video_enable(); +#endif + return(enable); +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_enable + *--------------------------------------------------------------------------- + */ +void gfx_get_alpha_enable(int *enable) +{ +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + sc1200_get_alpha_enable(enable); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + redcloud_get_alpha_enable(enable); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + castle_get_alpha_enable(enable); +#endif + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_size + *--------------------------------------------------------------------------- + */ +void gfx_get_alpha_size(unsigned short *x, unsigned short *y, + unsigned short *width, unsigned short *height) +{ +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + sc1200_get_alpha_size(x, y, width, height); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + redcloud_get_alpha_size(x, y, width, height); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + castle_get_alpha_size(x, y, width, height); +#endif + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_value + *--------------------------------------------------------------------------- + */ +void gfx_get_alpha_value(unsigned char *alpha, char *delta) +{ +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + sc1200_get_alpha_value(alpha, delta); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + redcloud_get_alpha_value(alpha, delta); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + castle_get_alpha_value(alpha, delta); +#endif + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_priority + *--------------------------------------------------------------------------- + */ +void gfx_get_alpha_priority(int *priority) +{ +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + sc1200_get_alpha_priority(priority); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + redcloud_get_alpha_priority(priority); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + castle_get_alpha_priority(priority); +#endif + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_color + *--------------------------------------------------------------------------- + */ +void gfx_get_alpha_color(unsigned long *color) +{ +#if GFX_VIDEO_SC1200 + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + sc1200_get_alpha_color(color); +#endif +#if GFX_VIDEO_REDCLOUD + if (gfx_video_type == GFX_VIDEO_TYPE_REDCLOUD) + redcloud_get_alpha_color(color); +#endif +#if GFX_VIDEO_CASTLE + if (gfx_video_type == GFX_VIDEO_TYPE_CASTLE) + castle_get_alpha_color(color); +#endif + return; +} + +#endif /* GFX_READ_ROUTINES */ + +#endif /* GFX_VIDEO_DYNAMIC */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_vip.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_vip.c 2005-12-14 11:31:27.000000000 -0700 @@ -0,0 +1,480 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * $Workfile: gfx_vip.c $ + * + * This file contains routines to control the video input port (VIP). + * + * gfx_set_vip_enable + * gfx_set_vip_capture_run_mode + * gfx_set_vip_base + * gfx_set_vip_pitch + * gfx_set_vip_mode + * gfx_set_vbi_enable + * gfx_set_vbi_mode + * gfx_set_vbi_base + * gfx_set_vbi_pitch + * gfx_set_vbi_direct + * gfx_set_vbi_interrupt + * gfx_set_vip_bus_request_threshold_high + * gfx_set_vip_last_line + * gfx_test_vip_odd_field + * gfx_test_vip_bases_updated + * gfx_test_vip_fifo_overflow + * gfx_get_vip_line + * gfx_get_vip_base + * gfx_get_vbi_pitch + * + * And the following routines if GFX_READ_ROUTINES is set: + * + * gfx_get_vip_enable + * gfx_get_vip_pitch + * gfx_get_vip_mode + * gfx_get_vbi_enable + * gfx_get_vbi_mode + * gfx_get_vbi_base + * gfx_get_vbi_direct + * gfx_get_vbi_interrupt + * gfx_get_vip_bus_request_threshold_high + * */ + + +/* INCLUDE SUPPORT FOR SC1200, IF SPECIFIED. */ + +#if GFX_VIP_SC1200 +#include "vip_1200.c" +#endif + +/* WRAPPERS IF DYNAMIC SELECTION */ +/* Extra layer to call either CS5530 or SC1200 routines. */ + +#if GFX_VIP_DYNAMIC + +/*----------------------------------------------------------------------------- + * gfx_set_vip_enable + *----------------------------------------------------------------------------- + */ +int gfx_set_vip_enable(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vip_enable(enable); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vip_capture_run_mode + *----------------------------------------------------------------------------- + */ +int gfx_set_vip_capture_run_mode(int mode) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vip_capture_run_mode(mode); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vip_base + *----------------------------------------------------------------------------- + */ +int gfx_set_vip_base(unsigned long even, unsigned long odd) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vip_base(even, odd); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vip_pitch + *----------------------------------------------------------------------------- + */ +int gfx_set_vip_pitch(unsigned long pitch) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vip_pitch(pitch); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vip_mode + *----------------------------------------------------------------------------- + */ +int gfx_set_vip_mode(int mode) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vip_mode(mode); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vbi_enable + *----------------------------------------------------------------------------- + */ +int gfx_set_vbi_enable(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vbi_enable(enable); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vbi_mode + *----------------------------------------------------------------------------- + */ +int gfx_set_vbi_mode(int mode) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vbi_mode(mode); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vbi_base + *----------------------------------------------------------------------------- + */ +int gfx_set_vbi_base(unsigned long even, unsigned long odd) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vbi_base(even, odd); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vbi_pitch + *----------------------------------------------------------------------------- + */ +int gfx_set_vbi_pitch(unsigned long pitch) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vbi_pitch(pitch); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vbi_direct + *----------------------------------------------------------------------------- + */ +int gfx_set_vbi_direct(unsigned long even_lines, unsigned long odd_lines) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vbi_direct(even_lines, odd_lines); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vbi_interrupt + *----------------------------------------------------------------------------- + */ +int gfx_set_vbi_interrupt(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vbi_interrupt(enable); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vip_bus_request_threshold_high + *----------------------------------------------------------------------------- + */ +int gfx_set_vip_bus_request_threshold_high(int enable) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vip_bus_request_threshold_high(enable); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_vip_last_line + *----------------------------------------------------------------------------- + */ +int gfx_set_vip_last_line(int last_line) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_set_vip_last_line(last_line); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_test_vip_odd_field + *----------------------------------------------------------------------------- + */ +int gfx_test_vip_odd_field(void) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_test_vip_odd_field(); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_test_vip_bases_updated + *----------------------------------------------------------------------------- + */ +int gfx_test_vip_bases_updated(void) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_test_vip_bases_updated(); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_test_vip_fifo_overflow + *----------------------------------------------------------------------------- + */ +int gfx_test_vip_fifo_overflow(void) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_test_vip_fifo_overflow(); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vip_line + *----------------------------------------------------------------------------- + */ +int gfx_get_vip_line(void) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + status = sc1200_get_vip_line(); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vip_base + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_vip_base(int odd) +{ + unsigned long base = 0; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + base = sc1200_get_vip_base(odd); +#endif + return(base); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vbi_pitch + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_vbi_pitch(void) +{ + unsigned long pitch = 0; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + pitch = sc1200_get_vbi_pitch(); +#endif + return(pitch); +} + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +#if GFX_READ_ROUTINES + +/*----------------------------------------------------------------------------- + * gfx_get_vip_enable + *----------------------------------------------------------------------------- + */ +int gfx_get_vip_enable(void) +{ + int enable = 0; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + enable = sc1200_get_vip_enable(); +#endif + return(enable); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vip_pitch + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_vip_pitch(void) +{ + unsigned long pitch = 0; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + pitch = sc1200_get_vip_pitch(); +#endif + return(pitch); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vip_mode + *----------------------------------------------------------------------------- + */ +int gfx_get_vip_mode(void) +{ + int mode = 0; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + mode = sc1200_get_vip_mode(); +#endif + return(mode); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vbi_enable + *----------------------------------------------------------------------------- + */ +int gfx_get_vbi_enable(void) +{ + int enable = 0; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + enable = sc1200_get_vbi_enable(); +#endif + return(enable); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vbi_mode + *----------------------------------------------------------------------------- + */ +int gfx_get_vbi_mode(void) +{ + int mode = 0; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + mode = sc1200_get_vbi_mode(); +#endif + return(mode); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vbi_base + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_vbi_base(int odd) +{ + unsigned long base = 0; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + base = sc1200_get_vbi_base(odd); +#endif + return(base); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vbi_direct + *----------------------------------------------------------------------------- + */ +unsigned long gfx_get_vbi_direct(int odd) +{ + unsigned long vbi_direct_lines = 0; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + vbi_direct_lines = sc1200_get_vbi_direct(odd); +#endif + return(vbi_direct_lines); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vbi_interrupt + *----------------------------------------------------------------------------- + */ +int gfx_get_vbi_interrupt(void) +{ + int enable = 0; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + enable = sc1200_get_vbi_interrupt(); +#endif + return(enable); +} + +/*----------------------------------------------------------------------------- + * gfx_get_vip_bus_request_threshold_high + *----------------------------------------------------------------------------- + */ +int gfx_get_vip_bus_request_threshold_high(void) +{ + int enable = 0; +#if GFX_VIP_SC1200 + if (gfx_vip_type == GFX_VIP_TYPE_SC1200) + enable = sc1200_get_vip_bus_request_threshold_high(); +#endif + return(enable); +} + +#endif /* GFX_READ_ROUTINES */ + +#endif /* GFX_VIP_DYNAMIC */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_type.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_type.h 2005-12-14 11:34:39.000000000 -0700 @@ -0,0 +1,325 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This header file defines the pneumonics used when calling Durango routines. + * This file is automatically included by gfx_rtns.h + * */ + + +#ifndef _gfx_type_h +#define _gfx_type_h + +/* MSR DEFINITIONS */ + +typedef enum DevStatus { FOUND, NOT_KNOWN, REQ_NOT_FOUND, REQ_NOT_INSTALLED } DEV_STATUS; + +typedef struct msr { + DEV_STATUS Present; /* Node enumeration status */ + unsigned char Id; /* Device ID (from MSR specs) */ + unsigned long Address; /* Address - 32-bit MBus address at which 'Id' is found */ +} MSR; + +typedef struct mValue { + unsigned long high; + unsigned long low; +} Q_WORD; + +typedef struct mbusNode { + unsigned long address; + unsigned int deviceId; + unsigned int claimed; +} MBUS_NODE; + +/* MSR ARRAY INDEXES */ +/* These are indexes into the array of MBus devices. These */ +/* should not be confused with the class codes at MSR register */ +/* 0x2000. */ + +#define RC_ID_MBIU0 0x00 +#define RC_ID_MBIU1 0x01 +#define RC_ID_MCP 0x02 +#define RC_ID_MPCI 0x03 +#define RC_ID_MC 0x04 +#define RC_ID_GP 0x05 +#define RC_ID_VG 0x06 +#define RC_ID_DF 0x07 +#define RC_ID_FG 0x08 +#define RC_ID_VA 0x09 +#define CP_ID_MBIU 0x0A +#define CP_ID_MPCI 0x0B +#define CP_ID_USB2 0x0C +#define CP_ID_ATAC 0x0D +#define CP_ID_MDD 0x0E +#define CP_ID_ACC 0x0F +#define CP_ID_USB1 0x10 +#define CP_ID_MCP 0x11 + +/* MBUS DEVICE CLASS CODES */ +/* These are the device ids for the known Redcloud MBus devices. */ + +#define RC_CC_MBIU 0x01 +#define RC_CC_MCP 0x02 +#define RC_CC_MPCI 0x05 +#define RC_CC_MC 0x20 +#define RC_CC_GP 0x3D +#define RC_CC_VG 0x3E +#define RC_CC_DF 0x3F +#define RC_CC_FG 0xF0 +#define RC_CC_VA 0x86 +#define CP_CC_MBIU 0x01 +#define CP_CC_MPCI 0x05 +#define CP_CC_USB2 0x42 +#define CP_CC_ATAC 0x47 +#define CP_CC_MDD 0xDF +#define CP_CC_ACC 0x33 +#define CP_CC_USB1 0x42 +#define CP_CC_MCP 0x02 + +/* VAIL AND MBIUS ARE AT KNOWN ADDRESSES */ +/* We can initialize the addresses of these devices in advance, */ +/* as their location should never change. */ + +#define RC_MB0_MBIU0 0x10000000 +#define RC_MB0_MBIU1 0x40000000 +#define CP_MB0_MBIU0 0x51010000 +#define RC_MB0_CPU 0x00000000 +#define FAKE_ADDRESS 0xFFFFFFFF + +/* MSR PORT DESCRIPTORS */ + +#define NOT_POPULATED 0 +#define NOT_INSTALLED 0xFFFE +#define REFLECTIVE 0xFFFF + +/* CRC DATA SOURCES */ + +#define CRC_SOURCE_GFX_DATA 0x00 +#define CRC_SOURCE_CRT_RGB 0x01 +#define CRC_SOURCE_FP_DATA 0x02 + + +/* TV DEFINITIONS */ + +typedef enum TVStandardType { + TV_STANDARD_NTSC = 1, + TV_STANDARD_PAL +} TVStandardType; + +typedef enum GfxOnTVType { + GFX_ON_TV_SQUARE_PIXELS = 1, + GFX_ON_TV_NO_SCALING +} GfxOnTVType; + +#define CRT_DISABLE 0x00 +#define CRT_ENABLE 0x01 +#define CRT_STANDBY 0x02 +#define CRT_SUSPEND 0x03 + +#define TV_OUTPUT_COMPOSITE 0x01 +#define TV_OUTPUT_S_VIDEO 0x02 +#define TV_OUTPUT_YUV 0x03 +#define TV_OUTPUT_SCART 0x04 + +#define TV_FLICKER_FILTER_NONE 0x01 +#define TV_FLICKER_FILTER_NORMAL 0x02 +#define TV_FLICKER_FILTER_INTERLACED 0x03 + +#define TV_YC_DELAY_NONE 0x01 +#define TV_Y_DELAY_ONE_PIXEL 0x02 +#define TV_C_DELAY_ONE_PIXEL 0x03 +#define TV_C_DELAY_TWO_PIXELS 0x04 + +#define TV_SUB_CARRIER_RESET_NEVER 0x01 +#define TV_SUB_CARRIER_RESET_EVERY_TWO_LINES 0x02 +#define TV_SUB_CARRIER_RESET_EVERY_TWO_FRAMES 0x03 +#define TV_SUB_CARRIER_RESET_EVERY_FOUR_FRAMES 0x04 + +#define TVENC_RESET_EVERY_ODD_FIELD 0x01 +#define TVENC_RESET_EVERY_EVEN_FIELD 0x02 +#define TVENC_RESET_NEXT_ODD_FIELD 0x03 +#define TVENC_RESET_NEXT_EVEN_FIELD 0x04 +#define TVENC_RESET_EVERY_FIELD 0x05 +#define TVENC_RESET_EVERY_X_ODD_FIELDS 0x06 +#define TVENC_RESET_EVERY_X_EVEN_FIELDS 0x07 + +/* VBI FORMATS */ + +#define VBI_FORMAT_VIDEO 0x1 +#define VBI_FORMAT_RAW 0x2 +#define VBI_FORMAT_CC 0x4 +#define VBI_FORMAT_NABTS 0x8 + +/* VIDEO DEFINITIONS */ + +#define VIDEO_FORMAT_UYVY 0x0 +#define VIDEO_FORMAT_Y2YU 0x1 +#define VIDEO_FORMAT_YUYV 0x2 +#define VIDEO_FORMAT_YVYU 0x3 +#define VIDEO_FORMAT_Y0Y1Y2Y3 0x4 +#define VIDEO_FORMAT_Y3Y2Y1Y0 0x5 +#define VIDEO_FORMAT_Y1Y0Y3Y2 0x6 +#define VIDEO_FORMAT_Y1Y2Y3Y0 0x7 +#define VIDEO_FORMAT_RGB 0x8 +#define VIDEO_FORMAT_P2M_P2L_P1M_P1L 0x9 +#define VIDEO_FORMAT_P1M_P1L_P2M_P2L 0xA +#define VIDEO_FORMAT_P1M_P2L_P2M_P1L 0xB + +#define VIDEO_DOWNSCALE_KEEP_1_OF 0x1 +#define VIDEO_DOWNSCALE_DROP_1_OF 0x2 + +typedef enum VideoSourceType { /* The source from which the video processor shows full screen video */ + VIDEO_SOURCE_MEMORY = 1, + VIDEO_SOURCE_DVIP +} VideoSourceType; + +typedef enum VbiSourceType { /* The source from which the video processor takes VBI */ + VBI_SOURCE_MEMORY = 1, + VBI_SOURCE_DVIP +} VbiSourceType; + +/* GENLOCK DEFINITIONS */ + +#define GENLOCK_SINGLE 0x001 +#define GENLOCK_FIELD_SYNC 0x001 +#define GENLOCK_CONTINUOUS 0x002 +#define GENLOCK_SYNCED_EDGE_FALLING 0x004 +#define GENLOCK_SYNCING_EDGE_FALLING 0x008 +#define GENLOCK_TIMEOUT 0x010 +#define GENLOCK_TVENC_RESET_EVEN_FIELD 0x020 +#define GENLOCK_TVENC_RESET_BEFORE_DELAY 0x040 +#define GENLOCK_TVENC_RESET 0x080 +#define GENLOCK_SYNC_TO_TVENC 0x100 + +/* VIP DEFINITIONS */ + +#define VIP_MODE_C 0x1 + +#define VIP_CAPTURE_STOP_LINE 0x1 +#define VIP_CAPTURE_STOP_FIELD 0x2 +#define VIP_CAPTURE_START_FIELD 0x4 + +#define VBI_ANCILLARY 0x1 +#define VBI_TASK_A 0x2 +#define VBI_TASK_B 0x4 + +/* VGA STRUCTURE */ + +#define GFX_STD_CRTC_REGS 25 +#define GFX_EXT_CRTC_REGS 16 + +#define GFX_VGA_FLAG_MISC_OUTPUT 0x00000001 +#define GFX_VGA_FLAG_STD_CRTC 0x00000002 +#define GFX_VGA_FLAG_EXT_CRTC 0x00000004 + +/* FS450 TV Standard flags */ + +#define GFX_TV_STANDARD_NTSC_M 0x0001 +#define GFX_TV_STANDARD_NTSC_M_J 0x0002 +#define GFX_TV_STANDARD_PAL_B 0x0004 +#define GFX_TV_STANDARD_PAL_D 0x0008 +#define GFX_TV_STANDARD_PAL_H 0x0010 +#define GFX_TV_STANDARD_PAL_I 0x0020 +#define GFX_TV_STANDARD_PAL_M 0x0040 +#define GFX_TV_STANDARD_PAL_N 0x0080 +#define GFX_TV_STANDARD_PAL_G 0x0100 + +/* FS450 VGA Mode flags */ + +#define GFX_VGA_MODE_UNKNOWN 0 +#define GFX_VGA_MODE_640X480 0x0001 +#define GFX_VGA_MODE_720X487 0x0002 +#define GFX_VGA_MODE_720X576 0x0004 +#define GFX_VGA_MODE_800X600 0x0008 +#define GFX_VGA_MODE_1024X768 0x0010 + +/* FS450 TVout mode flags */ + +#define GFX_TVOUT_MODE_CVBS 0x0001 +#define GFX_TVOUT_MODE_YC 0x0002 +#define GFX_TVOUT_MODE_RGB 0x0004 +#define GFX_TVOUT_MODE_CVBS_YC (GFX_TVOUT_MODE_CVBS | GFX_TVOUT_MODE_YC) + +/* FS450 Luma and Chroma Filters */ + +#define GFX_LUMA_FILTER 0x0001 +#define GFX_CHROMA_FILTER 0x0002 + +/* APS Trigger Bits */ + +#define GFX_APS_TRIGGER_OFF 0 +#define GFX_APS_TRIGGER_AGC_ONLY 1 +#define GFX_APS_TRIGGER_AGC_2_LINE 2 +#define GFX_APS_TRIGGER_AGC_4_LINE 3 + +typedef struct { + int xsize; + int ysize; + int hz; + int clock; + unsigned char miscOutput; + unsigned char stdCRTCregs[GFX_STD_CRTC_REGS]; + unsigned char extCRTCregs[GFX_EXT_CRTC_REGS]; +} gfx_vga_struct; + +/* POSSIBLE STATUS VALUES */ + +#define GFX_STATUS_UNSUPPORTED (-3) +#define GFX_STATUS_BAD_PARAMETER (-2) +#define GFX_STATUS_ERROR (-1) +#define GFX_STATUS_OK 0 + +/* CPU AND VIDEO TYPES */ + +#define GFX_CPU_GXLV 1 +#define GFX_CPU_SC1200 2 +#define GFX_CPU_REDCLOUD 3 +#define GFX_CPU_CASTLE 4 +#define GFX_CPU_PYRAMID 0x20801 + + +#define GFX_VID_CS5530 1 +#define GFX_VID_SC1200 2 +#define GFX_VID_REDCLOUD 3 +#define GFX_VID_CASTLE 4 + +/* CHIP NAME AND REVISION */ + +typedef enum ChipType { + CHIP_NOT_DETECTED, + SC1200_REV_A, + SC1200_REV_B1_B2, + SC1200_REV_B3, + SC1200_REV_C1, + SC1200_REV_D1, + SC1200_REV_D1_1, + SC1200_REV_D2_MVD, /* Macrovision disabled */ + SC1200_REV_D2_MVE, /* Macrovision enabled */ + SC1200_FUTURE_REV +} ChipType; + +#endif /* !_gfx_type_h */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/disp_gu1.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/disp_gu1.c 2005-12-14 11:37:32.000000000 -0700 @@ -0,0 +1,2394 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +void gu1_enable_compression(void); /* private routine definition */ +void gu1_disable_compression(void); /* private routine definition */ +void gfx_reset_video(void); /* private routine definition */ +int gfx_set_display_control(int sync_polarities); /* private routine definition */ +int gu1_set_specified_mode(DISPLAYMODE *pMode, int bpp); + +/* VIDEO BUFFER SIZE */ + +unsigned long vid_buf_size = 0; +int vid_enabled = 0; + +/*----------------------------------------------------------------------------- + * GU1_DELAY_APPROXIMATE (PRIVATE ROUTINE - NOT PART OF DURANGO API) + * + * Delay the requested number of milliseconds by reading a register. This function + * generally takes longer than the requested time. + *-----------------------------------------------------------------------------*/ + +#define READS_PER_MILLISECOND 60000L + +void gu1_delay_approximate (unsigned long milliseconds) +{ + /* ASSUME 300 MHz, 5 CLOCKS PER READ */ + + unsigned long loop; + loop = milliseconds * READS_PER_MILLISECOND; + while (loop-- > 0) + { + READ_REG32(DC_UNLOCK); + } +} + +/*----------------------------------------------------------------------------- + * GU1_DELAY_PRECISE (PRIVATE ROUTINE - NOT PART OF DURANGO API) + * + * Delay the number of milliseconds on a more precise level, varying only by + * 1/10 of a ms. This function should only be called if an SC1200 is present. + *-----------------------------------------------------------------------------*/ +void gu1_delay_precise (unsigned long milliseconds) +{ +#if GFX_VIDEO_SC1200 + +#define LOOP 1000 + unsigned long i, timer_start, timer_end, total_ticks, previous_ticks, temp_ticks; + + /* Get current time */ + timer_start = IND(SC1200_CB_BASE_ADDR + SC1200_CB_TMVALUE); + + /* Calculate expected end time */ + if (INB(SC1200_CB_BASE_ADDR + SC1200_CB_TMCNFG) & SC1200_TMCLKSEL_27MHZ) + total_ticks = 27000 * milliseconds; /* timer resolution is 27 MHz */ + else + total_ticks = 1000 * milliseconds; /* timer resolution is 1 MHz */ + + if (total_ticks > ((unsigned long)0xffffffff - timer_start)) /* wrap-around */ + timer_end = total_ticks - ((unsigned long)0xffffffff - timer_start); + else + timer_end = timer_start + total_ticks; + + /* in case of wrap around */ + if (timer_end < timer_start) + { + previous_ticks = timer_start; + while (1) + { + temp_ticks = IND(SC1200_CB_BASE_ADDR + SC1200_CB_TMVALUE); + if (temp_ticks < previous_ticks) + break; + else + previous_ticks = temp_ticks; + for (i = 0; i < LOOP; i++) + READ_REG32(DC_UNLOCK); + } + } + /* now the non-wrap around part */ + while (1) + { + for (i = 0; i < LOOP; i++) + READ_REG32(DC_UNLOCK); + if(IND(SC1200_CB_BASE_ADDR + SC1200_CB_TMVALUE) > timer_end) + break; + } + +#endif /* GFX_VIDEO_SC1200 */ +} + +/*----------------------------------------------------------------------------- + * WARNING!!!! INACCURATE DELAY MECHANISM + * + * In an effort to keep the code self contained and operating system + * independent, the delay loop just performs reads of a display controller + * register. This time will vary for faster processors. The delay can always + * be longer than intended, only effecting the time of the mode switch + * (obviously want it to still be under a second). Problems with the hardware + * only arise if the delay is not long enough. + * + * For the SC1200, the high resolution timer can be used as an accurate mechanism + * for keeping time. However, in order to avoid a busy loop of IO reads, the + * timer is polled in-between busy loops, and therefore the actual delay might + * be longer than the requested delay by the time of one busy loop + * (which on a 200 MHz system took 95 us) + * + * There are thus two delay functions which are called from the main API routine. + * One is meant to be more precise and should only called if an SC1200 is present. + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_delay_milliseconds(unsigned long milliseconds) +#else +void gfx_delay_milliseconds(unsigned long milliseconds) +#endif +{ +#if GFX_VIDEO_SC1200 + +#if GFX_VIDEO_DYNAMIC + if (gfx_video_type == GFX_VIDEO_TYPE_SC1200) + { +#endif + gu1_delay_precise(milliseconds); + return; +#if GFX_VIDEO_DYNAMIC + } +#endif + +#endif /* GFX_VIDEO_SC1200 */ + + gu1_delay_approximate(milliseconds); +} + +#if GFX_DISPLAY_DYNAMIC +void gu1_delay_microseconds(unsigned long microseconds) +#else +void gfx_delay_microseconds(unsigned long microseconds) +#endif +{ + /* ASSUME 300 MHz, 2 CLOCKS PER INCREMENT */ + + unsigned long loop_count = microseconds * 150; + + while (loop_count-- > 0) + { + ; + } +} +/*----------------------------------------------------------------------------- + * GFX_VIDEO_SHUTDOWN + * + * This routine disables the display controller output. + *----------------------------------------------------------------------------- + */ +void gu1_video_shutdown(void) +{ + unsigned long unlock; + unsigned long gcfg, tcfg; + + /* DISABLE COMPRESSION */ + + gu1_disable_compression(); + + /* ALSO DISABLE VIDEO */ + /* Use private "reset video" routine to do all that is needed. */ + /* SC1200, for example, also disables the alpha blending regions. */ + + gfx_reset_video(); + + /* UNLOCK THE DISPLAY CONTROLLER REGISTERS */ + + unlock = READ_REG32(DC_UNLOCK); + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + + /* READ THE CURRENT GX VALUES */ + + gcfg = READ_REG32(DC_GENERAL_CFG); + tcfg = READ_REG32(DC_TIMING_CFG); + + /* BLANK THE GX DISPLAY AND DISABLE THE TIMING GENERATOR */ + + tcfg &= ~((unsigned long)DC_TCFG_BLKE | (unsigned long)DC_TCFG_TGEN); + WRITE_REG32(DC_TIMING_CFG, tcfg); + + /* DELAY: WAIT FOR PENDING MEMORY REQUESTS */ + /* This delay is used to make sure that all pending requests to the */ + /* memory controller have completed before disabling the FIFO load. */ + + gfx_delay_milliseconds(1); + + /* DISABLE DISPLAY FIFO LOAD AND DISABLE COMPRESSION */ + + gcfg &= ~(unsigned long)(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); + WRITE_REG32(DC_GENERAL_CFG, gcfg); + WRITE_REG32(DC_UNLOCK, unlock); + return; +} + +/*----------------------------------------------------------------------------- + * GFX_SET_DISPLAY_BPP + * + * This routine programs the bpp in the display controller. + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_set_display_bpp(unsigned short bpp) +#else +int gfx_set_display_bpp(unsigned short bpp) +#endif +{ + unsigned long ocfg, lock; + + lock = READ_REG32 (DC_UNLOCK); + ocfg = READ_REG32 (DC_OUTPUT_CFG) & ~(DC_OCFG_8BPP | DC_OCFG_555); + + /* SET DC PIXEL FORMAT */ + + if (bpp == 8) ocfg |= DC_OCFG_8BPP; + else if (bpp == 15) ocfg |= DC_OCFG_555; + else if (bpp != 16) return GFX_STATUS_BAD_PARAMETER; + + WRITE_REG32 (DC_UNLOCK, DC_UNLOCK_VALUE); + WRITE_REG32 (DC_OUTPUT_CFG, ocfg); + WRITE_REG32 (DC_UNLOCK, lock); + + /* SET BPP IN GRAPHICS PIPELINE */ + + gfx_set_bpp (bpp); + + return 0; +} + +/*----------------------------------------------------------------------------- + * GFX_SET_SPECIFIED_MODE + * This routine uses the parameters in the specified display mode structure + * to program the display controller hardware. + *----------------------------------------------------------------------------- + */ +int gu1_set_specified_mode(DISPLAYMODE *pMode, int bpp) +{ + unsigned long unlock, value; + unsigned long gcfg, tcfg, ocfg; + unsigned long size, pitch; + unsigned long hactive, vactive; + gbpp = bpp; + + /* CHECK WHETHER TIMING CHANGE IS ALLOWED */ + /* Flag used for locking also overrides timing change restriction */ + + if (gfx_timing_lock && !(pMode->flags & GFX_MODE_LOCK_TIMING)) + return GFX_STATUS_ERROR; + + /* SET GLOBAL FLAG */ + + if (pMode->flags & GFX_MODE_LOCK_TIMING) + gfx_timing_lock = 1; + + /* DISABLE COMPRESSION */ + + gu1_disable_compression(); + + /* ALSO DISABLE VIDEO */ + /* Use private "reset video" routine to do all that is needed. */ + /* SC1200, for example, also disables the alpha blending regions. */ + + gfx_reset_video(); + + /* UNLOCK THE DISPLAY CONTROLLER REGISTERS */ + + unlock = READ_REG32(DC_UNLOCK); + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + + /* READ THE CURRENT GX VALUES */ + + gcfg = READ_REG32(DC_GENERAL_CFG); + tcfg = READ_REG32(DC_TIMING_CFG); + + /* BLANK THE GX DISPLAY AND DISABLE THE TIMING GENERATOR */ + + tcfg &= ~((unsigned long)DC_TCFG_BLKE | (unsigned long)DC_TCFG_TGEN); + WRITE_REG32(DC_TIMING_CFG, tcfg); + + /* DELAY: WAIT FOR PENDING MEMORY REQUESTS + * This delay is used to make sure that all pending requests to the + * memory controller have completed before disabling the FIFO load. + */ + + gfx_delay_milliseconds(1); + + /* DISABLE DISPLAY FIFO LOAD AND DISABLE COMPRESSION */ + + gcfg &= ~(unsigned long)(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE); + WRITE_REG32(DC_GENERAL_CFG, gcfg); + + /* CLEAR THE "DCLK_MUL" FIELD */ + + gcfg &= ~(unsigned long)(DC_GCFG_DDCK | DC_GCFG_DPCK | DC_GCFG_DFCK); + gcfg &= ~(unsigned long)DC_GCFG_DCLK_MASK; + WRITE_REG32(DC_GENERAL_CFG, gcfg); + + /* SET THE DOT CLOCK FREQUENCY */ + /* Mask off the divide by two bit (bit 31) */ + + gfx_set_clock_frequency(pMode->frequency & 0x7FFFFFFF); + + /* DELAY: WAIT FOR THE PLL TO SETTLE */ + /* This allows the dot clock frequency that was just set to settle. */ + + gfx_delay_milliseconds(1); + + /* SET THE "DCLK_MUL" FIELD OF DC_GENERAL_CFG */ + /* The GX hardware divides the dot clock, so 2x really means that the */ + /* internal dot clock equals the external dot clock. */ + + if (pMode->frequency & 0x80000000) gcfg |= 0x0040; + else gcfg |= 0x0080; + WRITE_REG32(DC_GENERAL_CFG, gcfg); + + /* DELAY: WAIT FOR THE ADL TO LOCK */ + /* This allows the clock generatation within GX to settle. This is */ + /* needed since some of the register writes that follow require that */ + /* clock to be present. */ + + gfx_delay_milliseconds(1); + + /* SET THE GX DISPLAY CONTROLLER PARAMETERS */ + + WRITE_REG32(DC_FB_ST_OFFSET, 0); + WRITE_REG32(DC_CB_ST_OFFSET, 0); + WRITE_REG32(DC_CURS_ST_OFFSET, 0); + + /* SET LINE SIZE AND PITCH */ + /* Flat panels use the current flat panel line size to */ + /* calculate the pitch, but load the true line size */ + /* for the mode into the "Frame Buffer Line Size" field */ + /* of DC_BUF_SIZE. */ + + if (PanelEnable) + size = ModeWidth; + else + size = pMode->hactive; + + if (bpp > 8) size <<= 1; + + /* ONLY PYRAMID SUPPORTS 4K LINE SIZE */ + + if (size <= 1024) + { + pitch = 1024; + + /* SPECIAL CASE */ + /* Graphics acceleration in 16-bit pixel line double modes */ + /* requires a pitch of 2048. */ + + if ((pMode->flags & GFX_MODE_LINE_DOUBLE) && bpp > 8) + pitch <<= 1; + } + else + { + if (gfx_cpu_version == GFX_CPU_PYRAMID) + pitch = (size <= 2048) ? 2048 : 4096; + else + pitch = 2048; + } + WRITE_REG32(DC_LINE_DELTA, pitch >> 2); + + if (PanelEnable) + { + size = pMode->hactive; + if (bpp > 8) + size <<= 1; + } + + /* ADD 2 TO SIZE FOR POSSIBLE START ADDRESS ALIGNMENTS */ + + WRITE_REG32(DC_BUF_SIZE, (size >> 3) + 2); + + /* ALWAYS ENABLE "PANEL" DATA FROM MEDIAGX */ + /* That is really just the 18 BPP data bus to the companion chip */ + + ocfg = DC_OCFG_PCKE | DC_OCFG_PDEL | DC_OCFG_PDEH; + + /* SET PIXEL FORMAT */ + + if (bpp == 8) ocfg |= DC_OCFG_8BPP; + else if (bpp == 15) ocfg |= DC_OCFG_555; + + /* ENABLE TIMING GENERATOR, SYNCS, AND FP DATA */ + + tcfg = DC_TCFG_FPPE | DC_TCFG_HSYE | DC_TCFG_VSYE | DC_TCFG_BLKE | + DC_TCFG_TGEN; + + /* SET FIFO PRIORITY, DCLK MULTIPLIER, AND FIFO ENABLE */ + /* Default 6/5 for FIFO, 2x for DCLK multiplier. */ + + gcfg = (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE; + + /* INCREASE FIFO PRIORITY FOR LARGE MODES */ + + if (pMode->hactive==1280 && pMode->vactive==1024) + { + if ((bpp == 8) && (pMode->flags & GFX_MODE_85HZ)) + gcfg = (8l << DC_GCFG_DFHPEL_POS) | (7l << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE; + if ((bpp > 8) && (pMode->flags & GFX_MODE_75HZ)) + gcfg = (7l << DC_GCFG_DFHPEL_POS) | (6l << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE; + if ((bpp > 8) && (pMode->flags & GFX_MODE_85HZ)) + gcfg = (9l << DC_GCFG_DFHPEL_POS) | (8l << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE; + } + + /* SET DOT CLOCK MULTIPLIER */ + /* Bit 31 of frequency indicates divide frequency by two */ + + if (pMode->frequency & 0x80000000) gcfg |= (1l << DC_GCFG_DCLK_POS); + else gcfg |= (2l << DC_GCFG_DCLK_POS); + + /* DIVIDE VIDEO CLOCK */ + /* CPU core frequencies above 266 MHz will divide the video */ + /* clock by 4 to ensure that we are running below 150 MHz. */ + + if(gfx_cpu_frequency > 266) + gcfg |= DC_GCFG_VCLK_DIV; + + + /* ALWAYS ENABLE VIDEO IN THE DISPLAY CONTROLLER */ + /* Enabling video at an inopportune momemt can corrupt the DC fetch */ + /* engine and cause screen artifacts or system hang. */ + + gcfg |= (DC_GCFG_VIDE | DC_GCFG_VRDY); + + /* SET THE PIXEL AND LINE DOUBLE BITS IF NECESSARY */ + + hactive = pMode->hactive; + vactive = pMode->vactive; + gfx_line_double = 0; + gfx_pixel_double = 0; + + if (pMode->flags & GFX_MODE_LINE_DOUBLE) + { + gcfg |= DC_GCFG_LDBL; + hactive <<= 1; + + /* SET GLOBAL FLAG */ + + gfx_line_double = 1; + } + + if (pMode->flags & GFX_MODE_PIXEL_DOUBLE) + { + tcfg |= DC_TCFG_PXDB; + vactive <<= 1; + + /* SET GLOBAL FLAG */ + + gfx_pixel_double = 1; + } + + /* COMBINE AND SET TIMING VALUES */ + + value = (unsigned long) (hactive - 1) | + (((unsigned long) (pMode->htotal - 1)) << 16); + WRITE_REG32(DC_H_TIMING_1, value); + value = (unsigned long) (pMode->hblankstart - 1) | + (((unsigned long) (pMode->hblankend - 1)) << 16); + WRITE_REG32(DC_H_TIMING_2, value); + value = (unsigned long) (pMode->hsyncstart - 1) | + (((unsigned long) (pMode->hsyncend - 1)) << 16); + WRITE_REG32(DC_H_TIMING_3, value); + WRITE_REG32(DC_FP_H_TIMING, value); + value = (unsigned long) (vactive - 1) | + (((unsigned long) (pMode->vtotal - 1)) << 16); + WRITE_REG32(DC_V_TIMING_1, value); + value = (unsigned long) (pMode->vblankstart - 1) | + (((unsigned long) (pMode->vblankend - 1)) << 16); + WRITE_REG32(DC_V_TIMING_2, value); + value = (unsigned long) (pMode->vsyncstart - 1) | + (((unsigned long) (pMode->vsyncend - 1)) << 16); + WRITE_REG32(DC_V_TIMING_3, value); + value = (unsigned long) (pMode->vsyncstart - 2) | + (((unsigned long) (pMode->vsyncend - 2)) << 16); + WRITE_REG32(DC_FP_V_TIMING, value); + + WRITE_REG32(DC_OUTPUT_CFG, ocfg); + WRITE_REG32(DC_TIMING_CFG, tcfg); + gfx_delay_milliseconds(1); /* delay after TIMING_CFG */ + WRITE_REG32(DC_GENERAL_CFG, gcfg); + + /* ENABLE FLAT PANEL CENTERING */ + /* For 640x480 modes displayed with the 9211 within a 800x600 */ + /* flat panel display, turn on flat panel centering. */ + + if (PanelEnable) + { + if (ModeWidth < PanelWidth) + { + tcfg = READ_REG32(DC_TIMING_CFG); + tcfg = tcfg | DC_TCFG_FCEN; + WRITE_REG32(DC_TIMING_CFG, tcfg); + gfx_delay_milliseconds(1); /* delay after TIMING_CFG */ + } + } + + /* CONFIGURE DISPLAY OUTPUT FROM VIDEO PROCESSOR */ + + gfx_set_display_control (((pMode->flags & GFX_MODE_NEG_HSYNC) ? 1 : 0) | + ((pMode->flags & GFX_MODE_NEG_VSYNC) ? 2 : 0)); + + /* RESTORE VALUE OF DC_UNLOCK */ + + WRITE_REG32(DC_UNLOCK, unlock); + + /* ALSO WRITE GP_BLIT_STATUS FOR PITCH AND 8/18 BPP */ + /* Remember, only Pyramid supports 4K line pitch */ + + value = 0; + if (bpp > 8) value |= BC_16BPP; + if( (gfx_cpu_version == GFX_CPU_PYRAMID) && ( pitch > 2048 )) + value |= BC_FB_WIDTH_4096; + else if (pitch > 1024) + value |= BC_FB_WIDTH_2048; + WRITE_REG16(GP_BLIT_STATUS, (unsigned short) value); + + return GFX_STATUS_OK; + +} /* end gfx_set_specified_mode() */ + +/*---------------------------------------------------------------------------- + * GFX_IS_DISPLAY_MODE_SUPPORTED + * + * This routine sets the specified display mode. + * + * Returns the index of the mode if successful and mode returned, -1 if the mode + * could not be found. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_is_display_mode_supported(int xres, int yres, int bpp, int hz) +#else +int gfx_is_display_mode_supported(int xres, int yres, int bpp, int hz) +#endif +{ + unsigned int mode=0; + unsigned long hz_flag = 0, bpp_flag = 0; + + /* SET FLAGS TO MATCH REFRESH RATE */ + + if (hz == 56) hz_flag = GFX_MODE_56HZ; + else if (hz == 60) hz_flag = GFX_MODE_60HZ; + else if (hz == 70) hz_flag = GFX_MODE_70HZ; + else if (hz == 72) hz_flag = GFX_MODE_72HZ; + else if (hz == 75) hz_flag = GFX_MODE_75HZ; + else if (hz == 85) hz_flag = GFX_MODE_85HZ; + else return -1; + + /* SET BPP FLAGS TO LIMIT MODE SELECTION */ + + if (bpp == 8) bpp_flag = GFX_MODE_8BPP; + else if (bpp == 15) bpp_flag = GFX_MODE_15BPP; + else if (bpp == 16) bpp_flag = GFX_MODE_16BPP; + else return -1; + + /* ONLY PYRAMID SUPPORTS 4K PITCH */ + + if (gfx_cpu_version != GFX_CPU_PYRAMID && xres > 1024) + { + if (bpp > 8) + return (-1); /* return with mode not found */ + } + + /* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */ + + for (mode = 0; mode < NUM_GX_DISPLAY_MODES; mode++) { + if ((DisplayParams[mode].hactive == (unsigned short)xres) && + (DisplayParams[mode].vactive == (unsigned short)yres) && + (DisplayParams[mode].flags & hz_flag) && + (DisplayParams[mode].flags & bpp_flag)) { + + /* SET THE DISPLAY CONTROLLER FOR THE SELECTED MODE */ + + return(mode); + } + } + return(-1); +} + +/*---------------------------------------------------------------------------- + * GFX_SET_DISPLAY_MODE + * + * This routine sets the specified display mode. + * + * Returns 1 if successful, 0 if mode could not be set. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_set_display_mode(int xres, int yres, int bpp, int hz) +#else +int gfx_set_display_mode(int xres, int yres, int bpp, int hz) +#endif +{ + int mode; + + /* DISABLE FLAT PANEL */ + /* Flat Panel settings are enabled by the function gfx_set_fixed_timings */ + /* and disabled by gfx_set_display_mode. */ + + PanelEnable = 0; + + mode = gfx_is_display_mode_supported(xres, yres, bpp, hz); + if(mode >= 0) { + if (gu1_set_specified_mode(&DisplayParams[mode], bpp) == GFX_STATUS_OK) + return(1); + } + return(0); +} + +/*---------------------------------------------------------------------------- + * GFX_SET_DISPLAY_TIMINGS + * + * This routine sets the display controller mode using the specified timing + * values (as opposed to using the tables internal to Durango). + * + * Returns GFX_STATUS_OK on success, GFX_STATUS_ERROR otherwise. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_set_display_timings(unsigned short bpp, unsigned short flags, + unsigned short hactive, unsigned short hblankstart, + unsigned short hsyncstart, unsigned short hsyncend, + unsigned short hblankend, unsigned short htotal, + unsigned short vactive, unsigned short vblankstart, + unsigned short vsyncstart, unsigned short vsyncend, + unsigned short vblankend, unsigned short vtotal, + unsigned long frequency) +#else +int gfx_set_display_timings(unsigned short bpp, unsigned short flags, + unsigned short hactive, unsigned short hblankstart, + unsigned short hsyncstart, unsigned short hsyncend, + unsigned short hblankend, unsigned short htotal, + unsigned short vactive, unsigned short vblankstart, + unsigned short vsyncstart, unsigned short vsyncend, + unsigned short vblankend, unsigned short vtotal, + unsigned long frequency) +#endif +{ + /* SET MODE STRUCTURE WITH SPECIFIED VALUES */ + + gfx_display_mode.flags = 0; + if (flags & 1) gfx_display_mode.flags |= GFX_MODE_NEG_HSYNC; + if (flags & 2) gfx_display_mode.flags |= GFX_MODE_NEG_VSYNC; + if (flags & 0x1000) gfx_display_mode.flags |= GFX_MODE_LOCK_TIMING; + gfx_display_mode.hactive = hactive; + gfx_display_mode.hblankstart = hblankstart; + gfx_display_mode.hsyncstart = hsyncstart; + gfx_display_mode.hsyncend = hsyncend; + gfx_display_mode.hblankend = hblankend; + gfx_display_mode.htotal = htotal; + gfx_display_mode.vactive = vactive; + gfx_display_mode.vblankstart = vblankstart; + gfx_display_mode.vsyncstart = vsyncstart; + gfx_display_mode.vsyncend = vsyncend; + gfx_display_mode.vblankend = vblankend; + gfx_display_mode.vtotal = vtotal; + gfx_display_mode.frequency = frequency; + + /* CALL ROUTINE TO SET MODE */ + + return (gu1_set_specified_mode(&gfx_display_mode, bpp)); +} + +/*---------------------------------------------------------------------------- + * GFX_SET_VTOTAL + * + * This routine sets the display controller vertical total to + * "vtotal". As a side effect it also sets vertical blank end. + * It should be used when only this value needs to be changed, + * due to speed considerations. + * + * Note: it is the caller's responsibility to make sure that + * a legal vtotal is used, i.e. that "vtotal" is greater than or + * equal to vsync end. + * + * Always returns 0. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_set_vtotal(unsigned short vtotal) +#else +int gfx_set_vtotal(unsigned short vtotal) +#endif +{ + unsigned long unlock, tcfg, timing1, timing2; + + /* UNLOCK THE DISPLAY CONTROLLER REGISTERS */ + + unlock = READ_REG32(DC_UNLOCK); + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + + /* READ THE CURRENT GX VALUES */ + + tcfg = READ_REG32(DC_TIMING_CFG); + timing1 = READ_REG32(DC_V_TIMING_1); + timing2 = READ_REG32(DC_V_TIMING_2); + + /* DISABLE THE TIMING GENERATOR */ + + WRITE_REG32(DC_TIMING_CFG, tcfg & ~(unsigned long)DC_TCFG_TGEN); + + /* WRITE NEW TIMING VALUES */ + + WRITE_REG32(DC_V_TIMING_1, (timing1 & 0xffff) | (unsigned long)(vtotal - 1) << 16); + WRITE_REG32(DC_V_TIMING_2, (timing2 & 0xffff) | (unsigned long)(vtotal - 1) << 16); + + /* RESTORE GX VALUES */ + + WRITE_REG32(DC_TIMING_CFG, tcfg); + WRITE_REG32(DC_UNLOCK, unlock); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_pitch + * + * This routine sets the pitch of the frame buffer to the specified value. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_set_display_pitch(unsigned short pitch) +#else +void gfx_set_display_pitch(unsigned short pitch) +#endif +{ + unsigned long value = 0; + unsigned long lock = READ_REG32(DC_UNLOCK); + + value = READ_REG32(DC_LINE_DELTA) & 0xFFFFF000; + value |= (pitch >> 2); + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + WRITE_REG32(DC_LINE_DELTA, value); + WRITE_REG32(DC_UNLOCK, lock); + + /* ALSO UPDATE PITCH IN GRAPHICS ENGINE */ + /* Pyramid alone supports 4K line pitch */ + + value = (unsigned long) READ_REG16(GP_BLIT_STATUS); + value &= ~(BC_FB_WIDTH_2048 | BC_FB_WIDTH_4096); + + if((gfx_cpu_version == GFX_CPU_PYRAMID) && ( pitch > 2048 )) + value |= BC_FB_WIDTH_4096; + + else if( pitch > 1024 ) + value |= BC_FB_WIDTH_2048; + + WRITE_REG16(GP_BLIT_STATUS, (unsigned short) value); + return; +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_offset + * + * This routine sets the start address of the frame buffer. It is + * typically used to pan across a virtual desktop (frame buffer larger than + * the displayed screen) or to flip the display between multiple buffers. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_set_display_offset(unsigned long offset) +#else +void gfx_set_display_offset(unsigned long offset) +#endif +{ + /* UPDATE FRAME BUFFER OFFSET */ + + unsigned long lock; + lock = READ_REG32(DC_UNLOCK); + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + + /* START ADDRESS EFFECTS DISPLAY COMPRESSION */ + /* Disable compression for non-zero start addresss values. */ + /* Enable compression if offset is zero and comression is intended to */ + /* be enabled from a previous call to "gfx_set_compression_enable". */ + /* Compression should be disabled BEFORE the offset is changed */ + /* and enabled AFTER the offset is changed. */ + + if (offset == 0) + { + WRITE_REG32(DC_FB_ST_OFFSET, offset); + if (gfx_compression_enabled) + { + /* WAIT FOR THE OFFSET TO BE LATCHED */ + gfx_wait_vertical_blank (); + gu1_enable_compression(); + } + } + else + { + /* ONLY DISABLE COMPRESSION ONCE */ + + if (gfx_compression_active) + gu1_disable_compression(); + + WRITE_REG32(DC_FB_ST_OFFSET, offset); + } + + WRITE_REG32(DC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_palette_entry + * + * This routine sets an palette entry in the display controller. + * A 32-bit X:R:G:B value. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_set_display_palette_entry(unsigned long index, unsigned long palette) +#else +int gfx_set_display_palette_entry(unsigned long index, unsigned long palette) +#endif +{ + unsigned long data; + + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + WRITE_REG32(DC_PAL_ADDRESS, index); + data = ((palette >> 2) & 0x0003F) | + ((palette >> 4) & 0x00FC0) | + ((palette >> 6) & 0x3F000); + WRITE_REG32(DC_PAL_DATA, data); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_palette + * + * This routine sets the entire palette in the display controller. + * A pointer is provided to a 256 entry table of 32-bit X:R:G:B values. + * Restriction: + * Due to SC1200 Issue #748 (in Notes DB) this function should be called only + * when DCLK is active, i.e PLL is already powered up and genlock is not active. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_set_display_palette(unsigned long *palette) +#else +int gfx_set_display_palette(unsigned long *palette) +#endif +{ + unsigned long data, i; + WRITE_REG32(DC_PAL_ADDRESS, 0); + if (palette) + { + for (i = 0; i < 256; i++) + { + /* CONVERT 24 BPP COLOR DATA TO 18 BPP COLOR DATA */ + + data = ((palette[i] >> 2) & 0x0003F) | + ((palette[i] >> 4) & 0x00FC0) | + ((palette[i] >> 6) & 0x3F000); + WRITE_REG32(DC_PAL_DATA, data); + } + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_enable + * + * This routine enables or disables the hardware cursor. + * + * WARNING: The cusrsor start offset must be set by setting the cursor + * position before calling this routine to assure that memory reads do not + * go past the end of graphics memory (this can hang GXm). + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_set_cursor_enable(int enable) +#else +void gfx_set_cursor_enable(int enable) +#endif +{ + unsigned long unlock, gcfg; + + /* SET OR CLEAR CURSOR ENABLE BIT */ + + unlock = READ_REG32(DC_UNLOCK); + gcfg = READ_REG32(DC_GENERAL_CFG); + if (enable) gcfg |= DC_GCFG_CURE; + else gcfg &= ~(DC_GCFG_CURE); + + /* WRITE NEW REGISTER VALUE */ + + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + WRITE_REG32(DC_GENERAL_CFG, gcfg); + WRITE_REG32(DC_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_colors + * + * This routine sets the colors of the hardware cursor. + * Restriction: + * Due to SC1200 Issue #748 (in Notes DB) this function should be called only + * when DCLK is active, i.e PLL is already powered up. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor) +#else +void gfx_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor) +#endif +{ + unsigned long value; + + /* If genlock is enabled DCLK might be disabled in vertical blank. */ + /* Due to SC1200 Issue #748 in Notes DB this would fail the cursor color settings */ + /* So Wait for vertical blank to end */ + +#if GFX_VIDEO_SC1200 + if (gfx_test_timing_active()) + while ((gfx_get_vline()) > gfx_get_vactive()); +#endif + + /* SET CURSOR COLORS */ + + WRITE_REG32(DC_PAL_ADDRESS, 0x100); + value = ((bkcolor & 0x000000FC) >> 2) | + ((bkcolor & 0x0000FC00) >> (2+8-6)) | + ((bkcolor & 0x00FC0000) >> (2+16-12)); + WRITE_REG32(DC_PAL_DATA, value); + value = ((fgcolor & 0x000000FC) >> 2) | + ((fgcolor & 0x0000FC00) >> (2+8-6)) | + ((fgcolor & 0x00FC0000) >> (2+16-12)); + WRITE_REG32(DC_PAL_DATA, value); +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_position + * + * This routine sets the position of the hardware cusror. The starting + * offset of the cursor buffer must be specified so that the routine can + * properly clip scanlines if the cursor is off the top of the screen. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_set_cursor_position(unsigned long memoffset, + unsigned short xpos, unsigned short ypos, + unsigned short xhotspot, unsigned short yhotspot) +#else +void gfx_set_cursor_position(unsigned long memoffset, + unsigned short xpos, unsigned short ypos, + unsigned short xhotspot, unsigned short yhotspot) +#endif +{ + unsigned long unlock; + + short x, y; + short xoffset = 0; + short yoffset = 0; + + /* SUPPORT CURSOR IN EMULATED VGA MODES */ + /* Timings are for twice the resolution */ + + if (gfx_pixel_double) + xpos <<= 1; + if (gfx_line_double) + ypos <<= 1; + + x = (short) xpos - (short) xhotspot; + y = (short) ypos - (short) yhotspot; + if (x < -31) return; + if (y < -31) return; + if (x < 0) { xoffset = -x; x = 0; } + if (y < 0) { yoffset = -y; y = 0; } + memoffset += (unsigned long) yoffset << 3; + + if (PanelEnable) { + if (( ModeWidth > PanelWidth) || (ModeHeight > PanelHeight)) { + gfx_enable_panning (xpos, ypos); + x = x - (short)panelLeft; + y = y - (short)panelTop; + } + } + + /* SET CURSOR POSITION */ + + unlock = READ_REG32(DC_UNLOCK); + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + WRITE_REG32(DC_CURS_ST_OFFSET, memoffset); + WRITE_REG32(DC_CURSOR_X, (unsigned long) x | + (((unsigned long) xoffset) << 11)); + WRITE_REG32(DC_CURSOR_Y, (unsigned long) y | + (((unsigned long) yoffset) << 11)); + WRITE_REG32(DC_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_shape32 + * + * This routine loads 32x32 cursor data into the specified location in + * graphics memory. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_set_cursor_shape32(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +#else +void gfx_set_cursor_shape32(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +#endif +{ + int i; + unsigned long value; + for (i = 0; i < 32; i++) + { + /* CONVERT TO 16 BITS AND MASK, 16 BITS XOR MASK PER DWORD */ + + value = (andmask[i] & 0xFFFF0000) | (xormask[i] >> 16); + WRITE_FB32(memoffset, value); + memoffset += 4; + value = (andmask[i] << 16) | (xormask[i] & 0x0000FFFF); + WRITE_FB32(memoffset, value); + memoffset += 4; + } +} + +/*--------------------------------------------------------------------------- + * gu1_enable_compression + * + * This is a private routine to this module (not exposed in the Durango API). + * It enables display compression. + *--------------------------------------------------------------------------- + */ +void gu1_enable_compression(void) +{ + int i; + unsigned long unlock, gcfg, offset; + + /* DO NOT ENABLE IF START ADDRESS IS NOT ZERO */ + + offset = READ_REG32(DC_FB_ST_OFFSET) & 0x003FFFFF; + if (offset != 0) return; + + /* DO NOT ENABLE IF WE ARE WITHIN AN EMULATED VGA MODE */ + + if (gfx_line_double || gfx_pixel_double) + return; + + /* SET GLOBAL INDICATOR */ + + gfx_compression_active = 1; + + /* CLEAR DIRTY/VALID BITS IN MEMORY CONTROLLER */ + /* Software is required to do this before enabling compression. */ + /* Don't want controller to think that old lines are still valid. */ + + for (i = 0; i < 1024; i++) + { + WRITE_REG32(MC_DR_ADD, i); + WRITE_REG32(MC_DR_ACC, 0); + } + + /* TURN ON COMPRESSION CONTROL BITS */ + + unlock = READ_REG32(DC_UNLOCK); + gcfg = READ_REG32(DC_GENERAL_CFG); + gcfg |= DC_GCFG_CMPE | DC_GCFG_DECE; + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + WRITE_REG32(DC_GENERAL_CFG, gcfg); + WRITE_REG32(DC_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gu1_disable_compression + * + * This is a private routine to this module (not exposed in the Durango API). + * It disables display compression. + *--------------------------------------------------------------------------- + */ +void gu1_disable_compression(void) +{ + unsigned long unlock, gcfg; + + /* SET GLOBAL INDICATOR */ + + gfx_compression_active = 0; + + /* TURN OFF COMPRESSION CONTROL BITS */ + + unlock = READ_REG32(DC_UNLOCK); + gcfg = READ_REG32(DC_GENERAL_CFG); + gcfg &= ~(DC_GCFG_CMPE | DC_GCFG_DECE); + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + WRITE_REG32(DC_GENERAL_CFG, gcfg); + WRITE_REG32(DC_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_enable + * + * This routine enables or disables display compression. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_set_compression_enable(int enable) +#else +int gfx_set_compression_enable(int enable) +#endif +{ + /* SET GLOBAL VARIABLE FOR INTENDED STATE */ + /* Compression can only be enabled for non-zero start address values. */ + /* Keep state to enable compression on start address changes. */ + + gfx_compression_enabled = enable; + if (enable) gu1_enable_compression(); + else gu1_disable_compression(); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_offset + * + * This routine sets the base offset for the compression buffer. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_set_compression_offset(unsigned long offset) +#else +int gfx_set_compression_offset(unsigned long offset) +#endif +{ + unsigned long lock; + + /* MUST BE 16-BYTE ALIGNED FOR GXLV */ + + if (offset & 0x0F) return(1); + + /* SET REGISTER VALUE */ + + lock = READ_REG32(DC_UNLOCK); + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + WRITE_REG32(DC_CB_ST_OFFSET, offset); + WRITE_REG32(DC_UNLOCK, lock); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_pitch + * + * This routine sets the pitch, in bytes, of the compression buffer. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_set_compression_pitch(unsigned short pitch) +#else +int gfx_set_compression_pitch(unsigned short pitch) +#endif +{ + unsigned long lock, line_delta; + + /* SET REGISTER VALUE */ + + lock = READ_REG32(DC_UNLOCK); + line_delta = READ_REG32(DC_LINE_DELTA) & 0xFF800FFF; + line_delta |= ((unsigned long)pitch << 10l) & 0x007FF000; + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + WRITE_REG32(DC_LINE_DELTA, line_delta); + WRITE_REG32(DC_UNLOCK, lock); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_size + * + * This routine sets the line size of the compression buffer, which is the + * maximum number of bytes allowed to store a compressed line. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_set_compression_size(unsigned short size) +#else +int gfx_set_compression_size(unsigned short size) +#endif +{ + unsigned long lock, buf_size; + + /* SUBTRACT 16 FROM SIZE */ + /* The display controller will actually write */ + /* 2 extra QWords. So, if we assume that "size" */ + /* refers to the allocated size, we must subtract */ + /* 16 bytes. */ + + size -= 16; + + /* SET REGISTER VALUE */ + + lock = READ_REG32(DC_UNLOCK); + buf_size = READ_REG32(DC_BUF_SIZE) & 0xFFFF01FF; + buf_size |= (((size >> 2) + 1) & 0x7F) << 9; + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + WRITE_REG32(DC_BUF_SIZE, buf_size); + WRITE_REG32(DC_UNLOCK, lock); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_enable (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine enables/disables video on GX. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_set_display_video_enable(int enable) +#else +void gfx_set_display_video_enable(int enable) +#endif +{ + unsigned long lock, gcfg, buf_size; + lock = READ_REG32 (DC_UNLOCK); + gcfg = READ_REG32 (DC_GENERAL_CFG); + buf_size = READ_REG32 (DC_BUF_SIZE); + + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + + vid_enabled = enable; + + /* SET THE BUFFER SIZE TO A NON-ZERO VALUE ONLY WHEN */ + /* ENABLING VIDEO */ + + if (enable) + { + gcfg |= (DC_GCFG_VIDE | DC_GCFG_VRDY); + WRITE_REG32 (DC_GENERAL_CFG, gcfg); + + WRITE_REG32 (DC_BUF_SIZE, (buf_size & 0x0000FFFFl) | vid_buf_size); + } + + /* CLEAR THE VIDEO BUFFER SIZE WHEN DISABLING VIDEO */ + + else + { + gcfg &= ~(DC_GCFG_VIDE); + WRITE_REG32 (DC_GENERAL_CFG, gcfg); + + vid_buf_size = buf_size & 0xFFFF0000l; + WRITE_REG32 (DC_BUF_SIZE, buf_size & 0x0000FFFFl); + } + + WRITE_REG32(DC_UNLOCK, lock); + return; +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_size (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_size". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_set_display_video_size(unsigned short width, unsigned short height) +#else +void gfx_set_display_video_size(unsigned short width, unsigned short height) +#endif +{ + unsigned long lock, size, value; + size = (unsigned long) (width << 1) * (unsigned long) height; + + /* STORE THE VIDEO BUFFER SIZE AS A GLOBAL */ + + vid_buf_size = ((size + 63) >> 6) << 16; + + lock = READ_REG32(DC_UNLOCK); + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + value = READ_REG32(DC_BUF_SIZE) & 0x0000FFFF; + value |= vid_buf_size; + WRITE_REG32(DC_BUF_SIZE, value); + WRITE_REG32(DC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_offset (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_offset". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_set_display_video_offset(unsigned long offset) +#else +void gfx_set_display_video_offset(unsigned long offset) +#endif +{ + unsigned long lock; + lock = READ_REG32(DC_UNLOCK); + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + offset &= 0x003FFFFF; + WRITE_REG32(DC_VID_ST_OFFSET, offset); + WRITE_REG32(DC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_priority_high + * + * This routine controls the x-bus round robin arbitration mechanism. + * When enable is TRUE, graphics pipeline requests and non-critical display + * controller requests are arbitrated at the same priority as processor + * requests. When FALSE processor requests are arbitrated at a higher priority. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_set_display_priority_high(int enable) +#else +void gfx_set_display_priority_high(int enable) +#endif +{ + unsigned long lock, control; + lock = READ_REG32(DC_UNLOCK); + control = READ_REG32(MC_MEM_CNTRL1); + WRITE_REG32(DC_UNLOCK, DC_UNLOCK_VALUE); + if (enable) + control |= MC_XBUSARB; + else control &= ~(MC_XBUSARB); + WRITE_REG32(MC_MEM_CNTRL1, control); + WRITE_REG32(DC_UNLOCK, lock); + return; +} + +/*--------------------------------------------------------------------------- + * gfx_test_timing_active + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_test_timing_active(void) +#else +int gfx_test_timing_active(void) +#endif +{ + if (READ_REG32(DC_TIMING_CFG) & DC_TCFG_TGEN) + return(1); + else return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_test_vertical_active + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_test_vertical_active(void) +#else +int gfx_test_vertical_active(void) +#endif +{ + if (READ_REG32(DC_TIMING_CFG) & DC_TCFG_VNA) + return(0); + else return(1); +} + +/*--------------------------------------------------------------------------- + * gfx_wait_vertical_blank + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_wait_vertical_blank(void) +#else +int gfx_wait_vertical_blank(void) +#endif +{ + if (gfx_test_timing_active()) + { + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_enable_panning + * + * This routine enables the panning when the Mode is bigger than the panel + * size. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_enable_panning(int x, int y) +#else +void gfx_enable_panning(int x, int y) +#endif +{ + unsigned long modeBytesPerPixel; + unsigned long modeBytesPerScanline = 0; + unsigned long startAddress = 0; + + modeBytesPerPixel = (gbpp + 7)/8; + modeBytesPerScanline = (((ModeWidth + 1023) / 1024) * 1024) * modeBytesPerPixel; + + /* TEST FOR NO-WORK */ + + if (x >= DeltaX && (unsigned short)x < (PanelWidth + DeltaX) && + y >= DeltaY && (unsigned short)y < (PanelHeight + DeltaY)) + return; + + + /* ADJUST PANNING VARIABLES WHEN CURSOR EXCEEDS BOUNDARY */ + /* Test the boundary conditions for each coordinate and update */ + /* all variables and the starting offset accordingly. */ + + if (x < DeltaX) + DeltaX = x; + + else if ((unsigned short)x >= (DeltaX + PanelWidth)) + DeltaX = x - PanelWidth + 1; + + if (y < DeltaY) + DeltaY = y; + + else if ((unsigned short)y >= (DeltaY + PanelHeight)) + DeltaY = y - PanelHeight + 1; + + + /* CALCULATE THE START OFFSET */ + + startAddress = (DeltaX * modeBytesPerPixel) + (DeltaY * modeBytesPerScanline); + + gfx_set_display_offset(startAddress); + + + /* SET PANEL COORDINATES */ + /* Panel's x position must be DWORD aligned */ + + panelTop = DeltaY; + panelLeft = DeltaX * modeBytesPerPixel; + + if (panelLeft & 3) + panelLeft = (panelLeft & 0xFFFFFFFC) + 4; + + panelLeft /= modeBytesPerPixel; + +} + +/*--------------------------------------------------------------------------- + * gfx_set_fixed_timings + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#else +int gfx_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#endif +{ + unsigned int mode; + + ModeWidth = width; + ModeHeight = height; + PanelWidth = (unsigned short)panelResX; + PanelHeight = (unsigned short)panelResY; + PanelEnable = 1; + + /* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */ + for (mode = 0; mode < NUM_FIXED_TIMINGS_MODES; mode++) { + if ((FixedParams[mode].xres == width) && + (FixedParams[mode].yres == height) && + (FixedParams[mode].panelresx == panelResX) && + (FixedParams[mode].panelresy == panelResY)) { + + /* SET THE 92xx FOR THE SELECTED MODE */ + FIXEDTIMINGS *fmode = &FixedParams[mode]; + + gfx_set_display_timings(bpp, 3, fmode->hactive,fmode->hblankstart, fmode->hsyncstart, fmode->hsyncend, + fmode->hblankend, fmode->htotal, fmode->vactive, fmode->vblankstart, + fmode->vsyncstart, fmode->vsyncend, fmode->vblankend, fmode->vtotal, fmode->frequency); + + return(1); + } /* end if() */ + } /* end for() */ + + return(-1); +} + +/*--------------------------------------------------------------------------- + * gfx_set_panel_present + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#else +int gfx_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#endif +{ + /* SET VALID BPP */ + /* 16BPP is the default. */ + + if (bpp != 8 && bpp != 15 && bpp != 16) + bpp = 16; + + /* RECORD PANEL PARAMETERS */ + /* This routine does not touch any panel timings. It is used when custom panel */ + /* settings are set up in advance by the BIOS or an application, but the */ + /* application still requires access to other panel functionality provided by */ + /* Durango (i.e. panning). */ + + ModeWidth = width; + ModeHeight = height; + PanelWidth = (unsigned short)panelResX; + PanelHeight = (unsigned short)panelResY; + PanelEnable = 1; + gbpp = bpp; + + /* PROGRAM THE BPP IN THE DISPLAY CONTROLLER */ + + gfx_set_display_bpp (bpp); + + return(GFX_STATUS_OK); +} + +/*-----------------------------------------------------------------------* + * THE FOLLOWING READ ROUTINES ARE ALWAYS INCLUDED: * + * gfx_get_hsync_end, gfx_get_htotal, gfx_get_vsync_end, gfx_get_vtotal * + * are used by the video overlay routines. * + * * + * gfx_get_vline and gfx_vactive are used to prevent an issue for the * + * SC1200. * + * * + * The others are part of the Durango API. * + *-----------------------------------------------------------------------*/ + +/*--------------------------------------------------------------------------- + * gfx_get_display_pitch + * + * This routine returns the current pitch of the frame buffer, in bytes. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_display_pitch(void) +#else +unsigned short gfx_get_display_pitch(void) +#endif +{ + unsigned long value; + if (gfx_cpu_version == GFX_CPU_PYRAMID) {/* Pyramid update for 4KB line pitch */ + value = (READ_REG32(DC_LINE_DELTA) & 0x07FF) << 2; + } else { + value = (READ_REG32(DC_LINE_DELTA) & 0x03FF) << 2; + } + + return((unsigned short) value); +} + +/*---------------------------------------------------------------------------- + * GFX_GET_DISPLAY_DETAILS + * + * This routine gets the specified display mode. + * + * Returns 1 if successful, 0 if mode could not be get. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_get_display_details(unsigned int mode, int *xres, int *yres, int *hz) +#else +int gfx_get_display_details(unsigned int mode, int *xres, int *yres, int *hz) +#endif +{ + if(mode < NUM_GX_DISPLAY_MODES){ + if(DisplayParams[mode].flags & GFX_MODE_56HZ) + *hz = 56; + else if(DisplayParams[mode].flags & GFX_MODE_60HZ) + *hz = 60; + else if(DisplayParams[mode].flags & GFX_MODE_70HZ) + *hz = 70; + else if(DisplayParams[mode].flags & GFX_MODE_72HZ) + *hz = 72; + else if(DisplayParams[mode].flags & GFX_MODE_75HZ) + *hz = 75; + else if(DisplayParams[mode].flags & GFX_MODE_85HZ) + *hz = 85; + + *xres = DisplayParams[mode].hactive; + *yres = DisplayParams[mode].vactive; + + return(1); + } + return(0); +} + +/*---------------------------------------------------------------------------- + * GFX_GET_DISPLAY_MODE_COUNT + * + * Returns number of modes supported. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_get_display_mode_count(void) +#else +int gfx_get_display_mode_count(void) +#endif +{ + return(NUM_GX_DISPLAY_MODES); +} + +/*---------------------------------------------------------------------------- + * gfx_get_frame_buffer_line_size + * + * Returns the current frame buffer line size, in bytes + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu1_get_frame_buffer_line_size(void) +#else +unsigned long gfx_get_frame_buffer_line_size(void) +#endif +{ + return ((READ_REG32 (DC_BUF_SIZE) & 0x1FF) << 3); +} + +/*---------------------------------------------------------------------------- + * gfx_mode_frequency_supported + * + * This routine examines if the requested mode with pixel frequency is supported. + * + * Returns >0 if successful , <0 if freq. could not be found and matched. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency) +#else +int gfx_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency) +#endif +{ + unsigned int index; + unsigned long value; + unsigned long bpp_flag = 0; + + bpp_flag = GFX_MODE_8BPP; + if (bpp > 8) bpp_flag = GFX_MODE_16BPP; + + for (index = 0; index < NUM_GX_DISPLAY_MODES; index++) + { + if ((DisplayParams[index].hactive == (unsigned short)xres) && + (DisplayParams[index].vactive == (unsigned short)yres) && + (DisplayParams[index].flags & bpp_flag) && + (DisplayParams[index].frequency == frequency)) + { + int hz=0; + value = DisplayParams[index].flags; + + if (value & GFX_MODE_56HZ) hz = 56; + else if (value & GFX_MODE_60HZ) hz = 60; + else if (value & GFX_MODE_70HZ) hz = 70; + else if (value & GFX_MODE_72HZ) hz = 72; + else if (value & GFX_MODE_75HZ) hz = 75; + else if (value & GFX_MODE_85HZ) hz = 85; + return(hz); + } + } + return(-1); +} + +/*---------------------------------------------------------------------------- + * gfx_refreshrate_from_frequency + * + * This routine maps the frequency to close match refresh rate + * + * Returns . + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency) +#else +int gfx_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency) +#endif +{ + unsigned int index, closematch=0; + unsigned long value; + unsigned long bpp_flag = 0; + long min, diff; + + *hz = 60; + + bpp_flag = GFX_MODE_8BPP; + if (bpp > 8) bpp_flag = GFX_MODE_16BPP; + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + + min = 0x7fffffff; + for (index = 0; index < NUM_GX_DISPLAY_MODES; index++) + { + if ((DisplayParams[index].htotal == (unsigned short)xres) && + (DisplayParams[index].vtotal == (unsigned short)yres) && + (DisplayParams[index].flags & bpp_flag)) + { + diff = (long)frequency - (long)DisplayParams[index].frequency; + if(diff < 0) diff = -diff; + + if (diff < min) + { + min = diff; + closematch = index; + } + } + } + + value = DisplayParams[closematch].flags; + + if (value & GFX_MODE_56HZ) *hz = 56; + else if (value & GFX_MODE_60HZ) *hz = 60; + else if (value & GFX_MODE_70HZ) *hz = 70; + else if (value & GFX_MODE_72HZ) *hz = 72; + else if (value & GFX_MODE_75HZ) *hz = 75; + else if (value & GFX_MODE_85HZ) *hz = 85; + + return(1); +} + +/*---------------------------------------------------------------------------- + * gfx_refreshrate_from_mode + * + * This routine is identical to the gfx_get_refreshrate_from_frequency, + * except that the active timing values are compared instead of the total + * values. Some modes (such as 70Hz and 72Hz) may be confused in this routine. + * + * Returns . + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency) +#else +int gfx_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency) +#endif +{ + unsigned int index, closematch=0; + unsigned long value; + unsigned long bpp_flag = 0; + long min, diff; + + *hz = 60; + + bpp_flag = GFX_MODE_8BPP; + if (bpp > 8) bpp_flag = GFX_MODE_16BPP; + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + + min = 0x7fffffff; + for (index = 0; index < NUM_GX_DISPLAY_MODES; index++) + { + if ((DisplayParams[index].hactive == (unsigned short)xres) && + (DisplayParams[index].vactive == (unsigned short)yres) && + (DisplayParams[index].flags & bpp_flag)) + { + diff = (long)frequency - (long)DisplayParams[index].frequency; + if(diff < 0) diff = -diff; + + if (diff < min) + { + min = diff; + closematch = index; + } + } + } + + value = DisplayParams[closematch].flags; + + if (value & GFX_MODE_56HZ) *hz = 56; + else if (value & GFX_MODE_60HZ) *hz = 60; + else if (value & GFX_MODE_70HZ) *hz = 70; + else if (value & GFX_MODE_72HZ) *hz = 72; + else if (value & GFX_MODE_75HZ) *hz = 75; + else if (value & GFX_MODE_85HZ) *hz = 85; + + return(1); +} + +/*---------------------------------------------------------------------------- + * gfx_get_frequency_from_refreshrate + * + * This routine maps the refresh rate to the closest matching PLL frequency. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency) +#else +int gfx_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency) +#endif +{ + unsigned int index; + int retval = -1; + unsigned long hz_flag = 0; + unsigned long bpp_flag = 0; + + *frequency = 0; + + if (hz == 56) hz_flag = GFX_MODE_56HZ; + else if (hz == 60) hz_flag = GFX_MODE_60HZ; + else if (hz == 70) hz_flag = GFX_MODE_70HZ; + else if (hz == 72) hz_flag = GFX_MODE_72HZ; + else if (hz == 75) hz_flag = GFX_MODE_75HZ; + else if (hz == 85) hz_flag = GFX_MODE_85HZ; + + bpp_flag = GFX_MODE_8BPP; + if (bpp > 8) bpp_flag = GFX_MODE_16BPP; + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + + for (index = 0; index < NUM_GX_DISPLAY_MODES; index++) + { + if ((DisplayParams[index].hactive == (unsigned short)xres) && + (DisplayParams[index].vactive == (unsigned short)yres) && + (DisplayParams[index].flags & bpp_flag) && + (DisplayParams[index].flags & hz_flag)) + { + *frequency = DisplayParams[index].frequency; + retval = 1; + } + } + return retval; +} + +/*--------------------------------------------------------------------------- + * gfx_get_max_supported_pixel_clock + * + * This routine returns the maximum recommended speed for the pixel clock. The + * return value is an integer of the format xxxyyy, where xxx.yyy is the maximum + * floating point pixel clock speed. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu1_get_max_supported_pixel_clock (void) +#else +unsigned long gfx_get_max_supported_pixel_clock (void) +#endif + +{ + /* ALL CHIPS CAN HANDLE 1280X1024@85HZ - 157.5 MHz */ + + return 157500; +} + +/*---------------------------------------------------------------------------- + * gfx_get_display_mode + * + * This routine gets the specified display mode. + * + * Returns >0 if successful and mode returned, <0 if mode could not be found. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_get_display_mode(int *xres, int *yres, int *bpp, int *hz) +#else +int gfx_get_display_mode(int *xres, int *yres, int *bpp, int *hz) +#endif +{ + unsigned int mode=0; + unsigned long pll_freq = 0, bpp_flag = 0; + + *xres = gfx_get_hactive(); + *yres = gfx_get_vactive(); + *bpp = gfx_get_display_bpp(); + pll_freq = gfx_get_clock_frequency(); + + /* SUPPORT EMULATED VGA MODES */ + + if (gfx_pixel_double) + *xres >>= 1; + + if (gfx_line_double) + *yres >>= 1; + + /* SET BPP FLAGS TO LIMIT MODE SELECTION */ + + bpp_flag = GFX_MODE_8BPP; + if (*bpp > 8) bpp_flag = GFX_MODE_16BPP; + + for (mode = 0; mode < NUM_GX_DISPLAY_MODES; mode++) { + if ((DisplayParams[mode].hactive == (unsigned short)*xres) && + (DisplayParams[mode].vactive == (unsigned short)*yres) && + (DisplayParams[mode].frequency == pll_freq) && + (DisplayParams[mode].flags & bpp_flag)) { + + pll_freq = DisplayParams[mode].flags; + + if (pll_freq & GFX_MODE_56HZ) *hz = 56; + else if (pll_freq & GFX_MODE_60HZ) *hz = 60; + else if (pll_freq & GFX_MODE_70HZ) *hz = 70; + else if (pll_freq & GFX_MODE_72HZ) *hz = 72; + else if (pll_freq & GFX_MODE_75HZ) *hz = 75; + else if (pll_freq & GFX_MODE_85HZ) *hz = 85; + + return(1); + } + } + return(-1); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hactive + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_hactive(void) +#else +unsigned short gfx_get_hactive(void) +#endif +{ + return((unsigned short)((READ_REG32(DC_H_TIMING_1) & 0x07F8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hsync_start + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_hsync_start(void) +#else +unsigned short gfx_get_hsync_start(void) +#endif +{ + return((unsigned short)((READ_REG32(DC_H_TIMING_3) & 0x07F8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hsync_end + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_hsync_end(void) +#else +unsigned short gfx_get_hsync_end(void) +#endif +{ + return((unsigned short)(((READ_REG32(DC_H_TIMING_3) >> 16) & 0x07F8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_htotal + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_htotal(void) +#else +unsigned short gfx_get_htotal(void) +#endif +{ + return((unsigned short)(((READ_REG32(DC_H_TIMING_1) >> 16) & 0x07F8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vactive + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_vactive(void) +#else +unsigned short gfx_get_vactive(void) +#endif +{ + return((unsigned short)((READ_REG32(DC_V_TIMING_1) & 0x07FF) + 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vsync_end + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_vsync_end(void) +#else +unsigned short gfx_get_vsync_end(void) +#endif +{ + return((unsigned short)(((READ_REG32(DC_V_TIMING_3) >> 16) & 0x07FF) + 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vtotal + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_vtotal(void) +#else +unsigned short gfx_get_vtotal(void) +#endif +{ + return((unsigned short)(((READ_REG32(DC_V_TIMING_1) >> 16) & 0x07FF) + 1)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_bpp + * + * This routine returns the current color depth of the active display. + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_display_bpp(void) +#else +unsigned short gfx_get_display_bpp(void) +#endif +{ + switch(READ_REG32(DC_OUTPUT_CFG) & 3) + { + case 0: return(16); + case 2: return(15); + } + return(8); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vline + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_vline(void) +#else +unsigned short gfx_get_vline(void) +#endif +{ + unsigned short current_scan_line; + + /* Read similar value twice to ensure that the value is not transitioning */ + + do current_scan_line = (unsigned short)READ_REG32(DC_V_LINE_CNT) & 0x07FF; + while(current_scan_line != (unsigned short)(READ_REG32(DC_V_LINE_CNT) & 0x07FF)); + + return(current_scan_line); +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_offset + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu1_get_display_offset(void) +#else +unsigned long gfx_get_display_offset(void) +#endif +{ + return(READ_REG32(DC_FB_ST_OFFSET) & 0x003FFFFF); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_offset + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu1_get_cursor_offset(void) +#else +unsigned long gfx_get_cursor_offset(void) +#endif +{ + return(READ_REG32(DC_CURS_ST_OFFSET) & 0x003FFFFF); +} + + +#if GFX_READ_ROUTINES + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +/*--------------------------------------------------------------------------- + * gfx_get_hblank_start + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_hblank_start(void) +#else +unsigned short gfx_get_hblank_start(void) +#endif +{ + return((unsigned short)((READ_REG32(DC_H_TIMING_2) & 0x07F8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hblank_end + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_hblank_end(void) +#else +unsigned short gfx_get_hblank_end(void) +#endif +{ + return((unsigned short)(((READ_REG32(DC_H_TIMING_2) >> 16) & 0x07F8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vblank_start + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_vblank_start(void) +#else +unsigned short gfx_get_vblank_start(void) +#endif +{ + return((unsigned short)((READ_REG32(DC_V_TIMING_2) & 0x07FF) + 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vsync_start + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_vsync_start(void) +#else +unsigned short gfx_get_vsync_start(void) +#endif +{ + return((unsigned short)((READ_REG32(DC_V_TIMING_3) & 0x07FF) + 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vblank_end + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_vblank_end(void) +#else +unsigned short gfx_get_vblank_end(void) +#endif +{ + return((unsigned short)(((READ_REG32(DC_V_TIMING_2) >> 16) & 0x07FF) + 1)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_palette_entry + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_get_display_palette_entry(unsigned long index, unsigned long *palette) +#else +int gfx_get_display_palette_entry(unsigned long index, unsigned long *palette) +#endif +{ + unsigned long data; + + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + WRITE_REG32(DC_PAL_ADDRESS, index); + data = READ_REG32(DC_PAL_DATA); + data = ((data << 2) & 0x000000FC) | + ((data << 4) & 0x0000FC00) | + ((data << 6) & 0x00FC0000); + + *palette = data; + + return 0; +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_palette + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu1_get_display_palette(unsigned long *palette) +#else +void gfx_get_display_palette(unsigned long *palette) +#endif +{ + unsigned long i, data; + WRITE_REG32(DC_PAL_ADDRESS, 0); + for (i = 0; i < 256; i++) + { + data = READ_REG32(DC_PAL_DATA); + data = ((data << 2) & 0x000000FC) | + ((data << 4) & 0x0000FC00) | + ((data << 6) & 0x00FC0000); + palette[i] = data; + } +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_enable + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu1_get_cursor_enable(void) +#else +unsigned long gfx_get_cursor_enable(void) +#endif +{ + return(READ_REG32(DC_GENERAL_CFG) & DC_GCFG_CURE); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_position + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu1_get_cursor_position(void) +#else +unsigned long gfx_get_cursor_position(void) +#endif +{ + return((READ_REG32(DC_CURSOR_X) & 0x07FF) | + ((READ_REG32(DC_CURSOR_Y) << 16) & 0x03FF0000)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_clip + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu1_get_cursor_clip(void) +#else +unsigned long gfx_get_cursor_clip(void) +#endif +{ + return(((READ_REG32(DC_CURSOR_X) >> 11) & 0x01F) | + ((READ_REG32(DC_CURSOR_Y) << 5) & 0x1F0000)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_color + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu1_get_cursor_color(int color) +#else +unsigned long gfx_get_cursor_color(int color) +#endif +{ + unsigned long data; + if (color) + { + WRITE_REG32(DC_PAL_ADDRESS, 0x101); + } + else + { + WRITE_REG32(DC_PAL_ADDRESS, 0x100); + } + data = READ_REG32(DC_PAL_DATA); + data = ((data << 6) & 0x00FC0000) | + ((data << 4) & 0x0000FC00) | + ((data << 2) & 0x000000FC); + return(data); +} + +/*----------------------------------------------------------------------------- + * gfx_get_compression_enable + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_get_compression_enable(void) +#else +int gfx_get_compression_enable(void) +#endif +{ + unsigned long gcfg; + gcfg = READ_REG32(DC_GENERAL_CFG); + if (gcfg & DC_GCFG_CMPE) return(1); + else return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_get_compression_offset + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu1_get_compression_offset(void) +#else +unsigned long gfx_get_compression_offset(void) +#endif +{ + unsigned long offset; + offset = READ_REG32(DC_CB_ST_OFFSET) & 0x003FFFFF; + return(offset); +} + +/*----------------------------------------------------------------------------- + * gfx_get_compression_pitch + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_compression_pitch(void) +#else +unsigned short gfx_get_compression_pitch(void) +#endif +{ + unsigned short pitch; + pitch = (unsigned short) (READ_REG32(DC_LINE_DELTA) >> 12) & 0x03FF; + return(pitch << 2); +} + +/*----------------------------------------------------------------------------- + * gfx_get_compression_size + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu1_get_compression_size(void) +#else +unsigned short gfx_get_compression_size(void) +#endif +{ + unsigned short size; + size = (unsigned short) ((READ_REG32(DC_BUF_SIZE) >> 9) & 0x7F) - 1; + return((size << 2) + 16); +} + +/*----------------------------------------------------------------------------- + * gfx_get_valid_bit + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_get_valid_bit(int line) +#else +int gfx_get_valid_bit(int line) +#endif +{ + int valid; + WRITE_REG32(MC_DR_ADD, line); + valid = (int)READ_REG32(MC_DR_ACC) & 1; + return(valid); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_offset (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_offset". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu1_get_display_video_offset(void) +#else +unsigned long gfx_get_display_video_offset(void) +#endif +{ + return(READ_REG32(DC_VID_ST_OFFSET) & 0x003FFFFF); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_size (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_size". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu1_get_display_video_size(void) +#else +unsigned long gfx_get_display_video_size(void) +#endif +{ + /* RETURN TOTAL SIZE, IN BYTES */ + + return((READ_REG32(DC_BUF_SIZE) >> 10) & 0x000FFFC0); +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_priority_high + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu1_get_display_priority_high(void) +#else +int gfx_get_display_priority_high(void) +#endif +{ + if (READ_REG32(MC_MEM_CNTRL1) & MC_XBUSARB) return(1); + else return(0); +} + +#endif /* GFX_READ_ROUTINES */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/disp_gu2.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/disp_gu2.c 2005-12-14 11:37:19.000000000 -0700 @@ -0,0 +1,2669 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines for the second generation display controller. + * */ + + +void gu2_enable_compression(void); /* private routine definition */ +void gu2_disable_compression(void); /* private routine definition */ +int gfx_set_display_control(int sync_polarities); /* private routine definition */ +void gfx_reset_video (void); +int gu2_set_specified_mode(DISPLAYMODE *pMode, int bpp); + + /*----------------------------------------------------------------------------- + * WARNING!!!! INACCURATE DELAY MECHANISM + * + * In an effort to keep the code self contained and operating system + * independent, the delay loop just performs reads of a display controller + * register. This time will vary for faster processors. The delay can always + * be longer than intended, only effecting the time of the mode switch + * (obviously want it to still be under a second). Problems with the hardware + * only arise if the delay is not long enough. + *----------------------------------------------------------------------------- + */ + +#define RC_READS_PER_MILLISECOND 15000L + +#if GFX_DISPLAY_DYNAMIC +void gu2_delay_milliseconds(unsigned long milliseconds) +#else +void gfx_delay_milliseconds(unsigned long milliseconds) +#endif +{ + /* ASSUME 300 MHZ 20 CLOCKS PER READ */ + + unsigned long loop; + loop = milliseconds * RC_READS_PER_MILLISECOND; + while (loop-- > 0) + { + READ_REG32 (MDC_UNLOCK); + } +} + +#if GFX_DISPLAY_DYNAMIC +void gu2_delay_microseconds(unsigned long microseconds) +#else +void gfx_delay_microseconds(unsigned long microseconds) +#endif +{ + /* ASSUME 400 MHz, 2 CLOCKS PER INCREMENT */ + + + unsigned long loop_count = microseconds * 15; + + while (loop_count-- > 0) + { + READ_REG32 (MDC_UNLOCK); + } +} + +/*----------------------------------------------------------------------------- + * GFX_SET_DISPLAY_BPP + * + * This routine programs the bpp in the display controller. + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_set_display_bpp(unsigned short bpp) +#else +int gfx_set_display_bpp(unsigned short bpp) +#endif +{ + unsigned long dcfg, lock; + + dcfg = READ_REG32 (MDC_DISPLAY_CFG) & ~(MDC_DCFG_DISP_MODE_MASK | MDC_DCFG_16BPP_MODE_MASK); + lock = READ_REG32 (MDC_UNLOCK); + + switch (bpp) + { + case 12: dcfg |= (MDC_DCFG_DISP_MODE_16BPP | MDC_DCFG_12BPP); break; + case 15: dcfg |= (MDC_DCFG_DISP_MODE_16BPP | MDC_DCFG_15BPP); break; + case 16: dcfg |= (MDC_DCFG_DISP_MODE_16BPP | MDC_DCFG_16BPP); break; + case 32: dcfg |= (MDC_DCFG_DISP_MODE_24BPP); break; + case 8: dcfg |= (MDC_DCFG_DISP_MODE_8BPP); break; + default: return GFX_STATUS_BAD_PARAMETER; + } + + WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32 (MDC_DISPLAY_CFG, dcfg); + WRITE_REG32 (MDC_UNLOCK, lock); + + /* SET BPP IN GRAPHICS PIPELINE */ + + gfx_set_bpp (bpp); + + return 0; +} + +/*----------------------------------------------------------------------------- + * gu2_set_specified_mode (private routine) + * This routine uses the parameters in the specified display mode structure + * to program the display controller hardware. + *----------------------------------------------------------------------------- + */ +int gu2_set_specified_mode(DISPLAYMODE *pMode, int bpp) +{ + unsigned long unlock, value; + unsigned long gcfg, dcfg; + unsigned long size, pitch; + unsigned long vid_buf_size; + unsigned long bpp_mask, temp, dv_size; + + /* CHECK WHETHER TIMING CHANGE IS ALLOWED */ + /* Flag used for locking also overrides timing change restriction */ + + if (gfx_timing_lock && !(pMode->flags & GFX_MODE_LOCK_TIMING)) + return GFX_STATUS_ERROR; + + /* CLEAR PANNING OFFSETS */ + + DeltaX = 0; + DeltaY = 0; + panelLeft = 0; + panelTop = 0; + + /* SET GLOBAL FLAG */ + + if (pMode->flags & GFX_MODE_LOCK_TIMING) + gfx_timing_lock = 1; + + /* CHECK FOR VALID BPP */ + /* As this function can be called directly from */ + /* gfx_set_display_timings, we must correct any */ + /* invalid bpp settings. */ + + switch (bpp) + { + case 12: bpp_mask = 0x00000900; break; + case 15: bpp_mask = 0x00000500; break; + case 16: bpp_mask = 0x00000100; break; + case 32: bpp_mask = 0x00000200; break; + default: bpp_mask = 0x00000000; bpp = 8; break; + } + + gbpp = bpp; + + /* DISABLE COMPRESSION */ + + gu2_disable_compression(); + + /* ALSO DISABLE VIDEO */ + /* Use private "reset video" routine to do all that is needed. */ + /* SC1200, for example, also disables the alpha blending regions. */ + + gfx_reset_video(); + + /* UNLOCK THE DISPLAY CONTROLLER REGISTERS */ + + unlock = READ_REG32 (MDC_UNLOCK); + WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE); + + /* READ THE CURRENT REGISTER VALUES */ + + gcfg = READ_REG32 (MDC_GENERAL_CFG); + dcfg = READ_REG32 (MDC_DISPLAY_CFG); + + /* BLANK THE DISPLAY IN THE DISPLAY FILTER */ + + gfx_set_crt_enable (0); + + /* DISABLE THE TIMING GENERATOR */ + + dcfg &= ~(unsigned long)MDC_DCFG_TGEN; + WRITE_REG32 (MDC_DISPLAY_CFG, dcfg); + + /* DELAY: WAIT FOR PENDING MEMORY REQUESTS */ + /* This delay is used to make sure that all pending requests to the */ + /* memory controller have completed before disabling the FIFO load. */ + + gfx_delay_milliseconds(5); + + /* DISABLE DISPLAY FIFO LOAD */ + + gcfg &= ~(unsigned long)MDC_GCFG_DFLE; + WRITE_REG32 (MDC_GENERAL_CFG, gcfg); + + /* PRESERVE VIDEO INFORMATION */ + + gcfg &= (unsigned long)(MDC_GCFG_YUVM | MDC_GCFG_VDSE); + dcfg = 0; + + /* SET THE DOT CLOCK FREQUENCY */ + /* Mask off the divide by two bit (bit 31) */ + + if (!(pMode->flags & GFX_MODE_EXCLUDE_PLL)) + gfx_set_clock_frequency(pMode->frequency & 0x7FFFFFFF); + + /* DELAY: WAIT FOR THE PLL TO SETTLE */ + /* This allows the dot clock frequency that was just set to settle. */ + + gfx_delay_milliseconds(10); + + /* SET THE GX DISPLAY CONTROLLER PARAMETERS */ + + WRITE_REG32 (MDC_FB_ST_OFFSET, 0); + WRITE_REG32 (MDC_CB_ST_OFFSET, 0); + WRITE_REG32 (MDC_CURS_ST_OFFSET, 0); + WRITE_REG32 (MDC_ICON_ST_OFFSET, 0); + + /* SET LINE SIZE AND PITCH */ + /* 1. Flat Panels must use the mode width and not */ + /* the timing width to set the pitch. */ + /* 2. Mode sets will use a pitch that is aligned */ + /* on a 1K boundary to preserve legacy. The */ + /* pitch can be overridden by a subsequent call */ + /* to gfx_set_display_pitch. */ + + if (PanelEnable) + size = ModeWidth; + else + size = pMode->hactive; + + if (bpp > 8) size <<= 1; + if (bpp > 16) size <<= 1; + + pitch = 1024; + dv_size = MDC_DV_LINE_SIZE_1024; + + if (size > 1024) + { + pitch = 2048; + dv_size = MDC_DV_LINE_SIZE_2048; + } + if (size > 2048) + { + pitch = 4096; + dv_size = MDC_DV_LINE_SIZE_4096; + } + if (size > 4096) + { + pitch = 8192; + dv_size = MDC_DV_LINE_SIZE_8192; + } + WRITE_REG32(MDC_GFX_PITCH, pitch >> 3); + + /* WRITE DIRTY/VALID CONTROL WITH LINE LENGTH */ + + temp = READ_REG32 (MDC_DV_CTL); + WRITE_REG32 (MDC_DV_CTL, (temp & ~MDC_DV_LINE_SIZE_MASK) | dv_size); + + if (PanelEnable) + { + size = pMode->hactive; + if (bpp > 8) size <<= 1; + if (bpp > 16) size <<= 1; + } + + /* SAVE PREVIOUSLY STORED VIDEO LINE SIZE */ + + vid_buf_size = READ_REG32(MDC_LINE_SIZE) & 0xFF000000; + + /* ADD 2 TO SIZE FOR POSSIBLE START ADDRESS ALIGNMENTS */ + + WRITE_REG32 (MDC_LINE_SIZE, ((size >> 3) + 2) | vid_buf_size); + + + /* ALWAYS ENABLE VIDEO AND GRAPHICS DATA */ + /* These bits are relics from a previous design and */ + /* should always be enabled. */ + + dcfg |= (unsigned long)(MDC_DCFG_VDEN | MDC_DCFG_GDEN); + + /* SET PIXEL FORMAT */ + + dcfg |= bpp_mask; + + /* ENABLE TIMING GENERATOR, TIM. REG. UPDATES, PALETTE BYPASS */ + /* AND VERT. INT. SELECT */ + + dcfg |= (unsigned long)(MDC_DCFG_TGEN | MDC_DCFG_TRUP | MDC_DCFG_PALB | MDC_DCFG_VISL); + + /* DISABLE ADDRESS MASKS */ + + dcfg |= MDC_DCFG_A20M; + dcfg |= MDC_DCFG_A18M; + + /* SET FIFO PRIORITIES AND DISPLAY FIFO LOAD ENABLE */ + /* Set the priorities higher for high resolution modes. */ + + if (pMode->hactive > 1024 || bpp == 32) + gcfg |= 0x000A901; + else + gcfg |= 0x0006501; + + + /* ENABLE FLAT PANEL CENTERING */ + /* For panel modes having a resolution smaller than the */ + /* panel resolution, turn on data centering. */ + + if (PanelEnable && ModeWidth < PanelWidth) + dcfg |= MDC_DCFG_DCEN; + + /* COMBINE AND SET TIMING VALUES */ + + value = (unsigned long) (pMode->hactive - 1) | + (((unsigned long) (pMode->htotal - 1)) << 16); + WRITE_REG32(MDC_H_ACTIVE_TIMING, value); + value = (unsigned long) (pMode->hblankstart - 1) | + (((unsigned long) (pMode->hblankend - 1)) << 16); + WRITE_REG32(MDC_H_BLANK_TIMING, value); + value = (unsigned long) (pMode->hsyncstart - 1) | + (((unsigned long) (pMode->hsyncend - 1)) << 16); + WRITE_REG32(MDC_H_SYNC_TIMING, value); + value = (unsigned long) (pMode->vactive - 1) | + (((unsigned long) (pMode->vtotal - 1)) << 16); + WRITE_REG32(MDC_V_ACTIVE_TIMING, value); + value = (unsigned long) (pMode->vblankstart - 1) | + (((unsigned long) (pMode->vblankend - 1)) << 16); + WRITE_REG32(MDC_V_BLANK_TIMING, value); + value = (unsigned long) (pMode->vsyncstart - 1) | + (((unsigned long) (pMode->vsyncend - 1)) << 16); + WRITE_REG32(MDC_V_SYNC_TIMING, value); + + WRITE_REG32 (MDC_DISPLAY_CFG, dcfg); + WRITE_REG32 (MDC_GENERAL_CFG, gcfg); + + /* CONFIGURE DISPLAY OUTPUT FROM VIDEO PROCESSOR */ + + gfx_set_display_control (((pMode->flags & GFX_MODE_NEG_HSYNC) ? 1 : 0) | + ((pMode->flags & GFX_MODE_NEG_VSYNC) ? 2 : 0)); + + /* RESTORE VALUE OF MDC_UNLOCK */ + + WRITE_REG32(MDC_UNLOCK, unlock); + + /* RESET THE PITCH VALUES IN THE GP */ + + gfx_reset_pitch ((unsigned short)pitch); + + gfx_set_bpp ((unsigned short)bpp); + + return GFX_STATUS_OK; +} + + /*---------------------------------------------------------------------------- + * GFX_IS_DISPLAY_MODE_SUPPORTED + * + * This routine sets the specified display mode. + * + * Returns 1 if successful, 0 if mode could not be set. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_is_display_mode_supported(int xres, int yres, int bpp, int hz) +#else +int gfx_is_display_mode_supported(int xres, int yres, int bpp, int hz) +#endif +{ + unsigned int mode; + unsigned long hz_flag = 0, bpp_flag = 0; + + /* SET FLAGS TO MATCH REFRESH RATE */ + + if (hz == 56) hz_flag = GFX_MODE_56HZ; + if (hz == 60) hz_flag = GFX_MODE_60HZ; + if (hz == 70) hz_flag = GFX_MODE_70HZ; + if (hz == 72) hz_flag = GFX_MODE_72HZ; + if (hz == 75) hz_flag = GFX_MODE_75HZ; + if (hz == 85) hz_flag = GFX_MODE_85HZ; + if (hz == 90) hz_flag = GFX_MODE_90HZ; + if (hz == 100) hz_flag = GFX_MODE_100HZ; + + /* SET BPP FLAGS TO LIMIT MODE SELECTION */ + + switch (bpp) + { + case 8: bpp_flag = GFX_MODE_8BPP; break; + case 12: bpp_flag = GFX_MODE_12BPP; break; + case 15: bpp_flag = GFX_MODE_15BPP; break; + case 16: bpp_flag = GFX_MODE_16BPP; break; + case 32: bpp_flag = GFX_MODE_24BPP; break; + default: return (-1); + } + + /* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */ + + for (mode = 0; mode < NUM_RC_DISPLAY_MODES; mode++) + { + if ((DisplayParams[mode].hactive == (unsigned short)xres) && + (DisplayParams[mode].vactive == (unsigned short)yres) && + (DisplayParams[mode].flags & hz_flag) && + (DisplayParams[mode].flags & bpp_flag)) + { + + /* REDCLOUD DOES NOT SUPPORT EMULATED VGA MODES */ + + if ((DisplayParams[mode].flags & GFX_MODE_PIXEL_DOUBLE) || + (DisplayParams[mode].flags & GFX_MODE_LINE_DOUBLE)) + continue; + + /* SET THE DISPLAY CONTROLLER FOR THE SELECTED MODE */ + + return(mode); + } + } + return(-1); +} + +/*---------------------------------------------------------------------------- + * gfx_set_display_mode + * + * This routine sets the specified display mode. + * + * Returns 1 if successful, 0 if mode could not be set. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_set_display_mode(int xres, int yres, int bpp, int hz) +#else +int gfx_set_display_mode(int xres, int yres, int bpp, int hz) +#endif +{ + int mode; + + /* DISABLE FLAT PANEL */ + /* Flat Panel settings are enabled by the function gfx_set_fixed_timings */ + /* and disabled by gfx_set_display_mode. */ + + PanelEnable = 0; + + mode = gfx_is_display_mode_supported(xres, yres, bpp, hz); + if(mode >= 0) + { + if (gu2_set_specified_mode(&DisplayParams[mode], bpp) == GFX_STATUS_OK) + return(1); + } + return(0); +} + +/*---------------------------------------------------------------------------- + * GFX_SET_DISPLAY_TIMINGS + * + * This routine sets the display controller mode using the specified timing + * values (as opposed to using the tables internal to Durango). + * + * Returns GFX_STATUS_OK ON SUCCESS, GFX_STATUS_ERROR otherwise. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_set_display_timings(unsigned short bpp, unsigned short flags, + unsigned short hactive, unsigned short hblankstart, + unsigned short hsyncstart, unsigned short hsyncend, + unsigned short hblankend, unsigned short htotal, + unsigned short vactive, unsigned short vblankstart, + unsigned short vsyncstart, unsigned short vsyncend, + unsigned short vblankend, unsigned short vtotal, + unsigned long frequency) +#else +int gfx_set_display_timings(unsigned short bpp, unsigned short flags, + unsigned short hactive, unsigned short hblankstart, + unsigned short hsyncstart, unsigned short hsyncend, + unsigned short hblankend, unsigned short htotal, + unsigned short vactive, unsigned short vblankstart, + unsigned short vsyncstart, unsigned short vsyncend, + unsigned short vblankend, unsigned short vtotal, + unsigned long frequency) +#endif +{ + /* SET MODE STRUCTURE WITH SPECIFIED VALUES */ + + gfx_display_mode.flags = 0; + if (flags & 1) gfx_display_mode.flags |= GFX_MODE_NEG_HSYNC; + if (flags & 2) gfx_display_mode.flags |= GFX_MODE_NEG_VSYNC; + if (flags & 4) gfx_display_mode.flags |= GFX_MODE_EXCLUDE_PLL; + if (flags & 0x1000) gfx_display_mode.flags |= GFX_MODE_LOCK_TIMING; + gfx_display_mode.hactive = hactive; + gfx_display_mode.hblankstart = hblankstart; + gfx_display_mode.hsyncstart = hsyncstart; + gfx_display_mode.hsyncend = hsyncend; + gfx_display_mode.hblankend = hblankend; + gfx_display_mode.htotal = htotal; + gfx_display_mode.vactive = vactive; + gfx_display_mode.vblankstart = vblankstart; + gfx_display_mode.vsyncstart = vsyncstart; + gfx_display_mode.vsyncend = vsyncend; + gfx_display_mode.vblankend = vblankend; + gfx_display_mode.vtotal = vtotal; + gfx_display_mode.frequency = frequency; + + /* CALL ROUTINE TO SET MODE */ + + return (gu2_set_specified_mode(&gfx_display_mode, bpp)); +} + +/*---------------------------------------------------------------------------- + * GFX_SET_VTOTAL + * + * This routine sets the display controller vertical total to + * "vtotal". As a side effect it also sets vertical blank end. + * It should be used when only this value needs to be changed, + * due to speed considerations. + * + * Note: it is the caller's responsibility to make sure that + * a legal vtotal is used, i.e. that "vtotal" is greater than or + * equal to vsync end. + * + * Always returns 0. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_set_vtotal(unsigned short vtotal) +#else +int gfx_set_vtotal(unsigned short vtotal) +#endif +{ + unsigned long unlock, dcfg, vactive, vblank; + + /* UNLOCK THE DISPLAY CONTROLLER REGISTERS */ + + unlock = READ_REG32(MDC_UNLOCK); + WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE); + + /* READ THE CURRENT RC VALUES */ + + dcfg = READ_REG32 (MDC_DISPLAY_CFG); + vactive = READ_REG32 (MDC_V_ACTIVE_TIMING); + vblank = READ_REG32 (MDC_V_BLANK_TIMING); + + /* DISABLE TIMING REGISTER UPDATES */ + + WRITE_REG32 (MDC_DISPLAY_CFG, dcfg & ~(unsigned long)MDC_DCFG_TRUP); + + /* WRITE NEW TIMING VALUES */ + + WRITE_REG32 (MDC_V_ACTIVE_TIMING, (vactive & MDC_VAT_VA_MASK) | (unsigned long)(vtotal - 1) << 16); + WRITE_REG32 (MDC_V_BLANK_TIMING, (vblank & MDC_VBT_VBS_MASK) | (unsigned long)(vtotal - 1) << 16); + + /* RESTORE OLD RC VALUES */ + + WRITE_REG32 (MDC_DISPLAY_CFG, dcfg); + WRITE_REG32 (MDC_UNLOCK, unlock); + + return (0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_pitch + * + * This routine sets the pitch of the frame buffer to the specified value. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_display_pitch(unsigned short pitch) +#else +void gfx_set_display_pitch(unsigned short pitch) +#endif +{ + unsigned long value = 0; + unsigned long lock = READ_REG32(MDC_UNLOCK); + + value = READ_REG32(MDC_GFX_PITCH) & 0xFFFF0000; + value |= (pitch >> 3); + WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32(MDC_GFX_PITCH, value); + + /* SET RENDERING PITCHES TO MATCH */ + + gfx_reset_pitch(pitch); + + /* SET THE FRAME DIRTY MODE */ + /* Non-standard pitches, i.e. pitches that */ + /* are not 1K, 2K or 4K must mark the entire */ + /* frame as dirty when writing to the frame */ + /* buffer. */ + + value = READ_REG32 (MDC_GENERAL_CFG); + + if (pitch == 1024 || pitch == 2048 || pitch == 4096 || pitch == 8192) + value &= ~(unsigned long)(MDC_GCFG_FDTY); + else + value |= (unsigned long)(MDC_GCFG_FDTY); + + WRITE_REG32 (MDC_GENERAL_CFG, value); + WRITE_REG32(MDC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_offset + * + * This routine sets the start address of the frame buffer. It is + * typically used to pan across a virtual desktop (frame buffer larger than + * the displayed screen) or to flip the display between multiple buffers. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_display_offset(unsigned long offset) +#else +void gfx_set_display_offset(unsigned long offset) +#endif +{ + /* UPDATE FRAME BUFFER OFFSET */ + unsigned long lock; + lock = READ_REG32(MDC_UNLOCK); + WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE); + + + /* START ADDRESS EFFECTS DISPLAY COMPRESSION */ + /* Disable compression for non-zero start addresss values. */ + /* Enable compression if offset is zero and comression is intended to */ + /* be enabled from a previous call to "gfx_set_compression_enable". */ + /* Compression should be disabled BEFORE the offset is changed */ + /* and enabled AFTER the offset is changed. */ + + if (offset == 0) + { + WRITE_REG32(MDC_FB_ST_OFFSET, offset); + if (gfx_compression_enabled) + { + /* WAIT FOR THE OFFSET TO BE LATCHED */ + gfx_wait_vertical_blank (); + gu2_enable_compression(); + } + } + else + { + /* ONLY DISABLE COMPRESSION ONCE */ + + if (gfx_compression_active) + gu2_disable_compression(); + + WRITE_REG32(MDC_FB_ST_OFFSET, offset); + } + + WRITE_REG32(MDC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_palette_entry + * + * This routine sets an palette entry in the display controller. + * A 32-bit X:R:G:B value. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_set_display_palette_entry(unsigned long index, unsigned long palette) +#else +int gfx_set_display_palette_entry(unsigned long index, unsigned long palette) +#endif +{ + unsigned long dcfg, unlock; + + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + unlock = READ_REG32 (MDC_UNLOCK); + dcfg = READ_REG32 (MDC_DISPLAY_CFG); + + WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32 (MDC_DISPLAY_CFG, dcfg & ~MDC_DCFG_PALB); + WRITE_REG32 (MDC_UNLOCK, unlock); + + WRITE_REG32 (MDC_PAL_ADDRESS, index); + WRITE_REG32 (MDC_PAL_DATA, palette); + + return GFX_STATUS_OK; +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_palette + * + * This routine sets the entire palette in the display controller. + * A pointer is provided to a 256 entry table of 32-bit X:R:G:B values. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_set_display_palette(unsigned long *palette) +#else +int gfx_set_display_palette(unsigned long *palette) +#endif +{ + unsigned long unlock, dcfg, i; + WRITE_REG32 (MDC_PAL_ADDRESS, 0); + + if (palette) + { + unlock = READ_REG32 (MDC_UNLOCK); + dcfg = READ_REG32 (MDC_DISPLAY_CFG); + + WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32 (MDC_DISPLAY_CFG, dcfg & ~MDC_DCFG_PALB); + WRITE_REG32 (MDC_UNLOCK, unlock); + + for (i = 0; i < 256; i++) + WRITE_REG32 (MDC_PAL_DATA, palette[i]); + + return GFX_STATUS_OK; + } + return GFX_STATUS_BAD_PARAMETER; +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_enable + * + * This routine enables or disables the hardware cursor. + * + * WARNING: The cursor start offset must be set by setting the cursor + * position before calling this routine to assure that memory reads do not + * go past the end of graphics memory (this can hang GXm). + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_cursor_enable(int enable) +#else +void gfx_set_cursor_enable(int enable) +#endif +{ + unsigned long unlock, gcfg; + + /* SET OR CLEAR CURSOR ENABLE BIT */ + + unlock = READ_REG32(MDC_UNLOCK); + gcfg = READ_REG32(MDC_GENERAL_CFG); + if (enable) gcfg |= MDC_GCFG_CURE; + else gcfg &= ~(MDC_GCFG_CURE); + + /* WRITE NEW REGISTER VALUE */ + + WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32(MDC_GENERAL_CFG, gcfg); + WRITE_REG32(MDC_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_colors + * + * This routine sets the colors of the hardware cursor. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor) +#else +void gfx_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor) +#endif +{ + /* SET CURSOR COLORS */ + + WRITE_REG32(MDC_PAL_ADDRESS, 0x100); + WRITE_REG32(MDC_PAL_DATA, bkcolor); + WRITE_REG32(MDC_PAL_DATA, fgcolor); +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_position + * + * This routine sets the position of the hardware cusror. The starting + * offset of the cursor buffer must be specified so that the routine can + * properly clip scanlines if the cursor is off the top of the screen. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_cursor_position(unsigned long memoffset, + unsigned short xpos, unsigned short ypos, + unsigned short xhotspot, unsigned short yhotspot) +#else +void gfx_set_cursor_position(unsigned long memoffset, + unsigned short xpos, unsigned short ypos, + unsigned short xhotspot, unsigned short yhotspot) +#endif +{ + unsigned long unlock; + + short x = (short) xpos - (short) xhotspot; + short y = (short) ypos - (short) yhotspot; + short xoffset = 0; + short yoffset = 0; + if (x < -63) return; + if (y < -63) return; + + if (PanelEnable) + { + if (( ModeWidth > PanelWidth) || (ModeHeight > PanelHeight)) + { + gfx_enable_panning(xpos, ypos); + x = x - (unsigned short)panelLeft; + y = y - (unsigned short)panelTop; + } + } + + /* ADJUST OFFSETS */ + /* Cursor movement and panning work as follows: The cursor position */ + /* refers to where the hotspot of the cursor is located. However, for */ + /* non-zero hotspots, the cursor buffer actually begins before the */ + /* specified position. */ + + if (x < 0) { xoffset = -x; x = 0; } + if (y < 0) { yoffset = -y; y = 0; } + memoffset += (unsigned long) yoffset << 4; + + /* SET CURSOR POSITION */ + + unlock = READ_REG32(MDC_UNLOCK); + WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32(MDC_CURS_ST_OFFSET, memoffset); + WRITE_REG32(MDC_CURSOR_X, (unsigned long) x | + (((unsigned long) xoffset) << 11)); + WRITE_REG32(MDC_CURSOR_Y, (unsigned long) y | + (((unsigned long) yoffset) << 11)); + WRITE_REG32(MDC_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_shape32 + * + * This routine loads 32x32 cursor data into the cursor buffer in graphics memory. + * As the Redcloud cursor is actually 64x64, we must pad the outside of the + * cursor data with transparent pixels. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_cursor_shape32(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +#else +void gfx_set_cursor_shape32(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +#endif +{ + int i; + + for (i = 0; i < 32; i++) + { + /* EVEN QWORDS CONTAIN THE AND MASK */ + + WRITE_FB32 (memoffset, 0xFFFFFFFF); + WRITE_FB32 (memoffset + 4, andmask[i]); + + /* ODD QWORDS CONTAIN THE XOR MASK */ + + WRITE_FB32 (memoffset + 8, 0x00000000); + WRITE_FB32 (memoffset + 12, xormask[i]); + + memoffset += 16; + } + + /* FILL THE LOWER HALF OF THE BUFFER WITH TRANSPARENT PIXELS */ + + for (i = 0; i < 32; i++) + { + WRITE_FB32 (memoffset, 0xFFFFFFFF); + WRITE_FB32 (memoffset + 4, 0xFFFFFFFF); + WRITE_FB32 (memoffset + 8, 0x00000000); + WRITE_FB32 (memoffset + 12, 0x00000000); + + memoffset += 16; + } +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_shape64 + * + * This routine loads 64x64 cursor data into the cursor buffer in graphics memory. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_cursor_shape64(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +#else +void gfx_set_cursor_shape64(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +#endif +{ + int i; + + for (i = 0; i < 128; i += 2) + { + /* EVEN QWORDS CONTAIN THE AND MASK */ + /* We invert the dwords to prevent the calling */ + /* application from having to think in terms of Qwords. */ + /* The hardware data order is actually 63:0, or 31:0 of */ + /* the second dword followed by 31:0 of the first dword. */ + + WRITE_FB32 (memoffset, andmask[i + 1]); + WRITE_FB32 (memoffset + 4, andmask[i]); + + /* ODD QWORDS CONTAIN THE XOR MASK */ + + WRITE_FB32 (memoffset + 8, xormask[i + 1]); + WRITE_FB32 (memoffset + 12, xormask[i]); + + memoffset += 16; + } +} + +/*--------------------------------------------------------------------------- + * gfx_set_icon_enable + * + * This routine enables or disables the hardware icon. The icon position + * and colors should be programmed prior to calling this routine for the + * first time. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_icon_enable(int enable) +#else +void gfx_set_icon_enable(int enable) +#endif +{ + unsigned long unlock, gcfg; + + /* SET OR CLEAR ICON ENABLE BIT */ + + unlock = READ_REG32(MDC_UNLOCK); + gcfg = READ_REG32(MDC_GENERAL_CFG); + if (enable) gcfg |= MDC_GCFG_ICNE; + else gcfg &= ~(MDC_GCFG_ICNE); + + /* WRITE NEW REGISTER VALUE */ + + WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32(MDC_GENERAL_CFG, gcfg); + WRITE_REG32(MDC_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_icon_colors + * + * This routine sets the three icon colors. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_icon_colors(unsigned long color0, unsigned long color1, unsigned long color2) +#else +void gfx_set_icon_colors(unsigned long color0, unsigned long color1, unsigned long color2) +#endif +{ + /* ICON COLORS LOCATED AT PALETTE INDEXES 102-104h */ + + WRITE_REG32 (MDC_PAL_ADDRESS, 0x102); + + WRITE_REG32 (MDC_PAL_DATA, color0); + WRITE_REG32 (MDC_PAL_DATA, color1); + WRITE_REG32 (MDC_PAL_DATA, color2); +} + +/*--------------------------------------------------------------------------- + * gfx_set_icon_position + * + * This routine sets the starting X coordinate for the hardware icon and the + * memory offset for the icon buffer. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_icon_position(unsigned long memoffset, unsigned short xpos) +#else +void gfx_set_icon_position(unsigned long memoffset, unsigned short xpos) +#endif +{ + unsigned long lock = READ_REG32 (MDC_UNLOCK); + + WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE); + + /* PROGRAM THE MEMORY OFFSET */ + + WRITE_REG32 (MDC_ICON_ST_OFFSET, memoffset & 0x0FFFFFFF); + + /* PROGRAM THE XCOORDINATE */ + + WRITE_REG32 (MDC_ICON_X, (unsigned long)(xpos & 0x07FF)); + + WRITE_REG32 (MDC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_icon_shape64 + * + * This routine initializes the icon buffer according to the current mode. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_icon_shape64(unsigned long memoffset, unsigned long *andmask, unsigned long *xormask, unsigned int lines) +#else +void gfx_set_icon_shape64(unsigned long memoffset, unsigned long *andmask, unsigned long *xormask, unsigned int lines) +#endif +{ + unsigned short i, height; + + height = lines << 1; + + for (i = 0; i < height; i += 2) + { + /* EVEN QWORDS CONTAIN THE AND MASK */ + /* Swap dwords to hide qword constraint */ + + WRITE_FB32 (memoffset, andmask[i + 1]); + WRITE_FB32 (memoffset + 4, andmask[i]); + + /* ODD QWORDS CONTAIN THE XOR MASK */ + + WRITE_FB32 (memoffset + 8, xormask[i + 1]); + WRITE_FB32 (memoffset + 12, xormask[i]); + + memoffset += 16; + } +} + +/*--------------------------------------------------------------------------- + * gu2_enable_compression + * + * This is a private routine to this module (not exposed in the Durango API). + * It enables display compression. + *--------------------------------------------------------------------------- + */ +void gu2_enable_compression(void) +{ + unsigned long unlock, gcfg, temp; + + /* DO NOT ENABLE IF START ADDRESS IS NOT ZERO */ + + if (READ_REG32(MDC_FB_ST_OFFSET) & 0x0FFFFFFF) + return; + + /* SET GLOBAL INDICATOR */ + + gfx_compression_active = 1; + + /* CLEAR DIRTY/VALID BITS IN MEMORY CONTROLLER */ + /* Software is required to do this before enabling compression. */ + /* Don't want controller to think that old lines are still valid. */ + /* Writing a 1 to bit 0 of the DV Control register will force the */ + /* hardware to clear all the valid bits. */ + + temp = READ_REG32 (MDC_DV_CTL); + WRITE_REG32 (MDC_DV_CTL, temp | 0x00000001); + + /* TURN ON COMPRESSION CONTROL BITS */ + + unlock = READ_REG32 (MDC_UNLOCK); + gcfg = READ_REG32 (MDC_GENERAL_CFG); + gcfg |= MDC_GCFG_CMPE | MDC_GCFG_DECE; + WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32 (MDC_GENERAL_CFG, gcfg); + WRITE_REG32 (MDC_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gu2_disable_compression + * + * This is a private routine to this module (not exposed in the Durango API). + * It disables display compression. + *--------------------------------------------------------------------------- + */ +void gu2_disable_compression(void) +{ + unsigned long unlock, gcfg; + + /* SET GLOBAL INDICATOR */ + + gfx_compression_active = 0; + + /* TURN OFF COMPRESSION CONTROL BITS */ + + unlock = READ_REG32(MDC_UNLOCK); + gcfg = READ_REG32(MDC_GENERAL_CFG); + gcfg &= ~(MDC_GCFG_CMPE | MDC_GCFG_DECE); + WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32 (MDC_GENERAL_CFG, gcfg); + WRITE_REG32 (MDC_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_enable + * + * This routine enables or disables display compression. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_set_compression_enable(int enable) +#else +int gfx_set_compression_enable(int enable) +#endif +{ + /* SET GLOBAL VARIABLE FOR INDENDED STATE */ + /* Compression can only be enabled for non-zero start address values. */ + /* Keep state to enable compression on start address changes. */ + + gfx_compression_enabled = enable; + if (enable) gu2_enable_compression(); + else gu2_disable_compression(); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_offset + * + * This routine sets the base offset for the compression buffer. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_set_compression_offset(unsigned long offset) +#else +int gfx_set_compression_offset(unsigned long offset) +#endif +{ + unsigned long lock; + + /* MUST BE 16-BYTE ALIGNED FOR REDCLOUD */ + + if (offset & 0x0F) return(1); + + /* SET REGISTER VALUE */ + + lock = READ_REG32(MDC_UNLOCK); + WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32(MDC_CB_ST_OFFSET, offset & 0x0FFFFFFF); + WRITE_REG32(MDC_UNLOCK, lock); + + return (0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_pitch + * + * This routine sets the pitch, in bytes, of the compression buffer. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_set_compression_pitch(unsigned short pitch) +#else +int gfx_set_compression_pitch(unsigned short pitch) +#endif +{ + unsigned long lock, line_delta; + + lock = READ_REG32(MDC_UNLOCK); + + /* SET REGISTER VALUE */ + + line_delta = READ_REG32(MDC_GFX_PITCH) & 0x0000FFFF; + line_delta |= (((unsigned long)pitch << 13) & 0xFFFF0000); + WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32(MDC_GFX_PITCH, line_delta); + WRITE_REG32(MDC_UNLOCK, lock); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_size + * + * This routine sets the line size of the compression buffer, which is the + * maximum number of bytes allowed to store a compressed line. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_set_compression_size(unsigned short size) +#else +int gfx_set_compression_size(unsigned short size) +#endif +{ + unsigned long lock, buf_size; + + /* SUBTRACT 32 FROM SIZE */ + /* The display controller will actually write */ + /* 4 extra QWords. So, if we assume that "size" */ + /* refers to the allocated size, we must subtract */ + /* 32 bytes. */ + + size -= 32; + + /* SET REGISTER VALUE */ + + lock = READ_REG32(MDC_UNLOCK); + buf_size = READ_REG32(MDC_LINE_SIZE) & 0xFF80FFFF; + buf_size |= ((((unsigned long)size >> 3) + 1) & 0x7F) << 16; + WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32(MDC_LINE_SIZE, buf_size); + WRITE_REG32(MDC_UNLOCK, lock); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_format (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_format". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_display_video_format(unsigned long format) +#else +void gfx_set_display_video_format(unsigned long format) +#endif +{ + unsigned long gcfg, lock; + + lock = READ_REG32 (MDC_UNLOCK); + gcfg = READ_REG32 (MDC_GENERAL_CFG); + + switch (format) + { + case VIDEO_FORMAT_Y0Y1Y2Y3: + case VIDEO_FORMAT_Y3Y2Y1Y0: + case VIDEO_FORMAT_Y1Y0Y3Y2: + case VIDEO_FORMAT_Y1Y2Y3Y0: + + gcfg |= MDC_GCFG_YUVM; + break; + + default: + + gcfg &= ~MDC_GCFG_YUVM; + break; + } + + WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32 (MDC_GENERAL_CFG, gcfg); + WRITE_REG32 (MDC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_enable (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_enable". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_display_video_enable(int enable) +#else +void gfx_set_display_video_enable(int enable) +#endif +{ + unsigned long lock, gcfg, dcfg; + + /* READ CURRENT VALUES */ + + lock = READ_REG32 (MDC_UNLOCK); + gcfg = READ_REG32 (MDC_GENERAL_CFG); + dcfg = READ_REG32 (MDC_DISPLAY_CFG); + + /* SET OR CLEAR VIDEO ENABLE IN GENERAL_CFG */ + + if (enable) gcfg |= MDC_GCFG_VIDE; + else gcfg &= ~MDC_GCFG_VIDE; + + /* WRITE REGISTER */ + + WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32 (MDC_GENERAL_CFG, gcfg); + WRITE_REG32 (MDC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_size (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_size". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_display_video_size(unsigned short width, unsigned short height) +#else +void gfx_set_display_video_size(unsigned short width, unsigned short height) +#endif +{ + unsigned long lock, value, yuv_420; + + /* READ CURRENT VALUES */ + + lock = READ_REG32 (MDC_UNLOCK); + value = READ_REG32 (MDC_LINE_SIZE) & 0x00FFFFFF; + yuv_420 = READ_REG32 (MDC_GENERAL_CFG) & MDC_GCFG_YUVM; + + /* LINE WIDTH IS 1/4 FOR 4:2:0 VIDEO */ + /* All data must be 32-byte aligned. */ + + if (yuv_420) + { + width >>= 1; + width = (width + 7) & 0xFFF8; + } + else + { + width <<= 1; + width = (width + 31) & 0xFFE0; + } + + /* ONLY THE LINE SIZE IS PROGRAMMED IN THE DISPLAY CONTROLLER */ + + value |= ((unsigned long)width << 21); + + /* WRITE THE REGISTER */ + + WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32 (MDC_LINE_SIZE, value); + WRITE_REG32 (MDC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_offset (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_offset". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_display_video_offset(unsigned long offset) +#else +void gfx_set_display_video_offset(unsigned long offset) +#endif +{ + unsigned long lock; + + lock = READ_REG32(MDC_UNLOCK); + WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE); + offset &= 0x0FFFFFF0; + WRITE_REG32(MDC_VID_Y_ST_OFFSET, offset); + WRITE_REG32(MDC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_yuv_offsets (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by gfx_set_video_yuv_offsets. It abstracts the version + * of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_display_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, + unsigned long voffset) +#else +void gfx_set_display_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, + unsigned long voffset) +#endif +{ + unsigned long lock; + + lock = READ_REG32(MDC_UNLOCK); + + yoffset &= 0x0FFFFFF0; + uoffset &= 0x0FFFFFF8; + voffset &= 0x0FFFFFF8; + + WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32(MDC_VID_Y_ST_OFFSET, yoffset); + WRITE_REG32(MDC_VID_U_ST_OFFSET, uoffset); + WRITE_REG32(MDC_VID_V_ST_OFFSET, voffset); + WRITE_REG32(MDC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_yuv_pitch (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by gfx_set_video_yuv_pitch. It abstracts the version + * of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_display_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch) +#else +void gfx_set_display_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch) +#endif +{ + unsigned long lock, pitch; + + lock = READ_REG32(MDC_UNLOCK); + + pitch = ((uvpitch << 13) & 0xFFFF0000) | ((ypitch >> 3) & 0xFFFF); + + WRITE_REG32(MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32(MDC_VID_YUV_PITCH, pitch); + WRITE_REG32(MDC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_downscale (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by gfx_set_video_vertical_downscale. It abstracts the version + * of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_display_video_downscale (unsigned short srch, unsigned short dsth) +#else +void gfx_set_display_video_downscale (unsigned short srch, unsigned short dsth) +#endif +{ + unsigned long lock, delta; + + lock = READ_REG32 (MDC_UNLOCK); + + /* CLIP SCALING LIMITS */ + /* Upscaling is performed in a separate function. */ + /* Maximum scale ratio is 1/2. */ + + if (dsth > srch || dsth <= (srch >> 1)) + delta = 0; + else + delta = (((unsigned long)srch << 14) / (unsigned long)dsth) << 18; + + WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32 (MDC_VID_DS_DELTA, delta); + WRITE_REG32 (MDC_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_downscale_enable (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_vertical_downscale_enable". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_set_display_video_vertical_downscale_enable(int enable) +#else +void gfx_set_display_video_vertical_downscale_enable(int enable) +#endif +{ + unsigned long gcfg, unlock; + + unlock = READ_REG32 (MDC_UNLOCK); + gcfg = READ_REG32 (MDC_GENERAL_CFG); + + if (enable) gcfg |= MDC_GCFG_VDSE; + else gcfg &= ~MDC_GCFG_VDSE; + + WRITE_REG32 (MDC_UNLOCK, MDC_UNLOCK_VALUE); + WRITE_REG32 (MDC_GENERAL_CFG, gcfg); + WRITE_REG32 (MDC_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gfx_test_timing_active + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_test_timing_active(void) +#else +int gfx_test_timing_active(void) +#endif +{ + if (READ_REG32 (MDC_DISPLAY_CFG) & MDC_DCFG_TGEN) + return(1); + else return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_test_vertical_active + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_test_vertical_active(void) +#else +int gfx_test_vertical_active(void) +#endif +{ + if (READ_REG32 (MDC_LINE_CNT_STATUS) & MDC_LNCNT_VNA) + return(0); + + return(1); +} + +/*--------------------------------------------------------------------------- + * gfx_wait_vertical_blank + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_wait_vertical_blank(void) +#else +int gfx_wait_vertical_blank(void) +#endif +{ + if (gfx_test_timing_active()) + { + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_enable_panning + * + * This routine enables the panning when the Mode is bigger than the panel + * size. + *--------------------------------------------------------------------------- + */ + +#if GFX_DISPLAY_DYNAMIC +void gu2_enable_panning(int x, int y) +#else +void gfx_enable_panning(int x, int y) +#endif +{ + unsigned long modeBytesPerPixel; + unsigned long modeBytesPerScanline = 0; + unsigned long startAddress = 0; + + modeBytesPerPixel = (gbpp + 7)/8; + modeBytesPerScanline = (READ_REG32 (MDC_GFX_PITCH) & 0x0000FFFF) << 3; + + /* TEST FOR NO-WORK */ + + if (x >= DeltaX && x < ((int)PanelWidth + DeltaX) && + y >= DeltaY && y < ((int)PanelHeight + DeltaY)) + return; + + /* ADJUST PANNING VARIABLES WHEN CURSOR EXCEEDS BOUNDARY */ + /* Test the boundary conditions for each coordinate and update */ + /* all variables and the starting offset accordingly. */ + + if (x < DeltaX) + DeltaX = x; + + else if (x >= (DeltaX + (int)PanelWidth)) + DeltaX = x - (int)PanelWidth + 1; + + if (y < DeltaY) + DeltaY = y; + + else if (y >= (DeltaY + (int)PanelHeight)) + DeltaY = y - (int)PanelHeight + 1; + + /* CALCULATE THE START OFFSET */ + + startAddress = (DeltaX * modeBytesPerPixel) + (DeltaY * modeBytesPerScanline); + + gfx_set_display_offset(startAddress); + + /* SET PANEL COORDINATES */ + /* Panel's x position must be DWORD aligned */ + + panelTop = DeltaY; + panelLeft = DeltaX * modeBytesPerPixel; + + if (panelLeft & 3) + panelLeft = (panelLeft & 0xFFFFFFFC) + 4; + + panelLeft /= modeBytesPerPixel; +} + +/*--------------------------------------------------------------------------- + * gfx_is_panel_mode_supported + *--------------------------------------------------------------------------- + */ + +#if GFX_DISPLAY_DYNAMIC +int gu2_is_panel_mode_supported(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#else +int gfx_is_panel_mode_supported(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#endif +{ + unsigned int mode; + + /* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */ + for (mode = 0; mode < NUM_FIXED_TIMINGS_MODES; mode++) + { + if ((FixedParams[mode].xres == width) && + (FixedParams[mode].yres == height) && + (FixedParams[mode].panelresx == panelResX) && + (FixedParams[mode].panelresy == panelResY)) + { + return ((int)mode); + } + } + + return -1; +} + +/*--------------------------------------------------------------------------- + * gfx_set_fixed_timings + *--------------------------------------------------------------------------- + */ + +#if GFX_DISPLAY_DYNAMIC +int gu2_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#else +int gfx_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#endif +{ + unsigned int mode; + + ModeWidth = width; + ModeHeight = height; + PanelWidth = (unsigned short)panelResX; + PanelHeight = (unsigned short)panelResY; + PanelEnable = 1; + + /* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */ + for (mode = 0; mode < NUM_FIXED_TIMINGS_MODES; mode++) { + if ((FixedParams[mode].xres == width) && + (FixedParams[mode].yres == height) && + (FixedParams[mode].panelresx == panelResX) && + (FixedParams[mode].panelresy == panelResY)) { + + /* SET THE 92xx FOR THE SELECTED MODE */ + FIXEDTIMINGS *fmode = &FixedParams[mode]; + + gfx_set_display_timings(bpp, 3, fmode->hactive,fmode->hblankstart, fmode->hsyncstart, fmode->hsyncend, + fmode->hblankend, fmode->htotal, fmode->vactive, fmode->vblankstart, + fmode->vsyncstart, fmode->vsyncend, fmode->vblankend, fmode->vtotal, fmode->frequency); + + return(1); + } /* end if() */ + } /* end for() */ + + return(-1); +} + +/*--------------------------------------------------------------------------- + * gfx_set_panel_present + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#else +int gfx_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#endif +{ + /* SET VALID BPP */ + /* 16BPP is the default. */ + + if (bpp != 8 && bpp != 12 && bpp != 15 && bpp != 16 && bpp != 32) + bpp = 16; + + /* RECORD PANEL PARAMETERS */ + /* This routine does not touch any panel timings. It is used when custom panel */ + /* settings are set up in advance by the BIOS or an application, but the */ + /* application still requires access to other panel functionality provided by */ + /* Durango (i.e. panning). */ + + ModeWidth = width; + ModeHeight = height; + PanelWidth = (unsigned short)panelResX; + PanelHeight = (unsigned short)panelResY; + PanelEnable = 1; + gbpp = bpp; + + /* PROGRAM THE BPP IN THE DISPLAY CONTROLLER */ + + gfx_set_display_bpp (bpp); + + return(GFX_STATUS_OK); +} + +/* THE FOLLOWING READ ROUTINES ARE ALWAYS INCLUDED: */ + +/*--------------------------------------------------------------------------- + * gfx_get_display_pitch + * + * This routine returns the current pitch of the frame buffer, in bytes. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_display_pitch(void) +#else +unsigned short gfx_get_display_pitch(void) +#endif +{ + return ((unsigned short)(READ_REG32 (MDC_GFX_PITCH) & 0x0000FFFF) << 3); +} + +/*---------------------------------------------------------------------------- + * gfx_mode_frequency_supported + * + * This routine examines if the requested mode with pixel frequency is supported. + * + * Returns >0 if successful , <0 if freq. could not be found and matched. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency) +#else +int gfx_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency) +#endif +{ + unsigned int index; + unsigned long value; + unsigned long bpp_flag = 0; + + switch (bpp) + { + case 8: bpp_flag = GFX_MODE_8BPP; break; + case 12: bpp_flag = GFX_MODE_12BPP; break; + case 15: bpp_flag = GFX_MODE_15BPP; break; + case 16: bpp_flag = GFX_MODE_16BPP; break; + case 32: bpp_flag = GFX_MODE_24BPP; break; + default: bpp_flag = GFX_MODE_8BPP; break; + } + + for (index = 0; index < NUM_RC_DISPLAY_MODES; index++) + { + if ((DisplayParams[index].hactive == (unsigned int)xres) && + (DisplayParams[index].vactive == (unsigned int)yres) && + (DisplayParams[index].flags & bpp_flag) && + (DisplayParams[index].frequency == frequency)) + { + int hz=0; + value = DisplayParams[index].flags; + + if (value & GFX_MODE_56HZ) hz = 56; + else if (value & GFX_MODE_60HZ) hz = 60; + else if (value & GFX_MODE_70HZ) hz = 70; + else if (value & GFX_MODE_72HZ) hz = 72; + else if (value & GFX_MODE_75HZ) hz = 75; + else if (value & GFX_MODE_85HZ) hz = 85; + else if (value & GFX_MODE_90HZ) hz = 90; + else if (value & GFX_MODE_100HZ) hz = 100; + return(hz); + } + } + + return(-1); +} + +/*---------------------------------------------------------------------------- + * gfx_refreshrate_from_frequency + * + * This routine maps the frequency to close match refresh rate + * + * Returns . + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency) +#else +int gfx_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency) +#endif +{ + unsigned int index, closematch=0; + unsigned long value; + unsigned long bpp_flag = 0; + long min, diff; + + *hz = 60; + + switch (bpp) + { + case 8: bpp_flag = GFX_MODE_8BPP; break; + case 12: bpp_flag = GFX_MODE_12BPP; break; + case 15: bpp_flag = GFX_MODE_15BPP; break; + case 16: bpp_flag = GFX_MODE_16BPP; break; + case 32: bpp_flag = GFX_MODE_24BPP; break; + default: bpp_flag = GFX_MODE_8BPP; break; + } + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + + min = 0x7fffffff; + for (index = 0; index < NUM_RC_DISPLAY_MODES; index++) + { + if ((DisplayParams[index].htotal == (unsigned int)xres) && + (DisplayParams[index].vtotal == (unsigned int)yres) && + (DisplayParams[index].flags & bpp_flag)) + { + diff = (long)frequency - (long)DisplayParams[index].frequency; + if(diff < 0) diff = -diff; + + if (diff < min) + { + min = diff; + closematch = index; + } + } + } + + value = DisplayParams[closematch].flags; + + if (value & GFX_MODE_56HZ) *hz = 56; + else if (value & GFX_MODE_60HZ) *hz = 60; + else if (value & GFX_MODE_70HZ) *hz = 70; + else if (value & GFX_MODE_72HZ) *hz = 72; + else if (value & GFX_MODE_75HZ) *hz = 75; + else if (value & GFX_MODE_85HZ) *hz = 85; + else if (value & GFX_MODE_90HZ) *hz = 90; + else if (value & GFX_MODE_100HZ) *hz = 100; + + return(1); +} + +/*---------------------------------------------------------------------------- + * gfx_refreshrate_from_mode + * + * This routine is identical to the gfx_get_refreshrate_from_frequency, + * except that the active timing values are compared instead of the total + * values. Some modes (such as 70Hz and 72Hz) may be confused in this routine. + * + * Returns . + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency) +#else +int gfx_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency) +#endif +{ + unsigned int index, closematch=0; + unsigned long value; + unsigned long bpp_flag = 0; + long min, diff; + + *hz = 60; + + switch (bpp) + { + case 8: bpp_flag = GFX_MODE_8BPP; break; + case 12: bpp_flag = GFX_MODE_12BPP; break; + case 15: bpp_flag = GFX_MODE_15BPP; break; + case 16: bpp_flag = GFX_MODE_16BPP; break; + case 32: bpp_flag = GFX_MODE_24BPP; break; + default: bpp_flag = GFX_MODE_8BPP; break; + } + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + + min = 0x7fffffff; + for (index = 0; index < NUM_RC_DISPLAY_MODES; index++) + { + if ((DisplayParams[index].hactive == (unsigned int)xres) && + (DisplayParams[index].vactive == (unsigned int)yres) && + (DisplayParams[index].flags & bpp_flag)) + { + diff = (long)frequency - (long)DisplayParams[index].frequency; + if(diff < 0) diff = -diff; + + if (diff < min) + { + min = diff; + closematch = index; + } + } + } + + value = DisplayParams[closematch].flags; + + if (value & GFX_MODE_56HZ) *hz = 56; + else if (value & GFX_MODE_60HZ) *hz = 60; + else if (value & GFX_MODE_70HZ) *hz = 70; + else if (value & GFX_MODE_72HZ) *hz = 72; + else if (value & GFX_MODE_75HZ) *hz = 75; + else if (value & GFX_MODE_85HZ) *hz = 85; + else if (value & GFX_MODE_90HZ) *hz = 90; + else if (value & GFX_MODE_100HZ) *hz = 100; + + return(1); +} + +/*---------------------------------------------------------------------------- + * gfx_get_frequency_from_refreshrate + * + * This routine maps the refresh rate to the closest matching PLL frequency. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency) +#else +int gfx_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency) +#endif +{ + unsigned int index; + int retval = -1; + unsigned long hz_flag = 0; + unsigned long bpp_flag = 0; + + *frequency = 0; + + if (hz == 56) hz_flag = GFX_MODE_56HZ; + if (hz == 60) hz_flag = GFX_MODE_60HZ; + else if (hz == 70) hz_flag = GFX_MODE_70HZ; + else if (hz == 72) hz_flag = GFX_MODE_72HZ; + else if (hz == 75) hz_flag = GFX_MODE_75HZ; + else if (hz == 85) hz_flag = GFX_MODE_85HZ; + else if (hz == 90) hz_flag = GFX_MODE_90HZ; + else if (hz == 100) hz_flag = GFX_MODE_100HZ; + + switch (bpp) + { + case 8: bpp_flag = GFX_MODE_8BPP; break; + case 12: bpp_flag = GFX_MODE_12BPP; break; + case 15: bpp_flag = GFX_MODE_15BPP; break; + case 16: bpp_flag = GFX_MODE_16BPP; break; + case 32: bpp_flag = GFX_MODE_24BPP; break; + default: bpp_flag = GFX_MODE_8BPP; break; + } + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + + for (index = 0; index < NUM_RC_DISPLAY_MODES; index++) + { + if ((DisplayParams[index].hactive == (unsigned short)xres) && + (DisplayParams[index].vactive == (unsigned short)yres) && + (DisplayParams[index].flags & bpp_flag) && + (DisplayParams[index].flags & hz_flag)) + { + *frequency = DisplayParams[index].frequency; + retval = 1; + } + } + return retval; +} + + +/*--------------------------------------------------------------------------- + * gfx_get_max_supported_pixel_clock + * + * This routine returns the maximum recommended speed for the pixel clock. The + * return value is an integer of the format xxxyyy, where xxx.yyy is the maximum + * floating point pixel clock speed. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_max_supported_pixel_clock (void) +#else +unsigned long gfx_get_max_supported_pixel_clock (void) +#endif + +{ + return 229500; +} + +/*---------------------------------------------------------------------------- + * gfx_get_display_mode + * + * This routine gets the specified display mode. + * + * Returns >0 if successful and mode returned, <0 if mode could not be found. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_get_display_mode(int *xres, int *yres, int *bpp, int *hz) +#else +int gfx_get_display_mode(int *xres, int *yres, int *bpp, int *hz) +#endif +{ + unsigned int mode=0; + unsigned long pll_freq = 0, bpp_flag = 0; + + *xres = gfx_get_hactive(); + *yres = gfx_get_vactive(); + *bpp = gfx_get_display_bpp(); + pll_freq = gfx_get_clock_frequency(); + + /* SET BPP FLAGS TO LIMIT MODE SELECTION */ + + switch (*bpp) + { + case 8: bpp_flag = GFX_MODE_8BPP; break; + case 12: bpp_flag = GFX_MODE_12BPP; break; + case 15: bpp_flag = GFX_MODE_15BPP; break; + case 16: bpp_flag = GFX_MODE_16BPP; break; + case 32: bpp_flag = GFX_MODE_24BPP; break; + default: bpp_flag = GFX_MODE_8BPP; break; + } + + for (mode = 0; mode < NUM_RC_DISPLAY_MODES; mode++) { + if ((DisplayParams[mode].hactive == (unsigned int)*xres) && + (DisplayParams[mode].vactive == (unsigned int)*yres) && + (DisplayParams[mode].frequency == pll_freq) && + (DisplayParams[mode].flags & bpp_flag)) { + + pll_freq = DisplayParams[mode].flags; + + if (pll_freq & GFX_MODE_56HZ) *hz = 56; + else if (pll_freq & GFX_MODE_60HZ) *hz = 60; + else if (pll_freq & GFX_MODE_70HZ) *hz = 70; + else if (pll_freq & GFX_MODE_72HZ) *hz = 72; + else if (pll_freq & GFX_MODE_75HZ) *hz = 75; + else if (pll_freq & GFX_MODE_85HZ) *hz = 85; + else if (pll_freq & GFX_MODE_90HZ) *hz = 90; + else if (pll_freq & GFX_MODE_100HZ) *hz = 100; + + return(1); + } + } + return(-1); +} + +/*---------------------------------------------------------------------------- + * GFX_GET_DISPLAY_DETAILS + * + * This routine gets the specified display mode. + * + * Returns 1 if successful, 0 if mode could not be get. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_get_display_details(unsigned int mode, int *xres, int *yres, int *hz) +#else +int gfx_get_display_details(unsigned int mode, int *xres, int *yres, int *hz) +#endif +{ + if(mode < NUM_RC_DISPLAY_MODES) + { + if(DisplayParams[mode].flags & GFX_MODE_56HZ) + *hz = 56; + else if(DisplayParams[mode].flags & GFX_MODE_60HZ) + *hz = 60; + else if(DisplayParams[mode].flags & GFX_MODE_70HZ) + *hz = 70; + else if(DisplayParams[mode].flags & GFX_MODE_72HZ) + *hz = 72; + else if(DisplayParams[mode].flags & GFX_MODE_75HZ) + *hz = 75; + else if(DisplayParams[mode].flags & GFX_MODE_85HZ) + *hz = 85; + else if(DisplayParams[mode].flags & GFX_MODE_90HZ) + *hz = 90; + else if(DisplayParams[mode].flags & GFX_MODE_100HZ) + *hz = 100; + + *xres = DisplayParams[mode].hactive; + *yres = DisplayParams[mode].vactive; + + if (DisplayParams[mode].flags & GFX_MODE_PIXEL_DOUBLE) + *xres >>= 1; + if (DisplayParams[mode].flags & GFX_MODE_LINE_DOUBLE) + *yres >>= 1; + + return(1); + } + return(0); +} + +/*---------------------------------------------------------------------------- + * GFX_GET_DISPLAY_MODE_COUNT + * + * This routine gets the number of available display modes. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_get_display_mode_count(void) +#else +int gfx_get_display_mode_count(void) +#endif +{ + return(NUM_RC_DISPLAY_MODES); +} + +/*---------------------------------------------------------------------------- + * gfx_get_frame_buffer_line_size + * + * Returns the current frame buffer line size, in bytes + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_frame_buffer_line_size(void) +#else +unsigned long gfx_get_frame_buffer_line_size(void) +#endif +{ + return ((READ_REG32 (MDC_LINE_SIZE) & 0x7FF) << 3); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hactive + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_hactive(void) +#else +unsigned short gfx_get_hactive(void) +#endif +{ + return((unsigned short)((READ_REG32(MDC_H_ACTIVE_TIMING) & 0x0FF8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hsync_start + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_hsync_start(void) +#else +unsigned short gfx_get_hsync_start(void) +#endif +{ + return ((unsigned short)((READ_REG32(MDC_H_SYNC_TIMING) & 0x0FF8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hsync_end + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_hsync_end(void) +#else +unsigned short gfx_get_hsync_end(void) +#endif +{ + return((unsigned short)(((READ_REG32(MDC_H_SYNC_TIMING) >> 16) & 0x0FF8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_htotal + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_htotal(void) +#else +unsigned short gfx_get_htotal(void) +#endif +{ + return((unsigned short)(((READ_REG32(MDC_H_ACTIVE_TIMING) >> 16) & 0x0FF8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vactive + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_vactive(void) +#else +unsigned short gfx_get_vactive(void) +#endif +{ + return((unsigned short)((READ_REG32(MDC_V_ACTIVE_TIMING) & 0x07FF) + 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vsync_end + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_vsync_end(void) +#else +unsigned short gfx_get_vsync_end(void) +#endif +{ + return((unsigned short)(((READ_REG32(MDC_V_SYNC_TIMING) >> 16) & 0x07FF) + 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vtotal + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_vtotal(void) +#else +unsigned short gfx_get_vtotal(void) +#endif +{ + return((unsigned short)(((READ_REG32(MDC_V_ACTIVE_TIMING) >> 16) & 0x07FF) + 1)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_bpp + * + * This routine returns the current color depth of the active display. + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_display_bpp(void) +#else +unsigned short gfx_get_display_bpp(void) +#endif +{ + unsigned long dcfg = READ_REG32 (MDC_DISPLAY_CFG); + + switch ((dcfg & MDC_DCFG_DISP_MODE_MASK) >> 8) + { + case 0: return (8); + case 2: return (32); + + case 1: + + switch ((dcfg & MDC_DCFG_16BPP_MODE_MASK) >> 10) + { + case 0: return (16); + case 1: return (15); + case 2: return (12); + default: return (0); + } + } + + /* INVALID SETTING */ + + return (0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vline + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_vline(void) +#else +unsigned short gfx_get_vline(void) +#endif +{ + unsigned short current_scan_line; + + /* Read similar value twice to ensure that the value is not transitioning */ + + do current_scan_line = (unsigned short)(READ_REG32(MDC_LINE_CNT_STATUS) & MDC_LNCNT_V_LINE_CNT); + while(current_scan_line != (unsigned short)(READ_REG32(MDC_LINE_CNT_STATUS) & MDC_LNCNT_V_LINE_CNT)); + + return (current_scan_line >> 16); +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_offset + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_display_offset(void) +#else +unsigned long gfx_get_display_offset(void) +#endif +{ + return (READ_REG32(MDC_FB_ST_OFFSET) & 0x0FFFFFFF); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_offset + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_cursor_offset(void) +#else +unsigned long gfx_get_cursor_offset(void) +#endif +{ + return (READ_REG32(MDC_CURS_ST_OFFSET) & 0x0FFFFFFF); +} + +#if GFX_READ_ROUTINES + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +/*--------------------------------------------------------------------------- + * gfx_get_hblank_start + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_hblank_start(void) +#else +unsigned short gfx_get_hblank_start(void) +#endif +{ + return ((unsigned short)((READ_REG32(MDC_H_BLANK_TIMING) & 0x0FF8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hblank_end + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_hblank_end(void) +#else +unsigned short gfx_get_hblank_end(void) +#endif +{ + return ((unsigned short)(((READ_REG32(MDC_H_BLANK_TIMING) >> 16) & 0x0FF8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vblank_start + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_vblank_start(void) +#else +unsigned short gfx_get_vblank_start(void) +#endif +{ + return ((unsigned short)((READ_REG32(MDC_V_BLANK_TIMING) & 0x07FF) + 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vsync_start + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_vsync_start(void) +#else +unsigned short gfx_get_vsync_start(void) +#endif +{ + return ((unsigned short)((READ_REG32(MDC_V_SYNC_TIMING) & 0x07FF) + 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vblank_end + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_vblank_end(void) +#else +unsigned short gfx_get_vblank_end(void) +#endif +{ + return ((unsigned short)(((READ_REG32(MDC_V_BLANK_TIMING) >> 16) & 0x07FF) + 1)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_palette_entry + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_get_display_palette_entry(unsigned long index, unsigned long *palette) +#else +int gfx_get_display_palette_entry(unsigned long index, unsigned long *palette) +#endif +{ + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + WRITE_REG32(MDC_PAL_ADDRESS, index); + *palette = READ_REG32(MDC_PAL_DATA); + + return 0; +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_palette + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_get_display_palette(unsigned long *palette) +#else +void gfx_get_display_palette(unsigned long *palette) +#endif +{ + unsigned long i; + + WRITE_REG32(MDC_PAL_ADDRESS, 0); + for (i = 0; i < 256; i++) + { + palette[i] = READ_REG32(MDC_PAL_DATA); + } +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_enable + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_cursor_enable(void) +#else +unsigned long gfx_get_cursor_enable(void) +#endif +{ + return (READ_REG32(MDC_GENERAL_CFG) & MDC_GCFG_CURE); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_position + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_cursor_position(void) +#else +unsigned long gfx_get_cursor_position(void) +#endif +{ + return((READ_REG32(MDC_CURSOR_X) & 0x07FF) | + ((READ_REG32(MDC_CURSOR_Y) << 16) & 0x07FF0000)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_offset + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_cursor_clip(void) +#else +unsigned long gfx_get_cursor_clip(void) +#endif +{ + return (((READ_REG32(MDC_CURSOR_X) >> 11) & 0x03F) | + ((READ_REG32(MDC_CURSOR_Y) << 5) & 0x3F0000)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_color + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_cursor_color(int color) +#else +unsigned long gfx_get_cursor_color(int color) +#endif +{ + if (color) + { + WRITE_REG32(MDC_PAL_ADDRESS, 0x101); + } + else + { + WRITE_REG32(MDC_PAL_ADDRESS, 0x100); + } + return READ_REG32(MDC_PAL_DATA); +} + +/*----------------------------------------------------------------------------- + * gfx_get_icon_enable + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_icon_enable(void) +#else +unsigned long gfx_get_icon_enable(void) +#endif +{ + return (READ_REG32(MDC_GENERAL_CFG) & MDC_GCFG_ICNE); +} + +/*----------------------------------------------------------------------------- + * gfx_get_icon_offset + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_icon_offset(void) +#else +unsigned long gfx_get_icon_offset(void) +#endif +{ + return (READ_REG32(MDC_ICON_ST_OFFSET) & 0x0FFFFFFF); +} + +/*----------------------------------------------------------------------------- + * gfx_get_icon_position + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_icon_position(void) +#else +unsigned long gfx_get_icon_position(void) +#endif +{ + return (READ_REG32(MDC_ICON_X) & 0x07FF); +} + +/*----------------------------------------------------------------------------- + * gfx_get_icon_color + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_icon_color(int color) +#else +unsigned long gfx_get_icon_color(int color) +#endif +{ + if (color >= 3) + return 0; + + WRITE_REG32(MDC_PAL_ADDRESS, 0x102 + color); + + return READ_REG32(MDC_PAL_DATA); +} + +/*----------------------------------------------------------------------------- + * gfx_get_compression_enable + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_get_compression_enable(void) +#else +int gfx_get_compression_enable(void) +#endif +{ + if (READ_REG32 (MDC_GENERAL_CFG) & MDC_GCFG_CMPE) + return (1); + + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_get_compression_offset + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_compression_offset(void) +#else +unsigned long gfx_get_compression_offset(void) +#endif +{ + return (READ_REG32(MDC_CB_ST_OFFSET) & 0x007FFFFF); +} + +/*----------------------------------------------------------------------------- + * gfx_get_compression_pitch + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_compression_pitch(void) +#else +unsigned short gfx_get_compression_pitch(void) +#endif +{ + unsigned short pitch; + pitch = (unsigned short)(READ_REG32(MDC_GFX_PITCH) >> 16); + return (pitch << 3); +} + +/*----------------------------------------------------------------------------- + * gfx_get_compression_size + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu2_get_compression_size(void) +#else +unsigned short gfx_get_compression_size(void) +#endif +{ + unsigned short size; + size = (unsigned short)((READ_REG32(MDC_LINE_SIZE) >> 16) & 0x7F) - 1; + return ((size << 3) + 32); +} + +/*----------------------------------------------------------------------------- + * gfx_get_valid_bit + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_get_valid_bit(int line) +#else +int gfx_get_valid_bit(int line) +#endif +{ + unsigned long offset; + int valid; + + offset = READ_REG32 (MDC_PHY_MEM_OFFSET) & 0xFF000000; + offset |= line; + + WRITE_REG32(MDC_PHY_MEM_OFFSET, offset); + valid = (int)READ_REG32 (MDC_DV_ACC) & 2; + + if (valid) return 1; + return 0; +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_offset (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_offset". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_display_video_offset(void) +#else +unsigned long gfx_get_display_video_offset(void) +#endif +{ + return (READ_REG32(MDC_VID_Y_ST_OFFSET) & 0x0FFFFFFF); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_yuv_offsets (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_yuv_offsets". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_get_display_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset) +#else +void gfx_get_display_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset) +#endif +{ + *yoffset = (READ_REG32(MDC_VID_Y_ST_OFFSET) & 0x0FFFFFFF); + *uoffset = (READ_REG32(MDC_VID_U_ST_OFFSET) & 0x0FFFFFFF); + *voffset = (READ_REG32(MDC_VID_V_ST_OFFSET) & 0x0FFFFFFF); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_yuv_pitch (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_yuv_pitch". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu2_get_display_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch) +#else +void gfx_get_display_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch) +#endif +{ + unsigned long pitch = READ_REG32 (MDC_VID_YUV_PITCH); + + *ypitch = ((pitch & 0xFFFF) << 3); + *uvpitch = (pitch >> 13) & 0x7FFF8; +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_downscale_delta (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_downscale_delta". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_display_video_downscale_delta(void) +#else +unsigned long gfx_get_display_video_downscale_delta(void) +#endif +{ + return (READ_REG32(MDC_VID_DS_DELTA) >> 18); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_downscale_enable (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_vertical_downscale_enable". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu2_get_display_video_downscale_enable(void) +#else +int gfx_get_display_video_downscale_enable(void) +#endif +{ + return ((int)((READ_REG32(MDC_GENERAL_CFG) >> 19) & 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_size (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_size". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu2_get_display_video_size(void) +#else +unsigned long gfx_get_display_video_size(void) +#endif +{ + /* RETURN THE LINE SIZE, AS THIS IS ALL THAT IS AVAILABLE */ + + return((READ_REG32(MDC_LINE_SIZE) >> 21) & 0x000007FF); +} + +#endif /* GFX_READ_ROUTINES */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/disp_gu3.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/disp_gu3.c 2005-12-14 11:37:09.000000000 -0700 @@ -0,0 +1,2438 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines for the second generation display controller. + * */ + +void gu3_enable_compression(void); /* private routine definition */ +void gu3_disable_compression(void); /* private routine definition */ +int gfx_set_display_control(int sync_polarities); /* private routine definition */ +void gfx_reset_video (void); +int gu3_set_specified_mode(DISPLAYMODE *pMode, int bpp); + + /*----------------------------------------------------------------------------- + * WARNING!!!! INACCURATE DELAY MECHANISM + * + * In an effort to keep the code self contained and operating system + * independent, the delay loop just performs reads of a display controller + * register. This time will vary for faster processors. The delay can always + * be longer than intended, only effecting the time of the mode switch + * (obviously want it to still be under a second). Problems with the hardware + * only arise if the delay is not long enough. + *----------------------------------------------------------------------------- + */ + +#define CSTL_READS_PER_MILLISECOND 15000L + +#if GFX_DISPLAY_DYNAMIC +void gu3_delay_milliseconds(unsigned long milliseconds) +#else +void gfx_delay_milliseconds(unsigned long milliseconds) +#endif +{ + /* ASSUME 300 MHZ 20 CLOCKS PER READ */ + + unsigned long loop; + loop = milliseconds * CSTL_READS_PER_MILLISECOND; + while (loop-- > 0) + { + READ_REG32 (DC3_UNLOCK); + } +} + +#if GFX_DISPLAY_DYNAMIC +void gu3_delay_microseconds(unsigned long microseconds) +#else +void gfx_delay_microseconds(unsigned long microseconds) +#endif +{ + /* ASSUME 300 MHz, 2 CLOCKS PER INCREMENT */ + + + unsigned long loop_count = microseconds * 15; + + while (loop_count-- > 0) + { + READ_REG32 (DC3_UNLOCK); + } +} + +/*----------------------------------------------------------------------------- + * GFX_SET_DISPLAY_BPP + * + * This routine programs the bpp in the display controller. + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_set_display_bpp(unsigned short bpp) +#else +int gfx_set_display_bpp(unsigned short bpp) +#endif +{ + unsigned long dcfg, lock; + + dcfg = READ_REG32 (DC3_DISPLAY_CFG) & ~(DC3_DCFG_DISP_MODE_MASK | DC3_DCFG_16BPP_MODE_MASK); + lock = READ_REG32 (DC3_UNLOCK); + + switch (bpp) + { + case 12: dcfg |= (DC3_DCFG_DISP_MODE_16BPP | DC3_DCFG_12BPP); break; + case 15: dcfg |= (DC3_DCFG_DISP_MODE_16BPP | DC3_DCFG_15BPP); break; + case 16: dcfg |= (DC3_DCFG_DISP_MODE_16BPP | DC3_DCFG_16BPP); break; + case 32: dcfg |= (DC3_DCFG_DISP_MODE_24BPP); break; + case 8: dcfg |= (DC3_DCFG_DISP_MODE_8BPP); break; + default: return GFX_STATUS_BAD_PARAMETER; + } + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_DISPLAY_CFG, dcfg); + WRITE_REG32 (DC3_UNLOCK, lock); + + /* SET BPP IN GRAPHICS PIPELINE */ + + gfx_set_bpp (bpp); + + return 0; +} + +/*----------------------------------------------------------------------------- + * gu3_set_specified_mode (private routine) + * This routine uses the parameters in the specified display mode structure + * to program the display controller hardware. + *----------------------------------------------------------------------------- + */ +int gu3_set_specified_mode(DISPLAYMODE *pMode, int bpp) +{ + Q_WORD msr_value; + unsigned long unlock, value; + unsigned long acfg, gcfg, dcfg; + unsigned long size, pitch; + unsigned long bpp_mask, temp, dv_size; + + /* CHECK WHETHER TIMING CHANGE IS ALLOWED */ + /* Flag used for locking also overrides timing change restriction */ + + if (gfx_timing_lock && !(pMode->flags & GFX_MODE_LOCK_TIMING)) + return GFX_STATUS_ERROR; + + /* CLEAR PANNING OFFSETS */ + + DeltaX = 0; + DeltaY = 0; + panelLeft = 0; + panelTop = 0; + + /* SET GLOBAL FLAG */ + + if (pMode->flags & GFX_MODE_LOCK_TIMING) + gfx_timing_lock = 1; + + /* CHECK FOR VALID BPP */ + /* As this function can be called directly from */ + /* gfx_set_display_timings, we must correct any */ + /* invalid bpp settings. */ + + switch (bpp) + { + case 12: bpp_mask = 0x00000900; break; + case 15: bpp_mask = 0x00000500; break; + case 16: bpp_mask = 0x00000100; break; + case 32: bpp_mask = 0x00000200; break; + default: bpp_mask = 0x00000000; bpp = 8; break; + } + + gbpp = bpp; + + /* DISABLE COMPRESSION */ + + gu3_disable_compression(); + + /* ALSO DISABLE VIDEO */ + /* Use private "reset video" routine to do all that is needed. */ + /* SC1200, for example, also disables the alpha blending regions. */ + + gfx_reset_video(); + + /* UNLOCK THE DISPLAY CONTROLLER REGISTERS */ + + unlock = READ_REG32 (DC3_UNLOCK); + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + + /* READ THE CURRENT REGISTER VALUES */ + + gcfg = READ_REG32 (DC3_GENERAL_CFG); + dcfg = READ_REG32 (DC3_DISPLAY_CFG); + + /* BLANK THE DISPLAY IN THE DISPLAY FILTER */ + + gfx_set_crt_enable (0); + + /* DISABLE THE TIMING GENERATOR */ + + dcfg &= ~(unsigned long)DC3_DCFG_TGEN; + WRITE_REG32 (DC3_DISPLAY_CFG, dcfg); + + /* DELAY: WAIT FOR PENDING MEMORY REQUESTS */ + /* This delay is used to make sure that all pending requests to the */ + /* memory controller have completed before disabling the FIFO load. */ + + gfx_delay_milliseconds(1); + + /* DISABLE DISPLAY FIFO LOAD */ + + gcfg &= ~(unsigned long)DC3_GCFG_DFLE; + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + + /* PRESERVE VIDEO INFORMATION */ + + gcfg &= (unsigned long)(DC3_GCFG_YUVM | DC3_GCFG_VDSE); + dcfg = 0; + + /* DISABLE VGA */ + /* VGA *MUST* be turned off before TGEN is enabled. If not, a condition */ + /* will result where VGA Enable is waiting for a VSync to be latched but */ + /* a VSync will not be generated until VGA is disabled. */ + + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + + /* SET THE DOT CLOCK FREQUENCY */ + /* Mask off the divide by two bit (bit 31) */ + + gfx_set_clock_frequency(pMode->frequency & 0x7FFFFFFF); + + /* DELAY: WAIT FOR THE PLL TO SETTLE */ + /* This allows the dot clock frequency that was just set to settle. */ + + gfx_delay_milliseconds(1); + + /* SET THE GX DISPLAY CONTROLLER PARAMETERS */ + + WRITE_REG32 (DC3_FB_ST_OFFSET, 0); + WRITE_REG32 (DC3_CB_ST_OFFSET, 0); + WRITE_REG32 (DC3_CURS_ST_OFFSET, 0); + + /* SET LINE SIZE AND PITCH */ + /* 1. Flat Panels must use the mode width and not */ + /* the timing width to set the pitch. */ + /* 2. Mode sets will use a pitch that is aligned */ + /* on a 1K boundary to preserve legacy. The */ + /* pitch can be overridden by a subsequent call */ + /* to gfx_set_display_pitch. */ + + if (PanelEnable) + size = ModeWidth; + else + size = pMode->hactive; + + if (bpp > 8) size <<= 1; + if (bpp > 16) size <<= 1; + + pitch = 1024; + dv_size = DC3_DV_LINE_SIZE_1024; + + if (size > 1024) + { + pitch = 2048; + dv_size = DC3_DV_LINE_SIZE_2048; + } + if (size > 2048) + { + pitch = 4096; + dv_size = DC3_DV_LINE_SIZE_4096; + } + if (size > 4096) + { + pitch = 8192; + dv_size = DC3_DV_LINE_SIZE_8192; + } + WRITE_REG32(DC3_GFX_PITCH, pitch >> 3); + + /* WRITE DIRTY/VALID CONTROL WITH LINE LENGTH */ + + temp = READ_REG32 (DC3_DV_CTL); + WRITE_REG32 (DC3_DV_CTL, (temp & ~DC3_DV_LINE_SIZE_MASK) | dv_size); + + if (PanelEnable) + { + size = pMode->hactive; + if (bpp > 8) size <<= 1; + if (bpp > 16) size <<= 1; + } + + WRITE_REG32 (DC3_LINE_SIZE, ((size >> 3))); + + /* ALWAYS ENABLE VIDEO AND GRAPHICS DATA */ + /* These bits are relics from a previous design and */ + /* should always be enabled. */ + + dcfg |= (unsigned long)(DC3_DCFG_VDEN | DC3_DCFG_GDEN); + + /* SET PIXEL FORMAT */ + + dcfg |= bpp_mask; + + /* ENABLE TIMING GENERATOR, TIM. REG. UPDATES, PALETTE BYPASS */ + /* AND VERT. INT. SELECT */ + + dcfg |= (unsigned long)(DC3_DCFG_TGEN | DC3_DCFG_TRUP | DC3_DCFG_PALB | DC3_DCFG_VISL); + + /* SET FIFO PRIORITIES AND DISPLAY FIFO LOAD ENABLE */ + + gcfg |= 0x0000BA01; + dcfg |= 0x000EA000; + acfg = 0x001A0000; + + /* SET THE DISPLAY CHARACTERISTICS FOR HIGH BANDWIDTH CASES */ + + gfx_msr_read (RC_ID_VG, DC3_VG_SPARE_MSR, &msr_value); + msr_value.low &= ~(VG_SPARE_DISABLE_CFIFO_HGO | VG_SPARE_VFIFO_ARB_SELECT | + VG_SPARE_LOAD_WM_LPEN_MASK | VG_SPARE_WM_LPEN_OVRD | + VG_SPARE_DISABLE_INIT_VID_PRI | VG_SPARE_DISABLE_VFIFO_WM); + msr_value.low |= VG_SPARE_DISABLE_CFIFO_HGO | VG_SPARE_VFIFO_ARB_SELECT; + gfx_msr_write (RC_ID_VG, DC3_VG_SPARE_MSR, &msr_value); + WRITE_REG32 (DC3_ARB_CFG, acfg); + + /* ENABLE FLAT PANEL CENTERING */ + /* For panel modes having a resolution smaller than the */ + /* panel resolution, turn on data centering. */ + + if (PanelEnable && ModeWidth < PanelWidth) + dcfg |= DC3_DCFG_DCEN; + + /* SET THE GRAPHICS SCALE */ + /* We do not support graphics scaling, but we need to ensure that the */ + /* scale is set correctly none the less. */ + + WRITE_REG32 (DC3_GFX_SCALE, 0x40004000); + WRITE_REG32 (DC3_IRQ_CTL, 0); + + /* COMBINE AND SET TIMING VALUES */ + + value = (unsigned long) (pMode->hactive - 1) | + (((unsigned long) (pMode->htotal - 1)) << 16); + WRITE_REG32(DC3_H_ACTIVE_TIMING, value); + value = (unsigned long) (pMode->hblankstart - 1) | + (((unsigned long) (pMode->hblankend - 1)) << 16); + WRITE_REG32(DC3_H_BLANK_TIMING, value); + value = (unsigned long) (pMode->hsyncstart - 1) | + (((unsigned long) (pMode->hsyncend - 1)) << 16); + WRITE_REG32(DC3_H_SYNC_TIMING, value); + value = (unsigned long) (pMode->vactive - 1) | + (((unsigned long) (pMode->vtotal - 1)) << 16); + WRITE_REG32(DC3_V_ACTIVE_TIMING, value); + value = (unsigned long) (pMode->vblankstart - 1) | + (((unsigned long) (pMode->vblankend - 1)) << 16); + WRITE_REG32(DC3_V_BLANK_TIMING, value); + value = (unsigned long) (pMode->vsyncstart - 1) | + (((unsigned long) (pMode->vsyncend - 1)) << 16); + WRITE_REG32(DC3_V_SYNC_TIMING, value); + + WRITE_REG32 (DC3_DISPLAY_CFG, dcfg); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + + /* CONFIGURE DISPLAY OUTPUT FROM VIDEO PROCESSOR */ + + gfx_set_display_control (((pMode->flags & GFX_MODE_NEG_HSYNC) ? 1 : 0) | + ((pMode->flags & GFX_MODE_NEG_VSYNC) ? 2 : 0)); + + /* RESTORE VALUE OF DC3_UNLOCK */ + + WRITE_REG32(DC3_UNLOCK, unlock); + + /* RESET THE PITCH VALUES IN THE GP */ + + gfx_reset_pitch ((unsigned short)pitch); + + gfx_set_bpp ((unsigned short)bpp); + + return GFX_STATUS_OK; +} + + /*---------------------------------------------------------------------------- + * GFX_IS_DISPLAY_MODE_SUPPORTED + * + * This routine sets the specified display mode. + * + * Returns 1 if successful, 0 if mode could not be set. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_is_display_mode_supported(int xres, int yres, int bpp, int hz) +#else +int gfx_is_display_mode_supported(int xres, int yres, int bpp, int hz) +#endif +{ + unsigned int mode; + unsigned long hz_flag = 0, bpp_flag = 0; + + /* SET FLAGS TO MATCH REFRESH RATE */ + + if (hz == 56) hz_flag = GFX_MODE_56HZ; + if (hz == 60) hz_flag = GFX_MODE_60HZ; + if (hz == 70) hz_flag = GFX_MODE_70HZ; + if (hz == 72) hz_flag = GFX_MODE_72HZ; + if (hz == 75) hz_flag = GFX_MODE_75HZ; + if (hz == 85) hz_flag = GFX_MODE_85HZ; + if (hz == 90) hz_flag = GFX_MODE_90HZ; + if (hz == 100) hz_flag = GFX_MODE_100HZ; + + /* SET BPP FLAGS TO LIMIT MODE SELECTION */ + + switch (bpp) + { + case 8: bpp_flag = GFX_MODE_8BPP; break; + case 12: bpp_flag = GFX_MODE_12BPP; break; + case 15: bpp_flag = GFX_MODE_15BPP; break; + case 16: bpp_flag = GFX_MODE_16BPP; break; + case 32: bpp_flag = GFX_MODE_24BPP; break; + default: return (-1); + } + + /* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */ + + for (mode = 0; mode < NUM_RC_DISPLAY_MODES; mode++) + { + if ((DisplayParams[mode].hactive == (unsigned short)xres) && + (DisplayParams[mode].vactive == (unsigned short)yres) && + (DisplayParams[mode].flags & hz_flag) && + (DisplayParams[mode].flags & bpp_flag)) + { + + /* CASTLE DOES NOT SUPPORT EMULATED VGA MODES */ + + if ((DisplayParams[mode].flags & GFX_MODE_PIXEL_DOUBLE) || + (DisplayParams[mode].flags & GFX_MODE_LINE_DOUBLE)) + continue; + + /* SET THE DISPLAY CONTROLLER FOR THE SELECTED MODE */ + + return(mode); + } + } + return(-1); +} + +/*---------------------------------------------------------------------------- + * gfx_set_display_mode + * + * This routine sets the specified display mode. + * + * Returns 1 if successful, 0 if mode could not be set. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_set_display_mode(int xres, int yres, int bpp, int hz) +#else +int gfx_set_display_mode(int xres, int yres, int bpp, int hz) +#endif +{ + int mode; + + /* DISABLE FLAT PANEL */ + /* Flat Panel settings are enabled by the function gfx_set_fixed_timings */ + /* and disabled by gfx_set_display_mode. */ + + PanelEnable = 0; + + mode = gfx_is_display_mode_supported(xres, yres, bpp, hz); + if(mode >= 0) + { + if (gu3_set_specified_mode(&DisplayParams[mode], bpp) == GFX_STATUS_OK) + return(1); + } + return(0); +} + +/*---------------------------------------------------------------------------- + * GFX_SET_DISPLAY_TIMINGS + * + * This routine sets the display controller mode using the specified timing + * values (as opposed to using the tables internal to Durango). + * + * Returns GFX_STATUS_OK ON SUCCESS, GFX_STATUS_ERROR otherwise. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_set_display_timings(unsigned short bpp, unsigned short flags, + unsigned short hactive, unsigned short hblankstart, + unsigned short hsyncstart, unsigned short hsyncend, + unsigned short hblankend, unsigned short htotal, + unsigned short vactive, unsigned short vblankstart, + unsigned short vsyncstart, unsigned short vsyncend, + unsigned short vblankend, unsigned short vtotal, + unsigned long frequency) +#else +int gfx_set_display_timings(unsigned short bpp, unsigned short flags, + unsigned short hactive, unsigned short hblankstart, + unsigned short hsyncstart, unsigned short hsyncend, + unsigned short hblankend, unsigned short htotal, + unsigned short vactive, unsigned short vblankstart, + unsigned short vsyncstart, unsigned short vsyncend, + unsigned short vblankend, unsigned short vtotal, + unsigned long frequency) +#endif +{ + /* SET MODE STRUCTURE WITH SPECIFIED VALUES */ + + gfx_display_mode.flags = 0; + if (flags & 1) gfx_display_mode.flags |= GFX_MODE_NEG_HSYNC; + if (flags & 2) gfx_display_mode.flags |= GFX_MODE_NEG_VSYNC; + if (flags & 0x1000) gfx_display_mode.flags |= GFX_MODE_LOCK_TIMING; + gfx_display_mode.hactive = hactive; + gfx_display_mode.hblankstart = hblankstart; + gfx_display_mode.hsyncstart = hsyncstart; + gfx_display_mode.hsyncend = hsyncend; + gfx_display_mode.hblankend = hblankend; + gfx_display_mode.htotal = htotal; + gfx_display_mode.vactive = vactive; + gfx_display_mode.vblankstart = vblankstart; + gfx_display_mode.vsyncstart = vsyncstart; + gfx_display_mode.vsyncend = vsyncend; + gfx_display_mode.vblankend = vblankend; + gfx_display_mode.vtotal = vtotal; + gfx_display_mode.frequency = frequency; + + /* CALL ROUTINE TO SET MODE */ + + return (gu3_set_specified_mode(&gfx_display_mode, bpp)); +} + +/*---------------------------------------------------------------------------- + * GFX_SET_VTOTAL + * + * This routine sets the display controller vertical total to + * "vtotal". As a side effect it also sets vertical blank end. + * It should be used when only this value needs to be changed, + * due to speed considerations. + * + * Note: it is the caller's responsibility to make sure that + * a legal vtotal is used, i.e. that "vtotal" is greater than or + * equal to vsync end. + * + * Always returns 0. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_set_vtotal(unsigned short vtotal) +#else +int gfx_set_vtotal(unsigned short vtotal) +#endif +{ + unsigned long unlock, dcfg, vactive, vblank; + + /* UNLOCK THE DISPLAY CONTROLLER REGISTERS */ + + unlock = READ_REG32(DC3_UNLOCK); + WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE); + + /* READ THE CURRENT RC VALUES */ + + dcfg = READ_REG32 (DC3_DISPLAY_CFG); + vactive = READ_REG32 (DC3_V_ACTIVE_TIMING); + vblank = READ_REG32 (DC3_V_BLANK_TIMING); + + /* DISABLE TIMING REGISTER UPDATES */ + + WRITE_REG32 (DC3_DISPLAY_CFG, dcfg & ~(unsigned long)DC3_DCFG_TRUP); + + /* WRITE NEW TIMING VALUES */ + + WRITE_REG32 (DC3_V_ACTIVE_TIMING, (vactive & DC3_VAT_VA_MASK) | (unsigned long)(vtotal - 1) << 16); + WRITE_REG32 (DC3_V_BLANK_TIMING, (vblank & DC3_VBT_VBS_MASK) | (unsigned long)(vtotal - 1) << 16); + + /* RESTORE OLD RC VALUES */ + + WRITE_REG32 (DC3_DISPLAY_CFG, dcfg); + WRITE_REG32 (DC3_UNLOCK, unlock); + + return (0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_pitch + * + * This routine sets the pitch of the frame buffer to the specified value. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_display_pitch(unsigned short pitch) +#else +void gfx_set_display_pitch(unsigned short pitch) +#endif +{ + unsigned long value = 0; + unsigned long lock = READ_REG32(DC3_UNLOCK); + + value = READ_REG32(DC3_GFX_PITCH) & 0xFFFF0000; + value |= (pitch >> 3); + WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32(DC3_GFX_PITCH, value); + + /* SET RENDERING PITCHES TO MATCH */ + + gfx_reset_pitch(pitch); + + /* SET THE FRAME DIRTY MODE */ + /* Non-standard pitches, i.e. pitches that */ + /* are not 1K, 2K or 4K must mark the entire */ + /* frame as dirty when writing to the frame */ + /* buffer. */ + + value = READ_REG32 (DC3_GENERAL_CFG); + + if (pitch == 1024 || pitch == 2048 || pitch == 4096 || pitch == 8192) + value &= ~(unsigned long)(DC3_GCFG_FDTY); + else + value |= (unsigned long)(DC3_GCFG_FDTY); + + WRITE_REG32 (DC3_GENERAL_CFG, value); + WRITE_REG32(DC3_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_offset + * + * This routine sets the start address of the frame buffer. It is + * typically used to pan across a virtual desktop (frame buffer larger than + * the displayed screen) or to flip the display between multiple buffers. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_display_offset(unsigned long offset) +#else +void gfx_set_display_offset(unsigned long offset) +#endif +{ + /* UPDATE FRAME BUFFER OFFSET */ + unsigned long lock; + lock = READ_REG32(DC3_UNLOCK); + WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE); + + /* START ADDRESS EFFECTS DISPLAY COMPRESSION */ + /* Disable compression for non-zero start addresss values. */ + /* Enable compression if offset is zero and comression is intended to */ + /* be enabled from a previous call to "gfx_set_compression_enable". */ + /* Compression should be disabled BEFORE the offset is changed */ + /* and enabled AFTER the offset is changed. */ + + if (offset == 0) + { + WRITE_REG32(DC3_FB_ST_OFFSET, offset); + if (gfx_compression_enabled) + { + /* WAIT FOR THE OFFSET TO BE LATCHED */ + gfx_wait_vertical_blank (); + gu3_enable_compression(); + } + } + else + { + /* ONLY DISABLE COMPRESSION ONCE */ + + if (gfx_compression_active) + gu3_disable_compression(); + + WRITE_REG32(DC3_FB_ST_OFFSET, offset); + } + + WRITE_REG32(DC3_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_palette_entry + * + * This routine sets an palette entry in the display controller. + * A 32-bit X:R:G:B value. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_set_display_palette_entry(unsigned long index, unsigned long palette) +#else +int gfx_set_display_palette_entry(unsigned long index, unsigned long palette) +#endif +{ + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + WRITE_REG32(DC3_PAL_ADDRESS, index); + WRITE_REG32(DC3_PAL_DATA, palette); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_palette + * + * This routine sets the entire palette in the display controller. + * A pointer is provided to a 256 entry table of 32-bit X:R:G:B values. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_set_display_palette(unsigned long *palette) +#else +int gfx_set_display_palette(unsigned long *palette) +#endif +{ + unsigned long i; + WRITE_REG32(DC3_PAL_ADDRESS, 0); + + if (palette) + { + for (i = 0; i < 256; i++) + { + WRITE_REG32(DC3_PAL_DATA, palette[i]); + } + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_enable + * + * This routine enables or disables the hardware cursor. + * + * WARNING: The cursor start offset must be set by setting the cursor + * position before calling this routine to assure that memory reads do not + * go past the end of graphics memory (this can hang GXm). + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_cursor_enable(int enable) +#else +void gfx_set_cursor_enable(int enable) +#endif +{ + unsigned long unlock, gcfg; + + /* SET OR CLEAR CURSOR ENABLE BIT */ + + unlock = READ_REG32(DC3_UNLOCK); + gcfg = READ_REG32(DC3_GENERAL_CFG); + if (enable) gcfg |= DC3_GCFG_CURE; + else gcfg &= ~(DC3_GCFG_CURE); + + /* WRITE NEW REGISTER VALUE */ + + WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32(DC3_GENERAL_CFG, gcfg); + WRITE_REG32(DC3_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_colors + * + * This routine sets the colors of the hardware cursor. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor) +#else +void gfx_set_cursor_colors(unsigned long bkcolor, unsigned long fgcolor) +#endif +{ + /* SET CURSOR COLORS */ + + WRITE_REG32(DC3_PAL_ADDRESS, 0x100); + WRITE_REG32(DC3_PAL_DATA, bkcolor); + WRITE_REG32(DC3_PAL_DATA, fgcolor); +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_position + * + * This routine sets the position of the hardware cusror. The starting + * offset of the cursor buffer must be specified so that the routine can + * properly clip scanlines if the cursor is off the top of the screen. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_cursor_position(unsigned long memoffset, + unsigned short xpos, unsigned short ypos, + unsigned short xhotspot, unsigned short yhotspot) +#else +void gfx_set_cursor_position(unsigned long memoffset, + unsigned short xpos, unsigned short ypos, + unsigned short xhotspot, unsigned short yhotspot) +#endif +{ + unsigned long unlock; + + short x = (short) xpos - (short) xhotspot; + short y = (short) ypos - (short) yhotspot; + short xoffset = 0; + short yoffset = 0; + if (x < -63) return; + if (y < -63) return; + + if (PanelEnable) + { + if (( ModeWidth > PanelWidth) || (ModeHeight > PanelHeight)) + { + gfx_enable_panning(xpos, ypos); + x = x - (unsigned short)panelLeft; + y = y - (unsigned short)panelTop; + } + } + + /* ADJUST OFFSETS */ + /* Cursor movement and panning work as follows: The cursor position */ + /* refers to where the hotspot of the cursor is located. However, for */ + /* non-zero hotspots, the cursor buffer actually begins before the */ + /* specified position. */ + + if (x < 0) { xoffset = -x; x = 0; } + if (y < 0) { yoffset = -y; y = 0; } + memoffset += (unsigned long) yoffset << 4; + + /* SET CURSOR POSITION */ + + unlock = READ_REG32(DC3_UNLOCK); + WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32(DC3_CURS_ST_OFFSET, memoffset); + WRITE_REG32(DC3_CURSOR_X, (unsigned long) x | + (((unsigned long) xoffset) << 11)); + WRITE_REG32(DC3_CURSOR_Y, (unsigned long) y | + (((unsigned long) yoffset) << 11)); + WRITE_REG32(DC3_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_shape32 + * + * This routine loads 32x32 cursor data into the cursor buffer in graphics memory. + * As the Castle cursor is actually 64x64, we must pad the outside of the + * cursor data with transparent pixels. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_cursor_shape32(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +#else +void gfx_set_cursor_shape32(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +#endif +{ + int i; + + for (i = 0; i < 32; i++) + { + /* EVEN QWORDS CONTAIN THE AND MASK */ + + WRITE_FB32 (memoffset, 0xFFFFFFFF); + WRITE_FB32 (memoffset + 4, andmask[i]); + + /* ODD QWORDS CONTAIN THE XOR MASK */ + + WRITE_FB32 (memoffset + 8, 0x00000000); + WRITE_FB32 (memoffset + 12, xormask[i]); + + memoffset += 16; + } + + /* FILL THE LOWER HALF OF THE BUFFER WITH TRANSPARENT PIXELS */ + + for (i = 0; i < 32; i++) + { + WRITE_FB32 (memoffset, 0xFFFFFFFF); + WRITE_FB32 (memoffset + 4, 0xFFFFFFFF); + WRITE_FB32 (memoffset + 8, 0x00000000); + WRITE_FB32 (memoffset + 12, 0x00000000); + + memoffset += 16; + } +} + +/*--------------------------------------------------------------------------- + * gfx_set_cursor_shape64 + * + * This routine loads 64x64 cursor data into the cursor buffer in graphics memory. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_cursor_shape64(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +#else +void gfx_set_cursor_shape64(unsigned long memoffset, + unsigned long *andmask, unsigned long *xormask) +#endif +{ + int i; + + for (i = 0; i < 128; i += 2) + { + /* EVEN QWORDS CONTAIN THE AND MASK */ + /* We invert the dwords to prevent the calling */ + /* application from having to think in terms of Qwords. */ + /* The hardware data order is actually 63:0, or 31:0 of */ + /* the second dword followed by 31:0 of the first dword. */ + + WRITE_FB32 (memoffset, andmask[i + 1]); + WRITE_FB32 (memoffset + 4, andmask[i]); + + /* ODD QWORDS CONTAIN THE XOR MASK */ + + WRITE_FB32 (memoffset + 8, xormask[i + 1]); + WRITE_FB32 (memoffset + 12, xormask[i]); + + memoffset += 16; + } +} + +/*--------------------------------------------------------------------------- + * gu3_enable_compression + * + * This is a private routine to this module (not exposed in the Durango API). + * It enables display compression. + *--------------------------------------------------------------------------- + */ +void gu3_enable_compression(void) +{ + unsigned long unlock, gcfg, temp; + + /* DO NOT ENABLE IF START ADDRESS IS NOT ZERO */ + + if (READ_REG32(DC3_FB_ST_OFFSET) & 0x0FFFFFFF) + return; + + /* SET GLOBAL INDICATOR */ + + gfx_compression_active = 1; + + /* CLEAR DIRTY/VALID BITS IN MEMORY CONTROLLER */ + /* Software is required to do this before enabling compression. */ + /* Don't want controller to think that old lines are still valid. */ + /* Writing a 1 to bit 0 of the DV Control register will force the */ + /* hardware to clear all the valid bits. */ + + unlock = READ_REG32 (DC3_UNLOCK); + temp = READ_REG32 (DC3_DV_CTL); + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_DV_CTL, temp | 0x00000001); + + /* TURN ON COMPRESSION CONTROL BITS */ + + gcfg = READ_REG32 (DC3_GENERAL_CFG); + gcfg |= DC3_GCFG_CMPE | DC3_GCFG_DECE; + + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + WRITE_REG32 (DC3_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gu3_disable_compression + * + * This is a private routine to this module (not exposed in the Durango API). + * It disables display compression. + *--------------------------------------------------------------------------- + */ +void gu3_disable_compression(void) +{ + unsigned long unlock, gcfg; + + /* SET GLOBAL INDICATOR */ + + gfx_compression_active = 0; + + /* TURN OFF COMPRESSION CONTROL BITS */ + + unlock = READ_REG32(DC3_UNLOCK); + gcfg = READ_REG32(DC3_GENERAL_CFG); + gcfg &= ~(DC3_GCFG_CMPE | DC3_GCFG_DECE); + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + WRITE_REG32 (DC3_UNLOCK, unlock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_enable + * + * This routine enables or disables display compression. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_set_compression_enable(int enable) +#else +int gfx_set_compression_enable(int enable) +#endif +{ + /* SET GLOBAL VARIABLE FOR INDENDED STATE */ + /* Compression can only be enabled for non-zero start address values. */ + /* Keep state to enable compression on start address changes. */ + + gfx_compression_enabled = enable; + if (enable) gu3_enable_compression(); + else gu3_disable_compression(); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_offset + * + * This routine sets the base offset for the compression buffer. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_set_compression_offset(unsigned long offset) +#else +int gfx_set_compression_offset(unsigned long offset) +#endif +{ + unsigned long lock; + + /* MUST BE 16-BYTE ALIGNED FOR CASTLE */ + + if (offset & 0x0F) return(1); + + /* SET REGISTER VALUE */ + + lock = READ_REG32(DC3_UNLOCK); + WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32(DC3_CB_ST_OFFSET, offset & 0x0FFFFFFF); + WRITE_REG32(DC3_UNLOCK, lock); + + return (0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_pitch + * + * This routine sets the pitch, in bytes, of the compression buffer. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_set_compression_pitch(unsigned short pitch) +#else +int gfx_set_compression_pitch(unsigned short pitch) +#endif +{ + unsigned long lock, line_delta; + + lock = READ_REG32(DC3_UNLOCK); + + /* SET REGISTER VALUE */ + + line_delta = READ_REG32(DC3_GFX_PITCH) & 0x0000FFFF; + line_delta |= (((unsigned long)pitch << 13) & 0xFFFF0000); + WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32(DC3_GFX_PITCH, line_delta); + WRITE_REG32(DC3_UNLOCK, lock); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_compression_size + * + * This routine sets the line size of the compression buffer, which is the + * maximum number of bytes allowed to store a compressed line. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_set_compression_size(unsigned short size) +#else +int gfx_set_compression_size(unsigned short size) +#endif +{ + unsigned long lock, buf_size; + + /* SUBTRACT 32 FROM SIZE */ + /* The display controller will actually write */ + /* 4 extra QWords. So, if we assume that "size" */ + /* refers to the allocated size, we must subtract */ + /* 32 bytes. */ + + size -= 32; + + /* SET REGISTER VALUE */ + + lock = READ_REG32(DC3_UNLOCK); + buf_size = READ_REG32(DC3_LINE_SIZE) & ~DC3_LINE_SIZE_CBLS_MASK; + buf_size |= ((((unsigned long)size >> 3) + 1) & 0x7F) << DC3_LINE_SIZE_CB_SHIFT; + WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32(DC3_LINE_SIZE, buf_size); + WRITE_REG32(DC3_UNLOCK, lock); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_color_key (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_color_key". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_display_video_color_key (unsigned long key, unsigned long mask, int enable) +#else +void gfx_set_display_video_color_key (unsigned long key, unsigned long mask, int enable) +#endif +{ + unsigned long colorkey = 0; + unsigned long lock; + + if (enable) + colorkey = (key & 0xFFFFFF) | DC3_CLR_KEY_ENABLE; + + lock = READ_REG32 (DC3_UNLOCK); + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + + WRITE_REG32 (DC3_COLOR_KEY, colorkey); + WRITE_REG32 (DC3_COLOR_MASK, (mask & 0xFFFFFF)); + + WRITE_REG32 (DC3_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_format (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_format". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_display_video_format(unsigned long format) +#else +void gfx_set_display_video_format(unsigned long format) +#endif +{ + unsigned long gcfg, lock; + + lock = READ_REG32 (DC3_UNLOCK); + gcfg = READ_REG32 (DC3_GENERAL_CFG); + + switch (format) + { + case VIDEO_FORMAT_Y0Y1Y2Y3: + case VIDEO_FORMAT_Y3Y2Y1Y0: + case VIDEO_FORMAT_Y1Y0Y3Y2: + case VIDEO_FORMAT_Y1Y2Y3Y0: + + gcfg |= DC3_GCFG_YUVM; + break; + + default: + + gcfg &= ~DC3_GCFG_YUVM; + break; + } + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + WRITE_REG32 (DC3_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_enable (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_enable". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_display_video_enable(int enable) +#else +void gfx_set_display_video_enable(int enable) +#endif +{ + unsigned long lock, gcfg, dcfg; + + /* READ CURRENT VALUES */ + + lock = READ_REG32 (DC3_UNLOCK); + gcfg = READ_REG32 (DC3_GENERAL_CFG); + dcfg = READ_REG32 (DC3_DISPLAY_CFG); + + /* SET OR CLEAR VIDEO ENABLE IN GENERAL_CFG */ + + if (enable) gcfg |= DC3_GCFG_VIDE; + else gcfg &= ~DC3_GCFG_VIDE; + + /* WRITE REGISTER */ + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_GENERAL_CFG, gcfg); + WRITE_REG32 (DC3_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_size (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_size". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_display_video_size(unsigned short width, unsigned short height) +#else +void gfx_set_display_video_size(unsigned short width, unsigned short height) +#endif +{ + unsigned long lock, value, yuv_420; + + /* READ CURRENT VALUES */ + + lock = READ_REG32 (DC3_UNLOCK); + value = READ_REG32 (DC3_LINE_SIZE) & ~DC3_LINE_SIZE_VLS_MASK; + yuv_420 = READ_REG32 (DC3_GENERAL_CFG) & DC3_GCFG_YUVM; + + /* LINE WIDTH IS 1/4 FOR 4:2:0 VIDEO */ + /* All data must be 32-byte aligned. */ + + if (yuv_420) + { + width >>= 1; + width = (width + 7) & 0xFFF8; + } + else + { + width <<= 1; + width = (width + 31) & 0xFFE0; + } + + /* ONLY THE LINE SIZE IS PROGRAMMED IN THE DISPLAY CONTROLLER */ + /* Shift by three less than the bit position to effect a divide by 8 */ + + value |= ((unsigned long)width << (DC3_LINE_SIZE_VB_SHIFT - 3)) & DC3_LINE_SIZE_VLS_MASK; + + /* WRITE THE REGISTER */ + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_LINE_SIZE, value); + WRITE_REG32 (DC3_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_offset (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_set_video_offset". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_display_video_offset(unsigned long offset) +#else +void gfx_set_display_video_offset(unsigned long offset) +#endif +{ + unsigned long lock; + + lock = READ_REG32(DC3_UNLOCK); + WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE); + offset &= 0x0FFFFFF0; + WRITE_REG32(DC3_VID_Y_ST_OFFSET, offset); + WRITE_REG32(DC3_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_yuv_offsets (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by gfx_set_video_yuv_offsets. It abstracts the version + * of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_display_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, + unsigned long voffset) +#else +void gfx_set_display_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, + unsigned long voffset) +#endif +{ + unsigned long lock; + + lock = READ_REG32(DC3_UNLOCK); + + yoffset &= 0x0FFFFFF0; + uoffset &= 0x0FFFFFF8; + voffset &= 0x0FFFFFF8; + + WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32(DC3_VID_Y_ST_OFFSET, yoffset); + WRITE_REG32(DC3_VID_U_ST_OFFSET, uoffset); + WRITE_REG32(DC3_VID_V_ST_OFFSET, voffset); + WRITE_REG32(DC3_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_set_display_video_yuv_pitch (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by gfx_set_video_yuv_pitch. It abstracts the version + * of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_set_display_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch) +#else +void gfx_set_display_video_yuv_pitch (unsigned long ypitch, unsigned long uvpitch) +#endif +{ + unsigned long lock, pitch; + + lock = READ_REG32(DC3_UNLOCK); + + pitch = ((uvpitch << 13) & 0xFFFF0000) | ((ypitch >> 3) & 0xFFFF); + + WRITE_REG32(DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32(DC3_VID_YUV_PITCH, pitch); + WRITE_REG32(DC3_UNLOCK, lock); +} + +/*--------------------------------------------------------------------------- + * gfx_test_timing_active + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_test_timing_active(void) +#else +int gfx_test_timing_active(void) +#endif +{ + if (READ_REG32 (DC3_DISPLAY_CFG) & DC3_DCFG_TGEN) + return(1); + else return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_test_vertical_active + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_test_vertical_active(void) +#else +int gfx_test_vertical_active(void) +#endif +{ + if (READ_REG32 (DC3_LINE_CNT_STATUS) & DC3_LNCNT_VNA) + return(0); + + return(1); +} + +/*--------------------------------------------------------------------------- + * gfx_wait_vertical_blank + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_wait_vertical_blank(void) +#else +int gfx_wait_vertical_blank(void) +#endif +{ + if (gfx_test_timing_active()) + { + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_enable_panning + * + * This routine enables the panning when the Mode is bigger than the panel + * size. + *--------------------------------------------------------------------------- + */ + +#if GFX_DISPLAY_DYNAMIC +void gu3_enable_panning(int x, int y) +#else +void gfx_enable_panning(int x, int y) +#endif +{ + unsigned long modeBytesPerPixel; + unsigned long modeBytesPerScanline = 0; + unsigned long startAddress = 0; + + modeBytesPerPixel = (gbpp + 7)/8; + modeBytesPerScanline = (READ_REG32 (DC3_GFX_PITCH) & 0x0000FFFF) << 3; + + /* TEST FOR NO-WORK */ + + if (x >= DeltaX && x < ((int)PanelWidth + DeltaX) && + y >= DeltaY && y < ((int)PanelHeight + DeltaY)) + return; + + /* ADJUST PANNING VARIABLES WHEN CURSOR EXCEEDS BOUNDARY */ + /* Test the boundary conditions for each coordinate and update */ + /* all variables and the starting offset accordingly. */ + + if (x < DeltaX) + DeltaX = x; + + else if (x >= (DeltaX + (int)PanelWidth)) + DeltaX = x - (int)PanelWidth + 1; + + if (y < DeltaY) + DeltaY = y; + + else if (y >= (DeltaY + (int)PanelHeight)) + DeltaY = y - (int)PanelHeight + 1; + + /* CALCULATE THE START OFFSET */ + + startAddress = (DeltaX * modeBytesPerPixel) + (DeltaY * modeBytesPerScanline); + + gfx_set_display_offset(startAddress); + + /* SET PANEL COORDINATES */ + /* Panel's x position must be DWORD aligned */ + + panelTop = DeltaY; + panelLeft = DeltaX * modeBytesPerPixel; + + if (panelLeft & 3) + panelLeft = (panelLeft & 0xFFFFFFFC) + 4; + + panelLeft /= modeBytesPerPixel; +} + +/*--------------------------------------------------------------------------- + * gfx_set_fixed_timings + *--------------------------------------------------------------------------- + */ + +#if GFX_DISPLAY_DYNAMIC +int gu3_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#else +int gfx_set_fixed_timings(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#endif +{ + unsigned int mode; + + ModeWidth = width; + ModeHeight = height; + PanelWidth = (unsigned short)panelResX; + PanelHeight = (unsigned short)panelResY; + PanelEnable = 1; + + /* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */ + for (mode = 0; mode < NUM_FIXED_TIMINGS_MODES; mode++) { + if ((FixedParams[mode].xres == width) && + (FixedParams[mode].yres == height) && + (FixedParams[mode].panelresx == panelResX) && + (FixedParams[mode].panelresy == panelResY)) { + + /* SET THE 92xx FOR THE SELECTED MODE */ + FIXEDTIMINGS *fmode = &FixedParams[mode]; + + gfx_set_display_timings(bpp, 3, fmode->hactive,fmode->hblankstart, fmode->hsyncstart, fmode->hsyncend, + fmode->hblankend, fmode->htotal, fmode->vactive, fmode->vblankstart, + fmode->vsyncstart, fmode->vsyncend, fmode->vblankend, fmode->vtotal, fmode->frequency); + + return(1); + } /* end if() */ + } /* end for() */ + + return(-1); +} + +/*--------------------------------------------------------------------------- + * gfx_set_panel_present + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#else +int gfx_set_panel_present(int panelResX, int panelResY, unsigned short width, unsigned short height, unsigned short bpp) +#endif +{ + /* SET VALID BPP */ + /* 16BPP is the default. */ + + if (bpp != 8 && bpp != 12 && bpp != 15 && bpp != 16 && bpp != 32) + bpp = 16; + + /* RECORD PANEL PARAMETERS */ + /* This routine does not touch any panel timings. It is used when custom panel */ + /* settings are set up in advance by the BIOS or an application, but the */ + /* application still requires access to other panel functionality provided by */ + /* Durango (i.e. panning). */ + + ModeWidth = width; + ModeHeight = height; + PanelWidth = (unsigned short)panelResX; + PanelHeight = (unsigned short)panelResY; + PanelEnable = 1; + gbpp = bpp; + + /* PROGRAM THE BPP IN THE DISPLAY CONTROLLER */ + + gfx_set_display_bpp (bpp); + + return(GFX_STATUS_OK); +} + +/* THE FOLLOWING READ ROUTINES ARE ALWAYS INCLUDED: */ + +/*--------------------------------------------------------------------------- + * gfx_get_display_pitch + * + * This routine returns the current pitch of the frame buffer, in bytes. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_display_pitch(void) +#else +unsigned short gfx_get_display_pitch(void) +#endif +{ + return ((unsigned short)(READ_REG32 (DC3_GFX_PITCH) & 0x0000FFFF) << 3); +} + +/*---------------------------------------------------------------------------- + * gfx_mode_frequency_supported + * + * This routine examines if the requested mode with pixel frequency is supported. + * + * Returns >0 if successful , <0 if freq. could not be found and matched. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency) +#else +int gfx_mode_frequency_supported(int xres, int yres, int bpp, unsigned long frequency) +#endif +{ + unsigned int index; + unsigned long value; + unsigned long bpp_flag = 0; + + switch (bpp) + { + case 8: bpp_flag = GFX_MODE_8BPP; break; + case 12: bpp_flag = GFX_MODE_12BPP; break; + case 15: bpp_flag = GFX_MODE_15BPP; break; + case 16: bpp_flag = GFX_MODE_16BPP; break; + case 32: bpp_flag = GFX_MODE_24BPP; break; + default: bpp_flag = GFX_MODE_8BPP; break; + } + + for (index = 0; index < NUM_RC_DISPLAY_MODES; index++) + { + if ((DisplayParams[index].hactive == (unsigned int)xres) && + (DisplayParams[index].vactive == (unsigned int)yres) && + (DisplayParams[index].flags & bpp_flag) && + (DisplayParams[index].frequency == frequency)) + { + int hz=0; + value = DisplayParams[index].flags; + + if (value & GFX_MODE_56HZ) hz = 56; + else if (value & GFX_MODE_60HZ) hz = 60; + else if (value & GFX_MODE_70HZ) hz = 70; + else if (value & GFX_MODE_72HZ) hz = 72; + else if (value & GFX_MODE_75HZ) hz = 75; + else if (value & GFX_MODE_85HZ) hz = 85; + else if (value & GFX_MODE_90HZ) hz = 90; + else if (value & GFX_MODE_100HZ) hz = 100; + return(hz); + } + } + + return(-1); +} + +/*---------------------------------------------------------------------------- + * gfx_refreshrate_from_frequency + * + * This routine maps the frequency to close match refresh rate + * + * Returns . + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency) +#else +int gfx_get_refreshrate_from_frequency(int xres, int yres, int bpp, int *hz, unsigned long frequency) +#endif +{ + unsigned int index, closematch=0; + unsigned long value; + unsigned long bpp_flag = 0; + long min, diff; + + *hz = 60; + + switch (bpp) + { + case 8: bpp_flag = GFX_MODE_8BPP; break; + case 12: bpp_flag = GFX_MODE_12BPP; break; + case 15: bpp_flag = GFX_MODE_15BPP; break; + case 16: bpp_flag = GFX_MODE_16BPP; break; + case 32: bpp_flag = GFX_MODE_24BPP; break; + default: bpp_flag = GFX_MODE_8BPP; break; + } + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + + min = 0x7fffffff; + for (index = 0; index < NUM_RC_DISPLAY_MODES; index++) + { + if ((DisplayParams[index].htotal == (unsigned int)xres) && + (DisplayParams[index].vtotal == (unsigned int)yres) && + (DisplayParams[index].flags & bpp_flag)) + { + diff = (long)frequency - (long)DisplayParams[index].frequency; + if(diff < 0) diff = -diff; + + if (diff < min) + { + min = diff; + closematch = index; + } + } + } + + value = DisplayParams[closematch].flags; + + if (value & GFX_MODE_56HZ) *hz = 56; + else if (value & GFX_MODE_60HZ) *hz = 60; + else if (value & GFX_MODE_70HZ) *hz = 70; + else if (value & GFX_MODE_72HZ) *hz = 72; + else if (value & GFX_MODE_75HZ) *hz = 75; + else if (value & GFX_MODE_85HZ) *hz = 85; + else if (value & GFX_MODE_90HZ) *hz = 90; + else if (value & GFX_MODE_100HZ) *hz = 100; + + return(1); +} + +/*---------------------------------------------------------------------------- + * gfx_refreshrate_from_mode + * + * This routine is identical to the gfx_get_refreshrate_from_frequency, + * except that the active timing values are compared instead of the total + * values. Some modes (such as 70Hz and 72Hz) may be confused in this routine. + * + * Returns . + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency) +#else +int gfx_get_refreshrate_from_mode(int xres, int yres, int bpp, int *hz, unsigned long frequency) +#endif +{ + unsigned int index, closematch=0; + unsigned long value; + unsigned long bpp_flag = 0; + long min, diff; + + *hz = 60; + + switch (bpp) + { + case 8: bpp_flag = GFX_MODE_8BPP; break; + case 12: bpp_flag = GFX_MODE_12BPP; break; + case 15: bpp_flag = GFX_MODE_15BPP; break; + case 16: bpp_flag = GFX_MODE_16BPP; break; + case 32: bpp_flag = GFX_MODE_24BPP; break; + default: bpp_flag = GFX_MODE_8BPP; break; + } + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + + min = 0x7fffffff; + for (index = 0; index < NUM_RC_DISPLAY_MODES; index++) + { + if ((DisplayParams[index].hactive == (unsigned int)xres) && + (DisplayParams[index].vactive == (unsigned int)yres) && + (DisplayParams[index].flags & bpp_flag)) + { + diff = (long)frequency - (long)DisplayParams[index].frequency; + if(diff < 0) diff = -diff; + + if (diff < min) + { + min = diff; + closematch = index; + } + } + } + + value = DisplayParams[closematch].flags; + + if (value & GFX_MODE_56HZ) *hz = 56; + else if (value & GFX_MODE_60HZ) *hz = 60; + else if (value & GFX_MODE_70HZ) *hz = 70; + else if (value & GFX_MODE_72HZ) *hz = 72; + else if (value & GFX_MODE_75HZ) *hz = 75; + else if (value & GFX_MODE_85HZ) *hz = 85; + else if (value & GFX_MODE_90HZ) *hz = 90; + else if (value & GFX_MODE_100HZ) *hz = 100; + + return(1); +} + +/*---------------------------------------------------------------------------- + * gfx_get_frequency_from_refreshrate + * + * This routine maps the refresh rate to the closest matching PLL frequency. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency) +#else +int gfx_get_frequency_from_refreshrate(int xres, int yres, int bpp, int hz, int *frequency) +#endif +{ + unsigned int index; + int retval = -1; + unsigned long hz_flag = 0; + unsigned long bpp_flag = 0; + + *frequency = 0; + + if (hz == 56) hz_flag = GFX_MODE_56HZ; + else if (hz == 60) hz_flag = GFX_MODE_60HZ; + else if (hz == 70) hz_flag = GFX_MODE_70HZ; + else if (hz == 72) hz_flag = GFX_MODE_72HZ; + else if (hz == 75) hz_flag = GFX_MODE_75HZ; + else if (hz == 85) hz_flag = GFX_MODE_85HZ; + else if (hz == 90) hz_flag = GFX_MODE_90HZ; + else if (hz == 100) hz_flag = GFX_MODE_100HZ; + + switch (bpp) + { + case 8: bpp_flag = GFX_MODE_8BPP; break; + case 12: bpp_flag = GFX_MODE_12BPP; break; + case 15: bpp_flag = GFX_MODE_15BPP; break; + case 16: bpp_flag = GFX_MODE_16BPP; break; + case 32: bpp_flag = GFX_MODE_24BPP; break; + default: bpp_flag = GFX_MODE_8BPP; break; + } + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + + for (index = 0; index < NUM_RC_DISPLAY_MODES; index++) + { + if ((DisplayParams[index].hactive == (unsigned short)xres) && + (DisplayParams[index].vactive == (unsigned short)yres) && + (DisplayParams[index].flags & bpp_flag) && + (DisplayParams[index].flags & hz_flag)) + { + *frequency = (int)DisplayParams[index].frequency; + retval = 1; + } + } + return retval; +} + + +/*--------------------------------------------------------------------------- + * gfx_get_max_supported_pixel_clock + * + * This routine returns the maximum recommended speed for the pixel clock. The + * return value is an integer of the format xxxyyy, where xxx.yyy is the maximum + * floating point pixel clock speed. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_max_supported_pixel_clock (void) +#else +unsigned long gfx_get_max_supported_pixel_clock (void) +#endif + +{ + return 229500; +} + +/*---------------------------------------------------------------------------- + * gfx_get_display_mode + * + * This routine gets the specified display mode. + * + * Returns >0 if successful and mode returned, <0 if mode could not be found. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_get_display_mode(int *xres, int *yres, int *bpp, int *hz) +#else +int gfx_get_display_mode(int *xres, int *yres, int *bpp, int *hz) +#endif +{ + unsigned int mode=0; + unsigned long pll_freq = 0, bpp_flag = 0; + + *xres = gfx_get_hactive(); + *yres = gfx_get_vactive(); + *bpp = gfx_get_display_bpp(); + pll_freq = gfx_get_clock_frequency(); + + /* SET BPP FLAGS TO LIMIT MODE SELECTION */ + + switch (*bpp) + { + case 8: bpp_flag = GFX_MODE_8BPP; break; + case 12: bpp_flag = GFX_MODE_12BPP; break; + case 15: bpp_flag = GFX_MODE_15BPP; break; + case 16: bpp_flag = GFX_MODE_16BPP; break; + case 32: bpp_flag = GFX_MODE_24BPP; break; + default: bpp_flag = GFX_MODE_8BPP; break; + } + + for (mode = 0; mode < NUM_RC_DISPLAY_MODES; mode++) { + if ((DisplayParams[mode].hactive == (unsigned int)*xres) && + (DisplayParams[mode].vactive == (unsigned int)*yres) && + (DisplayParams[mode].frequency == pll_freq) && + (DisplayParams[mode].flags & bpp_flag)) { + + pll_freq = DisplayParams[mode].flags; + + if (pll_freq & GFX_MODE_56HZ) *hz = 56; + else if (pll_freq & GFX_MODE_60HZ) *hz = 60; + else if (pll_freq & GFX_MODE_70HZ) *hz = 70; + else if (pll_freq & GFX_MODE_72HZ) *hz = 72; + else if (pll_freq & GFX_MODE_75HZ) *hz = 75; + else if (pll_freq & GFX_MODE_85HZ) *hz = 85; + else if (pll_freq & GFX_MODE_90HZ) *hz = 90; + else if (pll_freq & GFX_MODE_100HZ) *hz = 100; + + return(1); + } + } + return(-1); +} + +/*---------------------------------------------------------------------------- + * GFX_GET_DISPLAY_DETAILS + * + * This routine gets the specified display mode. + * + * Returns 1 if successful, 0 if mode could not be get. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_get_display_details(unsigned int mode, int *xres, int *yres, int *hz) +#else +int gfx_get_display_details(unsigned int mode, int *xres, int *yres, int *hz) +#endif +{ + if(mode < NUM_RC_DISPLAY_MODES) + { + if(DisplayParams[mode].flags & GFX_MODE_56HZ) + *hz = 56; + else if(DisplayParams[mode].flags & GFX_MODE_60HZ) + *hz = 60; + else if(DisplayParams[mode].flags & GFX_MODE_70HZ) + *hz = 70; + else if(DisplayParams[mode].flags & GFX_MODE_72HZ) + *hz = 72; + else if(DisplayParams[mode].flags & GFX_MODE_75HZ) + *hz = 75; + else if(DisplayParams[mode].flags & GFX_MODE_85HZ) + *hz = 85; + else if(DisplayParams[mode].flags & GFX_MODE_90HZ) + *hz = 90; + else if(DisplayParams[mode].flags & GFX_MODE_100HZ) + *hz = 100; + + *xres = DisplayParams[mode].hactive; + *yres = DisplayParams[mode].vactive; + + if (DisplayParams[mode].flags & GFX_MODE_PIXEL_DOUBLE) + *xres >>= 1; + if (DisplayParams[mode].flags & GFX_MODE_LINE_DOUBLE) + *yres >>= 1; + + return(1); + } + return(0); +} + +/*---------------------------------------------------------------------------- + * GFX_GET_DISPLAY_MODE_COUNT + * + * This routine gets the number of available display modes. + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_get_display_mode_count(void) +#else +int gfx_get_display_mode_count(void) +#endif +{ + return(NUM_RC_DISPLAY_MODES); +} + +/*---------------------------------------------------------------------------- + * gfx_get_frame_buffer_line_size + * + * Returns the current frame buffer line size, in bytes + *---------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_frame_buffer_line_size(void) +#else +unsigned long gfx_get_frame_buffer_line_size(void) +#endif +{ + return ((READ_REG32 (DC3_LINE_SIZE) & 0x3FF) << 3); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hactive + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_hactive(void) +#else +unsigned short gfx_get_hactive(void) +#endif +{ + return((unsigned short)((READ_REG32(DC3_H_ACTIVE_TIMING) & 0x0FF8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hsync_start + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_hsync_start(void) +#else +unsigned short gfx_get_hsync_start(void) +#endif +{ + return ((unsigned short)((READ_REG32(DC3_H_SYNC_TIMING) & 0x0FF8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hsync_end + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_hsync_end(void) +#else +unsigned short gfx_get_hsync_end(void) +#endif +{ + return((unsigned short)(((READ_REG32(DC3_H_SYNC_TIMING) >> 16) & 0x0FF8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_htotal + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_htotal(void) +#else +unsigned short gfx_get_htotal(void) +#endif +{ + return((unsigned short)(((READ_REG32(DC3_H_ACTIVE_TIMING) >> 16) & 0x0FF8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vactive + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_vactive(void) +#else +unsigned short gfx_get_vactive(void) +#endif +{ + return((unsigned short)((READ_REG32(DC3_V_ACTIVE_TIMING) & 0x07FF) + 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vsync_end + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_vsync_end(void) +#else +unsigned short gfx_get_vsync_end(void) +#endif +{ + return((unsigned short)(((READ_REG32(DC3_V_SYNC_TIMING) >> 16) & 0x07FF) + 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vtotal + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_vtotal(void) +#else +unsigned short gfx_get_vtotal(void) +#endif +{ + return((unsigned short)(((READ_REG32(DC3_V_ACTIVE_TIMING) >> 16) & 0x07FF) + 1)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_bpp + * + * This routine returns the current color depth of the active display. + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_display_bpp(void) +#else +unsigned short gfx_get_display_bpp(void) +#endif +{ + unsigned long dcfg = READ_REG32 (DC3_DISPLAY_CFG); + + switch ((dcfg & DC3_DCFG_DISP_MODE_MASK) >> 8) + { + case 0: return (8); + case 2: return (32); + + case 1: + + switch ((dcfg & DC3_DCFG_16BPP_MODE_MASK) >> 10) + { + case 0: return (16); + case 1: return (15); + case 2: return (12); + default: return (0); + } + } + + /* INVALID SETTING */ + + return (0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vline + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_vline(void) +#else +unsigned short gfx_get_vline(void) +#endif +{ + unsigned long current_scan_line; + + /* Read similar value twice to ensure that the value is not transitioning */ + + do current_scan_line = (READ_REG32(DC3_LINE_CNT_STATUS) & DC3_LNCNT_V_LINE_CNT); + while(current_scan_line != (READ_REG32(DC3_LINE_CNT_STATUS) & DC3_LNCNT_V_LINE_CNT)); + + return ((unsigned short)(current_scan_line >> 16)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_offset + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_display_offset(void) +#else +unsigned long gfx_get_display_offset(void) +#endif +{ + return (READ_REG32(DC3_FB_ST_OFFSET) & 0x0FFFFFFF); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_offset + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_cursor_offset(void) +#else +unsigned long gfx_get_cursor_offset(void) +#endif +{ + return (READ_REG32(DC3_CURS_ST_OFFSET) & 0x0FFFFFFF); +} + +#if GFX_READ_ROUTINES + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +/*--------------------------------------------------------------------------- + * gfx_get_hblank_start + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_hblank_start(void) +#else +unsigned short gfx_get_hblank_start(void) +#endif +{ + return ((unsigned short)((READ_REG32(DC3_H_BLANK_TIMING) & 0x0FF8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_hblank_end + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_hblank_end(void) +#else +unsigned short gfx_get_hblank_end(void) +#endif +{ + return ((unsigned short)(((READ_REG32(DC3_H_BLANK_TIMING) >> 16) & 0x0FF8) + 8)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vblank_start + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_vblank_start(void) +#else +unsigned short gfx_get_vblank_start(void) +#endif +{ + return ((unsigned short)((READ_REG32(DC3_V_BLANK_TIMING) & 0x07FF) + 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vsync_start + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_vsync_start(void) +#else +unsigned short gfx_get_vsync_start(void) +#endif +{ + return ((unsigned short)((READ_REG32(DC3_V_SYNC_TIMING) & 0x07FF) + 1)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_vblank_end + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_vblank_end(void) +#else +unsigned short gfx_get_vblank_end(void) +#endif +{ + return ((unsigned short)(((READ_REG32(DC3_V_BLANK_TIMING) >> 16) & 0x07FF) + 1)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_palette_entry + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_get_display_palette_entry(unsigned long index, unsigned long *palette) +#else +int gfx_get_display_palette_entry(unsigned long index, unsigned long *palette) +#endif +{ + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + WRITE_REG32(DC3_PAL_ADDRESS, index); + *palette = READ_REG32(DC3_PAL_DATA); + + return 0; +} + +/*----------------------------------------------------------------------------- + * gfx_get_display_palette + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_get_display_palette(unsigned long *palette) +#else +void gfx_get_display_palette(unsigned long *palette) +#endif +{ + unsigned long i; + + WRITE_REG32(DC3_PAL_ADDRESS, 0); + for (i = 0; i < 256; i++) + { + palette[i] = READ_REG32(DC3_PAL_DATA); + } +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_enable + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_cursor_enable(void) +#else +unsigned long gfx_get_cursor_enable(void) +#endif +{ + return (READ_REG32(DC3_GENERAL_CFG) & DC3_GCFG_CURE); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_position + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_cursor_position(void) +#else +unsigned long gfx_get_cursor_position(void) +#endif +{ + return((READ_REG32(DC3_CURSOR_X) & 0x07FF) | + ((READ_REG32(DC3_CURSOR_Y) << 16) & 0x07FF0000)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_offset + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_cursor_clip(void) +#else +unsigned long gfx_get_cursor_clip(void) +#endif +{ + return (((READ_REG32(DC3_CURSOR_X) >> 11) & 0x03F) | + ((READ_REG32(DC3_CURSOR_Y) << 5) & 0x3F0000)); +} + +/*----------------------------------------------------------------------------- + * gfx_get_cursor_color + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_cursor_color(int color) +#else +unsigned long gfx_get_cursor_color(int color) +#endif +{ + if (color) + { + WRITE_REG32(DC3_PAL_ADDRESS, 0x101); + } + else + { + WRITE_REG32(DC3_PAL_ADDRESS, 0x100); + } + return READ_REG32(DC3_PAL_DATA); +} + +/*----------------------------------------------------------------------------- + * gfx_get_compression_enable + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_get_compression_enable(void) +#else +int gfx_get_compression_enable(void) +#endif +{ + if (READ_REG32 (DC3_GENERAL_CFG) & DC3_GCFG_CMPE) + return (1); + + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_get_compression_offset + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_compression_offset(void) +#else +unsigned long gfx_get_compression_offset(void) +#endif +{ + return (READ_REG32(DC3_CB_ST_OFFSET) & 0x007FFFFF); +} + +/*----------------------------------------------------------------------------- + * gfx_get_compression_pitch + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_compression_pitch(void) +#else +unsigned short gfx_get_compression_pitch(void) +#endif +{ + unsigned short pitch; + pitch = (unsigned short)(READ_REG32(DC3_GFX_PITCH) >> 16); + return (pitch << 3); +} + +/*----------------------------------------------------------------------------- + * gfx_get_compression_size + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned short gu3_get_compression_size(void) +#else +unsigned short gfx_get_compression_size(void) +#endif +{ + unsigned short size; + size = (unsigned short)((READ_REG32(DC3_LINE_SIZE) >> DC3_LINE_SIZE_CB_SHIFT) & 0x7F) - 1; + return ((size << 3) + 32); +} + +/*----------------------------------------------------------------------------- + * gfx_get_valid_bit + *----------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +int gu3_get_valid_bit(int line) +#else +int gfx_get_valid_bit(int line) +#endif +{ + unsigned long lock; + unsigned long offset; + int valid; + + lock = READ_REG32 (DC3_UNLOCK); + offset = READ_REG32 (DC3_PHY_MEM_OFFSET) & 0xFF000000; + offset |= line; + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_PHY_MEM_OFFSET, offset); + WRITE_REG32 (DC3_UNLOCK, lock); + valid = (int)READ_REG32 (DC3_DV_ACC) & 2; + + if (valid) return 1; + return 0; +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_offset (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_offset". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_display_video_offset(void) +#else +unsigned long gfx_get_display_video_offset(void) +#endif +{ + return (READ_REG32(DC3_VID_Y_ST_OFFSET) & 0x0FFFFFFF); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_yuv_offsets (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_yuv_offsets". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_get_display_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset) +#else +void gfx_get_display_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset) +#endif +{ + *yoffset = (READ_REG32(DC3_VID_Y_ST_OFFSET) & 0x0FFFFFFF); + *uoffset = (READ_REG32(DC3_VID_U_ST_OFFSET) & 0x0FFFFFFF); + *voffset = (READ_REG32(DC3_VID_V_ST_OFFSET) & 0x0FFFFFFF); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_yuv_pitch (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_yuv_pitch". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +void gu3_get_display_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch) +#else +void gfx_get_display_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch) +#endif +{ + unsigned long pitch = READ_REG32 (DC3_VID_YUV_PITCH); + + *ypitch = ((pitch & 0xFFFF) << 3); + *uvpitch = (pitch >> 13) & 0x7FFF8; +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_size (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_size". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_display_video_size(void) +#else +unsigned long gfx_get_display_video_size(void) +#endif +{ + /* RETURN THE LINE SIZE, AS THIS IS ALL THAT IS AVAILABLE */ + /* Shift by three less to effect a multiply by 8. */ + + return((READ_REG32(DC3_LINE_SIZE) & DC3_LINE_SIZE_VLS_MASK) >> (DC3_LINE_SIZE_VB_SHIFT - 3)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_color_key (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_color_key". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_display_video_color_key(void) +#else +unsigned long gfx_get_display_video_color_key(void) +#endif +{ + return (READ_REG32 (DC3_COLOR_KEY) & 0xFFFFFF); +} + +/*--------------------------------------------------------------------------- + * gfx_get_display_video_color_key_mask (PRIVATE ROUTINE - NOT PART OF API) + * + * This routine is called by "gfx_get_video_color_key_mask". It abstracts the + * version of the display controller from the video overlay routines. + *--------------------------------------------------------------------------- + */ +#if GFX_DISPLAY_DYNAMIC +unsigned long gu3_get_display_video_color_key_mask(void) +#else +unsigned long gfx_get_display_video_color_key_mask(void) +#endif +{ + return (READ_REG32 (DC3_COLOR_MASK) & 0xFFFFFF); +} + +#endif /* GFX_READ_ROUTINES */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_tv.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/gfx_tv.c 2005-12-14 11:34:53.000000000 -0700 @@ -0,0 +1,751 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to program TVOUT and TV encoder. + * + * Routines: + * + * gfx_set_tv_format + * gfx_set_tv_output + * gfx_set_tv_enable + * gfx_set_tv_flicker_filter + * gfx_set_tv_sub_carrier_reset + * gfx_set_tv_vphase + * gfx_set_tv_YC_delay + * gfx_set_tvenc_reset_interval + * gfx_set_tv_cc_enable + * gfx_set_tv_cc_data + * gfx_test_tvout_odd_field + * gfx_test_tvenc_odd_field + * gfx_set_tv_field_status_invert + * gfx_get_tv_vphase + * */ + + +/* TV TIMINGS */ + +DISPLAYMODE TVTimings[] = { + +/* NTSC resolution */ + +{ 0x3 | /* negative syncs */ + GFX_MODE_TV_NTSC, /* NTSC format */ + 640, 640, 656, 744, 792, 792, /* horizontal timings */ + 480, 480, 490, 492, 517, 525, /* vertical timings */ + 0x0018EC4D, /* freq = 24.923052 MHz */ +}, + +/* PAL resolution */ + +{ 0x3 | /* negative syncs */ + GFX_MODE_TV_PAL, /* PAL format */ + 768, 768, 800, 848, 864, 864, /* horizontal timings */ + 576, 576, 586, 588, 625, 625, /* vertical timings */ + 0x001B0000, /* freq = 27.00 MHz */ +}, + +/* NTSC resolution non-square pixels */ + +{ 0x3 | /* negative syncs */ + GFX_MODE_TV_NTSC, /* NTSC format */ + 720, 720, 736, 752, 792, 792, /* horizontal timings */ + 480, 480, 490, 492, 517, 525, /* vertical timings */ + 0x0018EC4D, /* freq = 24.923052 MHz */ +}, + +/* PAL resolution non-square pixels */ + +{ 0x3 | /* negative syncs */ + GFX_MODE_TV_PAL, /* PAL format */ + 720, 720, 752, 816, 864, 864, /* horizontal timings */ + 576, 576, 586, 588, 625, 625, /* vertical timings */ + 0x001B0000, /* freq = 27.00 MHz */ +}}; + +#define NUM_TV_MODES sizeof(TVTimings)/sizeof(DISPLAYMODE) + +/* INCLUDE SUPPORT FOR SC1200 TV ENCODER, IF SPECIFIED */ + +#if GFX_TV_SC1200 +#include "tv_1200.c" +#endif + +/* INCLUDE SUPPORT FOR FS450 TV ENCODER, IF SPECIFIED */ + +#if GFX_TV_FS451 +#include "tv_fs450.c" +#endif + +/* WRAPPERS IF DYNAMIC SELECTION */ +/* Extra layer to call either SC1200 or FS450 TV encoder routines. */ + +#if GFX_TV_DYNAMIC + +/*----------------------------------------------------------------------------- + * gfx_set_tv_format + *----------------------------------------------------------------------------- + */ +int gfx_set_tv_format(TVStandardType format, GfxOnTVType resolution) +{ + int retval = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_set_tv_format(format, resolution); +#endif +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_tv_format(format, resolution); +#endif + return(retval); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_output + *----------------------------------------------------------------------------- + */ +int gfx_set_tv_output(int output) +{ + int retval = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_set_tv_output(output); +#endif +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_tv_output(output); +#endif + return(retval); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_enable + *----------------------------------------------------------------------------- + */ +int gfx_set_tv_enable(int enable) +{ + int retval = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_set_tv_enable(enable); +#endif +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_tv_enable(enable); +#endif + return(retval); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_flicker_filter + *----------------------------------------------------------------------------- + */ +int gfx_set_tv_flicker_filter(int ff) +{ + int retval = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_set_tv_flicker_filter(ff); +#endif + return(retval); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_sub_carrier_reset + *----------------------------------------------------------------------------- + */ +int gfx_set_tv_sub_carrier_reset(int screset) +{ + int retval = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_set_tv_sub_carrier_reset(screset); +#endif + return(retval); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_vphase + *----------------------------------------------------------------------------- + */ +int gfx_set_tv_vphase(int vphase) +{ + int retval = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_set_tv_vphase(vphase); +#endif + return(retval); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_YC_delay + *----------------------------------------------------------------------------- + */ +int gfx_set_tv_YC_delay(int delay) +{ + int retval = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_set_tv_YC_delay(delay); +#endif + return(retval); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tvenc_reset_interval + *----------------------------------------------------------------------------- + */ +int gfx_set_tvenc_reset_interval(int interval) +{ + int retval = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_set_tvenc_reset_interval(interval); +#endif + return(retval); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_cc_enable + *----------------------------------------------------------------------------- + */ +int gfx_set_tv_cc_enable(int enable) +{ + int retval = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_set_tv_cc_enable(enable); +#endif + return(retval); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_cc_data + * + * This routine writes the two specified characters to the CC data register + * of the TV encoder. + *----------------------------------------------------------------------------- + */ +int gfx_set_tv_cc_data(unsigned char data1, unsigned char data2) +{ + int retval = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_set_tv_cc_data(data1, data2); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_set_tv_display + * + * Set the timings in the display controller to support a TV resolution. + *--------------------------------------------------------------------------- + */ +int gfx_set_tv_display(int width, int height) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + status = sc1200_set_tv_display(width, height); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_test_tvout_odd_field + *--------------------------------------------------------------------------- + */ +int gfx_test_tvout_odd_field(void) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + status = sc1200_test_tvout_odd_field(); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_test_tvenc_odd_field + *--------------------------------------------------------------------------- + */ +int gfx_test_tvenc_odd_field(void) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + status = sc1200_test_tvenc_odd_field(); +#endif + return(status); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_field_status_invert + *----------------------------------------------------------------------------- + */ +int gfx_set_tv_field_status_invert(int enable) +{ + int retval = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_set_tv_field_status_invert(enable); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_get_tv_vphase + *--------------------------------------------------------------------------- + */ +int gfx_get_tv_vphase(void) +{ + int status = GFX_STATUS_UNSUPPORTED; +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + status = sc1200_get_tv_vphase(); +#endif + return(status); +} + +/*--------------------------------------------------------------------------- + * gfx_get_tv_enable + *--------------------------------------------------------------------------- + */ +int gfx_get_tv_enable(unsigned int *p_on) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_tv_enable( p_on); +#endif +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_get_tv_enable(p_on); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_get_tv_output + *--------------------------------------------------------------------------- + */ +int gfx_get_tv_output() +{ + int retval = -1; + +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_get_tv_output(); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_get_tv_mode_count + *--------------------------------------------------------------------------- + */ +int gfx_get_tv_mode_count(TVStandardType format) +{ + int retval = -1; + +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_get_tv_mode_count (format); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_get_tv_display_mode + *--------------------------------------------------------------------------- + */ +int gfx_get_tv_display_mode (int *width, int *height, int *bpp, int *hz) +{ + int retval = -1; + +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_get_tv_display_mode (width, height, bpp, hz); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_get_tv_display_mode_frequency + *--------------------------------------------------------------------------- + */ +int gfx_get_tv_display_mode_frequency (unsigned short width, unsigned short height, + TVStandardType format, int *frequency) +{ + int retval = -1; + +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_get_tv_display_mode_frequency (width, height, format, frequency); +#endif + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_is_tv_display_mode_supported + *--------------------------------------------------------------------------- + */ +int gfx_is_tv_display_mode_supported (unsigned short width, unsigned short height, TVStandardType format) +{ + int retval = -1; + +#if GFX_TV_SC1200 + if (gfx_tv_type & GFX_TV_TYPE_SC1200) + retval = sc1200_is_tv_display_mode_supported (width, height, format); +#endif + return(retval); +} + +/*------------------------------------------ + * The following functions were added to support + * the FS450 and will eventually be removed. There + * is no equivalent support in the SC1200. + *----------------------------------------------*/ + + +/* + * ========================================================================== + * + * TV standard +*/ + +int gfx_get_tv_standard(unsigned long *p_standard) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_tv_standard( p_standard); +#endif + return(retval); +} + +int gfx_get_available_tv_standards(unsigned long *p_standards) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_available_tv_standards( p_standards); +#endif + return(retval); +} + +int gfx_set_tv_standard(unsigned long standard) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_tv_standard(standard); +#endif + return(retval); +} + +/* +// ========================================================================== +// +// vga mode as known by the driver +*/ + +int gfx_get_tv_vga_mode(unsigned long *p_vga_mode) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_tv_vga_mode(p_vga_mode); +#endif + return(retval); +} + +int gfx_get_available_tv_vga_modes(unsigned long *p_vga_modes) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_available_tv_vga_modes(p_vga_modes); +#endif + return(retval); +} + +int gfx_set_tv_vga_mode(unsigned long vga_mode) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_tv_vga_mode(vga_mode); +#endif + return(retval); +} + + +/* +// ========================================================================== +// +// tvout mode +*/ + +int gfx_get_tvout_mode(unsigned long *p_tvout_mode) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_tvout_mode(p_tvout_mode); +#endif + return(retval); +} + +int gfx_set_tvout_mode(unsigned long tvout_mode) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_tvout_mode(tvout_mode); +#endif + return(retval); +} + +/* +// ========================================================================== +// +// Sharpness +*/ +int gfx_get_sharpness(int *p_sharpness) + +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_sharpness(p_sharpness); +#endif + return(retval); +} + +int gfx_set_sharpness(int sharpness) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_sharpness(sharpness); +#endif + return(retval); +} + +/* +// ========================================================================== +// +// flicker filter control. +*/ + +int gfx_get_flicker_filter(int *p_flicker) + +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_flicker_filter(p_flicker); +#endif + return(retval); +} + +int gfx_set_flicker_filter(int flicker) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_flicker_filter(flicker); +#endif + return(retval); +} + +/* +// ========================================================================== +// +// Overscan and Position +*/ + +int gfx_get_overscan(int *p_x, int *p_y) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_overscan(p_x, p_y); +#endif + return(retval); + +} + +int gfx_set_overscan(int x, int y) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_overscan(x, y); +#endif + return(retval); +} + +int gfx_get_position(int *p_x, int *p_y) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_position(p_x, p_y); +#endif + return(retval); +} + +int gfx_set_position(int x, int y) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_position(x, y); +#endif + return(retval); +} + +/* +// ========================================================================== +// +// Color, Brightness, and Contrast +*/ + +int gfx_get_color(int *p_color) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_color(p_color); +#endif + return(retval); +} + +int gfx_set_color(int color) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_color(color); +#endif + return(retval); +} + +int gfx_get_brightness(int *p_brightness) + +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_brightness(p_brightness); +#endif + return(retval); +} + +int gfx_set_brightness(int brightness) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_brightness(brightness); +#endif + return(retval); +} + +int gfx_get_contrast(int *p_contrast) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_contrast(p_contrast); +#endif + return(retval); +} + +int gfx_set_contrast(int contrast) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_contrast(contrast); +#endif + return(retval); +} + +/* +// ========================================================================== +// +// YC filters +*/ + +int gfx_get_yc_filter(unsigned int *p_yc_filter) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_yc_filter(p_yc_filter); +#endif + return(retval); +} + +int gfx_set_yc_filter(unsigned int yc_filter) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_yc_filter(yc_filter); +#endif + return(retval); +} + +int gfx_get_aps_trigger_bits(unsigned int *p_trigger_bits) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_get_aps_trigger_bits(p_trigger_bits); +#endif + return(retval); +} + +int gfx_set_aps_trigger_bits(unsigned int trigger_bits) +{ + int retval = -1; +#if GFX_TV_FS451 + if (gfx_tv_type & GFX_TV_TYPE_FS451) + retval = fs450_set_aps_trigger_bits(trigger_bits); +#endif + return(retval); +} + +#endif /* GFX_TV_DYNAMIC */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/vid_cstl.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/vid_cstl.c 2005-12-14 11:28:37.000000000 -0700 @@ -0,0 +1,2424 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + +/* DEFAULT FILTER COEFFICIENTS */ + +long DurangoVideoFilter[][2] = +{ + { 0x10000000, 0x00000000 }, /* 0, 4096, 0, 0 */ + { 0x10008008, 0x00000008 }, /* -8, 4096, 8, 0 */ + { 0x10008010, 0x80010011 }, /* -16, 4096, 17, -1 */ + { 0x10008019, 0x8001001A }, /* -25, 4096, 26, -1 */ + { 0x10008021, 0x80020023 }, /* -33, 4096, 35, -2 */ + { 0x0FFF8029, 0x8003002D }, /* -41, 4095, 45, -3 */ + { 0x0FFE8031, 0x80030036 }, /* -49, 4094, 54, -3 */ + { 0x0FFC8038, 0x80040040 }, /* -56, 4092, 64, -4 */ + { 0x0FFB8040, 0x8005004A }, /* -64, 4091, 74, -5 */ + { 0x0FF88047, 0x80050054 }, /* -71, 4088, 84, -5 */ + { 0x0FF6804E, 0x8006005E }, /* -78, 4086, 94, -6 */ + { 0x0FF48055, 0x80070068 }, /* -85, 4084, 104, -7 */ + { 0x0FF0805C, 0x80070073 }, /* -92, 4080, 115, -7 */ + { 0x0FEE8063, 0x8008007D }, /* -99, 4078, 125, -8 */ + { 0x0FEA8069, 0x80090088 }, /* -105, 4074, 136, -9 */ + { 0x0FE78070, 0x800A0093 }, /* -112, 4071, 147, -10 */ + { 0x0FE28076, 0x800A009E }, /* -118, 4066, 158, -10 */ + { 0x0FDD807C, 0x800B00AA }, /* -124, 4061, 170, -11 */ + { 0x0FD98082, 0x800C00B5 }, /* -130, 4057, 181, -12 */ + { 0x0FD48088, 0x800D00C1 }, /* -136, 4052, 193, -13 */ + { 0x0FCE808E, 0x800D00CD }, /* -142, 4046, 205, -13 */ + { 0x0FC88093, 0x800E00D9 }, /* -147, 4040, 217, -14 */ + { 0x0FC38099, 0x800F00E5 }, /* -153, 4035, 229, -15 */ + { 0x0FBD809E, 0x801000F1 }, /* -158, 4029, 241, -16 */ + { 0x0FB680A3, 0x801000FD }, /* -163, 4022, 253, -16 */ + { 0x0FAF80A8, 0x8011010A }, /* -168, 4015, 266, -17 */ + { 0x0FA880AD, 0x80120117 }, /* -173, 4008, 279, -18 */ + { 0x0FA180B2, 0x80130124 }, /* -178, 4001, 292, -19 */ + { 0x0F9980B6, 0x80140131 }, /* -182, 3993, 305, -20 */ + { 0x0F9280BB, 0x8015013E }, /* -187, 3986, 318, -21 */ + { 0x0F8880BF, 0x8015014C }, /* -191, 3976, 332, -21 */ + { 0x0F8080C3, 0x80160159 }, /* -195, 3968, 345, -22 */ + { 0x0F7880C8, 0x80170167 }, /* -200, 3960, 359, -23 */ + { 0x0F6E80CB, 0x80180175 }, /* -203, 3950, 373, -24 */ + { 0x0F6580CF, 0x80190183 }, /* -207, 3941, 387, -25 */ + { 0x0F5C80D3, 0x801A0191 }, /* -211, 3932, 401, -26 */ + { 0x0F5280D7, 0x801B01A0 }, /* -215, 3922, 416, -27 */ + { 0x0F4880DA, 0x801C01AE }, /* -218, 3912, 430, -28 */ + { 0x0F3D80DD, 0x801D01BD }, /* -221, 3901, 445, -29 */ + { 0x0F3280E0, 0x801E01CC }, /* -224, 3890, 460, -30 */ + { 0x0F2880E4, 0x801F01DB }, /* -228, 3880, 475, -31 */ + { 0x0F1C80E6, 0x802001EA }, /* -230, 3868, 490, -32 */ + { 0x0F1180E9, 0x802101F9 }, /* -233, 3857, 505, -33 */ + { 0x0F0480EB, 0x80210208 }, /* -235, 3844, 520, -33 */ + { 0x0EFA80EF, 0x80230218 }, /* -239, 3834, 536, -35 */ + { 0x0EEC80F0, 0x80230227 }, /* -240, 3820, 551, -35 */ + { 0x0EE080F3, 0x80240237 }, /* -243, 3808, 567, -36 */ + { 0x0ED380F5, 0x80250247 }, /* -245, 3795, 583, -37 */ + { 0x0EC780F7, 0x80270257 }, /* -247, 3783, 599, -39 */ + { 0x0EB980F9, 0x80280268 }, /* -249, 3769, 616, -40 */ + { 0x0EAC80FB, 0x80290278 }, /* -251, 3756, 632, -41 */ + { 0x0E9E80FD, 0x802A0289 }, /* -253, 3742, 649, -42 */ + { 0x0E9080FE, 0x802B0299 }, /* -254, 3728, 665, -43 */ + { 0x0E838100, 0x802D02AA }, /* -256, 3715, 682, -45 */ + { 0x0E758102, 0x802E02BB }, /* -258, 3701, 699, -46 */ + { 0x0E668103, 0x802F02CC }, /* -259, 3686, 716, -47 */ + { 0x0E568104, 0x803002DE }, /* -260, 3670, 734, -48 */ + { 0x0E498106, 0x803202EF }, /* -262, 3657, 751, -50 */ + { 0x0E398107, 0x80330301 }, /* -263, 3641, 769, -51 */ + { 0x0E298108, 0x80340313 }, /* -264, 3625, 787, -52 */ + { 0x0E1A8109, 0x80360325 }, /* -265, 3610, 805, -54 */ + { 0x0E0B810A, 0x80370336 }, /* -266, 3595, 822, -55 */ + { 0x0DFA810A, 0x80380348 }, /* -266, 3578, 840, -56 */ + { 0x0DEA810B, 0x803A035B }, /* -267, 3562, 859, -58 */ + { 0x0DDA810C, 0x803B036D }, /* -268, 3546, 877, -59 */ + { 0x0DCA810C, 0x803D037F }, /* -268, 3530, 895, -61 */ + { 0x0DB7810B, 0x803E0392 }, /* -267, 3511, 914, -62 */ + { 0x0DA7810C, 0x804003A5 }, /* -268, 3495, 933, -64 */ + { 0x0D95810C, 0x804103B8 }, /* -268, 3477, 952, -65 */ + { 0x0D85810C, 0x804303CA }, /* -268, 3461, 970, -67 */ + { 0x0D73810C, 0x804403DD }, /* -268, 3443, 989, -68 */ + { 0x0D61810C, 0x804603F1 }, /* -268, 3425, 1009, -70 */ + { 0x0D50810C, 0x80480404 }, /* -268, 3408, 1028, -72 */ + { 0x0D3E810C, 0x80490417 }, /* -268, 3390, 1047, -73 */ + { 0x0D2C810C, 0x804B042B }, /* -268, 3372, 1067, -75 */ + { 0x0D1B810C, 0x804D043E }, /* -268, 3355, 1086, -77 */ + { 0x0D07810B, 0x804E0452 }, /* -267, 3335, 1106, -78 */ + { 0x0CF5810B, 0x80500466 }, /* -267, 3317, 1126, -80 */ + { 0x0CE2810A, 0x8052047A }, /* -266, 3298, 1146, -82 */ + { 0x0CCF810A, 0x8053048E }, /* -266, 3279, 1166, -83 */ + { 0x0CBC8109, 0x805504A2 }, /* -265, 3260, 1186, -85 */ + { 0x0CA98108, 0x805704B6 }, /* -264, 3241, 1206, -87 */ + { 0x0C968108, 0x805904CB }, /* -264, 3222, 1227, -89 */ + { 0x0C838107, 0x805B04DF }, /* -263, 3203, 1247, -91 */ + { 0x0C6F8106, 0x805C04F3 }, /* -262, 3183, 1267, -92 */ + { 0x0C5B8105, 0x805E0508 }, /* -261, 3163, 1288, -94 */ + { 0x0C478104, 0x8060051D }, /* -260, 3143, 1309, -96 */ + { 0x0C348103, 0x80620531 }, /* -259, 3124, 1329, -98 */ + { 0x0C1F8102, 0x80640547 }, /* -258, 3103, 1351, -100 */ + { 0x0C0C8101, 0x8066055B }, /* -257, 3084, 1371, -102 */ + { 0x0BF88100, 0x80680570 }, /* -256, 3064, 1392, -104 */ + { 0x0BE380FE, 0x806A0585 }, /* -254, 3043, 1413, -106 */ + { 0x0BCF80FD, 0x806C059A }, /* -253, 3023, 1434, -108 */ + { 0x0BBA80FC, 0x806E05B0 }, /* -252, 3002, 1456, -110 */ + { 0x0BA480F9, 0x807005C5 }, /* -249, 2980, 1477, -112 */ + { 0x0B8F80F8, 0x807205DB }, /* -248, 2959, 1499, -114 */ + { 0x0B7A80F6, 0x807405F0 }, /* -246, 2938, 1520, -116 */ + { 0x0B6580F5, 0x80760606 }, /* -245, 2917, 1542, -118 */ + { 0x0B4F80F3, 0x8077061B }, /* -243, 2895, 1563, -119 */ + { 0x0B3A80F2, 0x80790631 }, /* -242, 2874, 1585, -121 */ + { 0x0B2480F0, 0x807B0647 }, /* -240, 2852, 1607, -123 */ + { 0x0B0F80EE, 0x807D065C }, /* -238, 2831, 1628, -125 */ + { 0x0AF980ED, 0x807F0673 }, /* -237, 2809, 1651, -127 */ + { 0x0AE480EB, 0x80810688 }, /* -235, 2788, 1672, -129 */ + { 0x0ACE80E9, 0x8084069F }, /* -233, 2766, 1695, -132 */ + { 0x0AB980E7, 0x808606B4 }, /* -231, 2745, 1716, -134 */ + { 0x0AA380E6, 0x808806CB }, /* -230, 2723, 1739, -136 */ + { 0x0A8D80E4, 0x808A06E1 }, /* -228, 2701, 1761, -138 */ + { 0x0A7780E2, 0x808C06F7 }, /* -226, 2679, 1783, -140 */ + { 0x0A6180E0, 0x808E070D }, /* -224, 2657, 1805, -142 */ + { 0x0A4B80DE, 0x80910724 }, /* -222, 2635, 1828, -145 */ + { 0x0A3580DC, 0x8093073A }, /* -220, 2613, 1850, -147 */ + { 0x0A1F80DA, 0x80950750 }, /* -218, 2591, 1872, -149 */ + { 0x0A0880D8, 0x80970767 }, /* -216, 2568, 1895, -151 */ + { 0x09F280D6, 0x8099077D }, /* -214, 2546, 1917, -153 */ + { 0x09DD80D4, 0x809C0793 }, /* -212, 2525, 1939, -156 */ + { 0x09C680D2, 0x809E07AA }, /* -210, 2502, 1962, -158 */ + { 0x09B080D0, 0x80A007C0 }, /* -208, 2480, 1984, -160 */ + { 0x099980CE, 0x80A207D7 }, /* -206, 2457, 2007, -162 */ + { 0x098380CB, 0x80A507ED }, /* -203, 2435, 2029, -165 */ + { 0x096C80C9, 0x80A70804 }, /* -201, 2412, 2052, -167 */ + { 0x095680C7, 0x80A9081A }, /* -199, 2390, 2074, -169 */ + { 0x094080C5, 0x80AB0830 }, /* -197, 2368, 2096, -171 */ + { 0x092980C3, 0x80AE0848 }, /* -195, 2345, 2120, -174 */ + { 0x091380C1, 0x80B0085E }, /* -193, 2323, 2142, -176 */ + { 0x08FC80BE, 0x80B20874 }, /* -190, 2300, 2164, -178 */ + { 0x08E580BC, 0x80B4088B }, /* -188, 2277, 2187, -180 */ + { 0x08D080BB, 0x80B708A2 }, /* -187, 2256, 2210, -183 */ + { 0x08B980B9, 0x80B908B9 }, /* -185, 2233, 2233, -185 */ + { 0x08A380B7, 0x80BB08CF }, /* -183, 2211, 2255, -187 */ + { 0x088B80B4, 0x80BC08E5 }, /* -180, 2187, 2277, -188 */ + { 0x087480B2, 0x80BE08FC }, /* -178, 2164, 2300, -190 */ + { 0x085E80B0, 0x80C10913 }, /* -176, 2142, 2323, -193 */ + { 0x084880AE, 0x80C30929 }, /* -174, 2120, 2345, -195 */ + { 0x083080AB, 0x80C50940 }, /* -171, 2096, 2368, -197 */ + { 0x081A80A9, 0x80C70956 }, /* -169, 2074, 2390, -199 */ + { 0x080480A7, 0x80C9096C }, /* -167, 2052, 2412, -201 */ + { 0x07ED80A5, 0x80CB0983 }, /* -165, 2029, 2435, -203 */ + { 0x07D780A2, 0x80CE0999 }, /* -162, 2007, 2457, -206 */ + { 0x07C080A0, 0x80D009B0 }, /* -160, 1984, 2480, -208 */ + { 0x07AA809E, 0x80D209C6 }, /* -158, 1962, 2502, -210 */ + { 0x0793809C, 0x80D409DD }, /* -156, 1939, 2525, -212 */ + { 0x077D8099, 0x80D609F2 }, /* -153, 1917, 2546, -214 */ + { 0x07668097, 0x80D80A09 }, /* -151, 1894, 2569, -216 */ + { 0x074F8095, 0x80DA0A20 }, /* -149, 1871, 2592, -218 */ + { 0x073A8093, 0x80DC0A35 }, /* -147, 1850, 2613, -220 */ + { 0x07238091, 0x80DE0A4C }, /* -145, 1827, 2636, -222 */ + { 0x070C808E, 0x80E00A62 }, /* -142, 1804, 2658, -224 */ + { 0x06F7808C, 0x80E20A77 }, /* -140, 1783, 2679, -226 */ + { 0x06E0808A, 0x80E40A8E }, /* -138, 1760, 2702, -228 */ + { 0x06CA8088, 0x80E60AA4 }, /* -136, 1738, 2724, -230 */ + { 0x06B48086, 0x80E70AB9 }, /* -134, 1716, 2745, -231 */ + { 0x069E8084, 0x80E90ACF }, /* -132, 1694, 2767, -233 */ + { 0x06878081, 0x80EB0AE5 }, /* -129, 1671, 2789, -235 */ + { 0x0672807F, 0x80ED0AFA }, /* -127, 1650, 2810, -237 */ + { 0x065C807D, 0x80EE0B0F }, /* -125, 1628, 2831, -238 */ + { 0x0646807B, 0x80F00B25 }, /* -123, 1606, 2853, -240 */ + { 0x06308079, 0x80F20B3B }, /* -121, 1584, 2875, -242 */ + { 0x061A8077, 0x80F30B50 }, /* -119, 1562, 2896, -243 */ + { 0x06068076, 0x80F50B65 }, /* -118, 1542, 2917, -245 */ + { 0x05F08074, 0x80F60B7A }, /* -116, 1520, 2938, -246 */ + { 0x05DB8072, 0x80F80B8F }, /* -114, 1499, 2959, -248 */ + { 0x05C58070, 0x80F90BA4 }, /* -112, 1477, 2980, -249 */ + { 0x05B1806E, 0x80FC0BB9 }, /* -110, 1457, 3001, -252 */ + { 0x059B806C, 0x80FD0BCE }, /* -108, 1435, 3022, -253 */ + { 0x0586806A, 0x80FE0BE2 }, /* -106, 1414, 3042, -254 */ + { 0x05718068, 0x81000BF7 }, /* -104, 1393, 3063, -256 */ + { 0x055C8066, 0x81010C0B }, /* -102, 1372, 3083, -257 */ + { 0x05478064, 0x81020C1F }, /* -100, 1351, 3103, -258 */ + { 0x05328062, 0x81030C33 }, /* -98, 1330, 3123, -259 */ + { 0x051D8060, 0x81040C47 }, /* -96, 1309, 3143, -260 */ + { 0x0508805E, 0x81050C5B }, /* -94, 1288, 3163, -261 */ + { 0x04F3805C, 0x81060C6F }, /* -92, 1267, 3183, -262 */ + { 0x04E0805B, 0x81070C82 }, /* -91, 1248, 3202, -263 */ + { 0x04CB8059, 0x81080C96 }, /* -89, 1227, 3222, -264 */ + { 0x04B68057, 0x81080CA9 }, /* -87, 1206, 3241, -264 */ + { 0x04A28055, 0x81090CBC }, /* -85, 1186, 3260, -265 */ + { 0x048E8053, 0x810A0CCF }, /* -83, 1166, 3279, -266 */ + { 0x047A8052, 0x810A0CE2 }, /* -82, 1146, 3298, -266 */ + { 0x04668050, 0x810B0CF5 }, /* -80, 1126, 3317, -267 */ + { 0x0451804E, 0x810B0D08 }, /* -78, 1105, 3336, -267 */ + { 0x043E804D, 0x810C0D1B }, /* -77, 1086, 3355, -268 */ + { 0x042B804B, 0x810C0D2C }, /* -75, 1067, 3372, -268 */ + { 0x04178049, 0x810C0D3E }, /* -73, 1047, 3390, -268 */ + { 0x04038048, 0x810C0D51 }, /* -72, 1027, 3409, -268 */ + { 0x03F08046, 0x810C0D62 }, /* -70, 1008, 3426, -268 */ + { 0x03DD8044, 0x810C0D73 }, /* -68, 989, 3443, -268 */ + { 0x03CA8043, 0x810C0D85 }, /* -67, 970, 3461, -268 */ + { 0x03B78041, 0x810C0D96 }, /* -65, 951, 3478, -268 */ + { 0x03A48040, 0x810C0DA8 }, /* -64, 932, 3496, -268 */ + { 0x0391803E, 0x810B0DB8 }, /* -62, 913, 3512, -267 */ + { 0x0380803D, 0x810C0DC9 }, /* -61, 896, 3529, -268 */ + { 0x036D803B, 0x810C0DDA }, /* -59, 877, 3546, -268 */ + { 0x035B803A, 0x810B0DEA }, /* -58, 859, 3562, -267 */ + { 0x03488038, 0x810A0DFA }, /* -56, 840, 3578, -266 */ + { 0x03368037, 0x810A0E0B }, /* -55, 822, 3595, -266 */ + { 0x03248036, 0x81090E1B }, /* -54, 804, 3611, -265 */ + { 0x03128034, 0x81080E2A }, /* -52, 786, 3626, -264 */ + { 0x03018033, 0x81070E39 }, /* -51, 769, 3641, -263 */ + { 0x02EF8032, 0x81060E49 }, /* -50, 751, 3657, -262 */ + { 0x02DE8030, 0x81040E56 }, /* -48, 734, 3670, -260 */ + { 0x02CC802F, 0x81030E66 }, /* -47, 716, 3686, -259 */ + { 0x02BB802E, 0x81020E75 }, /* -46, 699, 3701, -258 */ + { 0x02AA802D, 0x81000E83 }, /* -45, 682, 3715, -256 */ + { 0x0299802B, 0x80FE0E90 }, /* -43, 665, 3728, -254 */ + { 0x0288802A, 0x80FD0E9F }, /* -42, 648, 3743, -253 */ + { 0x02778029, 0x80FB0EAD }, /* -41, 631, 3757, -251 */ + { 0x02678028, 0x80F90EBA }, /* -40, 615, 3770, -249 */ + { 0x02568027, 0x80F70EC8 }, /* -39, 598, 3784, -247 */ + { 0x02468025, 0x80F50ED4 }, /* -37, 582, 3796, -245 */ + { 0x02368024, 0x80F30EE1 }, /* -36, 566, 3809, -243 */ + { 0x02268023, 0x80F00EED }, /* -35, 550, 3821, -240 */ + { 0x02188023, 0x80EF0EFA }, /* -35, 536, 3834, -239 */ + { 0x02078021, 0x80EB0F05 }, /* -33, 519, 3845, -235 */ + { 0x01F98021, 0x80E90F11 }, /* -33, 505, 3857, -233 */ + { 0x01EA8020, 0x80E60F1C }, /* -32, 490, 3868, -230 */ + { 0x01DC801F, 0x80E40F27 }, /* -31, 476, 3879, -228 */ + { 0x01CD801E, 0x80E00F31 }, /* -30, 461, 3889, -224 */ + { 0x01BE801D, 0x80DD0F3C }, /* -29, 446, 3900, -221 */ + { 0x01AF801C, 0x80DA0F47 }, /* -28, 431, 3911, -218 */ + { 0x01A1801B, 0x80D70F51 }, /* -27, 417, 3921, -215 */ + { 0x0192801A, 0x80D30F5B }, /* -26, 402, 3931, -211 */ + { 0x01848019, 0x80CF0F64 }, /* -25, 388, 3940, -207 */ + { 0x01768018, 0x80CB0F6D }, /* -24, 374, 3949, -203 */ + { 0x01688017, 0x80C80F77 }, /* -23, 360, 3959, -200 */ + { 0x015A8016, 0x80C30F7F }, /* -22, 346, 3967, -195 */ + { 0x014D8015, 0x80BF0F87 }, /* -21, 333, 3975, -191 */ + { 0x013F8015, 0x80BB0F91 }, /* -21, 319, 3985, -187 */ + { 0x01328014, 0x80B60F98 }, /* -20, 306, 3992, -182 */ + { 0x01258013, 0x80B20FA0 }, /* -19, 293, 4000, -178 */ + { 0x01188012, 0x80AD0FA7 }, /* -18, 280, 4007, -173 */ + { 0x010B8011, 0x80A80FAE }, /* -17, 267, 4014, -168 */ + { 0x00FE8010, 0x80A30FB5 }, /* -16, 254, 4021, -163 */ + { 0x00F28010, 0x809E0FBC }, /* -16, 242, 4028, -158 */ + { 0x00E6800F, 0x80990FC2 }, /* -15, 230, 4034, -153 */ + { 0x00DA800E, 0x80930FC7 }, /* -14, 218, 4039, -147 */ + { 0x00CE800D, 0x808E0FCD }, /* -13, 206, 4045, -142 */ + { 0x00C2800D, 0x80880FD3 }, /* -13, 194, 4051, -136 */ + { 0x00B6800C, 0x80820FD8 }, /* -12, 182, 4056, -130 */ + { 0x00AB800B, 0x807C0FDC }, /* -11, 171, 4060, -124 */ + { 0x009F800A, 0x80760FE1 }, /* -10, 159, 4065, -118 */ + { 0x0094800A, 0x80700FE6 }, /* -10, 148, 4070, -112 */ + { 0x00898009, 0x80690FE9 }, /* -9, 137, 4073, -105 */ + { 0x007E8008, 0x80630FED }, /* -8, 126, 4077, -99 */ + { 0x00748007, 0x805C0FEF }, /* -7, 116, 4079, -92 */ + { 0x00698007, 0x80550FF3 }, /* -7, 105, 4083, -85 */ + { 0x005F8006, 0x804E0FF5 }, /* -6, 95, 4085, -78 */ + { 0x00558005, 0x80470FF7 }, /* -5, 85, 4087, -71 */ + { 0x004B8005, 0x80400FFA }, /* -5, 75, 4090, -64 */ + { 0x00418004, 0x80380FFB }, /* -4, 65, 4091, -56 */ + { 0x00378003, 0x80310FFD }, /* -3, 55, 4093, -49 */ + { 0x002E8003, 0x80290FFE }, /* -3, 46, 4094, -41 */ + { 0x00238002, 0x80211000 }, /* -2, 35, 4096, -33 */ + { 0x001A8001, 0x80191000 }, /* -1, 26, 4096, -25 */ + { 0x00118001, 0x80101000 }, /* -1, 17, 4096, -16 */ + { 0x00080000, 0x80081000 }, /* 0, 8, 4096, -8 */ +}; + +/* CASTLE PLL TABLE */ + +typedef struct tagCASTLEPLL +{ + long frequency; /* 16.16 fixed point frequency */ + unsigned long pll_value; /* MCP DotPLL Register Upper 32(0x0015) */ +} CASTLEPLLENTRY; + +CASTLEPLLENTRY CASTLE_PLLtable[] = { + { 0x00192CCC, 0x0000215D }, /* 25.1750 */ + { 0x001C526E, 0x0000216C }, /* 28.3220 */ + { 0x001C8F5C, 0x0000218D }, /* 28.5600 */ + { 0x001F8000, 0x00003147 }, /* 31.5000 */ + { 0x00240000, 0x00000057 }, /* 36.0000 */ + { 0x0025E395, 0x0000219A }, /* 37.8890 */ + { 0x00280000, 0x00000045 }, /* 40.0000 */ + { 0x002B29BA, 0x00000089 }, /* 43.1630 */ + { 0x002CE666, 0x000010E7 }, /* 44.9000 */ + { 0x002DB851, 0x00002136 }, /* 45.7200 */ + { 0x00318000, 0x00003207 }, /* 49.5000 */ + { 0x00320000, 0x00002187 }, /* 50.0000 */ + { 0x00384000, 0x00004286 }, /* 56.2500 */ + { 0x003C10A3, 0x000010E5 }, /* 60.0650 */ + { 0x00410000, 0x00004214 }, /* 65.0000 */ + { 0x00442DD2, 0x00001105 }, /* 68.1790 */ + { 0x004B0000, 0x00003183 }, /* 75.0000 */ + { 0x004EC000, 0x00004284 }, /* 78.7500 */ + { 0x00519999, 0x00001104 }, /* 81.6000 */ + { 0x005E8000, 0x00006363 }, /* 94.5000 */ + { 0x00618560, 0x00005303 }, /* 97.5200 */ + { 0x00630000, 0x00002523 }, /* 99.0000 */ + { 0x00640000, 0x000000D1 }, /* 100.0000 */ + { 0x00642FDF, 0x00002183 }, /* 100.1870 */ + { 0x00656B85, 0x00002122 }, /* 101.4200 */ + { 0x006C0000, 0x00001081 }, /* 108.0000 */ + { 0x00708000, 0x000013E3 }, /* 112.5000 */ + { 0x00714F1A, 0x00006201 }, /* 113.3090 */ + { 0x0077A666, 0x00000041 }, /* 119.6500 */ + { 0x00806666, 0x00000072 }, /* 128.4000 */ + { 0x00821999, 0x00006382 }, /* 130.1000 */ + { 0x00858000, 0x00002182 }, /* 133.5000 */ + { 0x00870000, 0x000041B1 }, /* 135.0000 */ + { 0x00906147, 0x00000051 }, /* 144.3800 */ + { 0x009D8000, 0x000062D1 }, /* 157.5000 */ + { 0x00A20000, 0x000031A1 }, /* 162.0000 */ + { 0x00A933F7, 0x00000061 }, /* 169.2030 */ + { 0x00AF8000, 0x00002151 }, /* 175.5000 */ + { 0x00BD0000, 0x000052E1 }, /* 189.0000 */ + { 0x00BEF5C2, 0x00000071 }, /* 190.9600 */ + { 0x00C60000, 0x00003201 }, /* 198.0000 */ + { 0x00CA8000, 0x00004291 }, /* 202.5000 */ + { 0x00E58000, 0x00004170 }, /* 229.5000 */ +}; + +#define NUM_CASTLE_FREQUENCIES sizeof(CASTLE_PLLtable)/sizeof(CASTLEPLLENTRY) + + +/*--------------------------------------------------------------------------- + * gfx_reset_video (PRIVATE ROUTINE: NOT PART OF DURANGO API) + * + * This routine is used to disable all components of video overlay before + * performing a mode switch. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void castle_reset_video(void) +#else +void gfx_reset_video(void) +#endif +{ + gfx_set_video_enable(0); + gfx_select_alpha_region(1); + gfx_set_alpha_enable(0); + gfx_select_alpha_region(2); + gfx_set_alpha_enable(0); + + /* SET REGION 0 AFTER RESET */ + + gfx_select_alpha_region(0); + gfx_set_alpha_enable(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_display_control (PRIVATE ROUTINE: NOT PART OF DURANGO API) + * + * This routine configures the display output. + * + * "sync_polarities" is used to set the polarities of the sync pulses according + * to the following mask: + * + * Bit 0: If set to 1, negative horizontal polarity is programmed, + * otherwise positive horizontal polarity is programmed. + * Bit 1: If set to 1, negative vertical polarity is programmed, + * otherwise positive vertical polarity is programmed. + * + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_display_control(int sync_polarities) +#else +int gfx_set_display_control(int sync_polarities) +#endif +{ + unsigned long power; + unsigned long dcfg; + + /* CONFIGURE DISPLAY OUTPUT FROM VIDEO PROCESSOR */ + + dcfg = READ_VID32(CASTLE_DISPLAY_CONFIG); + dcfg &= ~(CASTLE_DCFG_CRT_SYNC_SKW_MASK | CASTLE_DCFG_PWR_SEQ_DLY_MASK | + CASTLE_DCFG_CRT_HSYNC_POL | CASTLE_DCFG_CRT_VSYNC_POL); + + dcfg |= (CASTLE_DCFG_CRT_SYNC_SKW_INIT | + CASTLE_DCFG_PWR_SEQ_DLY_INIT | + CASTLE_DCFG_GV_PAL_BYP); + + if (PanelEnable) + { + power = READ_VID32 (CASTLE_POWER_MANAGEMENT); + power |= CASTLE_PM_PANEL_POWER_ON; + WRITE_VID32 (CASTLE_POWER_MANAGEMENT, power); + } + + /* SET APPROPRIATE SYNC POLARITIES */ + + if (sync_polarities & 0x1) + dcfg |= CASTLE_DCFG_CRT_HSYNC_POL; + if (sync_polarities & 0x2) + dcfg |= CASTLE_DCFG_CRT_VSYNC_POL; + + WRITE_VID32 (CASTLE_DISPLAY_CONFIG, dcfg); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_clock_frequency + * + * This routine sets the clock frequency, specified as a 16.16 fixed point + * value (0x00318000 = 49.5 MHz). It will set the closest frequency found + * in the lookup table. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void castle_set_clock_frequency(unsigned long frequency) +#else +void gfx_set_clock_frequency(unsigned long frequency) +#endif +{ + Q_WORD msr_value; + unsigned int i, index = 0; + unsigned long value; + unsigned long unlock; + long timeout; + long min, diff; + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + + value = CASTLE_PLLtable[0].pll_value; + min = (long) CASTLE_PLLtable[0].frequency - frequency; + if (min < 0L) min = -min; + for (i = 1; i < NUM_CASTLE_FREQUENCIES; i++) + { + diff = (long) CASTLE_PLLtable[i].frequency - frequency; + if (diff < 0L) diff = -diff; + if (diff < min) + { + min = diff; + index = i; + } + } + + /* VERIFY THAT WE ARE NOT WRITING WHAT IS ALREADY IN THE REGISTERS */ + /* The Dot PLL reset bit is tied to VDD for flat panels. This can */ + /* cause a brief drop in flat panel power, which can cause serious */ + /* glitches on some panels. */ + + gfx_msr_read (RC_ID_MCP, MCP_DOTPLL, &msr_value); + + if ((msr_value.low & MCP_DOTPLL_LOCK) && + ((msr_value.low & MCP_DOTPLL_HALFPIX) == 0) && + (msr_value.high == CASTLE_PLLtable[index].pll_value)) + { + return; + } + + /* PROGRAM THE SETTINGS WITH THE RESET BIT SET */ + /* Clear the bypass bit to ensure that the programmed */ + /* M, N and P values are being used. */ + + msr_value.high = CASTLE_PLLtable[index].pll_value; + msr_value.low |= 0x00000001; + msr_value.low &= ~MCP_DOTPLL_BYPASS; + gfx_msr_write (RC_ID_MCP, MCP_DOTPLL, &msr_value); + + /* WAIT FOR THE LOCK BIT */ + /* The official word from LEDA is that the PLL may take up to 100 */ + /* us to lock and the lock bit is unreliable. We thus add a long */ + /* delay followed by a timed-out poll */ + + unlock = READ_REG32 (DC3_UNLOCK); + for (timeout = 0; timeout < 1280; timeout++) + WRITE_REG32 (DC3_UNLOCK, unlock); + + for (timeout = 0; timeout < 1000; timeout++) + { + gfx_msr_read (RC_ID_MCP, MCP_DOTPLL, &msr_value); + if (msr_value.low & MCP_DOTPLL_LOCK) + break; + } + + /* CLEAR THE RESET BIT */ + + msr_value.low &= 0xFFFFFFFE; + gfx_msr_write (RC_ID_MCP, MCP_DOTPLL, &msr_value); +} + +/*--------------------------------------------------------------------------- + * gfx_set_crt_enable + * + * This routine enables or disables the CRT output from the video processor. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_crt_enable(int enable) +#else +int gfx_set_crt_enable(int enable) +#endif +{ + unsigned long config, misc; + config = READ_VID32(CASTLE_DISPLAY_CONFIG); + misc = READ_VID32(CASTLE_VID_MISC); + + switch (enable) + { + case CRT_DISABLE: /* DISABLE EVERYTHING */ + + WRITE_VID32(CASTLE_DISPLAY_CONFIG, config & ~(CASTLE_DCFG_DIS_EN | CASTLE_DCFG_HSYNC_EN + | CASTLE_DCFG_VSYNC_EN | CASTLE_DCFG_DAC_BL_EN )); + WRITE_VID32(CASTLE_VID_MISC, misc | CASTLE_DAC_POWER_DOWN); + break; + + case CRT_ENABLE: /* ENABLE CRT DISPLAY, INCLUDING DISPLAY LOGIC */ + + WRITE_VID32(CASTLE_DISPLAY_CONFIG, config | CASTLE_DCFG_DIS_EN | CASTLE_DCFG_HSYNC_EN + | CASTLE_DCFG_VSYNC_EN | CASTLE_DCFG_DAC_BL_EN); + WRITE_VID32(CASTLE_VID_MISC, misc & ~CASTLE_DAC_POWER_DOWN & ~CASTLE_ANALOG_POWER_DOWN); + break; + + case CRT_STANDBY: /* HSYNC:OFF VSYNC:ON */ + + WRITE_VID32(CASTLE_DISPLAY_CONFIG, (config & ~(CASTLE_DCFG_DIS_EN | CASTLE_DCFG_HSYNC_EN + | CASTLE_DCFG_DAC_BL_EN)) | + CASTLE_DCFG_VSYNC_EN ); + WRITE_VID32(CASTLE_VID_MISC, misc | CASTLE_DAC_POWER_DOWN); + break; + + case CRT_SUSPEND: /* HSYNC:ON VSYNC:OFF */ + + WRITE_VID32(CASTLE_DISPLAY_CONFIG, (config & ~(CASTLE_DCFG_DIS_EN | CASTLE_DCFG_VSYNC_EN + | CASTLE_DCFG_DAC_BL_EN)) | + CASTLE_DCFG_HSYNC_EN ); + WRITE_VID32(CASTLE_VID_MISC, misc | CASTLE_DAC_POWER_DOWN); + break; + + default: + return (GFX_STATUS_BAD_PARAMETER); + } + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_enable + * + * This routine enables or disables the video overlay functionality. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_enable(int enable) +#else +int gfx_set_video_enable(int enable) +#endif +{ + unsigned long vcfg; + + /* WAIT FOR VERTICAL BLANK TO START */ + /* Otherwise a glitch can be observed. */ + + if (gfx_test_timing_active()) + { + if (!gfx_test_vertical_active()) + { + while(!gfx_test_vertical_active()); + } + while(gfx_test_vertical_active()); + } + + vcfg = READ_VID32(CASTLE_VIDEO_CONFIG); + if (enable) + { + /* ENABLE VIDEO OVERLAY FROM DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_enable(1); + + /* ENABLE DISPLAY FILTER VIDEO OVERLAY */ + + vcfg |= CASTLE_VCFG_VID_EN; + WRITE_VID32(CASTLE_VIDEO_CONFIG, vcfg); + } + else + { + /* DISABLE DISPLAY FILTER VIDEO OVERLAY */ + + vcfg &= ~CASTLE_VCFG_VID_EN; + WRITE_VID32(CASTLE_VIDEO_CONFIG, vcfg); + + /* DISABLE VIDEO OVERLAY FROM DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_enable(0); + } + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_format + * + * Sets input video format type, to one of the YUV formats or to RGB. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_format(unsigned long format) +#else +int gfx_set_video_format(unsigned long format) +#endif +{ + unsigned long ctrl, vcfg = 0; + + /* SET THE DISPLAY FILTER VIDEO INPUT FORMAT */ + + vcfg = READ_VID32(CASTLE_VIDEO_CONFIG); + ctrl = READ_VID32(CASTLE_VID_ALPHA_CONTROL); + ctrl &= ~(CASTLE_VIDEO_INPUT_IS_RGB | CASTLE_CSC_VIDEO_YUV_TO_RGB | CASTLE_CSC_GRAPHICS_RGB_TO_YUV); + vcfg &= ~(CASTLE_VCFG_VID_INP_FORMAT | CASTLE_VCFG_4_2_0_MODE); + switch(format) + { + case VIDEO_FORMAT_UYVY: + vcfg |= CASTLE_VCFG_UYVY_FORMAT; + ctrl |= CASTLE_CSC_VIDEO_YUV_TO_RGB; + break; + case VIDEO_FORMAT_YUYV: + vcfg |= CASTLE_VCFG_YUYV_FORMAT; + ctrl |= CASTLE_CSC_VIDEO_YUV_TO_RGB; + break; + case VIDEO_FORMAT_Y2YU: + vcfg |= CASTLE_VCFG_Y2YU_FORMAT; + ctrl |= CASTLE_CSC_VIDEO_YUV_TO_RGB; + break; + case VIDEO_FORMAT_YVYU: + vcfg |= CASTLE_VCFG_YVYU_FORMAT; + ctrl |= CASTLE_CSC_VIDEO_YUV_TO_RGB; + break; + case VIDEO_FORMAT_Y0Y1Y2Y3: + vcfg |= CASTLE_VCFG_UYVY_FORMAT; + ctrl |= CASTLE_CSC_VIDEO_YUV_TO_RGB; + vcfg |= CASTLE_VCFG_4_2_0_MODE; + break; + case VIDEO_FORMAT_Y3Y2Y1Y0: + vcfg |= CASTLE_VCFG_Y2YU_FORMAT; + ctrl |= CASTLE_CSC_VIDEO_YUV_TO_RGB; + vcfg |= CASTLE_VCFG_4_2_0_MODE; + break; + case VIDEO_FORMAT_Y1Y0Y3Y2: + vcfg |= CASTLE_VCFG_YUYV_FORMAT; + ctrl |= CASTLE_CSC_VIDEO_YUV_TO_RGB; + vcfg |= CASTLE_VCFG_4_2_0_MODE; + break; + case VIDEO_FORMAT_Y1Y2Y3Y0: + vcfg |= CASTLE_VCFG_YVYU_FORMAT; + ctrl |= CASTLE_CSC_VIDEO_YUV_TO_RGB; + vcfg |= CASTLE_VCFG_4_2_0_MODE; + break; + case VIDEO_FORMAT_RGB: + ctrl |= CASTLE_VIDEO_INPUT_IS_RGB; + vcfg |= CASTLE_VCFG_UYVY_FORMAT; + break; + case VIDEO_FORMAT_P2M_P2L_P1M_P1L: + ctrl |= CASTLE_VIDEO_INPUT_IS_RGB; + vcfg |= CASTLE_VCFG_Y2YU_FORMAT; + break; + case VIDEO_FORMAT_P1M_P1L_P2M_P2L: + ctrl |= CASTLE_VIDEO_INPUT_IS_RGB; + vcfg |= CASTLE_VCFG_YUYV_FORMAT; + break; + case VIDEO_FORMAT_P1M_P2L_P2M_P1L: + ctrl |= CASTLE_VIDEO_INPUT_IS_RGB; + vcfg |= CASTLE_VCFG_YVYU_FORMAT; + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + WRITE_VID32(CASTLE_VIDEO_CONFIG, vcfg); + WRITE_VID32(CASTLE_VID_ALPHA_CONTROL, ctrl); + + /* SET THE VIDEO FORMAT IN THE DISPLAY CONTROLLER */ + /* Use private routine to abstract display controller. */ + + gfx_set_display_video_format (format); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_size + * + * This routine specifies the size of the source data. It is used only + * to determine how much data to transfer per frame, and is not used to + * calculate the scaling value (that is handled by a separate routine). + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_size(unsigned short width, unsigned short height) +#else +int gfx_set_video_size(unsigned short width, unsigned short height) +#endif +{ + unsigned long size, vcfg, vid_420, pitch, scale; + + /* SET THE DISPLAY FILTER VIDEO LINE SIZE */ + /* Match the DC hardware alignment requirement. The line size must */ + /* always be 32-byte aligned. However, we can manage smaller */ + /* alignments by decreasing the pitch and clipping the video window. */ + /* The VG will fetch extra data for each line, but the decreased */ + /* pitch will ensure that it always begins fetching at the start of */ + /* the video line. */ + + vcfg = READ_VID32(CASTLE_VIDEO_CONFIG); + + vid_420 = vcfg & CASTLE_VCFG_4_2_0_MODE; + + vcfg &= ~(CASTLE_VCFG_LINE_SIZE_LOWER_MASK | CASTLE_VCFG_LINE_SIZE_UPPER | CASTLE_VCFG_LINE_SIZE_BIT9); + + size = ((width >> 1) + 7) & 0xFFF8; + pitch = ((width << 1) + 7) & 0xFFF8; + + vcfg |= (size & 0x00FF) << 8; + if (size & 0x0100) vcfg |= CASTLE_VCFG_LINE_SIZE_UPPER; + if (size & 0x0200) vcfg |= CASTLE_VCFG_LINE_SIZE_BIT9; + WRITE_VID32(CASTLE_VIDEO_CONFIG, vcfg); + + /* WRITE THE VIDEO HEIGHT */ + + scale = READ_VID32 (CASTLE_VIDEO_SCALER); + scale = (scale & ~0x7FF) | height; + WRITE_VID32 (CASTLE_VIDEO_SCALER, scale); + + /* SET VIDEO BUFFER LINE SIZE IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_size (width, height); + + /* SET VIDEO PITCH */ + /* We are only maintaining legacy for 4:2:2 video formats. */ + /* 4:2:0 video in previous chips was inadequate for most */ + /* common video formats. */ + + if (!vid_420) + gfx_set_video_yuv_pitch (pitch, pitch << 1); + + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_offset + * + * This routine sets the starting offset for the video buffer when only + * one offset needs to be specified. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_offset(unsigned long offset) +#else +int gfx_set_video_offset(unsigned long offset) +#endif +{ + /* SAVE VALUE FOR FUTURE CLIPPING OF THE TOP OF THE VIDEO WINDOW */ + + gfx_vid_offset = offset; + + /* SET VIDEO BUFFER OFFSET IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_offset(offset); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_yuv_offsets + * + * This routine sets the starting offset for the video buffer when displaying + * 4:2:0 video. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, unsigned long voffset) +#else +int gfx_set_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, unsigned long voffset) +#endif +{ + /* SAVE VALUE FOR FUTURE CLIPPING OF THE TOP OF THE VIDEO WINDOW */ + + gfx_vid_offset = yoffset; + gfx_vid_uoffset = uoffset; + gfx_vid_voffset = voffset; + + /* SET VIDEO BUFFER OFFSET IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_yuv_offsets(yoffset, uoffset, voffset); + + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_yuv_pitch + * + * This routine sets the byte offset between consecutive scanlines of YUV video data + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_yuv_pitch(unsigned long ypitch, unsigned long uvpitch) +#else +int gfx_set_video_yuv_pitch(unsigned long ypitch, unsigned long uvpitch) +#endif +{ + /* SET VIDEO PITCH IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_yuv_pitch (ypitch, uvpitch); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_scale + * + * This routine sets the scale factor for the video overlay window. The + * size of the source and destination regions are specified in pixels. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +#else +int gfx_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +#endif +{ + unsigned long xscale, yscale, i; + unsigned long scale; + unsigned long temp; + + /* SAVE PARAMETERS */ + /* These are needed for clipping the video window later. Zero */ + /* values indicate that the corresponding scale value should */ + /* not be changed. */ + + if (dstw != 0) + { + gfx_vid_srcw = srcw; + gfx_vid_dstw = dstw; + } + if (dsth != 0) + { + gfx_vid_srch = srch; + gfx_vid_dsth = dsth; + } + + /* CALCULATE DISPLAY FILTER SCALE FACTORS */ + /* Zero width and height indicate don't care conditions */ + + if (dstw != 0) + { + if (dstw <= srcw) + xscale = 0x10000; + else + xscale = (0x10000 * (unsigned long)srcw) / (unsigned long)dstw; + + WRITE_VID32 (CASTLE_VIDEO_XSCALE, xscale); + } + if (dsth != 0) + { + if (dsth <= srch) + yscale = 0x10000; + else + yscale = (0x10000 * (unsigned long)srch) / (unsigned long)dsth; + + WRITE_VID32 (CASTLE_VIDEO_YSCALE, yscale); + } + + /* ENABLE OR DISABLE FILTERING */ + + temp = READ_VID32 (CASTLE_VIDEO_CONFIG); + if (READ_VID32 (CASTLE_VIDEO_XSCALE) == 0x10000 && + READ_VID32 (CASTLE_VIDEO_YSCALE) == 0x10000) + { + WRITE_VID32 (CASTLE_VIDEO_CONFIG, (temp | CASTLE_VCFG_SC_BYP)); + } + else + { + scale = READ_VID32 (CASTLE_VIDEO_SCALER); + + WRITE_VID32 (CASTLE_VIDEO_SCALER, scale & ~CASTLE_SCALE_128_PHASES); + WRITE_VID32 (CASTLE_VIDEO_CONFIG, (temp & ~CASTLE_VCFG_SC_BYP)); + + /* PROGRAM THE COEFFICIENTS */ + + for (i = 0; i < 256; i++) + { + WRITE_VID32 ((CASTLE_COEFFICIENT_BASE + (i << 3)), DurangoVideoFilter[i][0]); + WRITE_VID32 ((CASTLE_COEFFICIENT_BASE + (i << 3) + 4), DurangoVideoFilter[i][1]); + } + } + /* CALL ROUTINE TO UPDATE WINDOW POSITION */ + /* This is required because the scale values affect the number of */ + /* source data pixels that need to be clipped, as well as the */ + /* amount of data that needs to be transferred. */ + + gfx_set_video_window(gfx_vid_xpos, gfx_vid_ypos, gfx_vid_width, gfx_vid_height); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_window + * + * This routine sets the position and size of the video overlay window. The + * x and y positions are specified in screen relative coordinates, and may be negative. + * The size of destination region is specified in pixels. The line size + * indicates the number of bytes of source data per scanline. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_window(short x, short y, unsigned short w, unsigned short h) +#else +int gfx_set_video_window(short x, short y, unsigned short w, unsigned short h) +#endif +{ + unsigned long hadjust, vadjust; + unsigned long xstart, ystart, xend, yend; + unsigned long lock; + + lock = READ_REG32 (DC3_UNLOCK); + + /* SAVE PARAMETERS */ + /* These are needed to call this routine if the scale value changes. */ + + gfx_vid_xpos = x; + gfx_vid_ypos = y; + gfx_vid_width = w; + gfx_vid_height = h; + + /* GET ADJUSTMENT VALUES */ + /* Use routines to abstract version of display controller. */ + + hadjust = gfx_get_htotal() - gfx_get_hsync_end() - 14l; + vadjust = gfx_get_vtotal() - gfx_get_vsync_end() + 1l; + + /* LEFT CLIPPING */ + + if (x < 0) + { + gfx_set_video_left_crop ((unsigned short)(-x)); + xstart = hadjust; + } + else + { + gfx_set_video_left_crop (0); + xstart = (unsigned long)x + hadjust; + } + + /* HORIZONTAL END */ + /* End positions in register are non-inclusive (one more than the actual end) */ + + if ((x + w) < gfx_get_hactive()) + xend = (unsigned long)x + (unsigned long)w + hadjust; + + /* RIGHT-CLIPPING */ + else + xend = (unsigned long)gfx_get_hactive() + hadjust; + + /* VERTICAL START */ + + ystart = (unsigned long)y + vadjust; + + /* VERTICAL END */ + + if ((y + h) < gfx_get_vactive()) + yend = (unsigned long)y + (unsigned long)h + vadjust; + + /* BOTTOM-CLIPPING */ + else + yend = (unsigned long)gfx_get_vactive() + vadjust; + + /* SET VIDEO POSITION */ + + WRITE_VID32(CASTLE_VIDEO_X_POS, (xend << 16) | xstart); + WRITE_VID32(CASTLE_VIDEO_Y_POS, (yend << 16) | ystart); + + /* SET COLOR KEY REGION */ + + WRITE_REG32 (DC3_UNLOCK, DC3_UNLOCK_VALUE); + WRITE_REG32 (DC3_COLOR_KEY_X, ((xend - hadjust) << 16) | (xstart - hadjust)); + WRITE_REG32 (DC3_COLOR_KEY_Y, ((yend - vadjust) << 16) | (ystart - vadjust)); + WRITE_REG32 (DC3_UNLOCK, lock); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_left_crop + * + * This routine sets the number of pixels which will be cropped from the + * beginning of each video line. The video window will begin to display only + * from the pixel following the cropped pixels, and the cropped pixels + * will be ignored. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_left_crop(unsigned short x) +#else +int gfx_set_video_left_crop(unsigned short x) +#endif +{ + unsigned long vcfg, initread; + + vcfg = READ_VID32(CASTLE_VIDEO_CONFIG) & ~CASTLE_VCFG_INIT_READ_MASK; + + /* CLIPPING ON LEFT */ + /* Adjust initial read for scale, checking for divide by zero. All video */ + /* formats must be clipped on a 4-pixel boundary */ + + if (gfx_vid_dstw) + { + initread = (unsigned long)x * gfx_vid_srcw / gfx_vid_dstw; + } + else + initread = 0; + + /* SET INITIAL READ ADDRESS */ + + vcfg = vcfg | ((initread << 14) & CASTLE_VCFG_INIT_READ_MASK); + WRITE_VID32(CASTLE_VIDEO_CONFIG, vcfg); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_color_key + * + * This routine specifies the color key value and mask for the video overlay + * hardware. To disable color key, the color and mask should both be set to + * zero. The hardware uses the color key in the following equation: + * + * ((source data) & (color key mask)) == ((color key) & (color key mask)) + * + * If "graphics" is set to TRUE, the source data is graphics, and color key + * is an RGB value. If "graphics" is set to FALSE, the source data is video, + * and the color key is an RGB value that is compared to the video data after + * it has gone through color space conversion (CSC). + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_color_key(unsigned long key, unsigned long mask, + int graphics) +#else +int gfx_set_video_color_key(unsigned long key, unsigned long mask, + int graphics) +#endif +{ + unsigned long dcfg; + + /* ENABLE OR DISABLE COLOR KEY LOGIC IN THE DISPLAY CONTROLLER */ + /* When chroma key is enabled, the color key logic should be */ + /* disabled in the VG to allow for per-pixel alpha blending. */ + + gfx_set_display_video_color_key (key, mask, graphics); + + dcfg = READ_VID32(CASTLE_DISPLAY_CONFIG); + + if (graphics) dcfg &= ~CASTLE_DCFG_VG_CK; + else dcfg |= CASTLE_DCFG_VG_CK; + + WRITE_VID32 (CASTLE_DISPLAY_CONFIG, dcfg); + WRITE_VID32 (CASTLE_VIDEO_COLOR_KEY, key & 0xFFFFFF); + WRITE_VID32 (CASTLE_VIDEO_COLOR_MASK, mask & 0xFFFFFF); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette + * + * This routine loads the video hardware palette. If a NULL pointer is + * specified, the palette is bypassed (for Castle, this means loading the + * palette with identity values). + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_palette(unsigned long *palette) +#else +int gfx_set_video_palette(unsigned long *palette) +#endif +{ + unsigned long i, entry; + + /* LOAD CASTLE VIDEO PALETTE */ + + WRITE_VID32(CASTLE_PALETTE_ADDRESS, 0); + for (i = 0; i < 256; i++) + { + if (palette) entry = palette[i]; + else entry = i | (i << 8) | (i << 16); + WRITE_VID32(CASTLE_PALETTE_DATA, entry); + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette_entry + * + * This routine loads a single entry of the video hardware palette. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_palette_entry(unsigned long index, unsigned long palette) +#else +int gfx_set_video_palette_entry(unsigned long index, unsigned long palette) +#endif +{ + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + /* SET A SINGLE ENTRY */ + + WRITE_VID32(CASTLE_PALETTE_ADDRESS, index); + WRITE_VID32(CASTLE_PALETTE_DATA, palette); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_request() + * + * This routine sets the horizontal (pixel) and vertical (line) video request + * values. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_request(short x, short y) +#else +int gfx_set_video_request(short x, short y) +#endif +{ + /* SET DISPLAY FILTER VIDEO REQUEST */ + + x += gfx_get_htotal() - gfx_get_hsync_end() - 2; + y += gfx_get_vtotal() - gfx_get_vsync_end() + 1; + + if ((x < 0) || (x > CASTLE_VIDEO_REQUEST_MASK) || + (y < 0) || (y > CASTLE_VIDEO_REQUEST_MASK)) + return GFX_STATUS_BAD_PARAMETER; + + WRITE_VID32(CASTLE_VIDEO_REQUEST, ((unsigned long)x << CASTLE_VIDEO_X_REQUEST_POS) | + ((unsigned long)y << CASTLE_VIDEO_Y_REQUEST_POS)); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_cursor() + * + * This routine configures the video hardware cursor. + * If the "mask"ed bits in the graphics pixel match "key", then either "color1" + * or "color2" will be used for this pixel, according to the value of bit + * number "select_color2" of the graphics pixel. + * + * key - 24 bit RGB value + * mask - 24 bit mask + * color1, color2 - RGB or YUV, depending on the current color space conversion + * select_color2 - value between 0 to 23 + * + * To disable match, a "mask" and "key" value of 0xffffff should be set, + * because the graphics pixels incoming to the video processor have maximum 16 + * bits set (0xF8FCF8). + * + * This feature is useful for disabling alpha blending of the cursor. + * Otherwise cursor image would be blurred (or completely invisible if video + * alpha is maximum value). + * Note: the cursor pixel replacements take place both inside and outside the + * video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_cursor(unsigned long key, unsigned long mask, unsigned short select_color2, + unsigned long color1, unsigned long color2) +#else +int gfx_set_video_cursor(unsigned long key, unsigned long mask, unsigned short select_color2, + unsigned long color1, unsigned long color2) +#endif +{ + if (select_color2 > CASTLE_CURSOR_COLOR_BITS) return GFX_STATUS_BAD_PARAMETER; + key = (key & CASTLE_COLOR_MASK) | ((unsigned long)select_color2 << CASTLE_CURSOR_COLOR_KEY_OFFSET_POS); + WRITE_VID32(CASTLE_CURSOR_COLOR_KEY, key); + WRITE_VID32(CASTLE_CURSOR_COLOR_MASK, mask); + WRITE_VID32(CASTLE_CURSOR_COLOR_1, color1); + WRITE_VID32(CASTLE_CURSOR_COLOR_2, color2); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_cursor_enable() + * + * This routine enables or disables the cursor color key mechanism. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_video_cursor_enable (int enable) +#else +int gfx_set_video_cursor_enable (int enable) +#endif +{ + unsigned long temp = READ_VID32 (CASTLE_CURSOR_COLOR_KEY); + + if (enable) temp |= CASTLE_CURSOR_COLOR_KEY_ENABLE; + else temp &= ~CASTLE_CURSOR_COLOR_KEY_ENABLE; + + WRITE_VID32 (CASTLE_CURSOR_COLOR_KEY, temp); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_enable + * + * This routine enables or disables the currently selected alpha region. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_alpha_enable(int enable) +#else +int gfx_set_alpha_enable(int enable) +#endif +{ + unsigned long address = 0, value = 0; + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = CASTLE_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 5); + value = READ_VID32(address); + if (enable) value |= CASTLE_ACTRL_WIN_ENABLE; + else value &= ~(CASTLE_ACTRL_WIN_ENABLE); + WRITE_VID32(address, value); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_window + * + * This routine sets the size of the currently selected alpha region. + * Note: "x" and "y" are signed to enable using negative values needed for + * implementing workarounds of hardware issues. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_alpha_window(short x, short y, + unsigned short width, unsigned short height) +#else +int gfx_set_alpha_window(short x, short y, + unsigned short width, unsigned short height) +#endif +{ + unsigned long address = 0; + + /* CHECK FOR CLIPPING */ + + if ((x + width) > gfx_get_hactive()) width = gfx_get_hactive() - x; + if ((y + height) > gfx_get_vactive()) height = gfx_get_vactive() - y; + + /* ADJUST POSITIONS */ + + x += gfx_get_htotal() - gfx_get_hsync_end() - 2; + y += gfx_get_vtotal() - gfx_get_vsync_end() + 1; + + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = CASTLE_ALPHA_XPOS_1 + ((unsigned long)gfx_alpha_select << 5); + + /* END POSITIONS IN REGISTERS ARE NON-INCLUSIVE (ONE MORE THAN ACTUAL END) */ + + WRITE_VID32(address, (unsigned long) x | + ((unsigned long) (x + width) << 16)); + WRITE_VID32(address + 8, (unsigned long) y | + ((unsigned long) (y + height) << 16)); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_value + * + * This routine sets the alpha value for the currently selected alpha + * region. It also specifies an increment/decrement value for fading. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_alpha_value(unsigned char alpha, char delta) +#else +int gfx_set_alpha_value(unsigned char alpha, char delta) +#endif +{ + unsigned long address = 0, value = 0; + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = CASTLE_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 5); + value = READ_VID32(address); + value &= CASTLE_ACTRL_WIN_ENABLE; /* keep only enable bit */ + value |= (unsigned long) alpha; + value |= (((unsigned long) delta) & 0xff) << 8; + value |= CASTLE_ACTRL_LOAD_ALPHA; + WRITE_VID32(address, value); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_priority + * + * This routine sets the priority of the currently selected alpha region. + * A higher value indicates a higher priority. + * Note: Priority of enabled alpha windows must be different. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_alpha_priority(int priority) +#else +int gfx_set_alpha_priority(int priority) +#endif +{ + unsigned long pos = 0, value = 0; + if (priority > 3) return(GFX_STATUS_BAD_PARAMETER); + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + value = READ_VID32(CASTLE_VID_ALPHA_CONTROL); + pos = 16 + (gfx_alpha_select << 1); + value &= ~(0x03l << pos); + value |= (unsigned long)priority << pos; + WRITE_VID32(CASTLE_VID_ALPHA_CONTROL, value); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_color + * + * This routine sets the color to be displayed inside the currently selected + * alpha window when there is a color key match (when the alpha color + * mechanism is enabled). + * "color" is an RGB value (for RGB blending) or a YUV value (for YUV blending). + * In Interlaced YUV blending mode, Y/2 value should be used. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_alpha_color(unsigned long color) +#else +int gfx_set_alpha_color(unsigned long color) +#endif +{ + unsigned long address = 0; + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = CASTLE_ALPHA_COLOR_1 + ((unsigned long)gfx_alpha_select << 5); + WRITE_VID32(address, color); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_color_enable + * + * Enable or disable the color mechanism in the alpha window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_alpha_color_enable(int enable) +#else +int gfx_set_alpha_color_enable(int enable) +#endif +{ + unsigned long color; + unsigned long address = 0; + + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = CASTLE_ALPHA_COLOR_1 + ((unsigned long)gfx_alpha_select << 5); + color = READ_VID32(address); + if (enable) + color |= CASTLE_ALPHA_COLOR_ENABLE; + else + color &= ~CASTLE_ALPHA_COLOR_ENABLE; + WRITE_VID32(address, color); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_no_ck_outside_alpha + * + * This function affects where inside the video window color key or chroma + * key comparison is done: + * If enable is TRUE, color/chroma key comparison is performed only inside + * the enabled alpha windows. Outside the (enabled) alpha windows, only video + * is displayed if color key is used, and only graphics is displayed if chroma + * key is used. + * If enable is FALSE, color/chroma key comparison is performed in all the + * video window area. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_set_no_ck_outside_alpha(int enable) +#else +int gfx_set_no_ck_outside_alpha(int enable) +#endif +{ + unsigned long value; + value = READ_VID32(CASTLE_VID_ALPHA_CONTROL); + if (enable) + WRITE_VID32(CASTLE_VID_ALPHA_CONTROL, value | CASTLE_NO_CK_OUTSIDE_ALPHA); + else + WRITE_VID32(CASTLE_VID_ALPHA_CONTROL, value & ~CASTLE_NO_CK_OUTSIDE_ALPHA); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_clock_frequency + * + * This routine returns the current clock frequency in 16.16 format. + * It reads the current register value and finds the match in the table. + * If no match is found, this routine returns 0. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long castle_get_clock_frequency(void) +#else +unsigned long gfx_get_clock_frequency(void) +#endif +{ + Q_WORD msr_value; + unsigned int index; + unsigned long value, mask = 0x00001FFF; + + /* READ PLL SETTING */ + + gfx_msr_read (RC_ID_MCP, MCP_DOTPLL, &msr_value); + value = msr_value.high & mask; + + /* SEARCH FOR A MATCH */ + + for (index = 0; index < NUM_CASTLE_FREQUENCIES; index++) + { + if ((CASTLE_PLLtable[index].pll_value & mask) == value) + return(CASTLE_PLLtable[index].frequency); + } + return(0); +} + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +#if GFX_READ_ROUTINES + +/*--------------------------------------------------------------------------- + * gfx_get_sync_polarities + * + * This routine returns the polarities of the sync pulses: + * Bit 0: Set if negative horizontal polarity. + * Bit 1: Set if negative vertical polarity. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_get_sync_polarities(void) +#else +int gfx_get_sync_polarities(void) +#endif +{ + int polarities = 0; + if (READ_VID32(CASTLE_DISPLAY_CONFIG) & CASTLE_DCFG_CRT_HSYNC_POL) polarities |= 1; + if (READ_VID32(CASTLE_DISPLAY_CONFIG) & CASTLE_DCFG_CRT_VSYNC_POL) polarities |= 2; + return(polarities); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_palette_entry + * + * This routine returns a single palette entry. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_get_video_palette_entry(unsigned long index, unsigned long *palette) +#else +int gfx_get_video_palette_entry(unsigned long index, unsigned long *palette) +#endif +{ + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + /* READ A SINGLE ENTRY */ + + WRITE_VID32 (CASTLE_PALETTE_ADDRESS, index); + *palette = READ_VID32 (CASTLE_PALETTE_DATA); + + return (GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_enable + * + * This routine returns the value "one" if video overlay is currently enabled, + * otherwise it returns the value "zero". + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_get_video_enable(void) +#else +int gfx_get_video_enable(void) +#endif +{ + if (READ_VID32(CASTLE_VIDEO_CONFIG) & CASTLE_VCFG_VID_EN) return(1); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_format + * + * This routine returns the current video overlay format. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_get_video_format(void) +#else +int gfx_get_video_format(void) +#endif +{ + unsigned long ctrl, vcfg; + + ctrl = READ_VID32(CASTLE_VID_ALPHA_CONTROL); + vcfg = READ_VID32(CASTLE_VIDEO_CONFIG); + + if (ctrl & CASTLE_VIDEO_INPUT_IS_RGB) + { + switch (vcfg & CASTLE_VCFG_VID_INP_FORMAT) + { + case CASTLE_VCFG_UYVY_FORMAT: return VIDEO_FORMAT_RGB; + case CASTLE_VCFG_Y2YU_FORMAT: return VIDEO_FORMAT_P2M_P2L_P1M_P1L; + case CASTLE_VCFG_YUYV_FORMAT: return VIDEO_FORMAT_P1M_P1L_P2M_P2L; + case CASTLE_VCFG_YVYU_FORMAT: return VIDEO_FORMAT_P1M_P2L_P2M_P1L; + } + } + + if (vcfg & CASTLE_VCFG_4_2_0_MODE) + { + switch (vcfg & CASTLE_VCFG_VID_INP_FORMAT) + { + case CASTLE_VCFG_UYVY_FORMAT: return VIDEO_FORMAT_Y0Y1Y2Y3; + case CASTLE_VCFG_Y2YU_FORMAT: return VIDEO_FORMAT_Y3Y2Y1Y0; + case CASTLE_VCFG_YUYV_FORMAT: return VIDEO_FORMAT_Y1Y0Y3Y2; + case CASTLE_VCFG_YVYU_FORMAT: return VIDEO_FORMAT_Y1Y2Y3Y0; + } + } + else + { + switch (vcfg & CASTLE_VCFG_VID_INP_FORMAT) + { + case CASTLE_VCFG_UYVY_FORMAT: return VIDEO_FORMAT_UYVY; + case CASTLE_VCFG_Y2YU_FORMAT: return VIDEO_FORMAT_Y2YU; + case CASTLE_VCFG_YUYV_FORMAT: return VIDEO_FORMAT_YUYV; + case CASTLE_VCFG_YVYU_FORMAT: return VIDEO_FORMAT_YVYU; + } + } + return (GFX_STATUS_ERROR); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_src_size + * + * This routine returns the size of the source video overlay buffer. The + * return value is (height << 16) | width. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long castle_get_video_src_size(void) +#else +unsigned long gfx_get_video_src_size(void) +#endif +{ + unsigned long width, height; + + /* DETERMINE SOURCE WIDTH FROM THE DISPLAY FILTER VIDEO LINE SIZE */ + + width = (READ_VID32(CASTLE_VIDEO_CONFIG) >> 7) & 0x000001FE; + if (READ_VID32(CASTLE_VIDEO_CONFIG) & CASTLE_VCFG_LINE_SIZE_UPPER) + width += 512l; + if (READ_VID32(CASTLE_VIDEO_CONFIG) & CASTLE_VCFG_LINE_SIZE_BIT9) + width += 1024l; + + /* DETERMINE SOURCE HEIGHT FROM THE DISPLAY FILTER SCALE REGISTER */ + + height = READ_VID32 (CASTLE_VIDEO_SCALER) & 0x7FF; + + return((height << 16) | width); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_line_size + * + * This routine returns the line size of the source video overlay buffer, in + * pixels. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long castle_get_video_line_size(void) +#else +unsigned long gfx_get_video_line_size(void) +#endif +{ + unsigned long width = 0; + + /* DETERMINE SOURCE WIDTH FROM THE CASTLE VIDEO LINE SIZE */ + + width = (READ_VID32(CASTLE_VIDEO_CONFIG) >> 7) & 0x000001FE; + if (READ_VID32(CASTLE_VIDEO_CONFIG) & CASTLE_VCFG_LINE_SIZE_UPPER) + width += 512l; + return(width); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_xclip + * + * This routine returns the number of bytes clipped on the left side of a + * video overlay line (skipped at beginning). + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long castle_get_video_xclip(void) +#else +unsigned long gfx_get_video_xclip(void) +#endif +{ + unsigned long clip = 0; + + /* DETERMINE SOURCE WIDTH FROM THE CASTLE VIDEO LINE SIZE */ + + clip = ((READ_VID32(CASTLE_VIDEO_CONFIG) >> 16) & 0x001FF) << 3; + return(clip); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_offset + * + * This routine returns the current offset for the video overlay buffer. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long castle_get_video_offset(void) +#else +unsigned long gfx_get_video_offset(void) +#endif +{ + return(gfx_get_display_video_offset()); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_yuv_offsets + * + * This routine returns the current offsets for the video overlay buffer when in 4:2:0. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void castle_get_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset) +#else +void gfx_get_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset) +#endif +{ + gfx_get_display_video_yuv_offsets(yoffset, uoffset, voffset); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_yuv_pitch + * + * This routine returns the current pitch values for the video overlay buffer. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void castle_get_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch) +#else +void gfx_get_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch) +#endif +{ + gfx_get_display_video_yuv_pitch(ypitch, uvpitch); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_dst_size + * + * This routine returns the size of the displayed video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long castle_get_video_dst_size(void) +#else +unsigned long gfx_get_video_dst_size(void) +#endif +{ + unsigned long xsize, ysize; + + xsize = READ_VID32(CASTLE_VIDEO_X_POS); + xsize = ((xsize >> 16) & 0x7FF) - (xsize & 0x7FF); + ysize = READ_VID32(CASTLE_VIDEO_Y_POS); + ysize = ((ysize >> 16) & 0x7FF) - (ysize & 0x7FF); + return((ysize << 16) | xsize); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_position + * + * This routine returns the position of the video overlay window. The + * return value is (ypos << 16) | xpos. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long castle_get_video_position(void) +#else +unsigned long gfx_get_video_position(void) +#endif +{ + unsigned long hadjust, vadjust; + unsigned long xpos, ypos; + + /* READ HARDWARE POSITION */ + + xpos = READ_VID32(CASTLE_VIDEO_X_POS) & 0x000007FF; + ypos = READ_VID32(CASTLE_VIDEO_Y_POS) & 0x000007FF; + + /* GET ADJUSTMENT VALUES */ + /* Use routines to abstract version of display controller. */ + + hadjust = (unsigned long)gfx_get_htotal() - (unsigned long)gfx_get_hsync_end() - 14l; + vadjust = (unsigned long)gfx_get_vtotal() - (unsigned long)gfx_get_vsync_end() + 1l; + xpos -= hadjust; + ypos -= vadjust; + return((ypos << 16) | (xpos & 0x0000FFFF)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key + * + * This routine returns the current video color key value. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long castle_get_video_color_key(void) +#else +unsigned long gfx_get_video_color_key(void) +#endif +{ + if (READ_VID32 (CASTLE_DISPLAY_CONFIG) & CASTLE_DCFG_VG_CK) + return(READ_VID32(CASTLE_VIDEO_COLOR_KEY)); + else + return(gfx_get_display_video_color_key()); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key_mask + * + * This routine returns the current video color mask value. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long castle_get_video_color_key_mask(void) +#else +unsigned long gfx_get_video_color_key_mask(void) +#endif +{ + if (READ_VID32 (CASTLE_DISPLAY_CONFIG) & CASTLE_DCFG_VG_CK) + return(READ_VID32(CASTLE_VIDEO_COLOR_MASK)); + else + return(gfx_get_display_video_color_key_mask()); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key_src + * + * This routine returns 0 for video data compare, 1 for graphics data. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_get_video_color_key_src(void) +#else +int gfx_get_video_color_key_src(void) +#endif +{ + if (READ_VID32(CASTLE_DISPLAY_CONFIG) & CASTLE_DCFG_VG_CK) return(0); + return(1); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_request + * + * This routine returns the horizontal (pixel) and vertical (lines) video + * request values. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_get_video_request(short *x, short *y) +#else +int gfx_get_video_request(short *x, short *y) +#endif +{ + unsigned long request = 0; + request = (READ_VID32(CASTLE_VIDEO_REQUEST)); + *x = (short)((request >> CASTLE_VIDEO_X_REQUEST_POS) & CASTLE_VIDEO_REQUEST_MASK); + *y = (short)((request >> CASTLE_VIDEO_Y_REQUEST_POS) & CASTLE_VIDEO_REQUEST_MASK); + + *x -= gfx_get_htotal() - gfx_get_hsync_end() - 2; + *y -= gfx_get_vtotal() - gfx_get_vsync_end() + 1; + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_cursor() + * + * This routine configures the video hardware cursor. + * If the "mask"ed bits in the graphics pixel match "key", then either "color1" + * or "color2" will be used for this pixel, according to the value of the bit + * in offset "select_color2". + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int castle_get_video_cursor(unsigned long *key, unsigned long *mask, unsigned short *select_color2, + unsigned long *color1, unsigned short *color2) +#else +int gfx_get_video_cursor(unsigned long *key, unsigned long *mask, unsigned short *select_color2, + unsigned long *color1, unsigned short *color2) +#endif +{ + *select_color2 = (unsigned short)(READ_VID32(CASTLE_CURSOR_COLOR_KEY) >> CASTLE_CURSOR_COLOR_KEY_OFFSET_POS); + *key = READ_VID32(CASTLE_CURSOR_COLOR_KEY) & CASTLE_COLOR_MASK; + *mask = READ_VID32(CASTLE_CURSOR_COLOR_MASK) & CASTLE_COLOR_MASK; + *color1 = READ_VID32(CASTLE_CURSOR_COLOR_1) & CASTLE_COLOR_MASK; + *color2 = (unsigned short)(READ_VID32(CASTLE_CURSOR_COLOR_2) & CASTLE_COLOR_MASK); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_read_crc + * + * This routine returns the hardware CRC value, which is used for automated + * testing. The value is like a checksum, but will change if pixels move + * locations. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long castle_read_crc(void) +#else +unsigned long gfx_read_crc(void) +#endif +{ + Q_WORD msr_value; + unsigned long crc = 0xFFFFFFFF; + + /* DISABLE 32-BIT CRCS */ + /* For GX1.x, this is a reserved bit, and is assumed to be a benign access */ + + gfx_msr_read (RC_ID_DF, CASTLE_MBD_MSR_DIAG_DF, &msr_value); + msr_value.low &= ~CASTLE_DIAG_32BIT_CRC; + gfx_msr_write (RC_ID_DF, CASTLE_MBD_MSR_DIAG_DF, &msr_value); + + if (gfx_test_timing_active()) + { + /* WAIT UNTIL ACTIVE DISPLAY */ + + while(!gfx_test_vertical_active()); + + /* RESET CRC DURING ACTIVE DISPLAY */ + + WRITE_VID32(CASTLE_VID_CRC, 0); + WRITE_VID32(CASTLE_VID_CRC, 1); + + /* WAIT UNTIL NOT ACTIVE, THEN ACTIVE, NOT ACTIVE, THEN ACTIVE */ + + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + crc = READ_VID32(CASTLE_VID_CRC) >> 8; + } + return(crc); +} + +/*--------------------------------------------------------------------------- + * gfx_read_crc32 + * + * This routine returns the 32-bit hardware CRC value, which is used for automated + * testing. The value is like a checksum, but will change if pixels move + * locations. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long castle_read_crc32(void) +#else +unsigned long gfx_read_crc32(void) +#endif +{ + Q_WORD msr_value; + unsigned long crc = 0xFFFFFFFF; + + /* ENABLE 32-BIT CRCS */ + /* For GX1.x, this is a reserved bit, and is assumed to be a benign access */ + + gfx_msr_read (RC_ID_DF, CASTLE_MBD_MSR_DIAG_DF, &msr_value); + msr_value.low |= CASTLE_DIAG_32BIT_CRC; + gfx_msr_write (RC_ID_DF, CASTLE_MBD_MSR_DIAG_DF, &msr_value); + + if (gfx_test_timing_active()) + { + /* WAIT UNTIL ACTIVE DISPLAY */ + + while(!gfx_test_vertical_active()); + + /* RESET CRC DURING ACTIVE DISPLAY */ + + WRITE_VID32(CASTLE_VID_CRC, 0); + WRITE_VID32(CASTLE_VID_CRC, 1); + + /* WAIT UNTIL NOT ACTIVE, THEN ACTIVE, NOT ACTIVE, THEN ACTIVE */ + + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + crc = READ_VID32(CASTLE_VID_CRC32); + } + return(crc); +} + +/*--------------------------------------------------------------------------- + * gfx_read_window_crc + * + * This routine returns the hardware CRC value for a subsection of the display. + * This value is used to debug whole-screen CRC failures. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long castle_read_window_crc(int source, unsigned short x, unsigned short y, + unsigned short width, unsigned short height, int crc32) +#else +unsigned long gfx_read_window_crc(int source, unsigned short x, unsigned short y, + unsigned short width, unsigned short height, int crc32) +#endif +{ + Q_WORD msr_value; + unsigned long xpos, ypos, crc = 0; + unsigned long old_fmt = 0; + unsigned int vsync_active_base, vsync_inactive_base, hsync_active_base; + unsigned int vsync_active_shift, vsync_inactive_shift, hsync_active_shift; + unsigned int vsync_bit, hsync_bit, sync_polarities = 0; + + /* CONFIGURE DISPLAY FILTER TO LOAD DATA ONTO LOWER 32-BITS */ + + msr_value.high = 0; + msr_value.low = (source == CRC_SOURCE_GFX_DATA) ? (RCDF_MBD_DIAG_EN0 | 0x0000000F) : + (RCDF_MBD_DIAG_EN0 | 0x0000000B); + gfx_msr_write (RC_ID_DF, MBD_MSR_DIAG, &msr_value); + + /* CONFIGURE DISPLAY FILTER FOR APPROPRIATE OUTPUT */ + + if (source != CRC_SOURCE_GFX_DATA) + { + gfx_msr_read (RC_ID_DF, MBD_MSR_CONFIG, &msr_value); + old_fmt = msr_value.low; + msr_value.low &= ~(RCDF_CONFIG_FMT_MASK); + msr_value.low |= ((source == CRC_SOURCE_FP_DATA) ? RCDF_CONFIG_FMT_FP : + RCDF_CONFIG_FMT_CRT); + gfx_msr_write (RC_ID_DF, MBD_MSR_CONFIG, &msr_value); + } + + /* CONFIGURE MCP TO LOAD REGB DATA ONTO UPPER 32-BITS */ + + msr_value.low = MCP_MBD_DIAG_EN1 | 0x00050000; + gfx_msr_write (RC_ID_MCP, MBD_MSR_DIAG, &msr_value); + + /* ENABLE HW CLOCK GATING AND SET MCP CLOCK TO DOT CLOCK */ + + msr_value.low = 1l; + gfx_msr_write (RC_ID_MCP, MBD_MSR_PM, &msr_value); + msr_value.low = 0; + gfx_msr_write (RC_ID_MCP, MCP_DBGCLKCTL, &msr_value); + msr_value.low = 3; + gfx_msr_write (RC_ID_MCP, MCP_DBGCLKCTL, &msr_value); + + /* DISABLE MCP ACTIONS */ + + msr_value.high = 0x00000000; + msr_value.low = 0x00000000; + gfx_msr_write (RC_ID_MCP, MCP_DIAGCTL, &msr_value); + + /* SET APPROPRIATE BASE ADDRESS */ + /* M-Sets use normal diag bits, while N-Sets use inverted diag bits */ + /* We thus use the M-sets when polling for a high signal and the N */ + /* sets when polling for a low signal. */ + + if (source != CRC_SOURCE_GFX_DATA) + { + sync_polarities = gfx_get_sync_polarities (); + vsync_bit = 29; + hsync_bit = 30; + } + else + { + vsync_bit = 25; + hsync_bit = 26; + } + + if (sync_polarities & 1) + { + hsync_active_base = MCP_SETM0CTL; + hsync_active_shift = 2; + } + else + { + hsync_active_base = MCP_SETN0CTL; + hsync_active_shift = 1; + } + if (sync_polarities & 2) + { + vsync_active_base = MCP_SETM0CTL; + vsync_inactive_base = MCP_SETN0CTL; + vsync_active_shift = 2; + vsync_inactive_shift = 1; + } + else + { + vsync_active_base = MCP_SETN0CTL; + vsync_inactive_base = MCP_SETM0CTL; + vsync_active_shift = 1; + vsync_inactive_shift = 2; + } + + /* SET STATE TRANSITIONS */ + + /* STATE 0-1 TRANSITION (SET 0) */ + /* XState = 00 and VSync Inactive */ + /* Note: DF VSync = Diag Bus Bit 29 */ + /* VG VSync = Diag Bus Bit 25 */ + + msr_value.low = 0x000000A0; + msr_value.high = 0x00008000 | ((unsigned long)vsync_bit << 16) | + ((unsigned long)vsync_bit << 21) | + ((unsigned long)vsync_bit << 26); + gfx_msr_write (RC_ID_MCP, vsync_inactive_base, &msr_value); + + /* STATE 1-2 TRANSITION (SET 4) */ + /* XState = 01 and VSync Active */ + + msr_value.low = 0x000000C0; + gfx_msr_write (RC_ID_MCP, vsync_active_base + 4, &msr_value); + + /* STATE 2-3 TRANSITION (SET 1) */ + /* XState = 10 and VSync Inactive */ + + msr_value.low = 0x00000120; + gfx_msr_write (RC_ID_MCP, vsync_inactive_base + 1, &msr_value); + + /* HORIZONTAL COUNTER (SET 5) */ + /* XState = 10 and HSync Active */ + /* Notes: DF HSync = Diag Bus Bit 30 */ + /* VG HSync = Diag Bus Bit 26 */ + + msr_value.high = 0x00008000 | ((unsigned long)hsync_bit << 16) | + ((unsigned long)hsync_bit << 21) | + ((unsigned long)hsync_bit << 26); + msr_value.low = 0x00000120; + gfx_msr_write (RC_ID_MCP, hsync_active_base + 5, &msr_value); + + /* HORIZONTAL COUNTER RESET (SET 4) */ + /* XState = 10 and H. Counter = limit */ + /* Note: H. Counter is lower 16-bits of */ + /* RegB. */ + + msr_value.high = 0x00000000; + msr_value.low = 0x00000128; + gfx_msr_write (RC_ID_MCP, vsync_inactive_base + 4, &msr_value); + + /* CRC TRIGGER (SET 0) */ + /* Cmp0 <= xpos < Cmp1 */ + /* Cmp2 <= ypos < Cmp2 */ + + msr_value.high = 0x00000000; + msr_value.low = 0x10C20120; + gfx_msr_write (RC_ID_MCP, vsync_active_base, &msr_value); + + /* SET COMPARATOR VALUES */ + /* Note: The VG data outputs from the DF are delayed by one pixel clock. */ + /* In this mode, we thus add one to horizontal comparator limits. */ + + /* COMPARATOR 0 */ + /* Lower limit = xpos + (h_blank_pixels - 1) - 3 */ + /* Notes: */ + /* 1. 3 is the pipeline delay for MCP register */ + /* data to access the diag bus */ + /* 2. h_blank_pixels = HTOTAL - HSYNC_END */ + + xpos = (unsigned long)x + ((unsigned long)gfx_get_htotal() - + (unsigned long)gfx_get_hsync_end() - 1l) - 3l; + if (source == CRC_SOURCE_GFX_DATA) xpos++; + msr_value.high = 0x00000000; + msr_value.low = xpos; + gfx_msr_write (RC_ID_MCP, MCP_CMPVAL0, &msr_value); + + /* COMPARATOR 1 */ + /* Upper limit = xpos + width + (h_blank_pixels - 1) - 3 */ + + msr_value.low = xpos + (unsigned long)width; + gfx_msr_write (RC_ID_MCP, MCP_CMPVAL0 + 2, &msr_value); + + /* COMPARATOR 2 */ + /* Lower limit = ypos + v_blank_pixels */ + /* Notes: */ + /* 1. v_blank_pixels = VTOTAL - VSYNC_END */ + + ypos = (unsigned long)y + (unsigned long)gfx_get_vtotal() - (unsigned long)gfx_get_vsync_end(); + msr_value.low = ypos << 16; + gfx_msr_write (RC_ID_MCP, MCP_CMPVAL0 + 4, &msr_value); + + /* COMPARATOR 3 */ + /* Upper limit = ypos + height + v_blank_pixels */ + + msr_value.low = (ypos + (unsigned long)height) << 16; + gfx_msr_write (RC_ID_MCP, MCP_CMPVAL0 + 6, &msr_value); + + /* SET COMPARATOR MASKS */ + + /* COMPARATORS 0 AND 1 REFER TO LOWER 16 BITS OF REGB */ + + msr_value.high = 0x00000000; + msr_value.low = 0x0000FFFF; + gfx_msr_write (RC_ID_MCP, MCP_CMPMASK0, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_CMPMASK0 + 2, &msr_value); + + /* COMPARATORS 2 AND 3 REFER TO UPPER 16 BITS OF REGB */ + + msr_value.low = 0xFFFF0000; + gfx_msr_write (RC_ID_MCP, MCP_CMPMASK0 + 4, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_CMPMASK0 + 6, &msr_value); + + /* SET REGA MASK TO CRC ONLY 24 BITS OF DATA */ + + msr_value.high = 0x00000000; + msr_value.low = 0x00FFFFFF; + gfx_msr_write (RC_ID_MCP, MCP_REGAMASK, &msr_value); + + /* SET REGB VALUE */ + /* Lower 16 bits use HTOTAL - SYNC TIME - 1 to set the counter rollover limit. */ + /* Upper 16 bits use 0xFFFF to remove auto-clear behavior. */ + + msr_value.high = 0x00000000; + msr_value.low = 0xFFFF0000 | + ((gfx_get_htotal() - (gfx_get_hsync_end() - gfx_get_hsync_start()) - 1) & 0xFFFF); + gfx_msr_write (RC_ID_MCP, MCP_REGBVAL, &msr_value); + + /* PROGRAM ACTIONS */ + + /* GOTO STATE 01 */ + + msr_value.high = 0x00000000; + msr_value.low = 0x00000008 | (1l << vsync_inactive_shift); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 14, &msr_value); + + /* GOTO STATE 10 */ + + msr_value.low = 0x00080000 | (1l << (vsync_active_shift + 16)); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 15, &msr_value); + + /* GOTO STATE 11 */ + + msr_value.low = 0x00000080 | (1l << (vsync_inactive_shift + 4)); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 16, &msr_value); + + /* CLEAR REGB (COUNTERS) */ + /* RegB is cleared upon transitioning to state 10 */ + /* RegA is not cleared as the initial value must be 0x00000001 */ + + msr_value.low = 0x00080000 | (1l << (vsync_active_shift + 16)); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0, &msr_value); + + /* CRC INTO REGA */ + /* INCREMENT H. COUNTER */ + /* cmp0 <= xpos < cmp1 */ + /* cmp2 <= ypos < cmp3 */ + /* XState = 10 */ + + msr_value.low = 0x00000008 | (1l << vsync_active_shift) | + 0x00800000 | (1l << (hsync_active_shift + 20)); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 1, &msr_value); + + /* INCREMENT V. COUNTER */ + /* V. Counter is incremented when the H. Counter */ + /* rolls over. */ + + msr_value.low = 0x00080000 | (1l << (vsync_inactive_shift + 16)); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 2, &msr_value); + + /* CLEAR ALL OTHER ACTIONS */ + /* This prevents side-effects from previous accesses to the MCP */ + /* debug logic. */ + msr_value.low = 0x00000000; + msr_value.high = 0x00000000; + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 3, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 4, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 5, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 6, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 7, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 8, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 9, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 10, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 11, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 12, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 13, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 17, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 18, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 19, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 20, &msr_value); + + /* SET REGA CRC VALUE TO 1 OR 0 */ + + if (!crc32) + msr_value.low = 0x00000001; + gfx_msr_write (RC_ID_MCP, MCP_REGA, &msr_value); + + /* SET XSTATE TO 0 */ + + msr_value.low = 0; + msr_value.high = 0; + gfx_msr_write (RC_ID_MCP, MCP_XSTATE, &msr_value); + + /* CONFIGURE DIAG CONTROL */ + /* Set all four comparators to watch the upper diag bus. */ + /* Set REGA action1 to legacy CRC or 32-bit CRC. */ + /* Set REGB action1 to increment lower 16 bits and clear at limit. */ + /* Set REGB action2 to increment upper 16 bits. */ + /* Enable all actions. */ + + if (crc32) + msr_value.low = 0x9A820055; + else + msr_value.low = 0x9A840055; + msr_value.high = 0x00000000; + gfx_msr_write (RC_ID_MCP, MCP_DIAGCTL, &msr_value); + + /* DELAY TWO FRAMES */ + + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + + /* VERIFY THAT XSTATE = 11 */ + + gfx_msr_read (RC_ID_MCP, MCP_XSTATE, &msr_value); + if ((msr_value.low & 3) == 3) + { + gfx_msr_read (RC_ID_MCP, MCP_REGA, &msr_value); + + crc = msr_value.low; + if (!crc32) + crc &= 0xFFFFFF; + } + + /* DISABLE MCP AND DF DIAG BUS OUTPUTS */ + + msr_value.low = 0x00000000; + msr_value.high = 0x00000000; + gfx_msr_write (RC_ID_DF, MBD_MSR_DIAG, &msr_value); + gfx_msr_write (RC_ID_MCP, MBD_MSR_DIAG, &msr_value); + + /* DISABLE MCP ACTIONS */ + + msr_value.high = 0x00000000; + msr_value.low = 0x00000000; + gfx_msr_write (RC_ID_MCP, MCP_DIAGCTL, &msr_value); + + /* RESTORE PREVIOUS OUTPUT FORMAT */ + + if (source != CRC_SOURCE_GFX_DATA) + { + gfx_msr_read (RC_ID_DF, MBD_MSR_CONFIG, &msr_value); + msr_value.low = old_fmt; + gfx_msr_write (RC_ID_DF, MBD_MSR_CONFIG, &msr_value); + } + return crc; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_enable + * + * This routine returns 1 if the selected alpha window is currently + * enabled, or 0 if it is currently disabled. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void castle_get_alpha_enable(int *enable) +#else +void gfx_get_alpha_enable(int *enable) +#endif +{ + unsigned long value = 0; + *enable = 0; + if (gfx_alpha_select <= 2) + { + value = READ_VID32(CASTLE_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 5)); + if (value & CASTLE_ACTRL_WIN_ENABLE) *enable = 1; + } + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_size + * + * This routine returns the size of the currently selected alpha region. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void castle_get_alpha_size(unsigned short *x, unsigned short *y, + unsigned short *width, unsigned short *height) +#else +void gfx_get_alpha_size(unsigned short *x, unsigned short *y, + unsigned short *width, unsigned short *height) +#endif +{ + unsigned long value = 0; + *x = 0; + *y = 0; + *width = 0; + *height = 0; + if (gfx_alpha_select <= 2) + { + value = READ_VID32(CASTLE_ALPHA_XPOS_1 + ((unsigned long)gfx_alpha_select << 5)); + *x = (unsigned short) (value & 0x000007FF); + *width = (unsigned short) ((value >> 16) & 0x000007FF) - *x; + value = READ_VID32(CASTLE_ALPHA_YPOS_1 + ((unsigned long)gfx_alpha_select << 5)); + *y = (unsigned short) (value & 0x000007FF); + *height = (unsigned short) ((value >> 16) & 0x000007FF) - *y; + } + *x -= gfx_get_htotal() - gfx_get_hsync_end() - 2; + *y -= gfx_get_vtotal() - gfx_get_vsync_end() + 1; + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_value + * + * This routine returns the alpha value and increment/decrement value of + * the currently selected alpha region. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void castle_get_alpha_value(unsigned char *alpha, char *delta) +#else +void gfx_get_alpha_value(unsigned char *alpha, char *delta) +#endif +{ + unsigned long value = 0; + *alpha = 0; + *delta = 0; + if (gfx_alpha_select <= 2) + { + value = READ_VID32(CASTLE_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 5)); + *alpha = (unsigned char) (value & 0x00FF); + *delta = (char) ((value >> 8) & 0x00FF); + } + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_priority + * + * This routine returns the priority of the currently selected alpha region. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void castle_get_alpha_priority(int *priority) +#else +void gfx_get_alpha_priority(int *priority) +#endif +{ + unsigned long pos = 0, value = 0; + *priority = 0; + if (gfx_alpha_select <= 2) + { + value = READ_VID32(CASTLE_VID_ALPHA_CONTROL); + pos = 16 + (gfx_alpha_select << 1); + *priority = (int) ((value >> pos) & 3); + } + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_color + * + * This routine returns the color register value for the currently selected + * alpha region. Bit 24 is set if the color register is enabled. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void castle_get_alpha_color(unsigned long *color) +#else +void gfx_get_alpha_color(unsigned long *color) +#endif +{ + *color = 0; + if (gfx_alpha_select <= 2) + { + *color = READ_VID32(CASTLE_ALPHA_COLOR_1 + ((unsigned long)gfx_alpha_select << 5)); + } + return; +} + +#endif /* GFX_READ_ROUTINES */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/tv_fs450.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/tv_fs450.c 2005-12-14 11:29:24.000000000 -0700 @@ -0,0 +1,3339 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to control the FS450 tvout encoder. + * */ + + + +#define FS450_DIRECTREG 0 + +#include "tv_fs450.h" + +/*========================================================================== +* +* Macros +* +*========================================================================== +*/ + +#undef fsmax +#undef fsmin +#define fsmax(a, b) ((a) > (b) ? (a) : (b)) +#define fsmin(a, b) ((a) < (b) ? (a) : (b)) + +#undef range_limit +#define range_limit(val,min_val,max_val) (fsmax((min_val),fsmin((val),(max_val)))) + +/*========================================================================== +* +* Registers +* +*========================================================================== +*/ + +#define MAX_REGISTERS 32 +#define MAX_BITS 32 + +#define READ 1 +#define WRITE 2 +#define READ_WRITE (READ | WRITE) + +typedef struct +{ + char *name; + unsigned long offset; + unsigned char bit_length; + unsigned char valid_bits; + unsigned char read_write; + char *bitfield_names[MAX_BITS]; +} S_REGISTER_DESCRIP; + +typedef struct +{ + int source; + char *name; + S_REGISTER_DESCRIP registers[MAX_REGISTERS]; +} S_SET_DESCRIP; + +const S_SET_DESCRIP *houston_regs(void); +const S_SET_DESCRIP *encoder_regs(void); +const S_SET_DESCRIP *macrovision_regs(void); +const S_SET_DESCRIP *gcc_regs(void); + +/*========================================================================== +* +* Houston Register Addresses & Bit Definitions +* +*========================================================================== +*/ + +#define HOUSTON_IHO 0x00 /*Input Horizontal Offset*/ +#define HOUSTON_IVO 0x02 /*Input Vertical Offset*/ +#define HOUSTON_IHA 0x04 /*Input Horizontal Active Width*/ +#define HOUSTON_VSC 0x06 /*Vertical Scaling Coeficient*/ +#define HOUSTON_HSC 0x08 /*Horizontal Scaling Coeficient*/ +#define HOUSTON_BYP 0x0A /*Bypass Register*/ +#define HOUSTON_CR 0x0C /*Control Register*/ +#define HOUSTON_SP 0x0E /*Status*/ +#define HOUSTON_NCONL 0x10 /*NCO numerator low word*/ +#define HOUSTON_NCONH 0x12 /*NCO numerator high word*/ +#define HOUSTON_NCODL 0x14 /*NCO denominator low word*/ +#define HOUSTON_NCODH 0x16 /*NCO denominator high word*/ +#define HOUSTON_APO 0x18 /**/ +#define HOUSTON_ALO 0x1A /**/ +#define HOUSTON_AFO 0x1C /**/ +#define HOUSTON_HSOUTWID 0x1E /**/ +#define HOUSTON_HSOUTST 0x20 /**/ +#define HOUSTON_HSOUTEND 0x22 /**/ +#define HOUSTON_SHP 0x24 /*Sharpness*/ +#define HOUSTON_FLK 0x26 /*Flicker Filter*/ +#define HOUSTON_BCONTL 0x28 /**/ +#define HOUSTON_BCONTH 0x2A /**/ +#define HOUSTON_BDONE 0x2C /**/ +#define HOUSTON_BDIAGL 0x2E /**/ +#define HOUSTON_BDIAGH 0x30 /**/ +#define HOUSTON_REV 0x32 /**/ +#define HOUSTON_MISC 0x34 /**/ +#define HOUSTON_FFO 0x36 /**/ +#define HOUSTON_FFO_LAT 0x38 /**/ +#define HOUSTON_VSOUTWID 0x3A +#define HOUSTON_VSOUTST 0x3C +#define HOUSTON_VSOUTEND 0x3E + +/*// BYP Register Bits*/ +#define BYP_RGB_BYPASS 0x0001 +#define BYP_HDS_BYPASS 0x0002 +#define BYP_HDS_TBYPASS 0x0004 +#define BYP_CAC_BYPASS 0x0008 +#define BYP_R2V_SBYPASS 0x0010 +#define BYP_R2V_BYPASS 0x0020 +#define BYP_VDS_BYPASS 0x0040 +#define BYP_FFT_BYPASS 0x0080 +#define BYP_FIF_BYPASS 0x0100 +#define BYP_FIF_TBYPASS 0x0200 +#define BYP_HUS_BYPASS 0x0400 +#define BYP_HUS_TBYPASS 0x0800 +#define BYP_CCR_BYPASS 0x1000 +#define BYP_PLL_BYPASS 0x2000 +#define BYP_NCO_BYPASS 0x4000 +#define BYP_ENC_BYPASS 0x8000 + +/*// CR Register Bits*/ +#define CR_RESET 0x0001 +#define CR_CLKOFF 0x0002 +#define CR_NCO_EN 0x0004 +#define CR_COMPOFF 0x0008 +#define CR_YCOFF 0x0010 +#define CR_LP_EN 0x0020 +#define CR_CACQ_CLR 0x0040 +#define CR_FFO_CLR 0x0080 +#define CR_656_PAL_NTSC 0x0100 +#define CR_656_STD_VMI 0x0200 +#define CR_OFMT 0x0400 +#define CR_UIM_CLK 0x0800 +#define CR_UIM_DEC 0x1000 +#define CR_BIPGEN_EN1 0x2000 +#define CR_UIM_MOD0 0x4000 +#define CR_UIM_MOD1 0x8000 + +/*// Status Register Bits*/ +#define SP_CACQ_ST 0x0001 +#define SP_FFO_ST 0x0002 +#define SP_REVID_MASK 0x7FFC +#define SP_MV_EN 0x8000 + +/*// BDONE Register Bits*/ +#define BDONE_BIST_DONE_A 0x0001 +#define BDONE_BIST_DONE_B 0x0002 +#define BDONE_BIST_DONE_C 0x0004 +#define BDONE_BIST_DONE_D 0x0008 +#define BDONE_BIST_DONE_E 0x0010 +#define BDONE_BIST_DONE_F 0x0020 +#define BDONE_BIST_DONE_G 0x0040 + +/*// BDIAGL Register Bits*/ +#define BDIAGL_BIST_DIAG_A 0x000F +#define BDIAGL_BIST_DIAG_B 0x00F0 +#define BDIAGL_BIST_DIAG_C 0x0F00 +#define BDIAGL_BIST_DIAG_D 0xF000 + +/*// BDIAGH Register Bits*/ +#define BDIAGH_BIST_DIAG_E 0x000F +#define BDIAGH_BIST_DIAG_F 0x000F +#define BDIAGH_BIST_DIAG_G 0x000F + +/*// MISC Register Bits*/ +#define MISC_TV_SHORT_FLD 0x0001 +#define MISC_ENC_TEST 0x0002 +#define MISC_DAC_TEST 0x0004 +#define MISC_MV_SOFT_EN 0x0008 +#define MISC_NCO_LOAD0 0x0010 +#define MISC_NCO_LOAD1 0x0020 +#define MISC_VGACKDIV 0x0200 +#define MISC_BRIDGE_SYNC 0x0400 +#define MISC_GTLIO_PD 0x8000 + + +/*========================================================================== +* +* Encoder Registers & Bit Definitions +* +*========================================================================== +*/ + +#define ENC_CHROMA_FREQ 0x40 +#define ENC_CHROMA_PHASE 0x44 +#define ENC_REG05 0x45 +#define ENC_REG06 0x46 +#define ENC_REG07 0x47 +#define ENC_HSYNC_WIDTH 0x48 +#define ENC_BURST_WIDTH 0x49 +#define ENC_BACK_PORCH 0x4A +#define ENC_CB_BURST_LEVEL 0x4B +#define ENC_CR_BURST_LEVEL 0x4C +#define ENC_SLAVE_MODE 0x4D +#define ENC_BLACK_LEVEL 0x4e +#define ENC_BLANK_LEVEL 0x50 +#define ENC_NUM_LINES 0x57 +#define ENC_WHITE_LEVEL 0x5e +#define ENC_CB_GAIN 0x60 +#define ENC_CR_GAIN 0x62 +#define ENC_TINT 0x65 +#define ENC_BREEZE_WAY 0x69 +#define ENC_FRONT_PORCH 0x6C +#define ENC_ACTIVELINE 0x71 +#define ENC_FIRST_LINE 0x73 +#define ENC_REG34 0x74 +#define ENC_SYNC_LEVEL 0x75 +#define ENC_VBI_BLANK_LEVEL 0x7C +#define ENC_RESET 0x7e +#define ENC_NOTCH_FILTER 0x8d + +/*========================================================================== +* +* Macrovision Registers & Bit Definitions +* +*========================================================================== +*/ + +#define MV_N0 0x59 +#define MV_N1 0x52 +#define MV_N2 0x7b +#define MV_N3 0x53 +#define MV_N4 0x79 +#define MV_N5 0x5d +#define MV_N6 0x7a +#define MV_N7 0x64 +#define MV_N8 0x54 +#define MV_N9 0x55 +#define MV_N10 0x56 +#define MV_N11 0x6d +#define MV_N12 0x6f +#define MV_N13 0x5a +#define MV_N14 0x5b +#define MV_N15 0x5c +#define MV_N16 0x63 +#define MV_N17 0x66 +#define MV_N18 0x68 +#define MV_N19 0x67 +#define MV_N20 0x61 +#define MV_N21 0x6a +#define MV_N22 0x76 +#define MV_AGC_PULSE_LEVEL 0x77 +#define MV_BP_PULSE_LEVEL 0x78 + +/*========================================================================== +* +* The TRACE macro can be used to display debug information. It can display +* one or more parameters in a formatted string like printf. No code will be +* generated for a release build. Use double parentheses for compatibility +* with C #define statements. Newline characters are not added +* automatically. Usage example: +* +* TRACE(("Number is %d, Name is %s.\n",iNumber,lpszName)) +* +*========================================================================== +*/ + +/*//#ifdef _DEBUG*/ +/*//void trace(const char *p_fmt,...);*/ +/*//#define TRACE(parameters) {trace parameters;}*/ +/*//#else*/ +#define TRACE(parameters) {} +/*//#endif*/ + +/****/ +/*// GCC timing structure.*/ +/****/ +typedef struct _S_TIMING_SPECS +{ + int vga_width; + int vga_lines; + int tv_width; + int tv_lines; + int h_total; + int h_sync; + int v_total; + int v_sync; +} S_TIMING_SPECS; + +/****/ +/*// Revision of Houston chip*/ +/****/ +#define HOUSTON_REV_A 0 +#define HOUSTON_REV_B 1 +static int houston_Rev(void); + +/*========================================================================== +* +* Functions +* +*========================================================================== +*/ + +static int houston_init(void); + +static unsigned char PLAL_FS450_i2c_address(void); +static int PLAL_FS450_UIM_mode(void); +static int PLAL_ReadRegister(S_REG_INFO *p_reg); +static int PLAL_WriteRegister(const S_REG_INFO *p_reg); +static int PLAL_IsTVOn(void); +static int PLAL_EnableVga(void); +static int PLAL_PrepForTVout(void); +static int PLAL_SetTVTimingRegisters(const S_TIMING_SPECS *p_specs); +static int PLAL_FinalEnableTVout(unsigned long vga_mode); + +/****/ +/*Direct Memory Access Functions*/ +/****/ +/*NOTE: Cx5530 is assumed hardcoded at 0x10000 offset*/ +/*from MediaGX base. F4Bar is bogus as described in the*/ +/*Cx5530 datasheet (actually points to GX frame buffer).*/ +/****/ +static int DMAL_ReadUInt32(unsigned long phys_addr, unsigned long *p_data) +{ + *p_data = READ_REG32(phys_addr); + return 0; +} + +static int DMAL_WriteUInt32(unsigned long phys_addr, unsigned long data) +{ + WRITE_REG32(phys_addr, data); + return 0; +} + +/****/ +/*Houston register access functions.*/ +/****/ +static int houston_ReadReg(unsigned int reg, unsigned long *p_value, unsigned int bytes) +{ + return gfx_i2c_read(1, PLAL_FS450_i2c_address(), (unsigned char)reg, + (unsigned char)bytes, (unsigned char *)p_value); +} + +static int houston_WriteReg(unsigned int reg, unsigned long value, unsigned int bytes) +{ + return gfx_i2c_write(1, PLAL_FS450_i2c_address(), (unsigned char)reg, + (unsigned char)bytes, (unsigned char *)&value); +} + +/****/ +/*TV configuration functions.*/ +/****/ +static int config_init(void); +static const S_TIMING_SPECS *p_specs(void); +static void config_power(int on); +static void config_vga_mode(unsigned long vga_mode); +static void config_tv_std(unsigned long tv_std, unsigned int trigger_bits); +static void conget_tv_std(unsigned long *p_tv_std); +static unsigned long supported_standards(void); +static void config_tvout_mode(unsigned long tvout_mode); +static void conget_tvout_mode(unsigned long *p_tvout_mode); +static void config_overscan_xy( unsigned long tv_std, unsigned long vga_mode, + int overscan_x, int overscan_y, int pos_x, int pos_y); +static void config_nco(unsigned long tv_std,unsigned long vga_mode); +static void config_sharpness(int sharpness); +static void conget_sharpness(int *p_sharpness); +static void config_flicker(int flicker); +static void conget_flicker(int *p_flicker); +static void config_color(int color); +static void conget_color(int *p_color); +static void config_brightness_contrast(unsigned long tv_std, unsigned int trigger_bits, + int brightness, int contrast); +static void conget_brightness_contrast(unsigned long tv_std, unsigned int trigger_bits, + int *p_brightness,int *p_contrast); +static void config_yc_filter(unsigned long tv_std,int luma_filter, int chroma_filter); +static void conget_yc_filter(int *p_luma_filter, int *p_chroma_filter); +static void config_macrovision(unsigned long tv_std, unsigned int cp_trigger_bits); +static void conget_macrovision(unsigned long tv_std, unsigned int *p_cp_trigger_bits); + +/****/ +/*Device settings.*/ +/****/ +typedef struct _S_DEVICE_SETTINGS +{ + int tv_on; + unsigned long vga_mode; + unsigned long tv_std; + unsigned long tvout_mode; + int overscan_x; + int overscan_y; + int position_x; + int position_y; + int sharpness; + int flicker; + int color; + int brightness; + int contrast; + unsigned char yc_filter; + unsigned int aps_trigger_bits; + int last_overscan_y; +} S_DEVICE_SETTINGS; + +static S_DEVICE_SETTINGS d; + +/*//==========================================================================*/ +/****/ +/*TV Setup Parameters*/ +/****/ +/*//==========================================================================*/ + +static const struct +{ + unsigned long chroma_freq[5]; + unsigned short chroma_phase[5]; + unsigned short cphase_rst[5]; + unsigned short color[5]; + unsigned short cr_burst_level[5]; + unsigned short cb_burst_level[5]; + unsigned short sys625_50[5]; + unsigned short vsync5[5]; + unsigned short pal_mode[5]; + unsigned short hsync_width[5]; + unsigned short burst_width[5]; + unsigned short back_porch[5]; + unsigned short front_porch[5]; + unsigned short breeze_way[5]; + unsigned short activeline[5]; + unsigned short blank_level[5]; + unsigned short vbi_blank_level[5]; + unsigned short black_level[5]; + unsigned short white_level[5]; + unsigned short hamp_offset[5]; + unsigned short sync_level[5]; + unsigned short tv_lines[5]; + unsigned short tv_width[5]; + unsigned short tv_active_lines[5]; + unsigned short tv_active_width[5]; + unsigned char notch_filter[5]; + unsigned short houston_cr[5]; + unsigned short houston_ncodl[5]; + unsigned short houston_ncodh[5]; +} tvsetup = +{ + /* ntsc, pal, ntsc-eij, pal-m, pal-n*/ + { 0x1f7cf021, 0xcb8a092a, 0x1f7cf021, 0xe3efe621, 0xcb8a092a }, /*chroma_freq*/ + { 0, 0, 0, 0, 0 }, /*chroma_phase*/ + { 2, 0, 2, 0, 0 }, /*cphase_rst*/ + { 54, 43, 54, 43, 43 }, /*color*/ + { 0, 31, 0, 29, 29 }, /*cr_burst_level*/ + { 59, 44, 59, 41, 41 }, /*cb_burst_level*/ + { 0, 1, 0, 0, 1 }, /*sys625_50*/ + { 0, 1, 0, 0, 0 }, /*vsync5*/ + { 0, 1, 0, 1, 1 }, /*pal_mode*/ + { 0x7a, 0x7a, 0x7a, 0x7a, 0x7a }, /*hsync_width*/ + { 0x40, 0x3c, 0x40, 0x40, 0x3c }, /*burst_width*/ + { 0x80, 0x9a, 0x80, 0x80, 0x9a }, /*back_porch*/ + { 0x24, 0x1e, 0x24, 0x24, 0x1e }, /*front_porch*/ + { 0x19, 0x1a, 0x19, 0x12, 0x1a }, /*breeze_way*/ + { 0xb4, 0xb4, 0xb4, 0xb4, 0xb4 }, /*active_line*/ + { 240, 251, 240, 240, 240 }, /*blank_level*/ + { 240, 251, 240, 240, 240 }, /*vbi_blank_level*/ + { 284, 252, 240, 252, 252 }, /*black_level*/ + { 823, 821, 823, 821, 821 }, /*white_level*/ + { 60, 48, 60, 48, 48 }, /*hamp_offset*/ + { 0x08, 0x08, 0x08, 0x08, 0x08 }, /*sync_level*/ + { 525, 625, 525, 525, 625 }, /*tv_lines*/ + { 858, 864, 858, 858, 864 }, /*tv_width*/ + { 487, 576, 487, 487, 576 }, /*tv_active_lines*/ + { 800, 800, 800, 800, 800 }, /*tv_active_width*/ + { 0x1a, 0x1d, 0x1a, 0x1d, 0x1d }, /*notch filter enabled*/ + { 0x0000, 0x0100, 0x0000, 0x0000, 0x0100 }, /*houston cr pal*/ + { 0x7e48, 0xf580, 0x7e48, 0x7e48, 0xf580 }, /*houston ncodl*/ + { 0x001b, 0x0020, 0x001b, 0x001b, 0x0020 } /*houston ncodh*/ +}; + +/****/ +/*MediaGX default underscan and centered position setups.*/ +/****/ +#define SCANTABLE_ENTRIES 5 +struct _scantable +{ + unsigned long mode; + unsigned short v_total[5]; + unsigned short v_sync[5]; + unsigned short iha[5]; + signed short iho[5]; + signed short hsc[5]; +}; + +static struct _scantable scantable[SCANTABLE_ENTRIES] = +{ + { + GFX_VGA_MODE_640X480, + { 617, 624, 617, 624, 624 }, /*v_total*/ + { 69, 88, 69, 88, 88 }, /*v_sync*/ + { 720, 720, 720, 720, 720 }, /*iha */ + { 0, 0, 0, 0, 0 }, /*iho */ + { -12, 0, -6, 0, 0 } /*hsc*/ + }, + { + GFX_VGA_MODE_800X600, + { 740, 740, 740, 740, 740 }, /*v_total*/ + { 90, 88, 90, 88, 88 }, /*v_sync*/ + { 720, 720, 508, 720, 720 }, /*iha */ + { -8, 11, -8, -8, 11 }, /*iho */ + { -27, -27, -27, -27, -27 } /*hsc*/ + }, + { + GFX_VGA_MODE_720X487, + { 525, 720, 525, 720, 720 }, /*v_total*/ + { 23, 230, 23, 230, 230 }, /*v_sync*/ + { 720, 720, 720, 720, 720 }, /*iha */ + { 0xa2, 0xa2, 0xa2, 0xa2, 0xa2 }, /*iho */ + { 0, 0, 0, 0, 0 } /*hsc*/ + }, + { + GFX_VGA_MODE_720X576, + { 720, 625, 720, 625, 625 }, /*v_total*/ + { 129, 25, 129, 25, 25 }, /*v_sync*/ + { 720, 720, 720, 720, 720 }, /*iha */ + { 0xaa, 0xaa, 0xaa, 0xaa, 0xaa }, /*iho */ + { 0, 0, 0, 0, 0 } /*hsc*/ + }, + { + GFX_VGA_MODE_1024X768, + { 933, 942, 933, 806, 806 }, /*v_total*/ + { 121, 112, 121, 88, 88 }, /*v_sync*/ + { 600, 600, 600, 600, 600 }, /*iha */ + { 0x3c, 0x23, 0x3c, 0x65, 0x65 }, /*iho */ + { 35, 26, 35, 26, 26 } /*hsc*/ + }, +}; + +/****/ +/*Houston fifo configuration constants.*/ +/****/ +struct _ffolat +{ + int v_total; + unsigned short ffolat; +}; + +struct _ffolativo +{ + int v_total; + unsigned short ivo; + unsigned short ffolat; +}; + +/*h_total=832, ivo=40, tv_width=858, tv_lines=525, vga_lines=480*/ +#define SIZE6X4NTSC 66 +static struct _ffolat ffo6x4ntsc[SIZE6X4NTSC+1] = +{ + { 541, 0x40 }, { 545, 0x40 }, { 549, 0x40 }, { 553, 0x40 }, + { 557, 0x58 }, { 561, 0x40 }, { 565, 0x40 }, { 569, 0x40 }, + { 573, 0x48 }, { 577, 0x40 }, { 581, 0x40 }, { 585, 0x40 }, + { 589, 0x40 }, { 593, 0x48 }, { 597, 0x40 }, { 601, 0x40 }, + { 605, 0x40 }, { 609, 0x40 }, { 613, 0x5b }, { 617, 0x48 }, + { 621, 0x60 }, { 625, 0x48 }, { 629, 0x48 }, { 633, 0x40 }, + { 637, 0x5e }, { 641, 0x40 }, { 645, 0x50 }, { 649, 0x56 }, + { 653, 0x58 }, { 657, 0x6c }, { 661, 0x40 }, { 665, 0x40 }, + { 669, 0x40 }, { 673, 0x40 }, { 677, 0x40 }, { 681, 0x40 }, + { 685, 0x40 }, { 689, 0x40 }, { 693, 0x40 }, { 697, 0x40 }, + { 701, 0x40 }, { 705, 0x40 }, { 709, 0x40 }, { 713, 0x40 }, + { 717, 0x40 }, { 721, 0x40 }, { 725, 0x40 }, { 729, 0x40 }, + { 733, 0x40 }, { 737, 0x40 }, { 741, 0x40 }, { 745, 0x40 }, + { 749, 0x40 }, { 753, 0x40 }, { 757, 0x40 }, { 761, 0x40 }, + { 765, 0x40 }, { 769, 0x40 }, { 773, 0x40 }, { 777, 0x40 }, + { 781, 0x40 }, { 785, 0x40 }, { 789, 0x40 }, { 793, 0x40 }, + { 797, 0x30 }, { 801, 0x40 }, + { -1, 0 } +}; + +#define SIZE6X4PAL 45 +static struct _ffolat ffo6x4pal[SIZE6X4PAL+1] = +{ + { 625, 0x60 }, { 629, 0x60 }, { 633, 0x60 }, { 637, 0x60 }, + { 641, 0x50 }, { 645, 0x60 }, { 649, 0x60 }, { 653, 0x60 }, + { 657, 0x60 }, { 661, 0x60 }, { 665, 0x60 }, { 669, 0x60 }, + { 673, 0x60 }, { 677, 0x60 }, { 681, 0x60 }, { 685, 0x60 }, + { 689, 0x60 }, { 693, 0x60 }, { 697, 0x60 }, { 701, 0x60 }, + { 705, 0x60 }, { 709, 0x60 }, { 713, 0x60 }, { 717, 0x60 }, + { 721, 0x60 }, { 725, 0x60 }, { 729, 0x60 }, { 733, 0x60 }, + { 737, 0x60 }, { 741, 0x60 }, { 745, 0x60 }, { 749, 0x60 }, + { 753, 0x60 }, { 757, 0x60 }, { 761, 0x60 }, { 765, 0x60 }, + { 769, 0x60 }, { 773, 0x60 }, { 777, 0x60 }, { 781, 0x60 }, + { 785, 0x60 }, { 789, 0x60 }, { 793, 0x60 }, { 797, 0x60 }, + { 801, 0x60 }, + { -1, 0 } +}; + +#define SIZE7X4NTSC 40 +static struct _ffolat ffo7x4ntsc[SIZE7X4NTSC+1] = +{ + { 525, 0x52 }, { 529, 0x52 }, { 533, 0x52 }, { 537, 0x52 }, + { 541, 0x52 }, { 545, 0x40 }, { 549, 0x40 }, { 553, 0x40 }, + { 557, 0x58 }, { 561, 0x40 }, { 565, 0x58 }, { 569, 0x40 }, + { 573, 0x48 }, { 577, 0x40 }, { 581, 0x40 }, { 585, 0x40 }, + { 589, 0x40 }, { 593, 0x48 }, { 597, 0x40 }, { 601, 0x40 }, + { 605, 0x40 }, { 609, 0x40 }, { 613, 0x5b }, { 617, 0x48 }, + { 621, 0x60 }, { 625, 0x48 }, { 629, 0x48 }, { 633, 0x40 }, + { 637, 0x5e }, { 641, 0x40 }, { 645, 0x50 }, { 649, 0x56 }, + { 653, 0x58 }, { 657, 0x6c }, { 661, 0x40 }, { 665, 0x40 }, + { 669, 0x40 }, { 673, 0x40 }, { 677, 0x40 }, { 681, 0x40 }, + { -1, 0 } +}; + +#define SIZE7X4PAL 24 +static struct _ffolat ffo7x4pal[SIZE7X4PAL+1] = +{ + { 625, 0x60 }, { 629, 0x60 }, { 633, 0x60 }, { 637, 0x60 }, + { 641, 0x50 }, { 645, 0x60 }, { 649, 0x60 }, { 653, 0x60 }, + { 657, 0x60 }, { 661, 0x60 }, { 665, 0x60 }, { 669, 0x60 }, + { 673, 0x60 }, { 677, 0x60 }, { 681, 0x60 }, { 685, 0x60 }, + { 689, 0x60 }, { 693, 0x60 }, { 697, 0x60 }, { 701, 0x60 }, + { 705, 0x60 }, { 709, 0x60 }, { 713, 0x60 }, { 717, 0x60 }, + { -1, 0 } +}; + +#define SIZE7X5NTSC 54 +static struct _ffolat ffo7x5ntsc[SIZE7X5NTSC+1] = +{ + { 590, 0x40 }, { 594, 0x48 }, { 598, 0x40 }, { 602, 0x40 }, + { 606, 0x40 }, { 610, 0x40 }, { 614, 0x5b }, { 618, 0x48 }, + { 622, 0x60 }, { 626, 0x48 }, { 630, 0x48 }, { 634, 0x40 }, + { 638, 0x5e }, { 642, 0x40 }, { 646, 0x50 }, { 650, 0x56 }, + { 654, 0x58 }, { 658, 0x6c }, { 662, 0x40 }, { 666, 0x40 }, + { 670, 0x40 }, { 674, 0x40 }, { 678, 0x40 }, { 682, 0x40 }, + { 686, 0x40 }, { 690, 0x40 }, { 694, 0x40 }, { 698, 0x40 }, + { 702, 0x40 }, { 706, 0x40 }, { 710, 0x40 }, { 714, 0x40 }, + { 718, 0x40 }, { 722, 0x40 }, { 726, 0x40 }, { 730, 0x40 }, + { 734, 0x40 }, { 738, 0x40 }, { 742, 0x40 }, { 746, 0x40 }, + { 750, 0x40 }, { 754, 0x40 }, { 758, 0x40 }, { 762, 0x40 }, + { 766, 0x40 }, { 770, 0x40 }, { 774, 0x40 }, { 778, 0x40 }, + { 782, 0x40 }, { 786, 0x40 }, { 790, 0x40 }, { 794, 0x40 }, + { 798, 0x30 }, { 802, 0x40 }, + { -1, 0 } +}; + +#define SIZE7X5PAL 45 +static struct _ffolat ffo7x5pal[SIZE7X5PAL+1] = +{ + { 625, 0x60 }, { 629, 0x60 }, { 633, 0x60 }, { 637, 0x60 }, + { 641, 0x50 }, { 645, 0x60 }, { 649, 0x60 }, { 653, 0x60 }, + { 657, 0x60 }, { 661, 0x60 }, { 665, 0x60 }, { 669, 0x60 }, + { 673, 0x60 }, { 677, 0x60 }, { 681, 0x60 }, { 685, 0x60 }, + { 689, 0x60 }, { 693, 0x60 }, { 697, 0x60 }, { 701, 0x60 }, + { 705, 0x60 }, { 709, 0x60 }, { 713, 0x60 }, { 717, 0x60 }, + { 721, 0x60 }, { 725, 0x60 }, { 729, 0x60 }, { 733, 0x60 }, + { 737, 0x60 }, { 741, 0x60 }, { 745, 0x60 }, { 749, 0x60 }, + { 753, 0x60 }, { 757, 0x60 }, { 761, 0x60 }, { 765, 0x60 }, + { 769, 0x60 }, { 773, 0x60 }, { 777, 0x60 }, { 781, 0x60 }, + { 785, 0x60 }, { 789, 0x60 }, { 793, 0x60 }, { 797, 0x60 }, + { 801, 0x60 }, + { -1, 0 } +}; + +/*h_total=1056, vga_lines=600*/ +#define SIZE8X6NTSC 37 +static struct _ffolat ffo8x6ntsc[SIZE8X6NTSC+1] = { + { 620, 0x40 }, /*v_total_min >= vsync+10 >= vga_lines+10 = 610*/ + { 625, 0x58 }, { 630, 0x40 }, { 635, 0x40 }, { 640, 0x40 }, + { 645, 0x46 }, { 650, 0x46 }, { 655, 0x4f }, { 660, 0x4c }, + { 665, 0x4a }, { 670, 0x50 }, { 675, 0x2f }, { 680, 0x48 }, + { 685, 0x38 }, { 690, 0x31 }, { 695, 0x40 }, { 700, 0x21 }, + { 705, 0x25 }, { 710, 0x40 }, { 715, 0x48 }, { 720, 0x50 }, + { 725, 0x30 }, { 730, 0x50 }, { 735, 0x50 }, { 740, 0x50 }, + { 745, 0x40 }, { 750, 0x38 }, { 755, 0x50 }, { 760, 0x50 }, + { 765, 0x40 }, { 770, 0x38 }, { 775, 0x40 }, { 780, 0x40 }, + { 785, 0x40 }, { 790, 0x38 }, { 795, 0x50 }, { 800, 0x50 }, + { -1, 0 } +}; + +/*h_total=1056, vga_lines=600*/ +#define SIZE8X6PAL 36 +static struct _ffolat ffo8x6pal[SIZE8X6PAL+1] = { + { 625, 0x80 }, { 630, 0x80 }, { 635, 0x5a }, { 640, 0x55 }, + { 645, 0x48 }, { 650, 0x65 }, { 655, 0x65 }, { 660, 0x50 }, + { 665, 0x80 }, { 670, 0x70 }, { 675, 0x56 }, { 680, 0x80 }, + { 685, 0x58 }, { 690, 0x31 }, { 695, 0x80 }, { 700, 0x60 }, + { 705, 0x45 }, { 710, 0x4a }, { 715, 0x50 }, { 720, 0x50 }, + { 725, 0x50 }, { 730, 0x45 }, { 735, 0x50 }, { 740, 0x50 }, + { 745, 0x50 }, { 750, 0x50 }, { 755, 0x50 }, { 760, 0x50 }, + { 765, 0x50 }, { 770, 0x50 }, { 775, 0x50 }, { 780, 0x50 }, + { 785, 0x50 }, { 790, 0x50 }, { 795, 0x50 }, { 800, 0x50 }, + { -1, 0 } +}; + +/*h_total=1344, vga_lines=768*/ +#define SIZE10X7NTSC 45 +static struct _ffolativo ffo10x7ntsc[SIZE10X7NTSC] = { + { 783, 0x4d, 0x40 }, + { 789, 0x47, 0x14 }, + { 795, 0x47, 0x7f }, + { 801, 0x47, 0x53 }, + { 807, 0x47, 0x11 }, + { 813, 0x47, 0x78 }, + { 819, 0x47, 0x54 }, + { 825, 0x47, 0x40 }, + { 831, 0x47, 0x0f }, + { 837, 0x4d, 0x40 }, + { 843, 0x47, 0x5a }, + { 849, 0x4d, 0x40 }, + { 855, 0x47, 0x4b }, + { 861, 0x4d, 0x40 }, + { 867, 0x47, 0x4b }, + { 873, 0x4d, 0x40 }, + { 879, 0x47, 0x07 }, + { 885, 0x48, 0x20 }, + { 891, 0x47, 0x82 }, + { 897, 0x47, 0x60 }, + { 903, 0x47, 0x7f }, + { 909, 0x4d, 0x40 }, + { 915, 0x48, 0x40 }, + { 921, 0x4c, 0x40 }, + { 927, 0x49, 0x40 }, + { 933, 0x48, 0x40 }, + { 939, 0x4a, 0x40 }, + { 945, 0x46, 0x40 }, + { 951, 0x4a, 0x40 }, + { 957, 0x4a, 0x40 }, + { 963, 0x4b, 0x40 }, + { 969, 0x4b, 0x40 }, + { 975, 0x48, 0x40 }, + { 981, 0x47, 0x40 }, + { 987, 0x47, 0x40 }, + { 993, 0x47, 0x40 }, + { 999, 0x48, 0x40 }, + { 1005, 0x48, 0x40 }, + { 1011, 0x47, 0x40 }, + { 1017, 0x47, 0x40 }, + { 1023, 0x48, 0x40 }, + { 1029, 0x48, 0x40 }, + { 1035, 0x46, 0x40 }, + { 1041, 0x47, 0x40 }, + { 1047, 0x47, 0x40 } +}; + +/*h_total=1344, vga_lines=768*/ +#define SIZE10X7PAL 46 +static struct _ffolativo ffo10x7pal[SIZE10X7PAL] = { + { 781, 0x49, 0x40 }, + { 787, 0x46, 0x40 }, + { 793, 0x48, 0x40 }, + { 799, 0x46, 0x40 }, + { 805, 0x49, 0x40 }, + { 811, 0x47, 0x40 }, + { 817, 0x46, 0x40 }, + { 823, 0x46, 0x56 }, + { 829, 0x46, 0x2d }, + { 835, 0x46, 0x40 }, + { 841, 0x46, 0x2d }, + { 847, 0x46, 0x3f }, + { 853, 0x46, 0x10 }, + { 859, 0x46, 0x86 }, + { 865, 0x46, 0xc9 }, + { 871, 0x46, 0x83 }, + { 877, 0x46, 0xa8 }, + { 883, 0x46, 0x81 }, + { 889, 0x46, 0xa5 }, + { 895, 0x46, 0xa9 }, + { 901, 0x46, 0x81 }, + { 907, 0x46, 0xa4 }, + { 913, 0x46, 0xa5 }, + { 919, 0x46, 0x7f }, + { 925, 0x46, 0xa2 }, + { 931, 0x46, 0x9d }, + { 937, 0x46, 0xc1 }, + { 943, 0x46, 0x96 }, + { 949, 0x46, 0xb7 }, + { 955, 0x46, 0xb1 }, + { 961, 0x46, 0x8a }, + { 967, 0x46, 0xa9 }, + { 973, 0x46, 0xa0 }, + { 979, 0x46, 0x40 }, + { 985, 0x46, 0x97 }, + { 991, 0x46, 0xb5 }, + { 997, 0x46, 0xaa }, + { 1003, 0x46, 0x83 }, + { 1009, 0x46, 0x9f }, + { 1015, 0x47, 0x40 }, + { 1021, 0x46, 0xad }, + { 1027, 0x46, 0x87 }, + { 1033, 0x46, 0xa2 }, + { 1039, 0x47, 0x40 }, + { 1045, 0x46, 0xac }, + { 1051, 0x46, 0x86 } +}; + +/*//==========================================================================*/ +/****/ +/*FS450 API Functions.*/ +/****/ +/*//==========================================================================*/ + +/****/ +/*Initialize device settings*/ +/****/ +static void initialize_houston_static_registers(void) +{ + houston_WriteReg(HOUSTON_BYP, 0, 2); + houston_WriteReg(HOUSTON_APO, 0, 2); + houston_WriteReg(HOUSTON_ALO, 0, 2); + houston_WriteReg(HOUSTON_AFO, 0, 2); + houston_WriteReg(HOUSTON_BCONTL,0, 2); + houston_WriteReg(HOUSTON_BCONTH,0, 2); + houston_WriteReg(HOUSTON_BDONE, 0, 2); + houston_WriteReg(HOUSTON_BDIAGL,0, 2); + houston_WriteReg(HOUSTON_BDIAGH,0, 2); + houston_WriteReg(HOUSTON_MISC, 0, 2); +} + +int FS450_init(void) +{ + int err; + + TRACE(("FS450_Init()\n")) + + err = houston_init(); + if (err) + return err; + + + initialize_houston_static_registers(); + +#if (1) + d.tv_on = PLAL_IsTVOn() ? 1 : 0; +#else + d.tv_on = 0; +#endif + +#if (1) + /*get the current tv standard*/ + conget_tv_std(&d.tv_std); +#else + /*default to VP_TV_STANDARD_NTSC_M*/ + d.tv_std = VP_TV_STANDARD_NTSC_M; + config_tv_std(d.tv_std); +#endif + + d.vga_mode = 0; + +#if (0) + /*get the current tvout mode*/ + conget_tvout_mode(&d.tvout_mode); +#else + /*default to VP_TVOUT_MODE_CVBS_YC*/ + d.tvout_mode = GFX_TVOUT_MODE_CVBS_YC; +#endif + +#if (0) + /*get the current sharpness*/ + conget_sharpness(d.sharpness); +#else + /*default to 1000 out of 1000*/ + d.sharpness = 1000; + config_sharpness(d.sharpness); +#endif + +#if (0) + /*get the current flicker*/ + conget_flicker(d.flicker); +#else + /*default to 800 out of 1000*/ + d.flicker = 800; + config_flicker(d.flicker); +#endif + +#if (0) + /*get the current size and position*/ +#else + /*default to zeros*/ + d.overscan_x = 0; + d.overscan_y = 0; + d.position_x = 0; + d.position_y = 0; +#endif + +#if (0) + /*get the current color*/ + conget_color(d.color); +#else + d.color = 50; + /*//d.color = tvsetup.color[k];*/ + config_color(d.color); +#endif + +#if (0) + /*get the current brightness and contrast*/ + conget_brightness_contrast(d.tv_std,d.aps_trigger_bits,d.brightness,d.contrast); +#else + /*default*/ + d.brightness = 50; + d.contrast = 60; + config_brightness_contrast(d.tv_std,d.aps_trigger_bits,d.brightness,d.contrast); +#endif + +#if (1) + /*get the current yc filtering*/ + { + int luma_filter,chroma_filter; + + conget_yc_filter(&luma_filter,&chroma_filter); + d.yc_filter = 0; + if (luma_filter) + d.yc_filter |= GFX_LUMA_FILTER; + if (chroma_filter) + d.yc_filter |= GFX_CHROMA_FILTER; + } +#else + /*default*/ + d.yc_filter = GFX_LUMA_FILTER + GFX_CHROMA_FILTER; +#endif + +#if (0) + /*get the current cp settings*/ + conget_macrovision(d.tv_std,&d.aps_trigger_bits); +#else + d.aps_trigger_bits = 0; + config_macrovision(d.tv_std,d.aps_trigger_bits); +#endif + + d.last_overscan_y = -10000; + + return 0; +} + +void FS450_cleanup(void) +{ +} + +/*//==========================================================================*/ +/****/ +/*// Required configuration calls to write new settings to the device*/ + +#define REQ_TV_STANDARD_BIT 0x0002 +#define REQ_VGA_MODE_BIT 0x0004 +#define REQ_TVOUT_MODE_BIT 0x0008 +#define REQ_SHARPNESS_BIT 0x0010 +#define REQ_FLICKER_BIT 0x0020 +#define REQ_OVERSCAN_POSITION_BIT 0x0040 +#define REQ_COLOR_BIT 0x0080 +#define REQ_BRIGHTNESS_CONTRAST_BIT 0x0100 +#define REQ_YC_FILTER_BIT 0x0200 +#define REQ_MACROVISION_BIT 0x0400 +#define REQ_NCO_BIT 0x1000 + +#define REQ_TV_STANDARD (REQ_TV_STANDARD_BIT | REQ_OVERSCAN_POSITION | REQ_BRIGHTNESS_CONTRAST | REQ_MACROVISION_BIT | REQ_YC_FILTER) +#define REQ_VGA_MODE (REQ_VGA_MODE_BIT | REQ_OVERSCAN_POSITION) +#define REQ_TVOUT_MODE (REQ_TVOUT_MODE_BIT) +#define REQ_SHARPNESS (REQ_SHARPNESS_BIT) +#define REQ_FLICKER (REQ_FLICKER_BIT) +#define REQ_OVERSCAN_POSITION (REQ_OVERSCAN_POSITION_BIT | REQ_NCO) +#define REQ_COLOR (REQ_COLOR_BIT) +#define REQ_BRIGHTNESS_CONTRAST (REQ_BRIGHTNESS_CONTRAST_BIT) +#define REQ_YC_FILTER (REQ_YC_FILTER_BIT) +#define REQ_MACROVISION (REQ_TV_STANDARD_BIT | REQ_BRIGHTNESS_CONTRAST_BIT | REQ_MACROVISION_BIT) +#define REQ_NCO (REQ_NCO_BIT) +#define REQ_ENCODER (REQ_TV_STANDARD | REQ_COLOR | REQ_BRIGHTNESS_CONTRAST | REQ_YC_FILTER) + +static int write_config(int req) +{ + unsigned long reg, reg_encoder_reset = 0; + int reset; + + /*if we're changing the nco, and the vertical scaling has changed...*/ + reset = ((REQ_NCO_BIT & req) && (d.overscan_y != d.last_overscan_y)); + if (reset) + { + /*put the encoder into reset while making changes*/ + houston_ReadReg(ENC_RESET, ®, 1); + houston_WriteReg(ENC_RESET, reg | 0x01, 1); + reg_encoder_reset = reg & 0x01; + } + + if (REQ_TV_STANDARD_BIT & req) + config_tv_std(d.tv_std, d.aps_trigger_bits); + + if (REQ_VGA_MODE_BIT & req) + config_vga_mode(d.vga_mode); + + if (REQ_TVOUT_MODE_BIT & req) + config_tvout_mode(d.tvout_mode); + + if (REQ_OVERSCAN_POSITION_BIT & req) + { + config_overscan_xy( + d.tv_std, + d.vga_mode, + d.overscan_x, + d.overscan_y, + d.position_x, + d.position_y); + + /*h_timing and v_timing and syncs.*/ + if (PLAL_IsTVOn()) + PLAL_SetTVTimingRegisters(p_specs()); + } + + if (REQ_NCO_BIT & req) + config_nco(d.tv_std,d.vga_mode); + + if (REQ_SHARPNESS_BIT & req) + config_sharpness(d.sharpness); + + if (REQ_FLICKER_BIT & req) + config_flicker(d.flicker); + + if (REQ_COLOR_BIT & req) + config_color(d.color); + + if (REQ_BRIGHTNESS_CONTRAST_BIT & req) + { + config_brightness_contrast( + d.tv_std, + d.aps_trigger_bits, + d.brightness, + d.contrast); + } + + if (REQ_YC_FILTER_BIT & req) + { + config_yc_filter( + d.tv_std, + (d.yc_filter & GFX_LUMA_FILTER), + (d.yc_filter & GFX_CHROMA_FILTER)); + } + + if (REQ_MACROVISION_BIT & req) + config_macrovision(d.tv_std,d.aps_trigger_bits); + + /*if we decided to put the encoder into reset, put it back*/ + if (reset) + { + houston_ReadReg(ENC_RESET, ®, 1); + houston_WriteReg(ENC_RESET, reg_encoder_reset | (reg & ~0x01), 1); + + d.last_overscan_y = d.overscan_y; + } + return 0; +} + +/*==========================================================================*/ +/****/ +/*// TV On*/ + +#if GFX_TV_DYNAMIC +int fs450_get_tv_enable(unsigned int *p_on) +#else +int gfx_get_tv_enable(unsigned int *p_on) +#endif +{ + if (!p_on) + return ERR_INVALID_PARAMETER; + + *p_on = d.tv_on; + + return 0; +} + +/*//int FS450_set_tv_on(unsigned int on)*/ +#if GFX_TV_DYNAMIC +int fs450_set_tv_enable(int on) +#else +int gfx_set_tv_enable(int on) +#endif +{ + unsigned long reg; + + /*if not mode change, just return*/ + if ((d.tv_on && on) || (!d.tv_on && !on)) + return 0; + + /*if turning off...*/ + if (!on) + { + /*reenable vga.*/ + PLAL_EnableVga(); + + /*power down houston*/ + config_power(0); + + d.tv_on = 0; + + return 0; + } + + /*turning on...*/ + + /*power up houston */ + config_power(1); + + /*assert encoder reset.*/ + houston_WriteReg(ENC_RESET, 0x01, 1); + + /*initial platform preparation*/ + PLAL_PrepForTVout(); + + /*configure encoder and nco.*/ + write_config( + REQ_VGA_MODE | + REQ_TV_STANDARD | + REQ_TVOUT_MODE | + REQ_OVERSCAN_POSITION | + REQ_YC_FILTER | + REQ_MACROVISION); + + /*set LP_EN and UIM*/ + houston_ReadReg(HOUSTON_CR, ®, 2); + reg |= CR_LP_EN; + reg &= ~(CR_UIM_MOD0 | CR_UIM_MOD1); + reg |= (PLAL_FS450_UIM_mode() << 14); + houston_WriteReg(HOUSTON_CR,reg,2); + + /*set platform timing registers*/ + PLAL_SetTVTimingRegisters(p_specs()); + + PLAL_FinalEnableTVout(d.vga_mode); + + /*sync bridge*/ + { + int retry_count = 0; + + /*sync 50 times*/ + while (retry_count++ < 50) + { + /*sync bridge.*/ + houston_ReadReg(HOUSTON_MISC, ®, 2); + reg |= MISC_BRIDGE_SYNC; + houston_WriteReg(HOUSTON_MISC, reg, 2); + reg &= ~MISC_BRIDGE_SYNC; + houston_WriteReg(HOUSTON_MISC, reg, 2); + } + } + + /*deassert encoder reset.*/ + houston_WriteReg(ENC_RESET, 0x00, 1); + + d.tv_on = 1; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_tv_defaults(int format) +#else +int gfx_set_tv_defaults(int format) +#endif +{ + return 0; +} + +/*==========================================================================*/ +/****/ +/*// TV standard*/ + +#if GFX_TV_DYNAMIC +int fs450_get_tv_standard(unsigned long *p_standard) +#else +int gfx_get_tv_standard(unsigned long *p_standard) +#endif +{ + if (!p_standard) + return ERR_INVALID_PARAMETER; + + *p_standard = d.tv_std; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_get_available_tv_standards(unsigned long *p_standards) +#else +int gfx_get_available_tv_standards(unsigned long *p_standards) +#endif +{ + if (!p_standards) + return ERR_INVALID_PARAMETER; + + *p_standards = supported_standards(); + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_tv_standard(unsigned long standard) +#else +int gfx_set_tv_standard(unsigned long standard) +#endif +{ + /*verify supported standard.*/ + if (!(standard & supported_standards())) + return ERR_INVALID_PARAMETER; + + /*disallow if tv is on*/ + if (d.tv_on) + return ERR_CANNOT_CHANGE_WHILE_TV_ON; + + d.tv_std = standard; +/*// d.color = tvsetup.color[k];*/ + + return write_config(REQ_TV_STANDARD); +} + +/*==========================================================================*/ +/****/ +/*// vga mode as known by the driver*/ +#if GFX_TV_DYNAMIC +int fs450_get_tv_vga_mode(unsigned long *p_vga_mode) +#else +int gfx_get_tv_vga_mode(unsigned long *p_vga_mode) +#endif + +{ + if (!p_vga_mode) + return ERR_INVALID_PARAMETER; + + *p_vga_mode = d.vga_mode; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_get_available_tv_vga_modes(unsigned long *p_vga_modes) +#else +int gfx_get_available_tv_vga_modes(unsigned long *p_vga_modes) +#endif +{ + if (!p_vga_modes) + return ERR_INVALID_PARAMETER; + + *p_vga_modes = + GFX_VGA_MODE_640X480 | + GFX_VGA_MODE_720X487 | + GFX_VGA_MODE_720X576 | + GFX_VGA_MODE_800X600; + if (houston_Rev() >= HOUSTON_REV_B) + *p_vga_modes |= GFX_VGA_MODE_1024X768; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_tv_vga_mode(unsigned long vga_mode) +#else +int gfx_set_tv_vga_mode(unsigned long vga_mode) +#endif +{ + /*reject if not a single valid VGA mode*/ + switch (vga_mode) + { + default: + return ERR_INVALID_PARAMETER; + + case GFX_VGA_MODE_640X480: + case GFX_VGA_MODE_720X487: + case GFX_VGA_MODE_720X576: + case GFX_VGA_MODE_800X600: + break; + + case GFX_VGA_MODE_1024X768: + if (houston_Rev() >= HOUSTON_REV_B) + break; + return ERR_INVALID_PARAMETER; + } + + /*if the mode has changed...*/ + if (vga_mode != d.vga_mode) + { + d.vga_mode = vga_mode; + + return write_config(REQ_VGA_MODE); + } + + return 0; +} + +/*==========================================================================*/ +/****/ +/*// tvout mode*/ + +#if GFX_TV_DYNAMIC +int fs450_get_tvout_mode(unsigned long *p_tvout_mode) +#else +int gfx_get_tvout_mode(unsigned long *p_tvout_mode) +#endif +{ + if (!p_tvout_mode) + return ERR_INVALID_PARAMETER; + + *p_tvout_mode = d.tvout_mode; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_tvout_mode(unsigned long tvout_mode) +#else +int gfx_set_tvout_mode(unsigned long tvout_mode) +#endif +{ + d.tvout_mode = tvout_mode; + + return write_config(REQ_TVOUT_MODE); +} + +/*==========================================================================*/ +/****/ +/*// Sharpness*/ + +#if GFX_TV_DYNAMIC +int fs450_get_sharpness(int *p_sharpness) +#else +int gfx_get_sharpness(int *p_sharpness) +#endif +{ + if (!p_sharpness) + return ERR_INVALID_PARAMETER; + + *p_sharpness = d.sharpness; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_sharpness(int sharpness) +#else +int gfx_set_sharpness(int sharpness) +#endif +{ + d.sharpness = range_limit(sharpness, 0, 1000); + + return write_config(REQ_SHARPNESS); +} + +/*==========================================================================*/ +/****/ +/*flicker filter control.*/ + +#if GFX_TV_DYNAMIC +int fs450_get_flicker_filter(int *p_flicker) +#else +int gfx_get_flicker_filter(int *p_flicker) +#endif +{ + if (!p_flicker) + return ERR_INVALID_PARAMETER; + + *p_flicker = d.flicker; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_flicker_filter(int flicker) +#else +int gfx_set_flicker_filter(int flicker) +#endif +{ + d.flicker = range_limit(flicker, 0, 1000); + + return write_config(REQ_FLICKER); +} + +/*==========================================================================*/ +/****/ +/*// Overscan and Position*/ + +#if GFX_TV_DYNAMIC +int fs450_get_overscan(int *p_x, int *p_y) +#else +int gfx_get_overscan(int *p_x, int *p_y) +#endif +{ + if (!p_x || !p_y) + return ERR_INVALID_PARAMETER; + + *p_x = d.overscan_x; + *p_y = d.overscan_y; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_overscan(int x, int y) +#else +int gfx_set_overscan(int x, int y) +#endif +{ + d.overscan_x = range_limit(x, -1000, 1000); + d.overscan_y = range_limit(y, -1000, 1000); + + return write_config(REQ_OVERSCAN_POSITION); +} + +#if GFX_TV_DYNAMIC +int fs450_get_position(int *p_x, int *p_y) +#else +int gfx_get_position(int *p_x, int *p_y) +#endif +{ + if (!p_x || !p_y) + return ERR_INVALID_PARAMETER; + + *p_x = d.position_x; + *p_y = d.position_y; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_position(int x, int y) +#else +int gfx_set_position(int x, int y) +#endif +{ + d.position_x = range_limit(x, -1000, 1000); + d.position_y = range_limit(y, -1000, 1000); + + return write_config(REQ_OVERSCAN_POSITION); +} + +/*==========================================================================*/ +/****/ +/*// Color, Brightness, and Contrast*/ + +#if GFX_TV_DYNAMIC +int fs450_get_color(int *p_color) +#else +int gfx_get_color(int *p_color) +#endif +{ + if (!p_color) + return ERR_INVALID_PARAMETER; + + *p_color = d.color; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_color(int color) +#else +int gfx_set_color(int color) +#endif +{ + d.color = range_limit(color, 0, 100); + + return write_config(REQ_COLOR); +} + +#if GFX_TV_DYNAMIC +int fs450_get_brightness(int *p_brightness) +#else +int gfx_get_brightness(int *p_brightness) +#endif +{ + if (!p_brightness) + return ERR_INVALID_PARAMETER; + + *p_brightness = d.brightness; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_brightness(int brightness) +#else +int gfx_set_brightness(int brightness) +#endif +{ + d.brightness = range_limit(brightness, 0, 100); + + return write_config(REQ_BRIGHTNESS_CONTRAST); +} + +#if GFX_TV_DYNAMIC +int fs450_get_contrast(int *p_contrast) +#else +int gfx_get_contrast(int *p_contrast) +#endif +{ + if (!p_contrast) + return ERR_INVALID_PARAMETER; + + *p_contrast = d.contrast; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_contrast(int constrast) +#else +int gfx_set_contrast(int constrast) +#endif +{ + d.contrast = range_limit(constrast, 0, 100); + + return write_config(REQ_BRIGHTNESS_CONTRAST); +} + +/*==========================================================================*/ +/****/ +/*// YC filters*/ + +#if GFX_TV_DYNAMIC +int fs450_get_yc_filter(unsigned int *p_yc_filter) +#else +int gfx_get_yc_filter(unsigned int *p_yc_filter) +#endif +{ + if (!p_yc_filter) + return ERR_INVALID_PARAMETER; + + if (houston_Rev() < HOUSTON_REV_B) + return ERR_NOT_SUPPORTED; + + *p_yc_filter = d.yc_filter; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_yc_filter(unsigned int yc_filter) +#else +int gfx_set_yc_filter(unsigned int yc_filter) +#endif +{ + if (houston_Rev() < HOUSTON_REV_B) + return ERR_NOT_SUPPORTED; + + /*luma filter.*/ + if (yc_filter & GFX_LUMA_FILTER) + d.yc_filter |= GFX_LUMA_FILTER; + else + d.yc_filter &= ~GFX_LUMA_FILTER; + + /*chroma filter.*/ + if (yc_filter & GFX_CHROMA_FILTER) + d.yc_filter |= GFX_CHROMA_FILTER; + else + d.yc_filter &= ~GFX_CHROMA_FILTER; + + return write_config(REQ_YC_FILTER); +} + + +#if GFX_TV_DYNAMIC +int fs450_get_aps_trigger_bits(unsigned int *p_trigger_bits) +#else +int gfx_get_aps_trigger_bits(unsigned int *p_trigger_bits) +#endif +{ + if (!p_trigger_bits) + return ERR_INVALID_PARAMETER; + + *p_trigger_bits = d.aps_trigger_bits; + + return 0; +} + +#if GFX_TV_DYNAMIC +int fs450_set_aps_trigger_bits(unsigned int trigger_bits) +#else +int gfx_set_aps_trigger_bits(unsigned int trigger_bits) +#endif +{ + d.aps_trigger_bits = trigger_bits; + + return write_config(REQ_MACROVISION); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_format + * + * This routine sets the TV encoder registers to the specified format + * and resolution. + * Currently only NTSC 640x480 is supported. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int fs450_set_tv_format(TVStandardType format, GfxOnTVType resolution) +#else +int gfx_set_tv_format(TVStandardType format, GfxOnTVType resolution) +#endif +{ + /* ### ADD ### IMPLEMENTATION */ + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_output + * + * This routine sets the TV encoder registers to the specified output type. + * Supported output types are : S-VIDEO and Composite. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int fs450_set_tv_output(int output) +#else +int gfx_set_tv_output(int output) +#endif +{ + /* ### ADD ### IMPLEMENTATION */ + return(0); +} + + +/*----------------------------------------------------------------------------- + * gfx_set_tv_cc_enable + * + * This routine enables or disables the use of the hardware CC registers + * in the TV encoder. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int fs450_set_tv_cc_enable(int enable) +#else +int gfx_set_tv_cc_enable(int enable) +#endif +{ + /* ### ADD ### IMPLEMENTATION */ + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_tv_cc_data + * + * This routine writes the two specified characters to the CC data register + * of the TV encoder. + *----------------------------------------------------------------------------- + */ +#if GFX_TV_DYNAMIC +int fs450_set_tv_cc_data(unsigned char data1, unsigned char data2) +#else +int gfx_set_tv_cc_data(unsigned char data1, unsigned char data2) +#endif +{ + /* ### ADD ### IMPLEMENTATION */ + return(0); +} + +#ifdef FS450_DIRECTREG + +/*//==========================================================================*/ +/****/ +/*// Direct Read and Write registers*/ + +int FS450_ReadRegister(S_REG_INFO *p_reg) +{ + unsigned long tmp; + + if (PLAL_ReadRegister(p_reg)) + return 0; + + if (SOURCE_HOUSTON == p_reg->source) + { + switch(p_reg->size) + { + case 1: + case 2: + { + houston_ReadReg((int)p_reg->offset, &tmp, (int)p_reg->size); + p_reg->value = tmp; + } + return 0; + + case 4: + { + houston_ReadReg((unsigned int)p_reg->offset, &tmp, 2); + p_reg->value = (tmp << 16); + houston_ReadReg((unsigned int)(p_reg->offset+2), &tmp, 2); + p_reg->value |= tmp; + } + return 0; + } + } + + return ERR_INVALID_PARAMETER; +} + +int FS450_WriteRegister(S_REG_INFO *p_reg) +{ + if (PLAL_WriteRegister(p_reg)) + return 0; + + if (SOURCE_HOUSTON == p_reg->source) + { + houston_WriteReg((unsigned int)p_reg->offset, p_reg->value, p_reg->size); + + return 0; + } + + return ERR_INVALID_PARAMETER; +} + +#endif + +/****/ +/*Houston initialization function.*/ +/****/ +static int g_houston_rev = -1; + +static int houston_init(void) +{ + /*//int errc;*/ + unsigned long write, read; + + TRACE(("houston_init()\n")) + + /*initialize I2C*/ + /*errc = I2C_init(); + if (errc) + return errc; + */ + + /*Before we begin, we must enable power to the TFT*/ + read = READ_VID32 (CS5530_DISPLAY_CONFIG); + read |= CS5530_DCFG_FP_PWR_EN | CS5530_DCFG_FP_DATA_EN; + WRITE_VID32 (CS5530_DISPLAY_CONFIG, read); + + + /*simple w/r test.*/ + write = 0x0055; + read = 0; + + houston_WriteReg(HOUSTON_IHO, write, 2); + houston_ReadReg(HOUSTON_IHO, &read, 2); + if (read != write) + { + houston_WriteReg(HOUSTON_IHO, write, 2); + houston_ReadReg(HOUSTON_IHO, &read, 2); + if (read != write) + { + /*chip is not there, do something appropriate?*/ + TRACE(("wrote HOUSTON_IHO=0x0055, read 0x%04x\n",read)) + return ERR_DEVICE_NOT_FOUND; + } + } + + /*read chip revision.*/ + houston_ReadReg(HOUSTON_REV, &read, 2); + g_houston_rev = (int) read; + + /*ok.*/ + return 0; +} + +static int houston_Rev(void) +{ + return g_houston_rev; +} + +static S_TIMING_SPECS g_specs; + +static const S_TIMING_SPECS *p_specs(void) +{ + return &g_specs; +} + +/*//==========================================================================*/ +/****/ +/*FS450 configuration functions.*/ +/****/ +/*//==========================================================================*/ +static int config_init(void) +{ + int err; + + TRACE(("config_init()\n")) + + err = houston_init(); + if (err) + return err; + + return 0; +} + + +/*==========================================================================*/ +/****/ +/*convert word to encoder 10 bit value.*/ + +static unsigned short w10bit2z(unsigned short w) +{ + return (w >> 2) | ((w & 0x03) << 8); +} + +static unsigned short z2w10bit(unsigned short z) +{ + return (0x03 & (z >> 8)) | ((0xFF & z) << 2); +} + + +/*==========================================================================*/ +/****/ +/*// TV Standards*/ + +static const struct +{ + unsigned long standard; + int tvsetup_index; +} g_tv_standards[] = +{ + {GFX_TV_STANDARD_NTSC_M, 0}, + {GFX_TV_STANDARD_NTSC_M_J, 2}, + {GFX_TV_STANDARD_PAL_B, 1}, + {GFX_TV_STANDARD_PAL_D, 1}, + {GFX_TV_STANDARD_PAL_H, 1}, + {GFX_TV_STANDARD_PAL_I, 1}, + {GFX_TV_STANDARD_PAL_M, 3}, + {GFX_TV_STANDARD_PAL_N, 4}, + {GFX_TV_STANDARD_PAL_G, 1}, +}; + +static int map_tvstd_to_index(unsigned long tv_std) +{ + unsigned int i; + + for (i = 0; i < sizeof(g_tv_standards) / sizeof(*g_tv_standards); i++) + { + if (tv_std == g_tv_standards[i].standard) + return g_tv_standards[i].tvsetup_index; + } + + return -1; +} + +static unsigned long supported_standards(void) +{ + unsigned long standards = 0; + unsigned int i; + + for (i = 0; i < sizeof(g_tv_standards) / sizeof(*g_tv_standards); i++) + { + if (g_tv_standards[i].tvsetup_index >= 0) + standards |= g_tv_standards[i].standard; + } + + return standards; +} + + +/*==========================================================================*/ + +static void config_power(int on) +{ + unsigned long reg; + + if (houston_Rev() < HOUSTON_REV_B) + { + /*no power down supported, but still turn of clock in off mode*/ + if (on) + { + houston_ReadReg(HOUSTON_CR, ®, 2); + reg &= ~(CR_CLKOFF | CR_RESET); + houston_WriteReg(HOUSTON_CR, reg, 2); + reg |= CR_RESET; + houston_WriteReg(HOUSTON_CR, reg, 2); + reg &= ~CR_RESET; + houston_WriteReg(HOUSTON_CR, reg, 2); + } + else + { + houston_ReadReg(HOUSTON_CR, ®, 2); + reg |= CR_CLKOFF; + houston_WriteReg(HOUSTON_CR, reg, 2); + } + + return; + } + + if (on) + { + /*!CLKOFF, !COMPOFF, !YCOFF*/ + /*and reset Houston*/ + houston_ReadReg(HOUSTON_CR, ®, 2); + reg &= ~(CR_CLKOFF | CR_RESET | CR_COMPOFF | CR_YCOFF); + houston_WriteReg(HOUSTON_CR, reg, 2); + reg |= CR_RESET; + houston_WriteReg(HOUSTON_CR, reg, 2); + reg &= ~CR_RESET; + houston_WriteReg(HOUSTON_CR, reg, 2); + + /*!GTLIO_PD*/ + houston_ReadReg(HOUSTON_MISC, ®, 2); + reg &= ~MISC_GTLIO_PD; + houston_WriteReg(HOUSTON_MISC,reg,2); + } + else + { + /*CLKOFF, COMPOFF, YCOFF*/ + houston_ReadReg(HOUSTON_CR, ®, 2); + reg |= (CR_CLKOFF | CR_COMPOFF | CR_YCOFF); + houston_WriteReg(HOUSTON_CR, reg, 2); + + /*GTLIO_PD*/ + houston_ReadReg(HOUSTON_MISC, ®, 2); + reg |= MISC_GTLIO_PD; + houston_WriteReg(HOUSTON_MISC,reg,2); + } +} + + +/*==========================================================================*/ +/****/ +/*// VGA mode*/ + +static void config_vga_mode(unsigned long vga_mode) +{ + /*h_total must be evenly divisible by 32?*/ + + static struct + { + unsigned long mode; + int width; + int lines; + int h_total; + } vgaparams[] = + { + {GFX_VGA_MODE_640X480, 640, 480, 1056}, + {GFX_VGA_MODE_720X487, 720, 487, 1056}, + {GFX_VGA_MODE_720X576, 720, 576, 1056}, + {GFX_VGA_MODE_800X600, 800, 600, 1056}, + {GFX_VGA_MODE_1024X768, 1024, 768, 1344}, + }; + + unsigned long cr, misc, byp; + unsigned int i; + + g_specs.vga_width = 0; + g_specs.vga_lines = 0; + g_specs.h_total = 0; + + for (i = 0; i < sizeof(vgaparams) / sizeof(*vgaparams); i++) + { + if (vga_mode == vgaparams[i].mode) + { + g_specs.vga_width = vgaparams[i].width; + g_specs.vga_lines = vgaparams[i].lines; + g_specs.h_total = vgaparams[i].h_total; + break; + } + } + if (!g_specs.h_total) + return; + + /*clock mux decimator and vga dual.*/ + houston_ReadReg(HOUSTON_CR, &cr, 2); + houston_ReadReg(HOUSTON_MISC, &misc, 2); + houston_ReadReg(HOUSTON_BYP, &byp, 2); + + if (vga_mode == GFX_VGA_MODE_1024X768) + { + /*XGA*/ + cr |= CR_UIM_DEC; + misc |= MISC_VGACKDIV; + byp |= (BYP_HDS_BYPASS | BYP_CAC_BYPASS); + } + else + { + /*VGA,SVGA*/ + cr &= ~CR_UIM_DEC; + misc &= ~MISC_VGACKDIV; + byp &= ~(BYP_HDS_BYPASS | BYP_CAC_BYPASS); + } + + houston_WriteReg(HOUSTON_CR, cr, 2); + houston_WriteReg(HOUSTON_MISC, misc, 2); + houston_WriteReg(HOUSTON_BYP, byp, 2); +} + + +/*==========================================================================*/ +/****/ +/*// Write settings for TV standard to device*/ + +static void config_tv_std(unsigned long tv_std, unsigned int trigger_bits) +{ + int k; + unsigned short reg34; + unsigned long cr, w; + unsigned long l; + + /*verify supported standard.*/ + k = map_tvstd_to_index(tv_std); + if (k < 0) + return; + + /*store tv width and lines*/ + g_specs.tv_width = tvsetup.tv_width[k]; + g_specs.tv_lines = tvsetup.tv_lines[k]; + + /*houston CR register.*/ + houston_ReadReg(HOUSTON_CR, &cr, 2); + cr &= ~CR_656_PAL_NTSC; + cr |= tvsetup.houston_cr[k]; + houston_WriteReg(HOUSTON_CR, cr, 2); + + /*setup the encoder.*/ + l = tvsetup.chroma_freq[k]; + houston_WriteReg(ENC_CHROMA_FREQ, (int)(l & 0x00ff), 1); + houston_WriteReg(ENC_CHROMA_FREQ+1, (int)((l>>8) & 0x00ff), 1); + houston_WriteReg(ENC_CHROMA_FREQ+2, (int)((l>>16) & 0x00ff), 1); + houston_WriteReg(ENC_CHROMA_FREQ+3, (int)((l>>24) & 0x00ff), 1); + + houston_WriteReg(ENC_CHROMA_PHASE, tvsetup.chroma_phase[k], 1); + houston_WriteReg(ENC_REG05, 0x00, 1); /*reg 0x05*/ + houston_WriteReg(ENC_REG06, 0x89, 1); /*reg 0x06*/ + houston_WriteReg(ENC_REG07, 0x00, 1); /*reg 0x07*/ + houston_WriteReg(ENC_HSYNC_WIDTH, tvsetup.hsync_width[k], 1); + houston_WriteReg(ENC_BURST_WIDTH, tvsetup.burst_width[k], 1); + houston_WriteReg(ENC_BACK_PORCH, tvsetup.back_porch[k], 1); + houston_WriteReg(ENC_CB_BURST_LEVEL, tvsetup.cb_burst_level[k], 1); + houston_WriteReg(ENC_CR_BURST_LEVEL, tvsetup.cr_burst_level[k], 1); + houston_WriteReg(ENC_SLAVE_MODE, 0x01, 1); /*slave mode*/ + if (trigger_bits == 0) + w = w10bit2z(tvsetup.blank_level[k]); /*blank level*/ + else + w = w10bit2z((unsigned short)(tvsetup.blank_level[k]-tvsetup.hamp_offset[k])); + houston_WriteReg(ENC_BLANK_LEVEL, w & 0x00ff, 1); + houston_WriteReg(ENC_BLANK_LEVEL+1, w >> 8, 1); + w = w10bit2z(tvsetup.tv_lines[k]); /*num_lines*/ + houston_WriteReg(ENC_NUM_LINES, w & 0x00ff, 1); + houston_WriteReg(ENC_NUM_LINES+1, w >> 8, 1); + + houston_WriteReg(ENC_TINT, 0x00, 1); /*tint*/ + houston_WriteReg(ENC_BREEZE_WAY, tvsetup.breeze_way[k], 1); + houston_WriteReg(ENC_FRONT_PORCH, tvsetup.front_porch[k], 1); + houston_WriteReg(ENC_ACTIVELINE, tvsetup.activeline[k], 1); + houston_WriteReg(ENC_FIRST_LINE, 0x15, 1); /*firstvideoline*/ + reg34 = + 0x80 | + (tvsetup.pal_mode[k] << 6) | + (tvsetup.sys625_50[k] << 3) | + (tvsetup.cphase_rst[k] << 1) | + (tvsetup.vsync5[k]); + houston_WriteReg(ENC_REG34, reg34, 1); /*reg 0x34*/ + houston_WriteReg(ENC_SYNC_LEVEL, tvsetup.sync_level[k], 1); + if (trigger_bits == 0) + w = w10bit2z(tvsetup.vbi_blank_level[k]); /*blank level*/ + else + w = w10bit2z((unsigned short)(tvsetup.vbi_blank_level[k]-1)); + houston_WriteReg(ENC_VBI_BLANK_LEVEL, w & 0x00ff, 1); + houston_WriteReg(ENC_VBI_BLANK_LEVEL+1, w >> 8, 1); +} + +static void conget_tv_std(unsigned long *p_tv_standard) +{ + unsigned long cr; + + if (!p_tv_standard) + return; + + /*just pick between NTSC and PAL*/ + houston_ReadReg(HOUSTON_CR, &cr, 2); + if (CR_656_PAL_NTSC & cr) + *p_tv_standard = GFX_TV_STANDARD_PAL_B; + else + *p_tv_standard = GFX_TV_STANDARD_NTSC_M; +} + +/*==========================================================================*/ +/****/ +/*// TVout mode*/ + +static void config_tvout_mode(unsigned long tvout_mode) +{ + unsigned long cr; + + houston_ReadReg(HOUSTON_CR, &cr, 2); + + /*all dacs off*/ + cr |= (CR_COMPOFF | CR_YCOFF); + /*not rgb*/ + cr &= ~CR_OFMT; + + /*turn on requested output*/ + if (GFX_TVOUT_MODE_CVBS & tvout_mode) + cr &= ~CR_COMPOFF; + if (GFX_TVOUT_MODE_YC & tvout_mode) + cr &= ~CR_YCOFF; + if (GFX_TVOUT_MODE_RGB & tvout_mode) + { + cr &= ~(CR_COMPOFF | CR_YCOFF); + cr |= CR_OFMT; + } + + houston_WriteReg(HOUSTON_CR, cr, 2); +} + +static void conget_tvout_mode(unsigned long *p_tvout_mode) +{ + unsigned long cr; + + if (!p_tvout_mode) + return; + + houston_ReadReg(HOUSTON_CR, &cr, 2); + + if (CR_OFMT & cr) + *p_tvout_mode = GFX_TVOUT_MODE_RGB; + else + { + *p_tvout_mode = 0; + if (!(CR_YCOFF & cr)) + *p_tvout_mode |= GFX_TVOUT_MODE_YC; + if (!(CR_COMPOFF & cr)) + *p_tvout_mode |= GFX_TVOUT_MODE_CVBS; + } +} + + +/*==========================================================================*/ +/****/ +/*// Size & Position*/ + +#define IS_NTSC(tv_std) (tv_std & ( \ + GFX_TV_STANDARD_NTSC_M | \ + GFX_TV_STANDARD_NTSC_M_J | \ + GFX_TV_STANDARD_PAL_M)) +#define IS_PAL(tv_std) (tv_std & ( \ + GFX_TV_STANDARD_PAL_B | \ + GFX_TV_STANDARD_PAL_D | \ + GFX_TV_STANDARD_PAL_H | \ + GFX_TV_STANDARD_PAL_I | \ + GFX_TV_STANDARD_PAL_N | \ + GFX_TV_STANDARD_PAL_G)) + +/*return fifo delay setting for mode, std, and total lines.*/ + +static void get_ffolat_ivo( + unsigned long vga_mode, + unsigned long tv_std, + long i, + unsigned short *ffolat, + unsigned short *ivo) +{ + switch (vga_mode) + { + case GFX_VGA_MODE_640X480: + if (IS_NTSC(tv_std)) + { + if (i > SIZE6X4NTSC-1) i = SIZE6X4NTSC-1; + *ffolat = ffo6x4ntsc[i].ffolat; + *ivo = 0x20; + } + else + { + if (i > SIZE6X4PAL-1) i = SIZE6X4PAL-1; + *ffolat = ffo6x4pal[i].ffolat; + *ivo = 0x28; + } + break; + + case GFX_VGA_MODE_800X600: + if (IS_NTSC(tv_std)) + { + if (i > SIZE8X6NTSC-1) i = SIZE8X6NTSC-1; + *ffolat = ffo8x6ntsc[i].ffolat; + *ivo = 0x3a; + } + else + { + if (i > SIZE8X6PAL-1) i = SIZE8X6PAL-1; + *ffolat = ffo8x6pal[i].ffolat; + *ivo = 0x39; + } + break; + + case GFX_VGA_MODE_720X487: + *ffolat = 0x40; /*//FFO7x4;*/ + *ivo = 0x1a; + break; + + case GFX_VGA_MODE_720X576: + *ffolat = 0x40; /*//FFO7x5;*/ + *ivo = 0x1a; + break; + + case GFX_VGA_MODE_1024X768: + default: + if (IS_NTSC(tv_std)) + { + if (i > SIZE10X7NTSC-1) i = SIZE10X7NTSC-1; + *ffolat = ffo10x7ntsc[i].ffolat; + *ivo = ffo10x7ntsc[i].ivo; + } + else + { + if (i > SIZE10X7PAL-1) i = SIZE10X7PAL-1; + *ffolat = ffo10x7pal[i].ffolat; + *ivo = ffo10x7pal[i].ivo; + } + break; + } +} + + +/*get vertical line min and max for mode and std.*/ + +static void get_vtotal_min_max( + unsigned long vga_mode, + unsigned long tv_std, + int *v_total_min, + int *v_total_max, + int *v_step) +{ + int k = map_tvstd_to_index(tv_std); + + switch (vga_mode) + { + case GFX_VGA_MODE_640X480: + if (IS_NTSC(tv_std)) + { + *v_total_min = ffo6x4ntsc[0].v_total; + *v_total_max = ffo6x4ntsc[SIZE6X4NTSC-1].v_total; + } + else + { + *v_total_min = ffo6x4pal[0].v_total; + *v_total_max = ffo6x4pal[SIZE6X4PAL-1].v_total; + } + *v_step = 4; + break; + + case GFX_VGA_MODE_800X600: + if (IS_NTSC(tv_std)) + { + *v_total_min = ffo8x6ntsc[0].v_total; + *v_total_max = ffo8x6ntsc[SIZE8X6NTSC-1].v_total; + } + else + { + *v_total_min = ffo8x6pal[0].v_total; + *v_total_max = ffo8x6pal[SIZE8X6PAL-1].v_total; + } + *v_step = 5; + break; + + case GFX_VGA_MODE_720X487: + case GFX_VGA_MODE_720X576: + *v_total_min = tvsetup.tv_lines[k]; + *v_total_max = tvsetup.tv_lines[k]; + *v_step = 4; + break; + + case GFX_VGA_MODE_1024X768: + if (IS_NTSC(tv_std)) + { + *v_total_min = ffo10x7ntsc[0].v_total; + *v_total_max = ffo10x7ntsc[SIZE10X7NTSC-1].v_total; + } + else + { + *v_total_min = ffo10x7pal[0].v_total; + *v_total_max = ffo10x7pal[SIZE10X7PAL-1].v_total; + } + *v_step = 6; + break; + } +} + +static void config_overscan_xy( + unsigned long tv_std, + unsigned long vga_mode, + int overscan_x, + int overscan_y, + int pos_x, + int pos_y) +{ + unsigned int vga_index; + unsigned long reg; + double vsc; + int k; + unsigned short ffolat, ivo; + int base_v_total, range, v_offset; + int v_total_min, v_total_max, v_step; + float r, f; + int vga_pixels,pre_pixels; + float hscale, hscale_min, hscale_max; + int hsc; + int iho, iho_max, ihw; + + /*tv_std is valid.*/ + k = map_tvstd_to_index(tv_std); + + /*store tv width and lines*/ + g_specs.tv_width = tvsetup.tv_width[k]; + g_specs.tv_lines = tvsetup.tv_lines[k]; + + /*determine vga mode index*/ + for (vga_index = 0; vga_index < SCANTABLE_ENTRIES; vga_index++) + { + if (scantable[vga_index].mode == vga_mode) + break; + } + if (vga_index >= SCANTABLE_ENTRIES) + return; + + /****/ + /*vertical scaling (v_total setup).*/ + /****/ + /*calculate vertical range.*/ + get_vtotal_min_max(vga_mode, tv_std, &v_total_min, &v_total_max, &v_step); + TRACE(("v_total min=%d, max=%d\n", v_total_min, v_total_max)) + base_v_total = scantable[vga_index].v_total[k]; + range = fsmax(base_v_total - v_total_min, v_total_max - base_v_total); + TRACE(("v_total range = %d\n",range)) + + /*map +/-1000 overscan y into +/-range.*/ + v_offset = (int) ((((float)overscan_y * range) / 1000.f) + .5f); + TRACE(("v_offset = %d\n", v_offset)) + + /*range limit v_total.*/ + g_specs.v_total = range_limit(base_v_total + v_offset, v_total_min, v_total_max); + + /*round to calibrated value.*/ + v_offset = (g_specs.v_total - v_total_min + (v_step/2)) / v_step; + g_specs.v_total = v_total_min + v_offset * v_step; + TRACE(("desired v_total=%d\n", g_specs.v_total)) + + /****/ + /*vertical positioning (vsync setup).*/ + /****/ + get_ffolat_ivo(vga_mode, tv_std, v_offset, &ffolat, &ivo); + houston_WriteReg(HOUSTON_IVO, ivo, 2); + + /*scale base sync offset by scaling ratio.*/ + r = (float) g_specs.v_total / (float) base_v_total; + v_offset = (int) (r * (float) scantable[vga_index].v_sync[k]); + + /*scale ivo.*/ + f = (float) ivo; + v_offset -= (int) (f - f/r); + + /*compensate for center screen.*/ + f = (float) tvsetup.tv_active_lines[k] / 2.f; + v_offset += (int) (f * r - f); + + /*calculate vsync.*/ + g_specs.v_sync = g_specs.v_total-v_offset + pos_y; + TRACE(("desired v_total=%d, desired v_sync=%d\n", g_specs.v_total, g_specs.v_sync)) + if (g_specs.v_sync < g_specs.vga_lines+10) + { + TRACE(("vsync too low\n")) + /*//d.v_total += d.vga_lines+10-d.v_sync;*/ + g_specs.v_sync = g_specs.vga_lines+10; + } + else if (g_specs.v_sync > g_specs.v_total-10) + { + TRACE(("vsync too high\n")) + g_specs.v_sync = g_specs.v_total-10; + } + TRACE(("v_total=%d v_sync=%d\n", g_specs.v_total, g_specs.v_sync)) + + /*FFOLAT.*/ + houston_WriteReg(HOUSTON_FFO_LAT, ffolat, 2); + + /*VSC.*/ + vsc = (65536.0f * (1.0f - (double)g_specs.tv_lines / (double)g_specs.v_total)) + 0.5f; + reg = ((unsigned long) -vsc) & 0xffff; + TRACE(("vsc=%04x, tv_lines=%d, v_total=%d\n", reg, g_specs.tv_lines, g_specs.v_total)) + houston_WriteReg(HOUSTON_VSC, (int)reg, 2); + + /****/ + /*horizontal scaling.*/ + /****/ + + /*vga pixels is vga width, except in 1024x768, where it's half that.*/ + vga_pixels = g_specs.vga_width; + if (1024 == vga_pixels) + vga_pixels /= 2; + + /*maximum scaling coefficient is tv_width / vga_pixels*/ + /*minimum is about 1/2, but that is quite small. arbitrarily set minimum at 75% maximum.*/ + hscale_max = (720.0f / vga_pixels); + hscale_min = fsmax((0.75f * hscale_max),(1.0f - (63.0f / 128.0f))); + TRACE(( + "hscale_min = %u.%u, hscale_max = %u.%u\n", + (int)hscale_min, + (int)((hscale_min - (int)hscale_min) * 1000), + (int)hscale_max, + (int)((hscale_max - (int)hscale_max) * 1000))) + + /*map overscan_x into min to max.*/ + hscale = hscale_min + ((overscan_x + 1000.0f) / 2000.0f) * (hscale_max - hscale_min); + TRACE(("hscale = %u.%u\n",(int)hscale,(int)((hscale - (int)hscale) * 1000))) + + /*determine hsc where hscale = (1 + hsc/128)*/ + if (hscale >= 1.0f) + hsc = (int)(128.f * (hscale - 1.0f) + .5f); + else + hsc = (int)(128.f * (hscale - 1.0f) - .5f); + TRACE(("hsc = %d\n",hsc)) + if (hsc >= 0) + houston_WriteReg(HOUSTON_HSC, hsc << 8, 2); + else + houston_WriteReg(HOUSTON_HSC, hsc & 0xFF, 2); + + /*recalculate hscale for future formulas*/ + hscale = 1.0f + (hsc / 128.0f); + TRACE(("recalculated hscale = %u.%u\n",(int)hscale,(int)((hscale - (int)hscale) * 1000))) + + /****/ + /*horizontal offset.*/ + /****/ + + /*place hsync 40 before halfway from vga_width to htotal*/ + /*but not less than vga_width + 10*/ + g_specs.h_sync = fsmax((g_specs.h_total + g_specs.vga_width) / 2 - 40, g_specs.vga_width + 10); + /*also, make it even*/ + g_specs.h_sync &= ~1; + TRACE(("hsync = %u\n",g_specs.h_sync)) + + /*iho range is 0 to iho_max.*/ + /*iho_max is 2 * iho_center.*/ + /*iho_center is pre_pixels - (tvwidth / hscale - vga pixels) / 2.*/ + /*pre_pixels = (htotal - hsync) * (vga_pixels / vga_width)*/ + /*note that the range is inverted also, because it specifies the number of pixels*/ + /*to skip, or subtract. iho=0 maps to farthest right.*/ + /*map -pos_x = +/-1000 into (0 to iho_max)*/ + pre_pixels = (int)((long)(g_specs.h_total - g_specs.h_sync) * vga_pixels / g_specs.vga_width); + iho_max = (2 * pre_pixels) - ((int)(720.0f / hscale + 0.5f) - vga_pixels); + TRACE(("iho_max = %u\n",iho_max)) + iho = (int) range_limit(((long)(1000 - pos_x) * iho_max / 2000)+scantable[vga_index].iho[k], 0, iho_max); + TRACE(("iho = %u\n",iho)) + houston_WriteReg(HOUSTON_IHO, iho, 2); + + /****/ + /*input horizontal width.*/ + /****/ + + /*input horizontal width is vga pixels + pre_pixels - iho*/ + /*additionally, ihw cannot exceed tv width / hscale*/ + /*and if hsc is negative, (ihw)(-hsc/128) cannot exceed ~250.*/ + /*and ihw should be even.*/ + ihw = fsmin( + vga_pixels + pre_pixels - iho, + (int)(720.0f / hscale)); + if (hsc < 0) + ihw = (int)fsmin(ihw,253L * 128 / (-hsc)); + ihw &= ~1; + TRACE(("ihw = %u\n",ihw)) + houston_WriteReg(HOUSTON_IHA, ihw, 2); + + f = (((float)g_specs.h_total * g_specs.v_total)*27.f) / + ((float)g_specs.tv_width * g_specs.tv_lines); + + TRACE(("freq=%u.%uMHz\n",(int)f,(int)((f - (int)f) * 1000))) +} + +/*==========================================================================*/ +/****/ +/*configure houston nco.*/ + +static void config_nco(unsigned long tv_std,unsigned long vga_mode) +{ + unsigned long cr, misc; + unsigned long reg; + int k = map_tvstd_to_index(tv_std); + + /*read and store CR.*/ + houston_ReadReg(HOUSTON_CR, &cr, 2); + + /*make sure NCO_EN (enable latch) bit is clear*/ + cr &= ~CR_NCO_EN; + houston_WriteReg(HOUSTON_CR, cr, 2); + + /*clear NCO_LOADX.*/ + houston_ReadReg(HOUSTON_MISC, &misc, 2); + misc &= ~(MISC_NCO_LOAD1 + MISC_NCO_LOAD0); + houston_WriteReg(HOUSTON_MISC, misc, 2); + + if (vga_mode == GFX_VGA_MODE_1024X768) + { + /*setup for M and N load (Nco_load=1).*/ + misc |= (MISC_NCO_LOAD0); + houston_WriteReg(HOUSTON_MISC, misc, 2); + + /*M and N.*/ + houston_WriteReg(HOUSTON_NCONL, 1024-2, 2); + houston_WriteReg(HOUSTON_NCODL, 128-1, 2); + + /*latch M/N in.*/ + cr |= CR_NCO_EN; + houston_WriteReg(HOUSTON_CR, cr, 2); + cr &= ~CR_NCO_EN; + houston_WriteReg(HOUSTON_CR, cr, 2); + + /*setup ncon and ncod load (Nco_load=0).*/ + misc &= ~(MISC_NCO_LOAD1 + MISC_NCO_LOAD0); + houston_WriteReg(HOUSTON_MISC, misc, 2); + + /*NCON.*/ + reg = ((unsigned long)g_specs.v_total * g_specs.h_total) / 2; + houston_WriteReg(HOUSTON_NCONH, reg >> 16, 2); + houston_WriteReg(HOUSTON_NCONL, reg & 0xffff, 2); + + /*NCOD.*/ + houston_WriteReg(HOUSTON_NCODL, tvsetup.houston_ncodl[k], 2); + houston_WriteReg(HOUSTON_NCODH, tvsetup.houston_ncodh[k], 2); + } + else + { + /*setup for M and N load (Nco_load=2).*/ + misc |= (MISC_NCO_LOAD1); + houston_WriteReg(HOUSTON_MISC, misc, 2); + + /*NCON.*/ + reg = (unsigned long)g_specs.v_total * g_specs.h_total; + houston_WriteReg(HOUSTON_NCONH, reg >> 16, 2); + houston_WriteReg(HOUSTON_NCONL, reg & 0xffff, 2); + + /*NCOD.*/ + houston_WriteReg(HOUSTON_NCODL, tvsetup.houston_ncodl[k], 2); + houston_WriteReg(HOUSTON_NCODH, tvsetup.houston_ncodh[k], 2); + + TRACE(( + "NCON = %lu (0x%08lx), NCOD = %lu (0x%08lx)\n", + reg, + reg, + ((unsigned long)tvsetup.houston_ncodh[k] << 16) + tvsetup.houston_ncodl[k], + ((unsigned long)tvsetup.houston_ncodh[k] << 16) + tvsetup.houston_ncodl[k])) + } + + /*latch M/N and NCON/NCOD in.*/ + cr |= CR_NCO_EN; + houston_WriteReg(HOUSTON_CR, cr, 2); + cr &= ~CR_NCO_EN; + houston_WriteReg(HOUSTON_CR, cr, 2); +} + + +/*==========================================================================*/ +/****/ +/*// Write sharpness settings to device*/ + +static void config_sharpness(int sharpness) +{ + unsigned int shp; + + /*map 0-1000 to 0-20.*/ + shp = (unsigned int)(0.5f + ((float)sharpness * 20.0f / 1000.0f)); + shp = range_limit(shp, 0, 20); + + houston_WriteReg(HOUSTON_SHP, shp, 2); +} + +static void conget_sharpness(int *p_sharpness) +{ + unsigned long shp; + + if (!p_sharpness) + return; + + houston_ReadReg(HOUSTON_SHP, &shp, 2); + + /*map 0-20 to 0-1000.*/ + *p_sharpness = (int)(0.5f + ((float)shp * 1000.0f / 20.0f)); +} + + +/*==========================================================================*/ +/****/ +/*// Write flicker settings to device*/ + +static void config_flicker(int flicker) +{ + unsigned int flk; + + /*map 0-1000 to 0-16.*/ + flk = (unsigned int)(0.5f + ((float)flicker * 16.0f / 1000.0f)); + flk = range_limit(flk,0,16); + + houston_WriteReg(HOUSTON_FLK, flk, 2); +} + +static void conget_flicker(int *p_flicker) +{ + unsigned long flk; + + if (!p_flicker) + return; + + houston_ReadReg(HOUSTON_FLK, &flk, 2); + + /*map 0-16 to 0-1000.*/ + *p_flicker = (int)(0.5f + ((float)flk * 1000.0f / 16.0f)); +} + + +/*==========================================================================*/ +/****/ +/*// Write color settings to device*/ + +static void config_color(int color) +{ + unsigned long clr; + + /*map 0-100 to 0-255.*/ + /*montreal production test needs 169 to be mappable, so*/ + /*use .8 rounding factor, 169=(int)(66.*2.55+.8).*/ + clr = (unsigned long)(0.8f + ((float)color * 255.0f / 100.0f)); + clr = range_limit(clr,0,255); + + houston_WriteReg(ENC_CR_GAIN, clr, 1); + houston_WriteReg(ENC_CB_GAIN, clr, 1); +} + +static void conget_color(int *p_color) +{ + unsigned long cr_gain; + + if (!p_color) + return; + + /*just get CR GAIN, CB GAIN should match.*/ + houston_ReadReg(ENC_CR_GAIN, &cr_gain, 1); + + /*map 0-255 to 0-100.*/ + *p_color = (int)(0.5f + ((float)cr_gain * 100.0f / 255.0f)); +} + + +/*==========================================================================*/ +/****/ +/*// Write brightness and contrast settings to device*/ + +#define NTSC_BLANK_LEVEL 240 + +static const int min_black_level = NTSC_BLANK_LEVEL+1; +static const int max_white_level = 1023; + +static void config_brightness_contrast(unsigned long tv_std, unsigned int trigger_bits, + int brightness, int contrast) +{ + int brightness_off; + float contrast_mult; + int black, white; + unsigned short w; + int k = map_tvstd_to_index(tv_std); + + /*0-100 maps to +/-220.*/ + brightness_off = (int)(0.5f + ((float)brightness * 440.0f / 100.0f)) - 220; + + /*0-100 maps to .75-1.25.*/ + contrast_mult = ((float) contrast * 0.5f / 100.0f) + 0.75f; + + black = tvsetup.black_level[k]; + if (trigger_bits != 0) + black -= tvsetup.hamp_offset[k]; + + white = tvsetup.white_level[k]; + if (trigger_bits != 0) + white -= tvsetup.hamp_offset[k]; + + black = (int) ((float) (black + brightness_off) * contrast_mult); + white = (int) ((float) (white + brightness_off) * contrast_mult); + if (black < min_black_level) + black = min_black_level; + if (white > max_white_level) + white = max_white_level; + + w = w10bit2z((unsigned short) black); + houston_WriteReg(ENC_BLACK_LEVEL, w & 0x00ff, 1); + houston_WriteReg(ENC_BLACK_LEVEL+1, w >> 8, 1); + w = w10bit2z((unsigned short) white); + houston_WriteReg(ENC_WHITE_LEVEL, w & 0x00ff, 1); + houston_WriteReg(ENC_WHITE_LEVEL+1, w >> 8, 1); +} + +static void conget_brightness_contrast(unsigned long tv_std, unsigned int trigger_bits, + int *p_brightness, int *p_contrast) +{ + int brightness_off; + float contrast_mult; + unsigned short black, white; + unsigned long zh,zl; + int k; + + if (!p_brightness || !p_contrast) + return; + + k = map_tvstd_to_index(tv_std); + + houston_ReadReg(ENC_BLACK_LEVEL, &zl, 1); + houston_ReadReg(ENC_BLACK_LEVEL+1, &zh, 1); + black = z2w10bit((unsigned short)(zl + (zh << 8))); + if (trigger_bits != 0) + black += tvsetup.hamp_offset[k]; + houston_ReadReg(ENC_WHITE_LEVEL, &zl, 1); + houston_ReadReg(ENC_WHITE_LEVEL+1, &zh, 1); + white = z2w10bit((unsigned short)(zl + (zh << 8))); + if (trigger_bits != 0) + white += tvsetup.hamp_offset[k]; + + /*this reverse computation does not account for clipping, but should*/ + /*provide somewhat reasonable numbers*/ + contrast_mult = ((float)white - (float)black) / ((float)tvsetup.white_level[k] - (float)tvsetup.black_level[k]); + brightness_off = (int)(((float)black / contrast_mult) - tvsetup.black_level[k]); + + /*+/-220 maps to 0-100.*/ + *p_brightness = range_limit((int)(0.5f + ((float)(brightness_off + 220) * 100.0f / 440.0f)),0,100); + + /*.75-1.25 maps to 0-100.*/ + *p_contrast = range_limit((int)(0.5f + ((float)(contrast_mult - 0.75f) * 100.0f / 0.5f)),0,100); +} + + +/*==========================================================================*/ +/****/ +/*configure luma/chroma filters.*/ + +static void config_yc_filter(unsigned long tv_std,int luma_filter, int chroma_filter) +{ + unsigned long reg, reg07, reg34; + + if (houston_Rev() < HOUSTON_REV_B) + return; + + /*luma filter.*/ + if (luma_filter) + reg = tvsetup.notch_filter[map_tvstd_to_index(tv_std)]; + else + reg = 0; + houston_WriteReg(ENC_NOTCH_FILTER, reg, 1); + + /*chroma filter.*/ + houston_ReadReg(ENC_REG07, ®07, 1); + houston_ReadReg(ENC_REG34, ®34, 1); + if (chroma_filter) + { + reg07 &= ~0x08; + reg34 &= ~0x20; + } + else + { + reg07 |= 0x08; + reg34 |= 0x20; + } + houston_WriteReg(ENC_REG07, reg07, 1); + houston_WriteReg(ENC_REG34, reg34, 1); +} + +static void conget_yc_filter(int *p_luma_filter, int *p_chroma_filter) +{ + unsigned long reg, reg07, reg34; + + if (!p_luma_filter || !p_chroma_filter) + return; + + if (houston_Rev() < HOUSTON_REV_B) + { + *p_luma_filter = 0; + *p_chroma_filter = 0; + return; + } + + /*luma filter.*/ + houston_ReadReg(ENC_NOTCH_FILTER, ®, 1); + *p_luma_filter = (reg ? 1 : 0); + + /*chroma filter.*/ + houston_ReadReg(ENC_REG07, ®07, 1); + houston_ReadReg(ENC_REG34, ®34, 1); + *p_chroma_filter = !((0x08 & reg07) || (0x20 & reg34)); +} + + +/*==========================================================================*/ +/****/ +/*// Macrovision*/ + +static void config_macrovision(unsigned long tv_std, unsigned int trigger_bits) +{ +/****/ +/*Constants to index into mvsetup columns.*/ +/****/ +#define nNTSC_APS00 0 /*ntsc mv off.*/ +#define nNTSC_APS01 1 /*ntsc AGC only.*/ +#define nNTSC_APS10 2 /*ntsc AGC + 2-line CS.*/ +#define nNTSC_APS11 3 /*ntsc AGC + 4-line CS.*/ +#define nPAL_APS00 4 /*pal mv off.*/ +#define nPAL_APSXX 5 /*pal mv on.*/ +#define nMVModes 6 + +/****/ +/*Macrovision setup table.*/ +/****/ +static const struct mvparms + { + unsigned short n0[nMVModes]; + unsigned short n1[nMVModes]; + unsigned short n2[nMVModes]; + unsigned short n3[nMVModes]; + unsigned short n4[nMVModes]; + unsigned short n5[nMVModes]; + unsigned short n6[nMVModes]; + unsigned short n7[nMVModes]; + unsigned short n8[nMVModes]; + unsigned short n9[nMVModes]; + unsigned short n10[nMVModes]; + unsigned short n11[nMVModes]; + unsigned short n12[nMVModes]; + unsigned short n13[nMVModes]; + unsigned short n14[nMVModes]; + unsigned short n15[nMVModes]; + unsigned short n16[nMVModes]; + unsigned short n17[nMVModes]; + unsigned short n18[nMVModes]; + unsigned short n19[nMVModes]; + unsigned short n20[nMVModes]; + unsigned short n21[nMVModes]; + unsigned short n22[nMVModes]; + unsigned short agc_pulse_level[nMVModes]; + unsigned short bp_pulse_level[nMVModes]; + } + +mvsetup = + + { /*// ntsc ntsc ntsc ntsc pal pal*/ + /*// MV AGC AGC + AGC + MV MV*/ + /*// off. only 2-line 4-line off. on.*/ + /*// CS. CS.*/ + { 0x00, 0x36, 0x3e, 0x3e, 0x00, 0x3e }, /*n0*/ + { 0x1d, 0x1d, 0x1d, 0x17, 0x1a, 0x1a }, /*n1*/ + { 0x11, 0x11, 0x11, 0x15, 0x22, 0x22 }, /*n2*/ + { 0x25, 0x25, 0x25, 0x21, 0x2a, 0x2a }, /*n3*/ + { 0x11, 0x11, 0x11, 0x15, 0x22, 0x22 }, /*n4*/ + { 0x01, 0x01, 0x01, 0x05, 0x05, 0x05 }, /*n5*/ + { 0x07, 0x07, 0x07, 0x05, 0x02, 0x02 }, /*n6*/ + { 0x00, 0x00, 0x00, 0x02, 0x00, 0x00 }, /*n7*/ + { 0x1b, 0x1b, 0x1b, 0x1b, 0x1c, 0x1c }, /*n8*/ + { 0x1b, 0x1b, 0x1b, 0x1b, 0x3d, 0x3d }, /*n9*/ + { 0x24, 0x24, 0x24, 0x24, 0x14, 0x14 }, /*n10*/ + { 0x780f, 0x780f, 0x780f, 0x780f, 0x7e07, 0x7e07 }, /*n11*/ + { 0x0000, 0x0000, 0x0000, 0x0000, 0x5402, 0x5402 }, /*n12*/ + { 0x0f, 0x0f, 0x0f, 0x0f, 0xfe, 0xfe }, /*n13*/ + { 0x0f, 0x0f, 0x0f, 0x0f, 0x7e, 0x7e }, /*n14*/ + { 0x60, 0x60, 0x60, 0x60, 0x60, 0x60 }, /*n15*/ + { 0x01, 0x01, 0x01, 0x01, 0x00, 0x00 }, /*n16*/ + { 0x0a, 0x0a, 0x0a, 0x0a, 0x08, 0x08 }, /*n17*/ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /*n18*/ + { 0x05, 0x05, 0x05, 0x05, 0x04, 0x04 }, /*n19*/ + { 0x04, 0x04, 0x04, 0x04, 0x07, 0x07 }, /*n20*/ + { 0x03ff, 0x03ff, 0x03ff, 0x03ff, 0x0155, 0x0155 }, /*n21*/ + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, /*n22*/ + { 0xa3, 0xa3, 0xa3, 0xa3, 0xa3, 0xa3 }, /*agc_pulse_level*/ + { 0xc8, 0xc8, 0xc8, 0xc8, 0xc8, 0xc8 }, /*bp_pulse_level*/ + }; + + int nMode; + unsigned long misc; + unsigned short n0; + + trigger_bits &= 0x3; + + /*Determine the OEM Macrovision Program Mode and Register 0 Data.*/ + if (IS_NTSC(tv_std)) + { + /*NTSC TV Standard.*/ + if (trigger_bits == 0) + { + /*turn Macrovision OFF.*/ + nMode = nNTSC_APS00; + } + else if (trigger_bits == 1) + { + /*AGC Only.*/ + nMode = nNTSC_APS01; + } + else if (trigger_bits == 2) + { + /*AGC + 2-line CS.*/ + nMode = nNTSC_APS10; + } + else + { + /*AGC + 4-line CS.*/ + nMode = nNTSC_APS11; + } + } + else + { + /*PAL TV Standard.*/ + if (trigger_bits == 0) + { + /*turn Macrovision OFF.*/ + nMode = nPAL_APS00; + } + else + { + /*APS 01, 10, or 11.*/ + nMode = nPAL_APSXX; + } + } + + /*Retrieve the Macrovision Program Mode Data*/ + if (tv_std != GFX_TV_STANDARD_PAL_M) + n0 = mvsetup.n0[nMode]; + else + { + /*PAL-M sets up like NTSC except for n0.*/ + if ((trigger_bits & 0x03) == 0) + n0 = mvsetup.n0[nPAL_APS00]; + else + n0 = mvsetup.n0[nPAL_APSXX]; + } + + /*download settings now.*/ + houston_WriteReg(MV_N0, n0, 1); + houston_WriteReg(MV_N1, mvsetup.n1[nMode], 1); + houston_WriteReg(MV_N2, mvsetup.n2[nMode], 1); + houston_WriteReg(MV_N3, mvsetup.n3[nMode], 1); + houston_WriteReg(MV_N4, mvsetup.n4[nMode], 1); + houston_WriteReg(MV_N5, mvsetup.n5[nMode], 1); + houston_WriteReg(MV_N6, mvsetup.n6[nMode], 1); + houston_WriteReg(MV_N7, mvsetup.n7[nMode], 1); + houston_WriteReg(MV_N8, mvsetup.n8[nMode], 1); + houston_WriteReg(MV_N9, mvsetup.n9[nMode], 1); + houston_WriteReg(MV_N10, mvsetup.n10[nMode], 1); + houston_WriteReg(MV_N11, mvsetup.n11[nMode] & 0xff, 1); + houston_WriteReg(MV_N11+1, mvsetup.n11[nMode] >> 8, 1); + houston_WriteReg(MV_N12, mvsetup.n12[nMode] & 0xff, 1); + houston_WriteReg(MV_N12+1, mvsetup.n12[nMode] >> 8, 1); + houston_WriteReg(MV_N13, mvsetup.n13[nMode], 1); + houston_WriteReg(MV_N14, mvsetup.n14[nMode], 1); + houston_WriteReg(MV_N15, mvsetup.n15[nMode], 1); + houston_WriteReg(MV_N16, mvsetup.n16[nMode], 1); + houston_WriteReg(MV_N17, mvsetup.n17[nMode], 1); + houston_WriteReg(MV_N18, mvsetup.n18[nMode], 1); + houston_WriteReg(MV_N19, mvsetup.n19[nMode], 1); + houston_WriteReg(MV_N20, mvsetup.n20[nMode], 1); + houston_WriteReg(MV_N21, mvsetup.n21[nMode] & 0xff, 1); + houston_WriteReg(MV_N21+1, mvsetup.n21[nMode] >> 8, 1); + houston_WriteReg(MV_N22, mvsetup.n22[nMode], 1); + houston_WriteReg(MV_AGC_PULSE_LEVEL, mvsetup.agc_pulse_level[nMode], 1); + houston_WriteReg(MV_BP_PULSE_LEVEL, mvsetup.bp_pulse_level[nMode], 1); + + houston_ReadReg(HOUSTON_MISC, &misc, 2); + if (trigger_bits == 0) + misc &= ~MISC_MV_SOFT_EN; + else + misc |= MISC_MV_SOFT_EN; + houston_WriteReg(HOUSTON_MISC, misc, 2); +} + +static void conget_macrovision(unsigned long tv_std, unsigned int *p_cp_trigger_bits) +{ + unsigned long n0,n1; + + if (!p_cp_trigger_bits) + return; + + houston_ReadReg(MV_N0,&n0,1); + houston_ReadReg(MV_N1,&n1,1); + + *p_cp_trigger_bits = 0; + + if (IS_NTSC(tv_std)) + { + switch(n0) + { + case 0: + *p_cp_trigger_bits = 0; + break; + + case 0x36: + *p_cp_trigger_bits = 1; + break; + + case 0x3E: + { + if (0x1D == n1) + *p_cp_trigger_bits = 2; + else + *p_cp_trigger_bits = 3; + } + break; + } + } + else if (IS_PAL(tv_std)) + { + if (0 == n0) + *p_cp_trigger_bits = 0; + else + { + /*don't know here what the non-zero trigger bits were*/ + *p_cp_trigger_bits = 1; + } + } +} + +/*// PLAL_MediaGX.cpp*/ +/*//==========================================================================*/ +/****/ +/*These functions provides implementation of platform-specific functions*/ +/*MediaGX platform.*/ +/****/ +/*//==========================================================================*/ + +/*MediaGX control registers.*/ +#define CCR3 0xC3 +#define GCR 0xb8 + +/*Media GX registers*/ +/* +#define DC_UNLOCK 0x8300 +#define DC_GENERAL_CFG 0x8304 +#define DC_TIMING_CFG 0x8308 +#define DC_OUTPUT_CFG 0x830c +#define DC_H_TIMING_1 0X8330 +#define DC_H_TIMING_2 0X8334 +#define DC_H_TIMING_3 0X8338 +#define DC_FP_H_TIMING 0X833c +#define DC_V_TIMING_1 0X8340 +#define DC_V_TIMING_2 0X8344 +#define DC_V_TIMING_3 0X8348 +#define DC_FP_V_TIMING 0X834c +*/ +/*Media GX general config register.*/ +#define GX_DCLK_MUL 0x00c0 +#define GX_DCLKx1 0x0040 +#define GX_DCLKx2 0x0080 +#define GX_DCLKx4 0x00c0 + +/*Media GX timing config register.*/ +#define GX_TGEN 0x0020 + +/*Cx5530 register offsets (from GX_BASE).*/ +#define CX_DISPLAY_CONFIG 0x10004 +#define CX_DOT_CLK 0x10024 +#define CX_TV_CONFIG 0x10028 + +/*Cx5530 display configuration register.*/ +#define CX_FPVSYNC_POL 0x0800 +#define CX_FPHSYNC_POL 0x0400 +#define CX_FPDATA_ENB 0x0080 +#define CX_FPPOWER_ENB 0x0040 +#define CX_CRTVSYNC_POL 0x0200 +#define CX_CRTHSYNC_POL 0x0100 + +/*Cx5530 dot clock configuration register.*/ +#define CX_TVCLK_SELECT 0x0400 + +/*Cx5530 tv configuration register*/ +#define CX_INVERT_FPCLK (1 << 6) + +/*//==========================================================================*/ +/****/ +/*// FS450 I2C Address*/ +/****/ +/*// There are two possible 7-bit addresses, 0x4A and 0x6A.*/ +/*// The address if selectable via pins on the FS450.*/ +/*// There are also two possible 10-bit addresses, 0x224 and 0x276, but this*/ +/*// source is not designed to use them.*/ +/****/ + +#define FS450_I2C_ADDRESS (0x4A) + +static unsigned char PLAL_FS450_i2c_address(void) +{ + return FS450_I2C_ADDRESS; +} + + +/*//==========================================================================*/ +/****/ +/*// FS450 UIM mode*/ +/****/ +/*// This mode is programmed in the FS450 command register when enabling TV*/ +/*// out.*/ + +static int PLAL_FS450_UIM_mode(void) +{ + return 3; +} + +/*//==========================================================================*/ +/****/ +/*// Read and Write MediaGX registers*/ + +static unsigned long ReadGx(unsigned long inRegAddr) +{ + unsigned long data; + + DMAL_ReadUInt32(inRegAddr, &data); + + return data; +} + +static void WriteGx(unsigned long inRegAddr, unsigned long inData) +{ + int is_timing_register; + unsigned long reg_timing_cfg; + + /*because the unlock register for the MediaGx video registers may not*/ + /*persist, we will write the unlock code before every write.*/ + DMAL_WriteUInt32(DC_UNLOCK, 0x4758); + + /*see if register is a timing register*/ + is_timing_register = + (DC_H_TIMING_1 == inRegAddr) || + (DC_H_TIMING_2 == inRegAddr) || + (DC_H_TIMING_3 == inRegAddr) || + (DC_FP_H_TIMING == inRegAddr) || + (DC_V_TIMING_1 == inRegAddr) || + (DC_V_TIMING_2 == inRegAddr) || + (DC_V_TIMING_3 == inRegAddr) || + (DC_FP_V_TIMING == inRegAddr); + + /*if the register is a timing register, clear the TGEN bit to allow modification*/ + if (is_timing_register) + { + DMAL_ReadUInt32(DC_TIMING_CFG, ®_timing_cfg); + DMAL_WriteUInt32(DC_TIMING_CFG, reg_timing_cfg & ~GX_TGEN); + } + + /*write the requested register*/ + DMAL_WriteUInt32(inRegAddr, inData); + + /*reset the TGEN bit to previous state*/ + if (is_timing_register) + { + DMAL_WriteUInt32(DC_TIMING_CFG, reg_timing_cfg); + } +} + +#ifdef FS450_DIRECTREG + +/*//==========================================================================*/ +/****/ +/*// Platform-specific processing for a Read or Write Register calls.*/ +/*// The functions should return true if the specified register belongs to*/ +/*// this platform.*/ + +static int PLAL_ReadRegister(S_REG_INFO *p_reg) +{ + if (!p_reg) + return 0; + + if (SOURCE_GCC == p_reg->source) + { + p_reg->value = ReadGx(p_reg->offset); + + return 1; + } + + return 0; +} + +static int PLAL_WriteRegister(const S_REG_INFO *p_reg) +{ + if (!p_reg) + return 0; + + if (SOURCE_GCC == p_reg->source) + { + WriteGx(p_reg->offset, p_reg->value); + + return 1; + } + + return 0; +} + +#endif + + +/*//==========================================================================*/ +/****/ +/*// Determine if TV is on*/ + +static int PLAL_IsTVOn(void) +{ + unsigned long reg; + + /*check Cx5530 dot clock*/ + reg = ReadGx(CX_DOT_CLK); + return (reg & CX_TVCLK_SELECT) ? 1 : 0; +} + + +/*//==========================================================================*/ +/****/ +/*// Platform-specific actions to reset to VGA mode*/ + +static int PLAL_EnableVga(void) +{ + unsigned long reg; + + /*2 x dclk*/ + reg = ReadGx(DC_GENERAL_CFG); + reg &= ~GX_DCLK_MUL; + reg |= GX_DCLKx2; + WriteGx(DC_GENERAL_CFG, reg); + + /*select pll dot clock.*/ + reg = ReadGx(CX_DOT_CLK); + reg &= ~CX_TVCLK_SELECT; + WriteGx(CX_DOT_CLK, reg); + + /*timing config, reset everything on dclk.*/ + reg = ReadGx(DC_TIMING_CFG); + reg &= ~GX_TGEN; + WriteGx(DC_TIMING_CFG, reg); + reg |= GX_TGEN; + WriteGx(DC_TIMING_CFG, reg); + + /*un-invert FP clock*/ + reg = ReadGx(CX_TV_CONFIG); + reg &= ~CX_INVERT_FPCLK; + WriteGx(CX_TV_CONFIG,reg); + + return 0; +} + + +/*//==========================================================================*/ +/****/ +/*// Platform-specific actions to enter TVout mode*/ + +static int PLAL_PrepForTVout(void) +{ + unsigned int reg; + + /*Cx5530 tv config.*/ + reg = 0; + WriteGx(CX_TV_CONFIG, reg); + + /*invert FP clock*/ + reg = (int)ReadGx(CX_TV_CONFIG); + reg |= CX_INVERT_FPCLK; + WriteGx(CX_TV_CONFIG,reg); + + return 0; +} + +static int PLAL_SetTVTimingRegisters(const S_TIMING_SPECS *p_specs) +{ + unsigned long reg; + + /*timing config, reset everything on dclk.*/ + reg = ReadGx(DC_TIMING_CFG); + reg &= ~GX_TGEN; + WriteGx(DC_TIMING_CFG, reg); + + /*htotal and hactive.*/ + reg = ((p_specs->h_total-1) << 16) | (p_specs->vga_width-1); + WriteGx(DC_H_TIMING_1, reg); + + /*hblank.*/ + reg = ((p_specs->h_total-1) << 16) | (p_specs->vga_width-1); + WriteGx(DC_H_TIMING_2, reg); + + /*hsync.*/ + reg = ((p_specs->h_sync+63) << 16) | p_specs->h_sync; + WriteGx(DC_H_TIMING_3, reg); + + /*fp hsync.*/ + WriteGx(DC_FP_H_TIMING, reg); + + /*vtotal and vactive.*/ + reg = ((p_specs->v_total-1) << 16) | (p_specs->vga_lines-1); + WriteGx(DC_V_TIMING_1, reg); + + /*vblank.*/ + reg = ((p_specs->v_total-1) << 16) | (p_specs->vga_lines-1); + WriteGx(DC_V_TIMING_2, reg); + + /*vsync.*/ + reg = ((p_specs->v_sync) << 16) | (p_specs->v_sync-1); + WriteGx(DC_V_TIMING_3, reg); + + /*fp vsync.*/ + reg = ((p_specs->v_sync-1) << 16) | (p_specs->v_sync-2); + WriteGx(DC_FP_V_TIMING, reg); + + /*timing config, reenable all dclk stuff.*/ + reg = ReadGx(DC_TIMING_CFG); + reg |= GX_TGEN; + WriteGx(DC_TIMING_CFG, reg); + + return 0; +} + +static int PLAL_FinalEnableTVout(unsigned long vga_mode) +{ + unsigned int reg; + + /*Cx5530 select tv dot clock.*/ + reg = (int)ReadGx(CX_DOT_CLK); + reg |= CX_TVCLK_SELECT; + WriteGx(CX_DOT_CLK, reg); + + /*2 x dclk (actually 1x)*/ + reg = (int)ReadGx(DC_GENERAL_CFG); + reg &= ~GX_DCLK_MUL; + WriteGx(DC_GENERAL_CFG, reg); + + + reg |= GX_DCLKx2; + WriteGx(DC_GENERAL_CFG, reg); + + /*Cx5530 display configuration register.*/ + reg = (int)ReadGx(CX_DISPLAY_CONFIG); + reg |= (CX_FPVSYNC_POL | CX_FPHSYNC_POL | CX_FPDATA_ENB | CX_FPPOWER_ENB); + WriteGx(CX_DISPLAY_CONFIG, reg); + +/*disable, shouldn't be necessary*/ +#if 0 + /*kick MediaGX clock multiplier to clean up clock*/ + reg = ReadGx(DC_GENERAL_CFG); + reg &= ~GX_DCLK_MUL; + WriteGx(DC_GENERAL_CFG, reg); + reg |= GX_DCLKx2; + WriteGx(DC_GENERAL_CFG, reg); +#endif + + return 0; +} + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/tv_fs450.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/tv_fs450.h 2005-12-14 11:29:16.000000000 -0700 @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file defines the common FS450 API. + * */ + + + +#ifndef __FS450_H__ +#define __FS450_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* ==========================================================================*/ +/* Init and cleanup functions*/ + +int FS450_init(void); +void FS450_cleanup(void); + /* call FS450_init at startup to probe for and initialize FS450.*/ + /* returns 0 if successful.*/ + +/* ==========================================================================*/ +/* TV output on or off*/ + +int FS450_get_tv_enable(unsigned int *p_on); +int FS450_set_tv_enable(unsigned int on); + /* on is 1 for TV on, 0 for off*/ + + +/* ==========================================================================*/ +/* TV standard*/ + +int FS450_get_tv_standard(unsigned long *p_standard); +int FS450_get_available_tv_standards(unsigned long *p_standards); +int FS450_set_tv_standard(unsigned long standard); + /* standard is one of the FS450_TV_STANDARD constants*/ + /* standards is a bitmask of zero or more FS450_TV_STANDARD constants*/ + +/* FS450 TV Standard flags*/ +#define FS450_TV_STANDARD_NTSC_M 0x0001 +#define FS450_TV_STANDARD_NTSC_M_J 0x0002 +#define FS450_TV_STANDARD_PAL_B 0x0004 +#define FS450_TV_STANDARD_PAL_D 0x0008 +#define FS450_TV_STANDARD_PAL_H 0x0010 +#define FS450_TV_STANDARD_PAL_I 0x0020 +#define FS450_TV_STANDARD_PAL_M 0x0040 +#define FS450_TV_STANDARD_PAL_N 0x0080 +#define FS450_TV_STANDARD_PAL_G 0x0100 + + +/* ==========================================================================*/ +/* VGA mode assumed by FS450*/ + +int FS450_get_vga_mode(unsigned long *p_vga_mode); +int FS450_get_available_vga_modes(unsigned long *p_vga_modes); +int FS450_set_vga_mode(unsigned long vga_mode); + /* vga_mode is one of the FS450_VGA_MODE constants*/ + /* vga_modes is a bitmask of zero or more FS450_VGA_MODE constants*/ + +/* FS450 VGA Mode flags*/ +#define FS450_VGA_MODE_UNKNOWN 0 +#define FS450_VGA_MODE_640X480 0x0001 +#define FS450_VGA_MODE_720X487 0x0002 +#define FS450_VGA_MODE_720X576 0x0004 +#define FS450_VGA_MODE_800X600 0x0008 +#define FS450_VGA_MODE_1024X768 0x0010 + + +/* ==========================================================================*/ +/* TVout mode*/ + +int FS450_get_tvout_mode(unsigned long *p_tvout_mode); +int FS450_set_tvout_mode(unsigned long tvout_mode); + /* tvout_mode is a bitmask of FS450_TVOUT_MODE constants*/ + +/* FS450 TVout mode flags*/ +#define FS450_TVOUT_MODE_CVBS 0x0001 +#define FS450_TVOUT_MODE_YC 0x0002 +#define FS450_TVOUT_MODE_RGB 0x0004 +#define FS450_TVOUT_MODE_CVBS_YC (FS450_TVOUT_MODE_CVBS | FS450_TVOUT_MODE_YC) + + +/* ==========================================================================*/ +/* Flicker control*/ + +int FS450_get_sharpness(int *p_sharpness); +int FS450_set_sharpness(int sharpness); + /* sharpness is a percentage in tenths of a percent, 0 to 1000*/ + +int FS450_get_flicker_filter(int *p_flicker); +int FS450_set_flicker_filter(int flicker); + /* flicker_filter is a percentage in tenths of a percent, 0 to 1000*/ + + +/* ==========================================================================*/ +/* Size and Position*/ + +int FS450_get_overscan(int *p_x, int *p_y); +int FS450_set_overscan(int x, int y); +int FS450_get_position(int *p_x, int *p_y); +int FS450_set_position(int x, int y); + /* x and y are horizontal and vertical adjustments, -1000 to +1000*/ + + +/* ==========================================================================*/ +/* Visual adjustments*/ + +int FS450_get_color(int *p_color); +int FS450_set_color(int color); + /* color is a percentage, 0 to 100*/ + +int FS450_get_brightness(int *p_brightness); +int FS450_set_brightness(int brightness); + /* brightness is a percentage, 0 to 100*/ + +int FS450_get_contrast(int *p_contrast); +int FS450_set_contrast(int constrast); + /* contrast is a percentage, 0 to 100*/ + +/* ==========================================================================*/ +/* Luma and Chroma filter*/ + +int FS450_get_yc_filter(unsigned int *p_yc_filter); +int FS450_set_yc_filter(unsigned int yc_filter); + /* yc_filter is a bitmask of FS450_LUMA_FILTER and/or FS450_CHROMA_FILTER*/ + +/* FS450 Luma and Chroma Filters*/ +#define FS450_LUMA_FILTER 0x0001 +#define FS450_CHROMA_FILTER 0x0002 + + +/* ==========================================================================*/ +/* Macrovision*/ + +int FS450_get_aps_trigger_bits(unsigned int *p_trigger_bits); +int FS450_set_aps_trigger_bits(unsigned int trigger_bits); + /* trigger_bits is one of the FS450_APS_TRIGGER constants*/ + +/* APS Trigger Bits*/ +#define FS450_APS_TRIGGER_OFF 0 +#define FS450_APS_TRIGGER_AGC_ONLY 1 +#define FS450_APS_TRIGGER_AGC_2_LINE 2 +#define FS450_APS_TRIGGER_AGC_4_LINE 3 + + +/* ==========================================================================*/ +/* direct access to Houston and platform registers (debug builds only)*/ +/* The two functions FS450_ReadRegister and FS450_WriteRegister allow access*/ +/* to device registers. These functions are intended for debugging purposes*/ +/* only and should not be included in a shipping product.*/ + +#ifdef FS450_DIRECTREG + +#define SOURCE_HOUSTON 0 +#define SOURCE_GCC 1 + +typedef struct _S_REG_INFO +{ + int source; + unsigned int size; + unsigned long offset; + unsigned long value; +} S_REG_INFO; + +int FS450_ReadRegister(S_REG_INFO *p_reg); +int FS450_WriteRegister(S_REG_INFO *p_reg); + +#endif + + +/* ==========================================================================*/ +/* Error Codes*/ + +#define ERR_INVALID_PARAMETER 0x1000 +#define ERR_NOT_SUPPORTED 0x1001 +#define ERR_CANNOT_CHANGE_WHILE_TV_ON 0x1002 + +#define ERR_DRIVER_NOT_FOUND 0x1100 +#define ERR_DRIVER_ERROR 0x1101 +#define ERR_DEVICE_NOT_FOUND 0x1120 + +#define ERR_I2C_MISSING_DEVICE 0x1200 +#define ERR_I2C_WRITE_FAILED 0x1201 +#define ERR_I2C_READ_FAILED 0x1202 + + + +#ifdef __cplusplus +} +#endif + +#endif + --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/msr_rdcl.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/msr_rdcl.c 2005-12-14 11:30:18.000000000 -0700 @@ -0,0 +1,616 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains MSR access routines for Redcloud. + * */ + + +void redcloud_build_mbus_tree(void); /* private routine definition */ +int redcloud_init_msr_devices(MSR aDev[], unsigned int array_size); /* private routine definition */ +DEV_STATUS redcloud_find_msr_device (MSR *pDev); /* private routine definition */ + + +/* REDCLOUD MSR BITMASKS */ + +#define MBD_MSR_CAP 0x2000 +#define MSR_CAP_ID_MASK 0xFF000 +#define MSR_CAP_ID_SHIFT 12 +#define MSR_CAP_REV_MASK 0x0F +#define MBIU_CAP 0x86 +#define NUM_PORTS_MASK 0x00380000 +#define NUM_PORTS_SHIFT 19 +#define MBIU_WHOAMI 0x8B +#define WHOAMI_MASK 0x07 + +/* REDCLOUD and CS5535 MSR DEVICES */ + +MSR msrDev[] = { + { FOUND, RC_CC_MBIU, RC_MB0_MBIU0 }, + { FOUND, RC_CC_MBIU, RC_MB0_MBIU1 }, + { NOT_KNOWN, RC_CC_MCP , FAKE_ADDRESS }, + { NOT_KNOWN, RC_CC_MPCI, FAKE_ADDRESS }, + { NOT_KNOWN, RC_CC_MC , FAKE_ADDRESS }, + { NOT_KNOWN, RC_CC_GP , FAKE_ADDRESS }, + { NOT_KNOWN, RC_CC_VG , FAKE_ADDRESS }, + { NOT_KNOWN, RC_CC_DF , FAKE_ADDRESS }, + { NOT_KNOWN, RC_CC_FG , FAKE_ADDRESS }, + { FOUND, RC_CC_VA , RC_MB0_CPU }, + { FOUND, CP_CC_MBIU, CP_MB0_MBIU0 }, + { NOT_KNOWN, CP_CC_MPCI, FAKE_ADDRESS }, + { NOT_KNOWN, CP_CC_USB2, FAKE_ADDRESS }, + { NOT_KNOWN, CP_CC_ATAC, FAKE_ADDRESS }, + { NOT_KNOWN, CP_CC_MDD , FAKE_ADDRESS }, + { NOT_KNOWN, CP_CC_ACC , FAKE_ADDRESS }, + { NOT_KNOWN, CP_CC_USB1, FAKE_ADDRESS }, + { NOT_KNOWN, CP_CC_MCP , FAKE_ADDRESS }, +}; +#define NUM_DEVS sizeof(msrDev) / sizeof(struct msr) + +/* CAPISTRANO DEVICE INDEX LIMITS */ +/* These defines represent the start and stop indexes into the device array */ +/* for all Capistrano devices. These should be updated whenever a device is */ +/* added or removed to the Capistrano list. */ + +#define CP_INDEX_START CP_ID_MBIU +#define CP_INDEX_STOP CP_ID_MCP + +/* GLOBAL MBUS CACHE STRUCTURES */ +/* These structures contain a "cached" copy of the MBUS topology */ +/* for easy future lookup. */ + +MBUS_NODE MBIU0[8], MBIU1[8], MBIU2[8]; + +/* REGISTER MACROS */ + +#define GET_DEVICE_ID( CAPABILITIES_HIGH, CAPABILITIES_LOW ) \ + ((unsigned int)(( (CAPABILITIES_LOW) & MSR_CAP_ID_MASK ) >> MSR_CAP_ID_SHIFT )) + +#define GET_NUM_PORTS( MBIU_CAP_HIGH, MBIU_CAP_LOW ) (((MBIU_CAP_HIGH) & NUM_PORTS_MASK ) >> NUM_PORTS_SHIFT) + +/*----------------------------------------------------------------------------- + * gfx_msr_init + * + * This routine initializes the base addresses of all known MBUS devices. + *----------------------------------------------------------------------------- + */ +#if GFX_MSR_DYNAMIC +int redcloud_msr_init(void) +#else +int gfx_msr_init(void) +#endif +{ + Q_WORD msrValue; + int return_value = 1; + + /* CHECK FOR VALID MBUS CONFIGURATION */ + /* The CPU and the two MBIUs are assumed to be at known static addresses, so */ + /* we will check the device IDs at these addresses as proof of a valid mbus */ + /* configuration. */ + + MSR_READ (MBD_MSR_CAP, RC_MB0_CPU, &(msrValue.high), &(msrValue.low)); + if (GET_DEVICE_ID (msrValue.high, msrValue.low) != RC_CC_VA) + return_value = 0; + + MSR_READ (MBD_MSR_CAP, RC_MB0_MBIU0, &(msrValue.high), &(msrValue.low)); + if (GET_DEVICE_ID (msrValue.high, msrValue.low) != RC_CC_MBIU) + return_value = 0; + + MSR_READ (MBD_MSR_CAP, RC_MB0_MBIU1, &(msrValue.high), &(msrValue.low)); + if (GET_DEVICE_ID (msrValue.high, msrValue.low) != RC_CC_MBIU) + return_value = 0; + + /* ENUMERATE VALID BUS */ + /* If all static devices were identified, continue with the enumeration */ + + if (return_value) + { + /* OPTIMIZATION */ + /* Build a local copy of the MBUS topology. This allows us to */ + /* quickly search the entire MBUS for a given device ID without */ + /* repeated MSR accesses. */ + + redcloud_build_mbus_tree (); + + /* INITIALIZE MSR DEVICES */ + + return_value = redcloud_init_msr_devices (msrDev, NUM_DEVS); + + } + + return return_value; + +} + +/*-------------------------------------------------------------------------- + * void redcloud_build_mbus_tree() (PRIVATE ROUTINE - NOT PART OF DURANGO API) + * + * This routine walks through the MBUS and records the address value and + * device ID found at each node. If a node (aka port) is not populated, + * that node returns '0'. The deviceID for that node is set to '0' + * (NOT_POPULATED) to reflect this. If the node being queried points back to + * Vail or MBIU0, the deviceID for that node is set to 'REFLECTIVE'. Reflective + * nodes are nodes that forward the given MBUS address BACK to the initiator. + *----------------------------------------------------------------------------- + */ +void redcloud_build_mbus_tree(void) +{ + unsigned long mbiu_port_count, reflective; + unsigned long port; + Q_WORD msrValue; + + /* */ + /* ENUMERATE MBIU0 */ + /* */ + + /* COUNT MBIU PORTS */ + + MSR_READ (MBIU_CAP, RC_MB0_MBIU0, &(msrValue.high), &(msrValue.low)); + mbiu_port_count = GET_NUM_PORTS (msrValue.high, msrValue.low); + + /* FIND REFLECTIVE PORT */ + /* Query the MBIU for the port through which we are communicating. */ + /* We will avoid accesses to this port to avoid a self-reference. */ + + MSR_READ (MBIU_WHOAMI, RC_MB0_MBIU0, &(msrValue.high), &(msrValue.low)); + reflective = msrValue.low & WHOAMI_MASK; + + /* ENUMERATE ALL PORTS */ + /* For every possible port, set the MBIU.deviceId to something. */ + + for (port = 0; port < 8; port++) + { + /* FILL IN CLAIMED FIELD */ + /* All MBIU ports can only be assigned to one device from the */ + /* Durango table */ + + MBIU0[port].claimed = 0; + + /* MBIU0 PORT NUMBERS ARE IN ADDRESS BITS 31:29 */ + + MBIU0[port].address = port << 29; + + /* SPECIAL CASE FOR MBIU0 */ + /* MBIU0 port 0 is a special case, as it points back to MBIU0. MBIU0 */ + /* responds at address 0x40000xxx, which does not equal 0 << 29. */ + + if (port == 0) MBIU0[port].deviceId = RC_CC_MBIU; + else if (port == reflective) MBIU0[port].deviceId = REFLECTIVE; + else if (port > mbiu_port_count) MBIU0[port].deviceId = NOT_POPULATED; + else + { + MSR_READ (MBD_MSR_CAP, MBIU0[port].address, &(msrValue.high), &(msrValue.low)); + MBIU0[port].deviceId = GET_DEVICE_ID (msrValue.high, msrValue.low); + } + } + + /* */ + /* ENUMERATE MBIU1 */ + /* */ + + /* COUNT MBIU PORTS */ + + MSR_READ (MBIU_CAP, RC_MB0_MBIU1, &(msrValue.high), &(msrValue.low)); + mbiu_port_count = GET_NUM_PORTS (msrValue.high, msrValue.low); + + /* FIND REFLECTIVE PORT */ + /* Query the MBIU for the port through which we are communicating. */ + /* We will avoid accesses to this port to avoid a self-reference. */ + + MSR_READ (MBIU_WHOAMI, RC_MB0_MBIU1, &(msrValue.high), &(msrValue.low)); + reflective = msrValue.low & WHOAMI_MASK; + + /* ENUMERATE ALL PORTS */ + /* For every possible port, set the MBIU.deviceId to something. */ + + for (port = 0; port < 8; port++) + { + /* FILL IN CLAIMED FIELD */ + /* All MBIU ports can only be assigned to one device from the */ + /* Durango table */ + + MBIU1[port].claimed = 0; + + /* MBIU1 PORT NUMBERS ARE IN 28:26 AND 31:29 = 010B */ + + MBIU1[port].address = (0x02l << 29) + (port << 26); + + if (port == reflective) MBIU1[port].deviceId = REFLECTIVE; + else if (port > mbiu_port_count) MBIU1[port].deviceId = NOT_POPULATED; + else + { + MSR_READ (MBD_MSR_CAP, MBIU1[port].address, &(msrValue.high), &(msrValue.low)); + MBIU1[port].deviceId = GET_DEVICE_ID (msrValue.high, msrValue.low); + } + } + + /* */ + /* ENUMERATE MBIU2 (CS5535) */ + /* (if present) */ + + MSR_READ (MBD_MSR_CAP, CP_MB0_MBIU0, &(msrValue.high), &(msrValue.low)); + if (GET_DEVICE_ID (msrValue.high, msrValue.low) == CP_CC_MBIU) + { + /* COUNT MBIU PORTS */ + + MSR_READ (MBIU_CAP, CP_MB0_MBIU0, &(msrValue.high), &(msrValue.low)); + mbiu_port_count = GET_NUM_PORTS (msrValue.high, msrValue.low); + + /* FIND REFLECTIVE PORT */ + /* Query the MBIU for the port through which we are communicating. */ + /* We will avoid accesses to this port to avoid a self-reference. */ + + MSR_READ (MBIU_WHOAMI, CP_MB0_MBIU0, &(msrValue.high), &(msrValue.low)); + reflective = msrValue.low & WHOAMI_MASK; + + /* ENUMERATE ALL PORTS */ + /* For every possible port, set the MBIU.deviceId to something. */ + + for (port = 0; port < 8; port++) + { + /* FILL IN CLAIMED FIELD */ + /* All MBIU ports can only be assigned to one device from the */ + /* Durango table */ + + MBIU2[port].claimed = 0; + + /* MBIU2 PORT NUMBERS ARE IN 22:20 AND 31:23 = 010100010B */ + + MBIU2[port].address = (0x02l << 29) + (0x04l << 26) + (0x02l << 23) + (port << 20); + + if (port == reflective) MBIU2[port].deviceId = REFLECTIVE; + else if (port > mbiu_port_count) MBIU2[port].deviceId = NOT_POPULATED; + else + { + MSR_READ (MBD_MSR_CAP, MBIU2[port].address, &(msrValue.high), &(msrValue.low)); + MBIU2[port].deviceId = GET_DEVICE_ID (msrValue.high, msrValue.low); + } + } + } + else + { + /* NO 5535 */ + /* If the CS5535 is not installed, fill in the cached table */ + /* with the 'NOT_INSTALLED' flag. Also, fill in the device */ + /* status from NOT_KNOWN to REQ_NOT_INSTALLED. */ + + for (port = 0; port < 8; port++) + { + MBIU2[port].claimed = 0; + MBIU2[port].deviceId = NOT_INSTALLED; + MBIU2[port].address = (0x02l << 29) + (0x04l << 26) + (0x02l << 23) + (port << 20); + } + for (port = CP_INDEX_START; port <= CP_INDEX_STOP; port++) + { + msrDev[port].Present = REQ_NOT_INSTALLED; + } + } +} + +/*------------------------------------------------------------------ + * redcloud_init_msr_devices (PRIVATE ROUTINE - NOT PART OF DURANGO API) + + * Handles the details of finding each possible device on the MBUS. + * If a given device is not found, its structure is left uninitialized. + * If a given device is found, its structure is updated. + * + * This init routine only checks for devices in aDev[]. + * + * Passed: + * aDev - is a pointer to the array of MBUS devices. + * arraySize - number of elements in aDev. + * + * Returns: + * 1 - If, for every device, its address was found. + * 0 - If, for any device, an error was encountered. + *------------------------------------------------------------------ + */ +int redcloud_init_msr_devices(MSR aDev[], unsigned int array_size) +{ + unsigned int i, issues = 0; + + /* TRY TO FIND EACH ITEM IN THE ARRAY */ + + for (i = 0; i < array_size; i++) + { + /* IGNORE DEVICES THAT ARE ALREADY FOUND */ + /* The addresses for "found" devices are already known. */ + + if (aDev[i].Present == FOUND || aDev[i].Present == REQ_NOT_INSTALLED) + continue; + + /* TRY TO FIND THE DEVICE ON THE MBUS */ + + aDev[i].Present = redcloud_find_msr_device (&aDev[i]); + + /* INCREMENT ERROR COUNT IF DEVICE NOT FOUND */ + + if (aDev[i].Present != FOUND) + issues++; + } + + return (issues == 0); +} + +/*------------------------------------------------------------------ + * redcloud_find_msr_device (PRIVATE ROUTINE - NOT PART OF DURANGO API) + * + * Passed: + * pDev - is a pointer to one element in the array of MBUS devices + * + * Returns: + * FOUND - Device was found and pDev->Address has been updated. + * + * REQ_NOT_FOUND - Device was not found and pDev->Address has not + * been updated. + * + *------------------------------------------------------------------ +*/ +DEV_STATUS redcloud_find_msr_device (MSR *pDev) +{ + unsigned int i; + + /* SEARCH DURANGO'S CACHED MBUS TOPOLOGY */ + /* This gets a little tricky. As the only identifier we have for each */ + /* device is the device ID and we have multiple devices of the same type */ + /* MCP, MPCI, USB, etc. we need to make some assumptions based on table */ + /* order. These are as follows: */ + /* 1. All Redcloud nodes are searched first, as we assume that they */ + /* are first in the table. */ + /* 2. If two devices have the same device ID and are found on the same */ + /* device (GX2, CS5535, etc.) we assume that they are listed such */ + /* that the first device in the table with this device ID has a lower */ + /* port address. */ + /* 3. After a device ID has been matched, the port is marked as */ + /* 'claimed', such that future enumerations continue searching the */ + /* GeodeLink topology. */ + + /* SEARCH MBIU0 */ + + for (i = 0; i < 8; i++) + { + if (MBIU0[i].deviceId == pDev->Id && !(MBIU0[i].claimed)) + { + MBIU0[i].claimed = 1; + pDev->Address = MBIU0[i].address; + return FOUND; + } + } + + /* SEARCH MBIU1 */ + + for (i = 0; i < 8; i++) + { + if (MBIU1[i].deviceId == pDev->Id && !(MBIU1[i].claimed)) + { + MBIU1[i].claimed = 1; + pDev->Address = MBIU1[i].address; + return FOUND; + } + } + + /* SEARCH MBIU2 */ + + for (i = 0; i < 8; i++) + { + if (MBIU2[i].deviceId == pDev->Id && !(MBIU2[i].claimed)) + { + MBIU2[i].claimed = 1; + pDev->Address = MBIU2[i].address; + return FOUND; + } + } + + return REQ_NOT_FOUND; +} + +/*-------------------------------------------------------------------- + * gfx_id_msr_device + * + * This routine handles reading the capabilities MSR register (typically 0x2000) + * and checking if the 'id' field matchs pDev.Id. This routine is + * used by applications/drivers that need to extend the list of known + * MBUS devices beyond those known by Durango. + * + * Passed: + * pDev - Pointer to MSR structure containing the device's ID. + * address - device address. + * + * Returns: + * FOUND - The IDs do match. + * REQ_NOT_FOUND - There was not a match. + * + *-------------------------------------------------------------------- + */ +#if GFX_MSR_DYNAMIC +DEV_STATUS redcloud_id_msr_device (MSR *pDev, unsigned long address) +#else +DEV_STATUS gfx_id_msr_device (MSR *pDev, unsigned long address) +#endif +{ + Q_WORD msrValue; + + MSR_READ (MBD_MSR_CAP, address, &(msrValue.high), &(msrValue.low)); + + if (GET_DEVICE_ID (msrValue.high, msrValue.low) == pDev->Id) + return FOUND; + else + return REQ_NOT_FOUND; +} + +/*-------------------------------------------------------------------- + * gfx_get_msr_dev_address + * + * This function returns the 32-bit address of the requested device. + * The device must be a known MBUS device. (It must be in Durango's + * device table.) DEV_STATUS should be checked to verify that the address + * was updated. + * + * + * Passed: + * device - device index of the device in question. + * *address - ptr to location where address should be stored. + * + * Returns: + * DEV_STATUS of device in question. (NOT_KNOWN if device is out of range.) + * *address - updated if 'device' is within range + * + * Notes: + * This function should only be called after gfx_msr_init + * + *-------------------------------------------------------------------- + */ +#if GFX_MSR_DYNAMIC +DEV_STATUS redcloud_get_msr_dev_address (unsigned int device, unsigned long *address) +#else +DEV_STATUS gfx_get_msr_dev_address (unsigned int device, unsigned long *address) +#endif +{ + if (device < NUM_DEVS) + { + if (msrDev[device].Present == FOUND) + *address = msrDev[device].Address; + + return msrDev[device].Present; + } + return NOT_KNOWN; + +} + +/*-------------------------------------------------------------------- + * gfx_get_glink_id_at_address + * + * This function returns the 16-bit deviceId at the requested address. + * DEV_STATUS should be checked to make sure that device was updated. + * + * Passed: + * device - ptr to location where device ID should be stored. + * address - address of desired device ID. + * + * Returns: + * FOUND if address is a valid address, NOT_KNOWN if address cannot be found + * on the mbus. + * *device - updated with device Id info. + * + * Notes: + * This function should be called after gfx_msr_init + * + *-------------------------------------------------------------------- + */ +#if GFX_MSR_DYNAMIC +DEV_STATUS redcloud_get_glink_id_at_address(unsigned int *device, unsigned long address) +#else +DEV_STATUS gfx_get_glink_id_at_address(unsigned int *device, unsigned long address) +#endif +{ + int port; + + for (port = 0; port < 8; port++) + { + if (MBIU0[port].address == address) + { + *device = MBIU0[port].deviceId; + return FOUND; + } + else if (MBIU1[port].address == address) + { + *device = MBIU1[port].deviceId; + return FOUND; + } + else if (MBIU2[port].address == address) + { + *device = MBIU2[port].deviceId; + return FOUND; + } + } + + return NOT_KNOWN; + +} + +/*-------------------------------------------------------------------- + * gfx_msr_read + * + * Performs a 64-bit read from 'msrRegister' in device 'device'. 'device' is + * an index into Durango's table of known MBUS devices. + * + * Returns: + * FOUND - if no errors were detected and msrValue has been updated. + * NOT_KNOWN - an error was detected. msrValue is not updated. + * REQ_NOT_FOUND - 'msrAddress' for 'devID' is unknown. Caller + * should call msrInit() first. msrValue is not updated. + * Notes: + * This function should be called after gfx_msr_init + *-------------------------------------------------------------------- + */ +#if GFX_MSR_DYNAMIC +DEV_STATUS redcloud_msr_read (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue) +#else +DEV_STATUS gfx_msr_read (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue) +#endif +{ + if (device < NUM_DEVS) + { + if (msrDev[device].Present == FOUND) + MSR_READ (msrRegister, msrDev[device].Address, &(msrValue->high), &(msrValue->low)); + + return msrDev[device].Present; + } + return NOT_KNOWN; +} + +/*-------------------------------------------------------------------- + * gfx_msr_write + * + * Performs a 64-bit write to 'msrRegister' in device 'devID'. + * + * Returns: + * FOUND - if no errors were detected and msrValue has been updated. + * NOT_KNOWN - an error was detected. msrValue is not updated. + * REQ_NOT_FOUND - 'msrAddress' for 'devID' is unknown. Caller + * should call msrInit() first. msrValue is not updated. + * + * Notes: + * This function is valid to call after initMSR_API() + * + *-------------------------------------------------------------------- + */ +#if GFX_MSR_DYNAMIC +DEV_STATUS redcloud_msr_write (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue) +#else +DEV_STATUS gfx_msr_write (unsigned int device, unsigned int msrRegister, Q_WORD *msrValue) +#endif +{ + if (device < NUM_DEVS) + { + if (msrDev[device].Present == FOUND) + MSR_WRITE (msrRegister, msrDev[device].Address, &(msrValue->high), &(msrValue->low)); + + return msrDev[device].Present; + } + return NOT_KNOWN; +} --- xc/programs/Xserver/hw/xfree86/drivers/amd/gfx/vid_rdcl.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/gfx/vid_rdcl.c 2005-12-14 11:28:22.000000000 -0700 @@ -0,0 +1,2668 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * This file contains routines to control the Redcloud display filter video overlay hardware. + * */ + + +unsigned long gfx_gamma_ram_redcloud[] = +{ + 0x00000000, 0x00040003, 0x00050104, 0x00060205, 0x00070306, 0x00080407, + 0x00090508, 0x000A0609, 0x000B070A, 0x000C080B, 0x000D090C, 0x000E0A0D, + 0x000F0B0E, 0x00100C0F, 0x00110D10, 0x00110E11, 0x00120F12, 0x00141013, + 0x00151114, 0x00161215, 0x00171316, 0x00181417, 0x00191518, 0x001A1619, + 0x001B171A, 0x001C181B, 0x001D191C, 0x001D1A1D, 0x001E1B1E, 0x00201C1F, + 0x00201D20, 0x00221E21, 0x00231F22, 0x00242023, 0x00252124, 0x00262225, + 0x00262326, 0x00282427, 0x00292528, 0x00292629, 0x002B272A, 0x002C282B, + 0x002D292C, 0x002E2A2D, 0x002F2B2E, 0x00302C2F, 0x00312D30, 0x00322E31, + 0x00332F32, 0x00343033, 0x00353134, 0x00363235, 0x00373336, 0x00383437, + 0x00393538, 0x003A3639, 0x003B373A, 0x003C383B, 0x003D393C, 0x003E3A3D, + 0x003F3B3E, 0x00403C3F, 0x00413D40, 0x00423E41, 0x00433F42, 0x00444043, + 0x00444144, 0x00454245, 0x00474346, 0x00484447, 0x00494548, 0x004A4649, + 0x004B474A, 0x004C484B, 0x004D494C, 0x004E4A4D, 0x004F4B4E, 0x00504C4F, + 0x00514D50, 0x00524E51, 0x00534F52, 0x00545053, 0x00555154, 0x00565255, + 0x00575356, 0x00585457, 0x00595558, 0x005A5659, 0x005B575A, 0x005C585B, + 0x005D595C, 0x005E5A5D, 0x005F5B5E, 0x00605C5F, 0x00615D60, 0x00625E61, + 0x00635F62, 0x00646063, 0x00656164, 0x00666265, 0x00676366, 0x00686467, + 0x00696568, 0x006A6669, 0x006B676A, 0x006C686B, 0x006D696C, 0x006E6A6D, + 0x006F6B6E, 0x00706C6F, 0x00716D70, 0x00726E71, 0x00736F72, 0x00747073, + 0x00757174, 0x00767275, 0x00777376, 0x00787477, 0x00797578, 0x007A7679, + 0x007B777A, 0x007C787B, 0x007D797C, 0x007E7A7D, 0x007F7B7E, 0x00807C7F, + 0x00817D80, 0x00827E81, 0x00837F82, 0x00848083, 0x00858184, 0x00868285, + 0x00878386, 0x00888487, 0x00898588, 0x008A8689, 0x008B878A, 0x008C888B, + 0x008D898C, 0x008E8A8D, 0x008F8B8E, 0x00908C8F, 0x00918D90, 0x00928E91, + 0x00938F92, 0x00949093, 0x00959194, 0x00969295, 0x00979396, 0x00989497, + 0x00999598, 0x009A9699, 0x009B979A, 0x009C989B, 0x009D999C, 0x009E9A9D, + 0x009F9B9E, 0x00A09C9F, 0x00A19DA0, 0x00A29EA1, 0x00A39FA2, 0x00A4A0A3, + 0x00A5A1A4, 0x00A6A2A5, 0x00A7A3A6, 0x00A8A4A7, 0x00A9A5A8, 0x00AAA6A9, + 0x00ABA7AA, 0x00ACA8AB, 0x00ADA9AC, 0x00AEAAAD, 0x00AFABAE, 0x00B0ACAF, + 0x00B1ADB0, 0x00B2AEB1, 0x00B3AFB2, 0x00B4B0B3, 0x00B5B1B4, 0x00B6B2B5, + 0x00B7B3B6, 0x00B8B4B7, 0x00B9B5B8, 0x00BAB6B9, 0x00BBB7BA, 0x00BCB8BB, + 0x00BDB9BC, 0x00BEBABD, 0x00BFBBBE, 0x00C0BCBF, 0x00C1BDC0, 0x00C2BEC1, + 0x00C3BFC2, 0x00C4C0C3, 0x00C5C1C4, 0x00C6C2C5, 0x00C7C3C6, 0x00C8C4C7, + 0x00C9C5C8, 0x00CAC6C9, 0x00CBC7CA, 0x00CCC8CB, 0x00CDC9CC, 0x00CECACD, + 0x00CFCBCE, 0x00D0CCCF, 0x00D1CDD0, 0x00D2CED1, 0x00D3CFD2, 0x00D4D0D3, + 0x00D5D1D4, 0x00D6D2D5, 0x00D7D3D6, 0x00D8D4D7, 0x00D9D5D8, 0x00DAD6D9, + 0x00DBD7DA, 0x00DCD8DB, 0x00DDD9DC, 0x00DEDADD, 0x00DFDBDE, 0x00E0DCDF, + 0x00E1DDE0, 0x00E2DEE1, 0x00E3DFE2, 0x00E4E0E3, 0x00E5E1E4, 0x00E6E2E5, + 0x00E7E3E6, 0x00E8E4E7, 0x00E9E5E8, 0x00EAE6E9, 0x00EBE7EA, 0x00ECE8EB, + 0x00EDE9EC, 0x00EEEAED, 0x00EFEBEE, 0x00F0ECEF, 0x00F1EDF0, 0x00F2EEF1, + 0x00F3EFF2, 0x00F4F0F3, 0x00F5F1F4, 0x00F6F2F5, 0x00F7F3F6, 0x00F8F4F7, + 0x00F9F5F8, 0x00FAF6F9, 0x00FBF7FA, 0x00FCF8FB, 0x00FDF9FC, 0x00FEFAFD, + 0x00FFFBFE, 0x00FFFCFE, 0x00FFFDFE, 0x00FFFFFF +}; + +/* REDCLOUD PLL TABLE */ + +typedef struct RCDFPLL +{ + long frequency; /* 16.16 fixed point frequency */ + unsigned long post_div3; /* MCP Frequency dividers and multipliers */ + unsigned long pre_mul2; + unsigned long pre_div2; + unsigned long pll_value; /* MCP DotPLL Register Upper 32(0x0015) */ +} RCDFPLLENTRY; + +RCDFPLLENTRY RCDF_PLLtable[] = { + { 0x0018EC4D, 1, 0, 0, 0x0000099E }, /* 24.9230 */ + { 0x00192CCC, 0, 0, 0, 0x00000037 }, /* 25.1750 */ + { 0x001C526E, 1, 0, 0, 0x000009DA }, /* 28.3220 */ + { 0x001C8F5C, 1, 0, 0, 0x0000005E }, /* 28.5600 */ + { 0x001F8000, 1, 0, 0, 0x000002D2 }, /* 31.5000 */ + { 0x00240000, 1, 0, 0, 0x000007E2 }, /* 36.0000 */ + { 0x00258000, 1, 0, 0, 0x0000057A }, /* 37.5000 */ + { 0x0025E395, 1, 0, 0, 0x000007FA }, /* 37.8890 */ + { 0x00280000, 1, 0, 0, 0x0000030A }, /* 40.0000 */ + { 0x002B29BA, 0, 0, 0, 0x0000005F }, /* 43.1630 */ + { 0x002CE666, 0, 0, 0, 0x00000063 }, /* 44.9000 */ + { 0x002DB851, 1, 0, 0, 0x00000BC9 }, /* 45.7200 */ + { 0x00318000, 0, 0, 0, 0x0000054B }, /* 49.5000 */ + { 0x00320000, 0, 0, 0, 0x0000006F }, /* 50.0000 */ + { 0x00325999, 0, 1, 0, 0x00000037 }, /* 50.3500 */ + { 0x00360000, 1, 1, 0, 0x00000B0D }, /* 54.0000 */ + { 0x00384000, 0, 0, 0, 0x000007F7 }, /* 56.2500 */ + { 0x0038643F, 0, 0, 0, 0x000007F7 }, /* 56.3916 */ + { 0x0038A4DD, 0, 0, 0, 0x0000057B }, /* 56.6444 */ + { 0x003B0000, 0, 1, 0, 0x00000707 }, /* 59.0000 */ + { 0x003C10A3, 0, 0, 0, 0x0000030B }, /* 60.0650 */ + { 0x003F0000, 1, 1, 0, 0x00000B39 }, /* 63.0000 */ + { 0x00410000, 1, 0, 0, 0x00000545 }, /* 65.0000 */ + { 0x00442DD2, 1, 0, 0, 0x000002E1 }, /* 68.1790 */ + { 0x00438000, 1, 1, 0, 0x00000FC1 }, /* 67.5000 */ + { 0x0046CCCC, 1, 0, 0, 0x00000561 }, /* 70.8000 */ + { 0x00480000, 1, 0, 0, 0x000007E1 }, /* 72.0000 */ + { 0x004A7B22, 0, 1, 0, 0x00000F4A }, /* 74.4810 */ + { 0x004B0000, 1, 0, 0, 0x000007F5 }, /* 75.0000 */ + { 0x004EC000, 1, 0, 0, 0x00000305 }, /* 78.7500 */ + { 0x00500000, 1, 1, 0, 0x00000709 }, /* 80.0000 */ + { 0x00519999, 0, 0, 0, 0x000009C6 }, /* 81.6000 */ + { 0x0059CCCC, 0, 1, 0, 0x00000262 }, /* 89.8000 */ + { 0x005E8000, 0, 0, 0, 0x000002D2 }, /* 94.5000 */ + { 0x00618560, 0, 0, 0, 0x00000546 }, /* 97.5200 */ + { 0x00630000, 0, 1, 0, 0x00000B4A }, /* 99.0000 */ + { 0x00642FDF, 0, 0, 0, 0x0000006E }, /* 100.1870 */ + { 0x00656B85, 0, 0, 0, 0x00000552 }, /* 101.4200 */ + { 0x006C0000, 0, 0, 0, 0x000007E2 }, /* 108.0000 */ + { 0x00708000, 0, 0, 0, 0x000007F6 }, /* 112.5000 */ + { 0x00714F1A, 0, 0, 0, 0x0000057A }, /* 113.3090 */ + { 0x0077A666, 0, 0, 0, 0x0000030A }, /* 119.6500 */ + { 0x00806666, 1, 0, 0, 0x00000068 }, /* 128.4000 */ + { 0x00820000, 1, 1, 0, 0x00000FB0 }, /* 130.0000 */ + { 0x00821999, 1, 0, 0, 0x00000544 }, /* 130.1000 */ + { 0x00858000, 1, 0, 0, 0x0000006C }, /* 133.5000 */ + { 0x00870000, 1, 0, 0, 0x00000550 }, /* 135.0000 */ + { 0x00906147, 1, 0, 0, 0x000007E0 }, /* 144.3800 */ + { 0x009D8000, 1, 0, 0, 0x00000304 }, /* 157.5000 */ + { 0x00A20000, 0, 0, 0, 0x000002B1 }, /* 162.0000 */ + { 0x00A933F7, 0, 0, 0, 0x000002B9 }, /* 169.2030 */ + { 0x00ACCC49, 0, 1, 0, 0x0000002D }, /* 172.798 */ + { 0x00AF8000, 0, 0, 0, 0x000002C1 }, /* 175.5000 */ + { 0x00BD0000, 0, 0, 0, 0x000002D1 }, /* 189.0000 */ + { 0x00BEF5C2, 0, 0, 0, 0x0000053D }, /* 190.9600 */ + { 0x00C60000, 0, 0, 0, 0x00000549 }, /* 198.0000 */ + { 0x00CA8000, 0, 0, 0, 0x00000551 }, /* 202.5000 */ + { 0x00E58000, 0, 0, 0, 0x0000057D }, /* 229.5000 */ +}; + +#define NUM_RCDF_FREQUENCIES sizeof(RCDF_PLLtable)/sizeof(RCDFPLLENTRY) + + +/*--------------------------------------------------------------------------- + * gfx_reset_video (PRIVATE ROUTINE: NOT PART OF DURANGO API) + * + * This routine is used to disable all components of video overlay before + * performing a mode switch. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void redcloud_reset_video(void) +#else +void gfx_reset_video(void) +#endif +{ + gfx_set_video_enable(0); + gfx_select_alpha_region(1); + gfx_set_alpha_enable(0); + gfx_select_alpha_region(2); + gfx_set_alpha_enable(0); + + /* SET REGION 0 AFTER RESET */ + + gfx_select_alpha_region(0); + gfx_set_alpha_enable(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_display_control (PRIVATE ROUTINE: NOT PART OF DURANGO API) + * + * This routine configures the display output. + * + * "sync_polarities" is used to set the polarities of the sync pulses according + * to the following mask: + * + * Bit 0: If set to 1, negative horizontal polarity is programmed, + * otherwise positive horizontal polarity is programmed. + * Bit 1: If set to 1, negative vertical polarity is programmed, + * otherwise positive vertical polarity is programmed. + * + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_display_control(int sync_polarities) +#else +int gfx_set_display_control(int sync_polarities) +#endif +{ + unsigned long power; + unsigned long dcfg; + + /* CONFIGURE DISPLAY OUTPUT FROM VIDEO PROCESSOR */ + + dcfg = READ_VID32(RCDF_DISPLAY_CONFIG); + dcfg &= ~(RCDF_DCFG_CRT_SYNC_SKW_MASK | RCDF_DCFG_PWR_SEQ_DLY_MASK | + RCDF_DCFG_CRT_HSYNC_POL | RCDF_DCFG_CRT_VSYNC_POL | + RCDF_DCFG_FP_PWR_EN | RCDF_DCFG_FP_DATA_EN); + + dcfg |= (RCDF_DCFG_CRT_SYNC_SKW_INIT | + RCDF_DCFG_PWR_SEQ_DLY_INIT | + RCDF_DCFG_GV_PAL_BYP); + + if (PanelEnable) + { + power = READ_VID32 (RCDF_POWER_MANAGEMENT); + power |= RCDF_PM_PANEL_POWER_ON; + WRITE_VID32 (RCDF_POWER_MANAGEMENT, power); + } + + /* SET APPROPRIATE SYNC POLARITIES */ + + if (sync_polarities & 0x1) + dcfg |= RCDF_DCFG_CRT_HSYNC_POL; + if (sync_polarities & 0x2) + dcfg |= RCDF_DCFG_CRT_VSYNC_POL; + + WRITE_VID32 (RCDF_DISPLAY_CONFIG, dcfg); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_clock_frequency + * + * This routine sets the clock frequency, specified as a 16.16 fixed point + * value (0x00318000 = 49.5 MHz). It will set the closest frequency found + * in the lookup table. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void redcloud_set_clock_frequency(unsigned long frequency) +#else +void gfx_set_clock_frequency(unsigned long frequency) +#endif +{ + Q_WORD msr_value, sys_value; + unsigned long sys_low; + unsigned int i, index = 0; + unsigned long value; + long timeout = 1000; + long min, diff; + + /* FIND THE REGISTER VALUES FOR THE DESIRED FREQUENCY */ + /* Search the table for the closest frequency (16.16 format). */ + + value = RCDF_PLLtable[0].pll_value; + min = (long) RCDF_PLLtable[0].frequency - frequency; + if (min < 0L) min = -min; + for (i = 1; i < NUM_RCDF_FREQUENCIES; i++) + { + diff = (long) RCDF_PLLtable[i].frequency - frequency; + if (diff < 0L) diff = -diff; + if (diff < min) + { + min = diff; + index = i; + } + } + + /* VERIFY THAT WE ARE NOT WRITING WHAT IS ALREADY IN THE REGISTERS */ + /* The Dot PLL reset bit is tied to VDD for flat panels. This can */ + /* cause a brief drop in flat panel power, which can cause serious */ + /* glitches on some panels. */ + + gfx_msr_read (RC_ID_MCP, MCP_DOTPLL, &msr_value); + gfx_msr_read (RC_ID_MCP, MCP_SYS_RSTPLL, &sys_value); + + sys_low = 0; + if (RCDF_PLLtable[index].post_div3) sys_low |= MCP_DOTPOSTDIV3; + if (RCDF_PLLtable[index].pre_div2) sys_low |= MCP_DOTPREDIV2; + if (RCDF_PLLtable[index].pre_mul2) sys_low |= MCP_DOTPREMULT2; + + if ((msr_value.low & MCP_DOTPLL_LOCK) && + (msr_value.high == RCDF_PLLtable[index].pll_value) && + ((sys_value.low & (MCP_DOTPOSTDIV3 | MCP_DOTPREDIV2 | MCP_DOTPREMULT2)) == sys_low)) + { + return; + } + + /* PROGRAM THE SETTINGS WITH THE RESET BIT SET */ + /* Clear the bypass bit to ensure that the programmed */ + /* M, N and P values are being used. */ + + msr_value.high = RCDF_PLLtable[index].pll_value; + msr_value.low |= 0x00000001; + msr_value.low &= ~MCP_DOTPLL_BYPASS; + gfx_msr_write (RC_ID_MCP, MCP_DOTPLL, &msr_value); + + /* PROGRAM THE MCP DIVIDER VALUES */ + + sys_value.low &= ~(MCP_DOTPOSTDIV3 | MCP_DOTPREDIV2 | MCP_DOTPREMULT2); + sys_value.low |= sys_low; + gfx_msr_write (RC_ID_MCP, MCP_SYS_RSTPLL, &sys_value); + + /* CLEAR THE RESET BIT */ + + msr_value.low &= 0xFFFFFFFE; + gfx_msr_write (RC_ID_MCP, MCP_DOTPLL, &msr_value); + + /* WAIT FOR LOCK BIT */ + + do + { + gfx_msr_read (RC_ID_MCP, MCP_DOTPLL, &msr_value); + } while (timeout-- && !(msr_value.low & MCP_DOTPLL_LOCK)); +} + +/*--------------------------------------------------------------------------- + * gfx_set_crt_enable + * + * This routine enables or disables the CRT output from the video processor. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_crt_enable(int enable) +#else +int gfx_set_crt_enable(int enable) +#endif +{ + unsigned long config, misc; + config = READ_VID32(RCDF_DISPLAY_CONFIG); + misc = READ_VID32(RCDF_VID_MISC); + + switch (enable) + { + case CRT_DISABLE: /* DISABLE EVERYTHING */ + + WRITE_VID32(RCDF_DISPLAY_CONFIG, config & ~(RCDF_DCFG_DIS_EN | RCDF_DCFG_HSYNC_EN + | RCDF_DCFG_VSYNC_EN | RCDF_DCFG_DAC_BL_EN )); + WRITE_VID32(RCDF_VID_MISC, misc | RCDF_DAC_POWER_DOWN); + break; + + case CRT_ENABLE: /* ENABLE CRT DISPLAY, INCLUDING DISPLAY LOGIC */ + + WRITE_VID32(RCDF_DISPLAY_CONFIG, config | RCDF_DCFG_DIS_EN | RCDF_DCFG_HSYNC_EN + | RCDF_DCFG_VSYNC_EN | RCDF_DCFG_DAC_BL_EN); + WRITE_VID32(RCDF_VID_MISC, misc & ~RCDF_DAC_POWER_DOWN & ~RCDF_ANALOG_POWER_DOWN); + break; + + case CRT_STANDBY: /* HSYNC:OFF VSYNC:ON */ + + WRITE_VID32(RCDF_DISPLAY_CONFIG, (config & ~(RCDF_DCFG_DIS_EN | RCDF_DCFG_HSYNC_EN + | RCDF_DCFG_DAC_BL_EN)) | + RCDF_DCFG_VSYNC_EN ); + WRITE_VID32(RCDF_VID_MISC, misc | RCDF_DAC_POWER_DOWN); + break; + + case CRT_SUSPEND: /* HSYNC:ON VSYNC:OFF */ + + WRITE_VID32(RCDF_DISPLAY_CONFIG, (config & ~(RCDF_DCFG_DIS_EN | RCDF_DCFG_VSYNC_EN + | RCDF_DCFG_DAC_BL_EN)) | + RCDF_DCFG_HSYNC_EN ); + WRITE_VID32(RCDF_VID_MISC, misc | RCDF_DAC_POWER_DOWN); + break; + + default: + return (GFX_STATUS_BAD_PARAMETER); + } + return(GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_enable + * + * This routine enables or disables the video overlay functionality. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_enable(int enable) +#else +int gfx_set_video_enable(int enable) +#endif +{ + unsigned long vcfg; + + /* WAIT FOR VERTICAL BLANK TO START */ + /* Otherwise a glitch can be observed. */ + + if (gfx_test_timing_active()) + { + if (!gfx_test_vertical_active()) + { + while(!gfx_test_vertical_active()); + } + while(gfx_test_vertical_active()); + } + + vcfg = READ_VID32(RCDF_VIDEO_CONFIG); + if (enable) + { + /* ENABLE VIDEO OVERLAY FROM DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_enable(1); + + /* ENABLE DISPLAY FILTER VIDEO OVERLAY */ + + vcfg |= RCDF_VCFG_VID_EN; + WRITE_VID32(RCDF_VIDEO_CONFIG, vcfg); + } + else + { + /* DISABLE DISPLAY FILTER VIDEO OVERLAY */ + + vcfg &= ~RCDF_VCFG_VID_EN; + WRITE_VID32(RCDF_VIDEO_CONFIG, vcfg); + + /* DISABLE VIDEO OVERLAY FROM DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_enable(0); + } + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_format + * + * Sets input video format type, to one of the YUV formats or to RGB. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_format(unsigned long format) +#else +int gfx_set_video_format(unsigned long format) +#endif +{ + unsigned long ctrl, vcfg = 0; + + /* SET THE DISPLAY FILTER VIDEO INPUT FORMAT */ + + vcfg = READ_VID32(RCDF_VIDEO_CONFIG); + ctrl = READ_VID32(RCDF_VID_ALPHA_CONTROL); + ctrl &= ~(RCDF_VIDEO_INPUT_IS_RGB | RCDF_CSC_VIDEO_YUV_TO_RGB); + vcfg &= ~(RCDF_VCFG_VID_INP_FORMAT | RCDF_VCFG_4_2_0_MODE); + switch(format) + { + case VIDEO_FORMAT_UYVY: + vcfg |= RCDF_VCFG_UYVY_FORMAT; + ctrl |= RCDF_CSC_VIDEO_YUV_TO_RGB; + break; + case VIDEO_FORMAT_YUYV: + vcfg |= RCDF_VCFG_YUYV_FORMAT; + ctrl |= RCDF_CSC_VIDEO_YUV_TO_RGB; + break; + case VIDEO_FORMAT_Y2YU: + vcfg |= RCDF_VCFG_Y2YU_FORMAT; + ctrl |= RCDF_CSC_VIDEO_YUV_TO_RGB; + break; + case VIDEO_FORMAT_YVYU: + vcfg |= RCDF_VCFG_YVYU_FORMAT; + ctrl |= RCDF_CSC_VIDEO_YUV_TO_RGB; + break; + case VIDEO_FORMAT_Y0Y1Y2Y3: + vcfg |= RCDF_VCFG_UYVY_FORMAT; + ctrl |= RCDF_CSC_VIDEO_YUV_TO_RGB; + vcfg |= RCDF_VCFG_4_2_0_MODE; + break; + case VIDEO_FORMAT_Y3Y2Y1Y0: + vcfg |= RCDF_VCFG_Y2YU_FORMAT; + ctrl |= RCDF_CSC_VIDEO_YUV_TO_RGB; + vcfg |= RCDF_VCFG_4_2_0_MODE; + break; + case VIDEO_FORMAT_Y1Y0Y3Y2: + vcfg |= RCDF_VCFG_YUYV_FORMAT; + ctrl |= RCDF_CSC_VIDEO_YUV_TO_RGB; + vcfg |= RCDF_VCFG_4_2_0_MODE; + break; + case VIDEO_FORMAT_Y1Y2Y3Y0: + vcfg |= RCDF_VCFG_YVYU_FORMAT; + ctrl |= RCDF_CSC_VIDEO_YUV_TO_RGB; + vcfg |= RCDF_VCFG_4_2_0_MODE; + break; + case VIDEO_FORMAT_RGB: + ctrl |= RCDF_VIDEO_INPUT_IS_RGB; + vcfg |= RCDF_VCFG_UYVY_FORMAT; + break; + case VIDEO_FORMAT_P2M_P2L_P1M_P1L: + ctrl |= RCDF_VIDEO_INPUT_IS_RGB; + vcfg |= RCDF_VCFG_Y2YU_FORMAT; + break; + case VIDEO_FORMAT_P1M_P1L_P2M_P2L: + ctrl |= RCDF_VIDEO_INPUT_IS_RGB; + vcfg |= RCDF_VCFG_YUYV_FORMAT; + break; + case VIDEO_FORMAT_P1M_P2L_P2M_P1L: + ctrl |= RCDF_VIDEO_INPUT_IS_RGB; + vcfg |= RCDF_VCFG_YVYU_FORMAT; + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + WRITE_VID32(RCDF_VIDEO_CONFIG, vcfg); + WRITE_VID32(RCDF_VID_ALPHA_CONTROL, ctrl); + + /* SET THE VIDEO FORMAT IN THE DISPLAY CONTROLLER */ + /* Use private routine to abstract display controller. */ + + gfx_set_display_video_format (format); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_size + * + * This routine specifies the size of the source data. It is used only + * to determine how much data to transfer per frame, and is not used to + * calculate the scaling value (that is handled by a separate routine). + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_size(unsigned short width, unsigned short height) +#else +int gfx_set_video_size(unsigned short width, unsigned short height) +#endif +{ + unsigned long size, vcfg, vid_420, pitch; + + /* SET THE DISPLAY FILTER VIDEO LINE SIZE */ + /* Match the DC hardware alignment requirement. The line size must */ + /* always be 32-byte aligned. However, we can manage smaller */ + /* alignments by decreasing the pitch and clipping the video window. */ + /* The VG will fetch extra data for each line, but the decreased */ + /* pitch will ensure that it always begins fetching at the start of */ + /* the video line. */ + + vcfg = READ_VID32(RCDF_VIDEO_CONFIG); + + vid_420 = vcfg & RCDF_VCFG_4_2_0_MODE; + + vcfg &= ~(RCDF_VCFG_LINE_SIZE_LOWER_MASK | RCDF_VCFG_LINE_SIZE_UPPER); + + size = ((width >> 1) + 7) & 0xFFF8; + pitch = ((width << 1) + 7) & 0xFFF8; + + vcfg |= (size & 0x00FF) << 8; + if (size & 0x0100) vcfg |= RCDF_VCFG_LINE_SIZE_UPPER; + WRITE_VID32(RCDF_VIDEO_CONFIG, vcfg); + + /* SET VIDEO BUFFER LINE SIZE IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_size (width, height); + + /* SET VIDEO PITCH */ + /* We are only maintaining legacy for 4:2:2 video formats. */ + /* 4:2:0 video in previous chips was inadequate for most */ + /* common video formats. */ + + if (!vid_420) + gfx_set_video_yuv_pitch (pitch, pitch << 1); + + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_offset + * + * This routine sets the starting offset for the video buffer when only + * one offset needs to be specified. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_offset(unsigned long offset) +#else +int gfx_set_video_offset(unsigned long offset) +#endif +{ + /* SAVE VALUE FOR FUTURE CLIPPING OF THE TOP OF THE VIDEO WINDOW */ + + gfx_vid_offset = offset; + + /* SET VIDEO BUFFER OFFSET IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_offset(offset); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_yuv_offsets + * + * This routine sets the starting offset for the video buffer when displaying + * 4:2:0 video. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, unsigned long voffset) +#else +int gfx_set_video_yuv_offsets(unsigned long yoffset, unsigned long uoffset, unsigned long voffset) +#endif +{ + /* SAVE VALUE FOR FUTURE CLIPPING OF THE TOP OF THE VIDEO WINDOW */ + + gfx_vid_offset = yoffset; + gfx_vid_uoffset = uoffset; + gfx_vid_voffset = voffset; + + /* SET VIDEO BUFFER OFFSET IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_yuv_offsets(yoffset, uoffset, voffset); + + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_set_video_yuv_pitch + * + * This routine sets the byte offset between consecutive scanlines of YUV video data + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_yuv_pitch(unsigned long ypitch, unsigned long uvpitch) +#else +int gfx_set_video_yuv_pitch(unsigned long ypitch, unsigned long uvpitch) +#endif +{ + /* SET VIDEO PITCH IN DISPLAY CONTROLLER */ + /* Use private routine to abstract the display controller. */ + + gfx_set_display_video_yuv_pitch (ypitch, uvpitch); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_scale + * + * This routine sets the scale factor for the video overlay window. The + * size of the source and destination regions are specified in pixels. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +#else +int gfx_set_video_scale(unsigned short srcw, unsigned short srch, + unsigned short dstw, unsigned short dsth) +#endif +{ + unsigned long xscale, yscale; + + /* SAVE PARAMETERS (unless don't-care zero destination arguments are used) */ + /* These are needed for clipping the video window later. */ + + if (dstw != 0) { + gfx_vid_srcw = srcw; + gfx_vid_dstw = dstw; + } + if (dsth != 0) { + gfx_vid_srch = srch; + gfx_vid_dsth = dsth; + } + + /* CALCULATE DISPLAY FILTER SCALE FACTORS */ + /* Zero width and height indicate don't care conditions */ + /* Downscaling is performed in a separate function. */ + + if (dstw == 0) xscale = READ_VID32(RCDF_VIDEO_SCALE) & 0xffff; /* keep previous if don't-care argument */ + else if (dstw <= srcw) xscale = 0x2000; /* horizontal downscaling is currently done in a separate function */ + else if ((srcw == 1) || (dstw == 1)) return GFX_STATUS_BAD_PARAMETER; + else xscale = (0x2000l * (srcw - 1l)) / (dstw - 1l); + + if (dsth == 0) yscale = (READ_VID32(RCDF_VIDEO_SCALE) & 0xffff0000) >> 16; /* keep previous if don't-care argument */ + else if (dsth <= srch) yscale = 0x2000; /* vertical downscaling is handled in a separate function */ + else if ((srch == 1) || (dsth == 1)) return GFX_STATUS_BAD_PARAMETER; + else yscale = (0x2000l * (srch - 1l)) / (dsth - 1l); + + WRITE_VID32(RCDF_VIDEO_SCALE, (yscale << 16) | xscale); + + /* CALL ROUTINE TO UPDATE WINDOW POSITION */ + /* This is required because the scale values affect the number of */ + /* source data pixels that need to be clipped, as well as the */ + /* amount of data that needs to be transferred. */ + + gfx_set_video_window(gfx_vid_xpos, gfx_vid_ypos, gfx_vid_width, gfx_vid_height); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_vertical_downscale + * + * This routine sets the vertical downscale factor for the video overlay window. + * The height of the source and destination regions are specified in pixels. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_vertical_downscale(unsigned short srch, unsigned short dsth) +#else +int gfx_set_video_vertical_downscale(unsigned short srch, unsigned short dsth) +#endif +{ + /* SET VIDEO SCALE IN DISPLAY CONTROLLER */ + /* Use private routine to abstract hardware */ + + gfx_set_display_video_downscale (srch, dsth); + return 0; +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_vertical_downscale_enable + * + * This routine sets the vertical downscale enable for the video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void redcloud_set_video_vertical_downscale_enable(int enable) +#else +void gfx_set_video_vertical_downscale_enable(int enable) +#endif +{ + /* SET VIDEO SCALE IN DISPLAY CONTROLLER */ + /* Use private routine to abstract hardware */ + + gfx_set_display_video_vertical_downscale_enable (enable); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_downscale_config + * + * This routine sets the downscale type and factor for the video overlay window. + * Note: No downscaling support for RGB565 and YUV420 video formats. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_downscale_config(unsigned short type, unsigned short m) +#else +int gfx_set_video_downscale_config(unsigned short type, unsigned short m) +#endif +{ + unsigned long downscale; + + if ((m < 1) || (m > 16)) return GFX_STATUS_BAD_PARAMETER; + + downscale = READ_VID32(RCDF_VIDEO_DOWNSCALER_CONTROL); + downscale &= ~(RCDF_VIDEO_DOWNSCALE_FACTOR_MASK | RCDF_VIDEO_DOWNSCALE_TYPE_MASK); + downscale |= ((unsigned long)(m - 1) << RCDF_VIDEO_DOWNSCALE_FACTOR_POS); + switch(type) + { + case VIDEO_DOWNSCALE_KEEP_1_OF: + downscale |= RCDF_VIDEO_DOWNSCALE_TYPE_A; + break; + case VIDEO_DOWNSCALE_DROP_1_OF: + downscale |= RCDF_VIDEO_DOWNSCALE_TYPE_B; + break; + default: + return GFX_STATUS_BAD_PARAMETER; + } + WRITE_VID32(RCDF_VIDEO_DOWNSCALER_CONTROL, downscale); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_downscale_coefficients + * + * This routine sets the downscale filter coefficients. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_downscale_coefficients(unsigned short coef1, unsigned short coef2, + unsigned short coef3, unsigned short coef4) +#else +int gfx_set_video_downscale_coefficients(unsigned short coef1, unsigned short coef2, + unsigned short coef3, unsigned short coef4) +#endif +{ + if ((coef1 + coef2 + coef3 + coef4) != 16) + return GFX_STATUS_BAD_PARAMETER; + + WRITE_VID32(RCDF_VIDEO_DOWNSCALER_COEFFICIENTS, + ((unsigned long)coef1 << RCDF_VIDEO_DOWNSCALER_COEF1_POS) | + ((unsigned long)coef2 << RCDF_VIDEO_DOWNSCALER_COEF2_POS) | + ((unsigned long)coef3 << RCDF_VIDEO_DOWNSCALER_COEF3_POS) | + ((unsigned long)coef4 << RCDF_VIDEO_DOWNSCALER_COEF4_POS)); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_downscale_enable + * + * This routine enables or disables downscaling for the video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_downscale_enable(int enable) +#else +int gfx_set_video_downscale_enable(int enable) +#endif +{ + unsigned long downscale; + + downscale = READ_VID32(RCDF_VIDEO_DOWNSCALER_CONTROL); + if (enable) + downscale |= RCDF_VIDEO_DOWNSCALE_ENABLE; + else + downscale &= ~RCDF_VIDEO_DOWNSCALE_ENABLE; + WRITE_VID32(RCDF_VIDEO_DOWNSCALER_CONTROL, downscale); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_window + * + * This routine sets the position and size of the video overlay window. The + * x and y positions are specified in screen relative coordinates, and may be negative. + * The size of destination region is specified in pixels. The line size + * indicates the number of bytes of source data per scanline. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_window(short x, short y, unsigned short w, unsigned short h) +#else +int gfx_set_video_window(short x, short y, unsigned short w, unsigned short h) +#endif +{ + unsigned long hadjust, vadjust; + unsigned long xstart, ystart, xend, yend; + + /* SAVE PARAMETERS */ + /* These are needed to call this routine if the scale value changes. */ + + gfx_vid_xpos = x; + gfx_vid_ypos = y; + gfx_vid_width = w; + gfx_vid_height = h; + + /* GET ADJUSTMENT VALUES */ + /* Use routines to abstract version of display controller. */ + + hadjust = gfx_get_htotal() - gfx_get_hsync_end() - 14l; + vadjust = gfx_get_vtotal() - gfx_get_vsync_end() + 1l; + + /* LEFT CLIPPING */ + + if (x < 0) + { + gfx_set_video_left_crop ((unsigned short)(-x)); + xstart = hadjust; + } + else + { + gfx_set_video_left_crop (0); + xstart = (unsigned long)x + hadjust; + } + + /* HORIZONTAL END */ + /* End positions in register are non-inclusive (one more than the actual end) */ + + if ((x + w) < gfx_get_hactive()) + xend = (unsigned long)x + (unsigned long)w + hadjust; + + /* RIGHT-CLIPPING */ + else + xend = (unsigned long)gfx_get_hactive() + hadjust; + + /* VERTICAL START */ + + ystart = (unsigned long)y + vadjust; + + /* VERTICAL END */ + + if ((y + h) < gfx_get_vactive()) + yend = (unsigned long)y + (unsigned long)h + vadjust; + + /* BOTTOM-CLIPPING */ + else + yend = (unsigned long)gfx_get_vactive() + vadjust; + + /* SET VIDEO POSITION */ + + WRITE_VID32(RCDF_VIDEO_X_POS, (xend << 16) | xstart); + WRITE_VID32(RCDF_VIDEO_Y_POS, (yend << 16) | ystart); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_left_crop + * + * This routine sets the number of pixels which will be cropped from the + * beginning of each video line. The video window will begin to display only + * from the pixel following the cropped pixels, and the cropped pixels + * will be ignored. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_left_crop(unsigned short x) +#else +int gfx_set_video_left_crop(unsigned short x) +#endif +{ + unsigned long vcfg, initread; + + vcfg = READ_VID32(RCDF_VIDEO_CONFIG); + + /* CLIPPING ON LEFT */ + /* Adjust initial read for scale, checking for divide by zero. Mask the */ + /* lower three bits when clipping 4:2:0 video. By masking the bits instead */ + /* of rounding up we ensure that we always clip less than or equal to the */ + /* desired number of pixels. This prevents visual artifacts from */ + /* over-clipping. We mask three bits to meet the HW requirement that 4:2:0 */ + /* clipping be 16-byte or 8-pixel aligned. */ + + if (gfx_vid_dstw) + { + initread = (unsigned long)x * gfx_vid_srcw / gfx_vid_dstw; + + if (vcfg & RCDF_VCFG_4_2_0_MODE) + initread &= 0xFFF8; + } + else + initread = 0; + + /* SET INITIAL READ ADDRESS */ + + vcfg &= ~RCDF_VCFG_INIT_READ_MASK; + vcfg |= (initread << 15) & RCDF_VCFG_INIT_READ_MASK; + WRITE_VID32(RCDF_VIDEO_CONFIG, vcfg); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_color_key + * + * This routine specifies the color key value and mask for the video overlay + * hardware. To disable color key, the color and mask should both be set to + * zero. The hardware uses the color key in the following equation: + * + * ((source data) & (color key mask)) == ((color key) & (color key mask)) + * + * If "graphics" is set to TRUE, the source data is graphics, and color key + * is an RGB value. If "graphics" is set to FALSE, the source data is the video, + * and color key is a YUV value. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_color_key(unsigned long key, unsigned long mask, + int graphics) +#else +int gfx_set_video_color_key(unsigned long key, unsigned long mask, + int graphics) +#endif +{ + unsigned long dcfg = 0; + + /* SET RCDF COLOR KEY VALUE */ + + WRITE_VID32(RCDF_VIDEO_COLOR_KEY, key); + WRITE_VID32(RCDF_VIDEO_COLOR_MASK, mask); + + /* SELECT GRAPHICS OR VIDEO DATA TO COMPARE TO THE COLOR KEY */ + + dcfg = READ_VID32(RCDF_DISPLAY_CONFIG); + if (graphics & 0x01) dcfg &= ~RCDF_DCFG_VG_CK; + else dcfg |= RCDF_DCFG_VG_CK; + WRITE_VID32(RCDF_DISPLAY_CONFIG, dcfg); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_filter + * + * This routine enables or disables the video overlay filters. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_filter(int xfilter, int yfilter) +#else +int gfx_set_video_filter(int xfilter, int yfilter) +#endif +{ + unsigned long vcfg = 0; + + /* ENABLE OR DISABLE DISPLAY FILTER VIDEO OVERLAY FILTERS */ + + vcfg = READ_VID32(RCDF_VIDEO_CONFIG); + vcfg &= ~(RCDF_VCFG_X_FILTER_EN | RCDF_VCFG_Y_FILTER_EN); + if (xfilter) vcfg |= RCDF_VCFG_X_FILTER_EN; + if (yfilter) vcfg |= RCDF_VCFG_Y_FILTER_EN; + WRITE_VID32(RCDF_VIDEO_CONFIG, vcfg); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette + * + * This routine loads the video hardware palette. If a NULL pointer is + * specified, the palette is bypassed (for Redcloud, this means loading the + * palette with identity values). + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_palette(unsigned long *palette) +#else +int gfx_set_video_palette(unsigned long *palette) +#endif +{ + unsigned long i, entry; + unsigned long misc, dcfg; + + /* ENABLE THE VIDEO PALETTE */ + /* Ensure that the video palette has an effect by routing video data */ + /* through the palette RAM and clearing the 'Bypass Both' bit. */ + + dcfg = READ_VID32 (RCDF_DISPLAY_CONFIG); + misc = READ_VID32 (RCDF_VID_MISC); + + dcfg |= RCDF_DCFG_GV_PAL_BYP; + misc &= ~RCDF_GAMMA_BYPASS_BOTH; + + WRITE_VID32 (RCDF_DISPLAY_CONFIG, dcfg); + WRITE_VID32 (RCDF_VID_MISC, misc); + + if (gfx_test_timing_active()) + { + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + } + + /* LOAD REDCLOUD VIDEO PALETTE */ + + WRITE_VID32(RCDF_PALETTE_ADDRESS, 0); + for (i = 0; i < 256; i++) + { + if (palette) entry = palette[i]; + else entry = gfx_gamma_ram_redcloud[i]; + WRITE_VID32(RCDF_PALETTE_DATA, entry); + } + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_graphics_palette + * + * This routine loads the video hardware palette. If a NULL pointer is + * specified, the palette is bypassed (for Redcloud, this means loading the + * palette with identity values). Note that this routine is identical to + * gfx_set_video_palette, except that the hardware is updated to route graphics + * data through the palette. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_graphics_palette(unsigned long *palette) +#else +int gfx_set_graphics_palette(unsigned long *palette) +#endif +{ + unsigned long i, entry; + unsigned long misc, dcfg; + + /* ENABLE THE VIDEO PALETTE */ + /* Ensure that the video palette has an effect by routing video data */ + /* through the palette RAM and clearing the 'Bypass Both' bit. */ + + dcfg = READ_VID32 (RCDF_DISPLAY_CONFIG); + misc = READ_VID32 (RCDF_VID_MISC); + + dcfg &= ~RCDF_DCFG_GV_PAL_BYP; + misc &= ~RCDF_GAMMA_BYPASS_BOTH; + + WRITE_VID32 (RCDF_DISPLAY_CONFIG, dcfg); + WRITE_VID32 (RCDF_VID_MISC, misc); + + if (gfx_test_timing_active()) + { + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + } + + /* LOAD REDCLOUD VIDEO PALETTE */ + + WRITE_VID32(RCDF_PALETTE_ADDRESS, 0); + for (i = 0; i < 256; i++) + { + if (palette) entry = palette[i]; + else entry = gfx_gamma_ram_redcloud[i]; + WRITE_VID32(RCDF_PALETTE_DATA, entry); + } + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_graphics_palette_entry + * + * This routine loads a single entry of the video hardware palette. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_graphics_palette_entry(unsigned long index, unsigned long palette) +#else +int gfx_set_graphics_palette_entry(unsigned long index, unsigned long palette) +#endif +{ + unsigned long dcfg, misc; + + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + /* ENABLE THE VIDEO PALETTE */ + /* Ensure that the video palette has an effect by routing video data */ + /* through the palette RAM and clearing the 'Bypass Both' bit. */ + + dcfg = READ_VID32 (RCDF_DISPLAY_CONFIG); + misc = READ_VID32 (RCDF_VID_MISC); + + dcfg &= ~RCDF_DCFG_GV_PAL_BYP; + misc &= ~RCDF_GAMMA_BYPASS_BOTH; + + WRITE_VID32 (RCDF_DISPLAY_CONFIG, dcfg); + WRITE_VID32 (RCDF_VID_MISC, misc); + + /* SET A SINGLE ENTRY */ + + WRITE_VID32(RCDF_PALETTE_ADDRESS, index); + WRITE_VID32(RCDF_PALETTE_DATA, palette); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette_entry + * + * This routine loads a single entry of the video hardware palette. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_palette_entry(unsigned long index, unsigned long palette) +#else +int gfx_set_video_palette_entry(unsigned long index, unsigned long palette) +#endif +{ + unsigned long dcfg, misc; + + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + /* ENABLE THE VIDEO PALETTE */ + /* Ensure that the video palette has an effect by routing video data */ + /* through the palette RAM and clearing the 'Bypass Both' bit. */ + + dcfg = READ_VID32 (RCDF_DISPLAY_CONFIG); + misc = READ_VID32 (RCDF_VID_MISC); + + dcfg |= RCDF_DCFG_GV_PAL_BYP; + misc &= ~RCDF_GAMMA_BYPASS_BOTH; + + WRITE_VID32 (RCDF_DISPLAY_CONFIG, dcfg); + WRITE_VID32 (RCDF_VID_MISC, misc); + + /* SET A SINGLE ENTRY */ + + WRITE_VID32(RCDF_PALETTE_ADDRESS, index); + WRITE_VID32(RCDF_PALETTE_DATA, palette); + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_palette_bypass + * + * This routine enables/disables the pallete RAM bypass. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_palette_bypass (int enable) +#else +int gfx_set_video_palette_bypass (int enable) +#endif +{ + unsigned long misc; + + misc = READ_VID32 (RCDF_VID_MISC); + + if (enable) misc |= RCDF_GAMMA_BYPASS_BOTH; + else misc &= ~RCDF_GAMMA_BYPASS_BOTH; + + WRITE_VID32 (RCDF_VID_MISC, misc); + + return 0; +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_request() + * + * This routine sets the horizontal (pixel) and vertical (line) video request + * values. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_request(short x, short y) +#else +int gfx_set_video_request(short x, short y) +#endif +{ + /* SET DISPLAY FILTER VIDEO REQUEST */ + + x += gfx_get_htotal() - gfx_get_hsync_end() - 2; + y += gfx_get_vtotal() - gfx_get_vsync_end() + 1; + + if ((x < 0) || (x > RCDF_VIDEO_REQUEST_MASK) || + (y < 0) || (y > RCDF_VIDEO_REQUEST_MASK)) + return GFX_STATUS_BAD_PARAMETER; + + WRITE_VID32(RCDF_VIDEO_REQUEST, ((unsigned long)x << RCDF_VIDEO_X_REQUEST_POS) | + ((unsigned long)y << RCDF_VIDEO_Y_REQUEST_POS)); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_cursor() + * + * This routine configures the video hardware cursor. + * If the "mask"ed bits in the graphics pixel match "key", then either "color1" + * or "color2" will be used for this pixel, according to the value of bit + * number "select_color2" of the graphics pixel. + * + * key - 24 bit RGB value + * mask - 24 bit mask + * color1, color2 - RGB or YUV, depending on the current color space conversion + * select_color2 - value between 0 to 23 + * + * To disable match, a "mask" and "key" value of 0xffffff should be set, + * because the graphics pixels incoming to the video processor have maximum 16 + * bits set (0xF8FCF8). + * + * This feature is useful for disabling alpha blending of the cursor. + * Otherwise cursor image would be blurred (or completely invisible if video + * alpha is maximum value). + * Note: the cursor pixel replacements take place both inside and outside the + * video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_cursor(unsigned long key, unsigned long mask, unsigned short select_color2, + unsigned long color1, unsigned long color2) +#else +int gfx_set_video_cursor(unsigned long key, unsigned long mask, unsigned short select_color2, + unsigned long color1, unsigned long color2) +#endif +{ + if (select_color2 > RCDF_CURSOR_COLOR_BITS) return GFX_STATUS_BAD_PARAMETER; + key = (key & RCDF_COLOR_MASK) | ((unsigned long)select_color2 << RCDF_CURSOR_COLOR_KEY_OFFSET_POS); + WRITE_VID32(RCDF_CURSOR_COLOR_KEY, key); + WRITE_VID32(RCDF_CURSOR_COLOR_MASK, mask); + WRITE_VID32(RCDF_CURSOR_COLOR_1, color1); + WRITE_VID32(RCDF_CURSOR_COLOR_2, color2); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_video_cursor() + * + * This routine configures the video hardware cursor. + * If the "mask"ed bits in the graphics pixel match "key", then either "color1" + * or "color2" will be used for this pixel, according to the value of bit + * number "select_color2" of the graphics pixel. + * + * key - 24 bit RGB value + * mask - 24 bit mask + * color1, color2 - RGB or YUV, depending on the current color space conversion + * select_color2 - value between 0 to 23 + * + * To disable match, a "mask" and "key" value of 0xffffff should be set, + * because the graphics pixels incoming to the video processor have maximum 16 + * bits set (0xF8FCF8). + * + * This feature is useful for disabling alpha blending of the cursor. + * Otherwise cursor image would be blurred (or completely invisible if video + * alpha is maximum value). + * Note: the cursor pixel replacements take place both inside and outside the + * video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_video_cursor_enable (int enable) +#else +int gfx_set_video_cursor_enable (int enable) +#endif +{ + unsigned long temp = READ_VID32 (RCDF_CURSOR_COLOR_KEY); + + if (enable) temp |= RCDF_CURSOR_COLOR_KEY_ENABLE; + else temp &= ~RCDF_CURSOR_COLOR_KEY_ENABLE; + + WRITE_VID32 (RCDF_CURSOR_COLOR_KEY, temp); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_enable + * + * This routine enables or disables the currently selected alpha region. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_alpha_enable(int enable) +#else +int gfx_set_alpha_enable(int enable) +#endif +{ + unsigned long address = 0, value = 0; + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = RCDF_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 5); + value = READ_VID32(address); + if (enable) value |= RCDF_ACTRL_WIN_ENABLE; + else value &= ~(RCDF_ACTRL_WIN_ENABLE); + WRITE_VID32(address, value); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_window + * + * This routine sets the size of the currently selected alpha region. + * Note: "x" and "y" are signed to enable using negative values needed for + * implementing workarounds of hardware issues. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_alpha_window(short x, short y, + unsigned short width, unsigned short height) +#else +int gfx_set_alpha_window(short x, short y, + unsigned short width, unsigned short height) +#endif +{ + unsigned long address = 0; + + /* CHECK FOR CLIPPING */ + + if ((x + width) > gfx_get_hactive()) width = gfx_get_hactive() - x; + if ((y + height) > gfx_get_vactive()) height = gfx_get_vactive() - y; + + /* ADJUST POSITIONS */ + + x += gfx_get_htotal() - gfx_get_hsync_end() - 2; + y += gfx_get_vtotal() - gfx_get_vsync_end() + 1; + + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = RCDF_ALPHA_XPOS_1 + ((unsigned long)gfx_alpha_select << 5); + + /* END POSITIONS IN REGISTERS ARE NON-INCLUSIVE (ONE MORE THAN ACTUAL END) */ + + WRITE_VID32(address, (unsigned long) x | + ((unsigned long) (x + width) << 16)); + WRITE_VID32(address + 8, (unsigned long) y | + ((unsigned long) (y + height) << 16)); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_value + * + * This routine sets the alpha value for the currently selected alpha + * region. It also specifies an increment/decrement value for fading. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_alpha_value(unsigned char alpha, char delta) +#else +int gfx_set_alpha_value(unsigned char alpha, char delta) +#endif +{ + unsigned long address = 0, value = 0; + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = RCDF_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 5); + value = READ_VID32(address); + value &= RCDF_ACTRL_WIN_ENABLE; /* keep only enable bit */ + value |= (unsigned long) alpha; + value |= (((unsigned long) delta) & 0xff) << 8; + value |= RCDF_ACTRL_LOAD_ALPHA; + WRITE_VID32(address, value); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_priority + * + * This routine sets the priority of the currently selected alpha region. + * A higher value indicates a higher priority. + * Note: Priority of enabled alpha windows must be different. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_alpha_priority(int priority) +#else +int gfx_set_alpha_priority(int priority) +#endif +{ + unsigned long pos = 0, value = 0; + if (priority > 3) return(GFX_STATUS_BAD_PARAMETER); + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + value = READ_VID32(RCDF_VID_ALPHA_CONTROL); + pos = 16 + (gfx_alpha_select << 1); + value &= ~(0x03l << pos); + value |= (unsigned long)priority << pos; + WRITE_VID32(RCDF_VID_ALPHA_CONTROL, value); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_color + * + * This routine sets the color to be displayed inside the currently selected + * alpha window when there is a color key match (when the alpha color + * mechanism is enabled). + * "color" is an RGB value (for RGB blending) or a YUV value (for YUV blending). + * In Interlaced YUV blending mode, Y/2 value should be used. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_alpha_color(unsigned long color) +#else +int gfx_set_alpha_color(unsigned long color) +#endif +{ + unsigned long address = 0; + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = RCDF_ALPHA_COLOR_1 + ((unsigned long)gfx_alpha_select << 5); + WRITE_VID32(address, color); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_alpha_color_enable + * + * Enable or disable the color mechanism in the alpha window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_alpha_color_enable(int enable) +#else +int gfx_set_alpha_color_enable(int enable) +#endif +{ + unsigned long color; + unsigned long address = 0; + + if (gfx_alpha_select > 2) return(GFX_STATUS_UNSUPPORTED); + address = RCDF_ALPHA_COLOR_1 + ((unsigned long)gfx_alpha_select << 5); + color = READ_VID32(address); + if (enable) + color |= RCDF_ALPHA_COLOR_ENABLE; + else + color &= ~RCDF_ALPHA_COLOR_ENABLE; + WRITE_VID32(address, color); + return(GFX_STATUS_OK); +} + +/*--------------------------------------------------------------------------- + * gfx_set_no_ck_outside_alpha + * + * This function affects where inside the video window color key or chroma + * key comparison is done: + * If enable is TRUE, color/chroma key comparison is performed only inside + * the enabled alpha windows. Outside the (enabled) alpha windows, only video + * is displayed if color key is used, and only graphics is displayed if chroma + * key is used. + * If enable is FALSE, color/chroma key comparison is performed in all the + * video window area. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_set_no_ck_outside_alpha(int enable) +#else +int gfx_set_no_ck_outside_alpha(int enable) +#endif +{ + unsigned long value; + value = READ_VID32(RCDF_VID_ALPHA_CONTROL); + if (enable) + WRITE_VID32(RCDF_VID_ALPHA_CONTROL, value | RCDF_NO_CK_OUTSIDE_ALPHA); + else + WRITE_VID32(RCDF_VID_ALPHA_CONTROL, value & ~RCDF_NO_CK_OUTSIDE_ALPHA); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_clock_frequency + * + * This routine returns the current clock frequency in 16.16 format. + * It reads the current register value and finds the match in the table. + * If no match is found, this routine returns 0. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_get_clock_frequency(void) +#else +unsigned long gfx_get_clock_frequency(void) +#endif +{ + Q_WORD msr_value; + unsigned int index; + unsigned long value, mask = 0x00001FFF; + unsigned long post_div3 = 0, pre_mult2 = 0; + + /* READ PLL SETTING */ + + gfx_msr_read (RC_ID_MCP, MCP_DOTPLL, &msr_value); + value = msr_value.high & mask; + + /* READ DIVISOR SETTINGS */ + + gfx_msr_read (RC_ID_MCP, MCP_SYS_RSTPLL, &msr_value); + post_div3 = (msr_value.low & MCP_DOTPOSTDIV3) ? 1 : 0; + pre_mult2 = (msr_value.low & MCP_DOTPREMULT2) ? 1 : 0; + + /* SEARCH FOR A MATCH */ + + for (index = 0; index < NUM_RCDF_FREQUENCIES; index++) + { + if ((RCDF_PLLtable[index].pll_value & mask) == value && + post_div3 == RCDF_PLLtable[index].post_div3 && + pre_mult2 == RCDF_PLLtable[index].pre_mul2) + return(RCDF_PLLtable[index].frequency); + } + return(0); +} + +/*************************************************************/ +/* READ ROUTINES | INCLUDED FOR DIAGNOSTIC PURPOSES ONLY */ +/*************************************************************/ + +#if GFX_READ_ROUTINES + +/*--------------------------------------------------------------------------- + * gfx_get_sync_polarities + * + * This routine returns the polarities of the sync pulses: + * Bit 0: Set if negative horizontal polarity. + * Bit 1: Set if negative vertical polarity. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_get_sync_polarities(void) +#else +int gfx_get_sync_polarities(void) +#endif +{ + int polarities = 0; + if (READ_VID32(RCDF_DISPLAY_CONFIG) & RCDF_DCFG_CRT_HSYNC_POL) polarities |= 1; + if (READ_VID32(RCDF_DISPLAY_CONFIG) & RCDF_DCFG_CRT_VSYNC_POL) polarities |= 2; + return(polarities); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_palette_entry + * + * This routine returns a single palette entry. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_get_video_palette_entry(unsigned long index, unsigned long *palette) +#else +int gfx_get_video_palette_entry(unsigned long index, unsigned long *palette) +#endif +{ + if (index > 0xFF) + return GFX_STATUS_BAD_PARAMETER; + + /* READ A SINGLE ENTRY */ + + WRITE_VID32 (RCDF_PALETTE_ADDRESS, index); + *palette = READ_VID32 (RCDF_PALETTE_DATA); + + return (GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_enable + * + * This routine returns the value "one" if video overlay is currently enabled, + * otherwise it returns the value "zero". + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_get_video_enable(void) +#else +int gfx_get_video_enable(void) +#endif +{ + if (READ_VID32(RCDF_VIDEO_CONFIG) & RCDF_VCFG_VID_EN) return(1); + return(0); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_format + * + * This routine returns the current video overlay format. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_get_video_format(void) +#else +int gfx_get_video_format(void) +#endif +{ + unsigned long ctrl, vcfg; + + ctrl = READ_VID32(RCDF_VID_ALPHA_CONTROL); + vcfg = READ_VID32(RCDF_VIDEO_CONFIG); + + if (ctrl & RCDF_VIDEO_INPUT_IS_RGB) + { + switch (vcfg & RCDF_VCFG_VID_INP_FORMAT) + { + case RCDF_VCFG_UYVY_FORMAT: return VIDEO_FORMAT_RGB; + case RCDF_VCFG_Y2YU_FORMAT: return VIDEO_FORMAT_P2M_P2L_P1M_P1L; + case RCDF_VCFG_YUYV_FORMAT: return VIDEO_FORMAT_P1M_P1L_P2M_P2L; + case RCDF_VCFG_YVYU_FORMAT: return VIDEO_FORMAT_P1M_P2L_P2M_P1L; + } + } + + if (vcfg & RCDF_VCFG_4_2_0_MODE) + { + switch (vcfg & RCDF_VCFG_VID_INP_FORMAT) + { + case RCDF_VCFG_UYVY_FORMAT: return VIDEO_FORMAT_Y0Y1Y2Y3; + case RCDF_VCFG_Y2YU_FORMAT: return VIDEO_FORMAT_Y3Y2Y1Y0; + case RCDF_VCFG_YUYV_FORMAT: return VIDEO_FORMAT_Y1Y0Y3Y2; + case RCDF_VCFG_YVYU_FORMAT: return VIDEO_FORMAT_Y1Y2Y3Y0; + } + } + else + { + switch (vcfg & RCDF_VCFG_VID_INP_FORMAT) + { + case RCDF_VCFG_UYVY_FORMAT: return VIDEO_FORMAT_UYVY; + case RCDF_VCFG_Y2YU_FORMAT: return VIDEO_FORMAT_Y2YU; + case RCDF_VCFG_YUYV_FORMAT: return VIDEO_FORMAT_YUYV; + case RCDF_VCFG_YVYU_FORMAT: return VIDEO_FORMAT_YVYU; + } + } + return (GFX_STATUS_ERROR); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_src_size + * + * This routine returns the size of the source video overlay buffer. The + * return value is (height << 16) | width. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_get_video_src_size(void) +#else +unsigned long gfx_get_video_src_size(void) +#endif +{ + unsigned long width, height, scale, delta; + int down_enable; + + /* DETERMINE SOURCE WIDTH FROM THE DISPLAY FILTER VIDEO LINE SIZE */ + + width = (READ_VID32(RCDF_VIDEO_CONFIG) >> 7) & 0x000001FE; + if (READ_VID32(RCDF_VIDEO_CONFIG) & RCDF_VCFG_LINE_SIZE_UPPER) + width += 512l; + + /* DETERMINE SOURCE HEIGHT FROM THE DISPLAY FILTER HEIGHT AND SCALE VALUES */ + /* There is no true "source buffer size" in Redcloud. Instead, the VG module */ + /* provides video data as needed on a per-line basis. The source buffer size */ + /* is always assumed to equal the amount of required video data. The returned */ + /* height is equal to the height of the required video buffer data (before all */ + /* scaling.) */ + + scale = (READ_VID32 (RCDF_VIDEO_SCALE) >> 16) & 0x3FFF; + height = ((READ_VID32 (RCDF_VIDEO_Y_POS) >> 16) & 0x7FF) - + (READ_VID32 (RCDF_VIDEO_Y_POS) & 0x7FF); + delta = gfx_get_video_downscale_delta(); + down_enable = gfx_get_video_vertical_downscale_enable(); + + /* REVERSE UPSCALING */ + + if (height) + height = ((scale * (height - 1l)) / 0x2000l) + 2l; + + /* REVERSE DOWNSCALING */ + /* Original lines = height * (0x3FFF + delta) / 0x3FFF */ + /* As this may cause rounding errors, we add 1 to the */ + /* returned source size. The return value of this */ + /* function could thus be off by 1. */ + + if (down_enable && height) + height = ((height * (0x3FFFl + delta)) / 0x3FFFl) + 1; + + return((height << 16) | width); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_line_size + * + * This routine returns the line size of the source video overlay buffer, in + * pixels. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_get_video_line_size(void) +#else +unsigned long gfx_get_video_line_size(void) +#endif +{ + unsigned long width = 0; + + /* DETERMINE SOURCE WIDTH FROM THE RCDF VIDEO LINE SIZE */ + + width = (READ_VID32(RCDF_VIDEO_CONFIG) >> 7) & 0x000001FE; + if (READ_VID32(RCDF_VIDEO_CONFIG) & RCDF_VCFG_LINE_SIZE_UPPER) + width += 512l; + return(width); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_xclip + * + * This routine returns the number of bytes clipped on the left side of a + * video overlay line (skipped at beginning). + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_get_video_xclip(void) +#else +unsigned long gfx_get_video_xclip(void) +#endif +{ + unsigned long clip = 0; + + /* DETERMINE SOURCE WIDTH FROM THE RCDF VIDEO LINE SIZE */ + + clip = (READ_VID32(RCDF_VIDEO_CONFIG) >> 14) & 0x000007FC; + return(clip); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_offset + * + * This routine returns the current offset for the video overlay buffer. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_get_video_offset(void) +#else +unsigned long gfx_get_video_offset(void) +#endif +{ + return(gfx_get_display_video_offset()); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_yuv_offsets + * + * This routine returns the current offsets for the video overlay buffer when in 4:2:0. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void redcloud_get_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset) +#else +void gfx_get_video_yuv_offsets(unsigned long *yoffset, unsigned long *uoffset, + unsigned long *voffset) +#endif +{ + gfx_get_display_video_yuv_offsets(yoffset, uoffset, voffset); +} + +/*----------------------------------------------------------------------------- + * gfx_get_video_yuv_pitch + * + * This routine returns the current pitch values for the video overlay buffer. + *----------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void redcloud_get_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch) +#else +void gfx_get_video_yuv_pitch(unsigned long *ypitch, unsigned long *uvpitch) +#endif +{ + gfx_get_display_video_yuv_pitch(ypitch, uvpitch); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_scale + * + * This routine returns the scale factor for the video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_get_video_scale(void) +#else +unsigned long gfx_get_video_scale(void) +#endif +{ + return(READ_VID32(RCDF_VIDEO_SCALE)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_downscale_delta + * + * This routine returns the vertical downscale factor for the video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_get_video_downscale_delta(void) +#else +unsigned long gfx_get_video_downscale_delta(void) +#endif +{ + /* USE PRIVATE ROUTINE TO ABSTRACT THE DIPSLAY CONTROLLER */ + + return (gfx_get_display_video_downscale_delta()); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_vertical_downscale_enable + * + * This routine returns the vertical downscale enable for the video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_get_video_vertical_downscale_enable(void) +#else +int gfx_get_video_vertical_downscale_enable(void) +#endif +{ + /* USE PRIVATE ROUTINE TO ABSTRACT THE DIPSLAY CONTROLLER */ + + return (gfx_get_display_video_downscale_enable ()); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_downscale_config + * + * This routine returns the current type and value of video downscaling. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_get_video_downscale_config(unsigned short *type, unsigned short *m) +#else +int gfx_get_video_downscale_config(unsigned short *type, unsigned short *m) +#endif +{ + unsigned long downscale; + + downscale = READ_VID32(RCDF_VIDEO_DOWNSCALER_CONTROL); + *m = (unsigned short)((downscale & RCDF_VIDEO_DOWNSCALE_FACTOR_MASK) >> RCDF_VIDEO_DOWNSCALE_FACTOR_POS) + 1; + + switch(downscale & RCDF_VIDEO_DOWNSCALE_TYPE_MASK) + { + case RCDF_VIDEO_DOWNSCALE_TYPE_A: + *type = VIDEO_DOWNSCALE_KEEP_1_OF; + break; + case RCDF_VIDEO_DOWNSCALE_TYPE_B: + *type = VIDEO_DOWNSCALE_DROP_1_OF; + break; + default: + return GFX_STATUS_ERROR; + break; + } + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_downscale_coefficients + * + * This routine returns the current video downscaling coefficients. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void redcloud_get_video_downscale_coefficients(unsigned short *coef1, unsigned short *coef2, + unsigned short *coef3, unsigned short *coef4) +#else +void gfx_get_video_downscale_coefficients(unsigned short *coef1, unsigned short *coef2, + unsigned short *coef3, unsigned short *coef4) +#endif +{ + unsigned long coef; + + coef = READ_VID32(RCDF_VIDEO_DOWNSCALER_COEFFICIENTS); + *coef1 = (unsigned short)((coef >> RCDF_VIDEO_DOWNSCALER_COEF1_POS) & RCDF_VIDEO_DOWNSCALER_COEF_MASK); + *coef2 = (unsigned short)((coef >> RCDF_VIDEO_DOWNSCALER_COEF2_POS) & RCDF_VIDEO_DOWNSCALER_COEF_MASK); + *coef3 = (unsigned short)((coef >> RCDF_VIDEO_DOWNSCALER_COEF3_POS) & RCDF_VIDEO_DOWNSCALER_COEF_MASK); + *coef4 = (unsigned short)((coef >> RCDF_VIDEO_DOWNSCALER_COEF4_POS) & RCDF_VIDEO_DOWNSCALER_COEF_MASK); + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_downscale_enable + * + * This routine returns 1 if video downscaling is currently enabled, + * or 0 if it is currently disabled. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void redcloud_get_video_downscale_enable(int *enable) +#else +void gfx_get_video_downscale_enable(int *enable) +#endif +{ + if (READ_VID32(RCDF_VIDEO_DOWNSCALER_CONTROL) & RCDF_VIDEO_DOWNSCALE_ENABLE) + *enable = 1; + else + *enable = 0; + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_dst_size + * + * This routine returns the size of the displayed video overlay window. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_get_video_dst_size(void) +#else +unsigned long gfx_get_video_dst_size(void) +#endif +{ + unsigned long xsize, ysize; + + xsize = READ_VID32(RCDF_VIDEO_X_POS); + xsize = ((xsize >> 16) & 0x7FF) - (xsize & 0x7FF); + ysize = READ_VID32(RCDF_VIDEO_Y_POS); + ysize = ((ysize >> 16) & 0x7FF) - (ysize & 0x7FF); + return((ysize << 16) | xsize); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_position + * + * This routine returns the position of the video overlay window. The + * return value is (ypos << 16) | xpos. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_get_video_position(void) +#else +unsigned long gfx_get_video_position(void) +#endif +{ + unsigned long hadjust, vadjust; + unsigned long xpos, ypos; + + /* READ HARDWARE POSITION */ + + xpos = READ_VID32(RCDF_VIDEO_X_POS) & 0x000007FF; + ypos = READ_VID32(RCDF_VIDEO_Y_POS) & 0x000007FF; + + /* GET ADJUSTMENT VALUES */ + /* Use routines to abstract version of display controller. */ + + hadjust = (unsigned long)gfx_get_htotal() - (unsigned long)gfx_get_hsync_end() - 14l; + vadjust = (unsigned long)gfx_get_vtotal() - (unsigned long)gfx_get_vsync_end() + 1l; + xpos -= hadjust; + ypos -= vadjust; + return((ypos << 16) | (xpos & 0x0000FFFF)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key + * + * This routine returns the current video color key value. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_get_video_color_key(void) +#else +unsigned long gfx_get_video_color_key(void) +#endif +{ + return(READ_VID32(RCDF_VIDEO_COLOR_KEY)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key_mask + * + * This routine returns the current video color mask value. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_get_video_color_key_mask(void) +#else +unsigned long gfx_get_video_color_key_mask(void) +#endif +{ + return(READ_VID32(RCDF_VIDEO_COLOR_MASK)); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_color_key_src + * + * This routine returns 0 for video data compare, 1 for graphics data. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_get_video_color_key_src(void) +#else +int gfx_get_video_color_key_src(void) +#endif +{ + if (READ_VID32(RCDF_DISPLAY_CONFIG) & RCDF_DCFG_VG_CK) return(0); + return(1); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_filter + * + * This routine returns if the filters are currently enabled. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_get_video_filter(void) +#else +int gfx_get_video_filter(void) +#endif +{ + int retval = 0; + if (READ_VID32(RCDF_VIDEO_CONFIG) & RCDF_VCFG_X_FILTER_EN) + retval |= 1; + if (READ_VID32(RCDF_VIDEO_CONFIG) & RCDF_VCFG_Y_FILTER_EN) + retval |= 2; + return(retval); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_request + * + * This routine returns the horizontal (pixel) and vertical (lines) video + * request values. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_get_video_request(short *x, short *y) +#else +int gfx_get_video_request(short *x, short *y) +#endif +{ + unsigned long request = 0; + request = (READ_VID32(RCDF_VIDEO_REQUEST)); + *x = (short)((request >> RCDF_VIDEO_X_REQUEST_POS) & RCDF_VIDEO_REQUEST_MASK); + *y = (short)((request >> RCDF_VIDEO_Y_REQUEST_POS) & RCDF_VIDEO_REQUEST_MASK); + + *x -= gfx_get_htotal() - gfx_get_hsync_end() - 2; + *y -= gfx_get_vtotal() - gfx_get_vsync_end() + 1; + + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_get_video_cursor() + * + * This routine configures the video hardware cursor. + * If the "mask"ed bits in the graphics pixel match "key", then either "color1" + * or "color2" will be used for this pixel, according to the value of the bit + * in offset "select_color2". + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +int redcloud_get_video_cursor(unsigned long *key, unsigned long *mask, unsigned short *select_color2, + unsigned long *color1, unsigned short *color2) +#else +int gfx_get_video_cursor(unsigned long *key, unsigned long *mask, unsigned short *select_color2, + unsigned long *color1, unsigned short *color2) +#endif +{ + *select_color2 = (unsigned short)(READ_VID32(RCDF_CURSOR_COLOR_KEY) >> RCDF_CURSOR_COLOR_KEY_OFFSET_POS); + *key = READ_VID32(RCDF_CURSOR_COLOR_KEY) & RCDF_COLOR_MASK; + *mask = READ_VID32(RCDF_CURSOR_COLOR_MASK) & RCDF_COLOR_MASK; + *color1 = READ_VID32(RCDF_CURSOR_COLOR_1) & RCDF_COLOR_MASK; + *color2 = (unsigned short)(READ_VID32(RCDF_CURSOR_COLOR_2) & RCDF_COLOR_MASK); + return(0); +} + +/*--------------------------------------------------------------------------- + * gfx_read_crc + * + * This routine returns the hardware CRC value, which is used for automated + * testing. The value is like a checksum, but will change if pixels move + * locations. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_read_crc(void) +#else +unsigned long gfx_read_crc(void) +#endif +{ + Q_WORD msr_value; + unsigned long crc = 0xFFFFFFFF; + + /* DISABLE 32-BIT CRCS */ + /* For GX1.x, this is a reserved bit, and is assumed to be a benign access */ + + gfx_msr_read (RC_ID_DF, RCDF_MBD_MSR_DIAG_DF, &msr_value); + msr_value.low &= ~RCDF_DIAG_32BIT_CRC; + gfx_msr_write (RC_ID_DF, RCDF_MBD_MSR_DIAG_DF, &msr_value); + + if (gfx_test_timing_active()) + { + /* WAIT UNTIL ACTIVE DISPLAY */ + + while(!gfx_test_vertical_active()); + + /* RESET CRC DURING ACTIVE DISPLAY */ + + WRITE_VID32(RCDF_VID_CRC, 0); + WRITE_VID32(RCDF_VID_CRC, 1); + + /* WAIT UNTIL NOT ACTIVE, THEN ACTIVE, NOT ACTIVE, THEN ACTIVE */ + + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + crc = READ_VID32(RCDF_VID_CRC) >> 8; + } + return(crc); +} + +/*--------------------------------------------------------------------------- + * gfx_read_crc32 + * + * This routine returns the 32-bit hardware CRC value, which is used for automated + * testing. The value is like a checksum, but will change if pixels move + * locations. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_read_crc32(void) +#else +unsigned long gfx_read_crc32(void) +#endif +{ + Q_WORD msr_value; + unsigned long crc = 0xFFFFFFFF; + + /* ENABLE 32-BIT CRCS */ + /* For GX1.x, this is a reserved bit, and is assumed to be a benign access */ + + gfx_msr_read (RC_ID_DF, RCDF_MBD_MSR_DIAG_DF, &msr_value); + msr_value.low |= RCDF_DIAG_32BIT_CRC; + gfx_msr_write (RC_ID_DF, RCDF_MBD_MSR_DIAG_DF, &msr_value); + + if (gfx_test_timing_active()) + { + /* WAIT UNTIL ACTIVE DISPLAY */ + + while(!gfx_test_vertical_active()); + + /* RESET CRC DURING ACTIVE DISPLAY */ + + WRITE_VID32(RCDF_VID_CRC, 0); + WRITE_VID32(RCDF_VID_CRC, 1); + + /* WAIT UNTIL NOT ACTIVE, THEN ACTIVE, NOT ACTIVE, THEN ACTIVE */ + + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + crc = READ_VID32(RCDF_VID_CRC32); + } + return(crc); +} + +/*--------------------------------------------------------------------------- + * gfx_read_window_crc + * + * This routine returns the hardware CRC value for a subsection of the display. + * This value is used to debug whole-screen CRC failures. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +unsigned long redcloud_read_window_crc(int source, unsigned short x, unsigned short y, + unsigned short width, unsigned short height, int crc32) +#else +unsigned long gfx_read_window_crc(int source, unsigned short x, unsigned short y, + unsigned short width, unsigned short height, int crc32) +#endif +{ + Q_WORD msr_value; + unsigned long xpos, ypos, crc = 0; + unsigned long old_fmt = 0; + unsigned int vsync_active_base, vsync_inactive_base, hsync_active_base; + unsigned int vsync_active_shift, vsync_inactive_shift, hsync_active_shift; + unsigned int vsync_bit, hsync_bit, sync_polarities = 0; + + /* CONFIGURE DISPLAY FILTER TO LOAD DATA ONTO LOWER 32-BITS */ + + msr_value.high = 0; + msr_value.low = (source == CRC_SOURCE_GFX_DATA) ? (RCDF_MBD_DIAG_EN0 | 0x0000000F) : + (RCDF_MBD_DIAG_EN0 | 0x0000000B); + gfx_msr_write (RC_ID_DF, MBD_MSR_DIAG, &msr_value); + + /* CONFIGURE DISPLAY FILTER FOR APPROPRIATE OUTPUT */ + + if (source != CRC_SOURCE_GFX_DATA) + { + gfx_msr_read (RC_ID_DF, MBD_MSR_CONFIG, &msr_value); + old_fmt = msr_value.low; + msr_value.low &= ~(RCDF_CONFIG_FMT_MASK); + msr_value.low |= ((source == CRC_SOURCE_FP_DATA) ? RCDF_CONFIG_FMT_FP : + RCDF_CONFIG_FMT_CRT); + gfx_msr_write (RC_ID_DF, MBD_MSR_CONFIG, &msr_value); + } + + /* CONFIGURE MCP TO LOAD REGB DATA ONTO UPPER 32-BITS */ + + msr_value.low = MCP_MBD_DIAG_EN1 | 0x00050000; + gfx_msr_write (RC_ID_MCP, MBD_MSR_DIAG, &msr_value); + + /* ENABLE HW CLOCK GATING AND SET MCP CLOCK TO DOT CLOCK */ + + msr_value.low = 1l; + gfx_msr_write (RC_ID_MCP, MBD_MSR_PM, &msr_value); + msr_value.low = 0; + gfx_msr_write (RC_ID_MCP, MCP_DBGCLKCTL, &msr_value); + msr_value.low = 3; + gfx_msr_write (RC_ID_MCP, MCP_DBGCLKCTL, &msr_value); + + /* DISABLE MCP ACTIONS */ + + msr_value.high = 0x00000000; + msr_value.low = 0x00000000; + gfx_msr_write (RC_ID_MCP, MCP_DIAGCTL, &msr_value); + + /* SET APPROPRIATE BASE ADDRESS */ + /* M-Sets use normal diag bits, while N-Sets use inverted diag bits */ + /* We thus use the M-sets when polling for a high signal and the N */ + /* sets when polling for a low signal. */ + + if (source != CRC_SOURCE_GFX_DATA) + { + sync_polarities = gfx_get_sync_polarities (); + vsync_bit = 29; + hsync_bit = 30; + } + else + { + vsync_bit = 25; + hsync_bit = 26; + } + + if (sync_polarities & 1) + { + hsync_active_base = MCP_SETM0CTL; + hsync_active_shift = 2; + } + else + { + hsync_active_base = MCP_SETN0CTL; + hsync_active_shift = 1; + } + if (sync_polarities & 2) + { + vsync_active_base = MCP_SETM0CTL; + vsync_inactive_base = MCP_SETN0CTL; + vsync_active_shift = 2; + vsync_inactive_shift = 1; + } + else + { + vsync_active_base = MCP_SETN0CTL; + vsync_inactive_base = MCP_SETM0CTL; + vsync_active_shift = 1; + vsync_inactive_shift = 2; + } + + /* SET STATE TRANSITIONS */ + + /* STATE 0-1 TRANSITION (SET 0) */ + /* XState = 00 and VSync Inactive */ + /* Note: DF VSync = Diag Bus Bit 29 */ + /* VG VSync = Diag Bus Bit 25 */ + + msr_value.low = 0x000000A0; + msr_value.high = 0x00008000 | ((unsigned long)vsync_bit << 16) | + ((unsigned long)vsync_bit << 21) | + ((unsigned long)vsync_bit << 26); + gfx_msr_write (RC_ID_MCP, vsync_inactive_base, &msr_value); + + /* STATE 1-2 TRANSITION (SET 4) */ + /* XState = 01 and VSync Active */ + + msr_value.low = 0x000000C0; + gfx_msr_write (RC_ID_MCP, vsync_active_base + 4, &msr_value); + + /* STATE 2-3 TRANSITION (SET 1) */ + /* XState = 10 and VSync Inactive */ + + msr_value.low = 0x00000120; + gfx_msr_write (RC_ID_MCP, vsync_inactive_base + 1, &msr_value); + + /* HORIZONTAL COUNTER (SET 5) */ + /* XState = 10 and HSync Active */ + /* Notes: DF HSync = Diag Bus Bit 30 */ + /* VG HSync = Diag Bus Bit 26 */ + + msr_value.high = 0x00008000 | ((unsigned long)hsync_bit << 16) | + ((unsigned long)hsync_bit << 21) | + ((unsigned long)hsync_bit << 26); + msr_value.low = 0x00000120; + gfx_msr_write (RC_ID_MCP, hsync_active_base + 5, &msr_value); + + /* HORIZONTAL COUNTER RESET (SET 4) */ + /* XState = 10 and H. Counter = limit */ + /* Note: H. Counter is lower 16-bits of */ + /* RegB. */ + + msr_value.high = 0x00000000; + msr_value.low = 0x00000128; + gfx_msr_write (RC_ID_MCP, vsync_inactive_base + 4, &msr_value); + + /* CRC TRIGGER (SET 0) */ + /* Cmp0 <= xpos < Cmp1 */ + /* Cmp2 <= ypos < Cmp2 */ + + msr_value.high = 0x00000000; + msr_value.low = 0x10C20120; + gfx_msr_write (RC_ID_MCP, vsync_active_base, &msr_value); + + /* SET COMPARATOR VALUES */ + /* Note: The VG data outputs from the DF are delayed by one pixel clock. */ + /* In this mode, we thus add one to horizontal comparator limits. */ + + /* COMPARATOR 0 */ + /* Lower limit = xpos + (h_blank_pixels - 1) - 3 */ + /* Notes: */ + /* 1. 3 is the pipeline delay for MCP register */ + /* data to access the diag bus */ + /* 2. h_blank_pixels = HTOTAL - HSYNC_END */ + + xpos = (unsigned long)x + ((unsigned long)gfx_get_htotal() - + (unsigned long)gfx_get_hsync_end() - 1l) - 3l; + if (source == CRC_SOURCE_GFX_DATA) xpos++; + msr_value.high = 0x00000000; + msr_value.low = xpos; + gfx_msr_write (RC_ID_MCP, MCP_CMPVAL0, &msr_value); + + /* COMPARATOR 1 */ + /* Upper limit = xpos + width + (h_blank_pixels - 1) - 3 */ + + msr_value.low = xpos + (unsigned long)width; + gfx_msr_write (RC_ID_MCP, MCP_CMPVAL0 + 2, &msr_value); + + /* COMPARATOR 2 */ + /* Lower limit = ypos + v_blank_pixels */ + /* Notes: */ + /* 1. v_blank_pixels = VTOTAL - VSYNC_END */ + + ypos = (unsigned long)y + (unsigned long)gfx_get_vtotal() - (unsigned long)gfx_get_vsync_end(); + msr_value.low = ypos << 16; + gfx_msr_write (RC_ID_MCP, MCP_CMPVAL0 + 4, &msr_value); + + /* COMPARATOR 3 */ + /* Upper limit = ypos + height + v_blank_pixels */ + + msr_value.low = (ypos + (unsigned long)height) << 16; + gfx_msr_write (RC_ID_MCP, MCP_CMPVAL0 + 6, &msr_value); + + /* SET COMPARATOR MASKS */ + + /* COMPARATORS 0 AND 1 REFER TO LOWER 16 BITS OF REGB */ + + msr_value.high = 0x00000000; + msr_value.low = 0x0000FFFF; + gfx_msr_write (RC_ID_MCP, MCP_CMPMASK0, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_CMPMASK0 + 2, &msr_value); + + /* COMPARATORS 2 AND 3 REFER TO UPPER 16 BITS OF REGB */ + + msr_value.low = 0xFFFF0000; + gfx_msr_write (RC_ID_MCP, MCP_CMPMASK0 + 4, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_CMPMASK0 + 6, &msr_value); + + /* SET REGA MASK TO CRC ONLY 24 BITS OF DATA */ + + msr_value.high = 0x00000000; + msr_value.low = 0x00FFFFFF; + gfx_msr_write (RC_ID_MCP, MCP_REGAMASK, &msr_value); + + /* SET REGB VALUE */ + /* Lower 16 bits use HTOTAL - SYNC TIME - 1 to set the counter rollover limit. */ + /* Upper 16 bits use 0xFFFF to remove auto-clear behavior. */ + + msr_value.high = 0x00000000; + msr_value.low = 0xFFFF0000 | + ((gfx_get_htotal() - (gfx_get_hsync_end() - gfx_get_hsync_start()) - 1) & 0xFFFF); + gfx_msr_write (RC_ID_MCP, MCP_REGBVAL, &msr_value); + + /* PROGRAM ACTIONS */ + + /* GOTO STATE 01 */ + + msr_value.high = 0x00000000; + msr_value.low = 0x00000008 | (1l << vsync_inactive_shift); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 14, &msr_value); + + /* GOTO STATE 10 */ + + msr_value.low = 0x00080000 | (1l << (vsync_active_shift + 16)); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 15, &msr_value); + + /* GOTO STATE 11 */ + + msr_value.low = 0x00000080 | (1l << (vsync_inactive_shift + 4)); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 16, &msr_value); + + /* CLEAR REGB (COUNTERS) */ + /* RegB is cleared upon transitioning to state 10 */ + /* RegA is not cleared as the initial value must be 0x00000001 */ + + msr_value.low = 0x00080000 | (1l << (vsync_active_shift + 16)); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0, &msr_value); + + /* CRC INTO REGA */ + /* INCREMENT H. COUNTER */ + /* cmp0 <= xpos < cmp1 */ + /* cmp2 <= ypos < cmp3 */ + /* XState = 10 */ + + msr_value.low = 0x00000008 | (1l << vsync_active_shift) | + 0x00800000 | (1l << (hsync_active_shift + 20)); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 1, &msr_value); + + /* INCREMENT V. COUNTER */ + /* V. Counter is incremented when the H. Counter */ + /* rolls over. */ + + msr_value.low = 0x00080000 | (1l << (vsync_inactive_shift + 16)); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 2, &msr_value); + + /* CLEAR ALL OTHER ACTIONS */ + /* This prevents side-effects from previous accesses to the MCP */ + /* debug logic. */ + msr_value.low = 0x00000000; + msr_value.high = 0x00000000; + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 3, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 4, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 5, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 6, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 7, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 8, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 9, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 10, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 11, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 12, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 13, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 17, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 18, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 19, &msr_value); + gfx_msr_write (RC_ID_MCP, MCP_ACTION0 + 20, &msr_value); + + /* SET REGA CRC VALUE TO 1 OR 0 */ + + if (!crc32) + msr_value.low = 0x00000001; + gfx_msr_write (RC_ID_MCP, MCP_REGA, &msr_value); + + /* SET XSTATE TO 0 */ + + msr_value.low = 0; + msr_value.high = 0; + gfx_msr_write (RC_ID_MCP, MCP_XSTATE, &msr_value); + + /* CONFIGURE DIAG CONTROL */ + /* Set all four comparators to watch the upper diag bus. */ + /* Set REGA action1 to legacy CRC or 32-bit CRC. */ + /* Set REGB action1 to increment lower 16 bits and clear at limit. */ + /* Set REGB action2 to increment upper 16 bits. */ + /* Enable all actions. */ + + if (crc32) + msr_value.low = 0x9A820055; + else + msr_value.low = 0x9A840055; + msr_value.high = 0x00000000; + gfx_msr_write (RC_ID_MCP, MCP_DIAGCTL, &msr_value); + + /* DELAY TWO FRAMES */ + + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + while(gfx_test_vertical_active()); + while(!gfx_test_vertical_active()); + + /* VERIFY THAT XSTATE = 11 */ + + gfx_msr_read (RC_ID_MCP, MCP_XSTATE, &msr_value); + if ((msr_value.low & 3) == 3) + { + gfx_msr_read (RC_ID_MCP, MCP_REGA, &msr_value); + + crc = msr_value.low; + if (!crc32) + crc &= 0xFFFFFF; + } + + /* DISABLE MCP AND DF DIAG BUS OUTPUTS */ + + msr_value.low = 0x00000000; + msr_value.high = 0x00000000; + gfx_msr_write (RC_ID_DF, MBD_MSR_DIAG, &msr_value); + gfx_msr_write (RC_ID_MCP, MBD_MSR_DIAG, &msr_value); + + /* DISABLE MCP ACTIONS */ + + msr_value.high = 0x00000000; + msr_value.low = 0x00000000; + gfx_msr_write (RC_ID_MCP, MCP_DIAGCTL, &msr_value); + + /* RESTORE PREVIOUS OUTPUT FORMAT */ + + if (source != CRC_SOURCE_GFX_DATA) + { + gfx_msr_read (RC_ID_DF, MBD_MSR_CONFIG, &msr_value); + msr_value.low = old_fmt; + gfx_msr_write (RC_ID_DF, MBD_MSR_CONFIG, &msr_value); + } + return crc; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_enable + * + * This routine returns 1 if the selected alpha window is currently + * enabled, or 0 if it is currently disabled. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void redcloud_get_alpha_enable(int *enable) +#else +void gfx_get_alpha_enable(int *enable) +#endif +{ + unsigned long value = 0; + *enable = 0; + if (gfx_alpha_select <= 2) + { + value = READ_VID32(RCDF_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 5)); + if (value & RCDF_ACTRL_WIN_ENABLE) *enable = 1; + } + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_size + * + * This routine returns the size of the currently selected alpha region. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void redcloud_get_alpha_size(unsigned short *x, unsigned short *y, + unsigned short *width, unsigned short *height) +#else +void gfx_get_alpha_size(unsigned short *x, unsigned short *y, + unsigned short *width, unsigned short *height) +#endif +{ + unsigned long value = 0; + *x = 0; + *y = 0; + *width = 0; + *height = 0; + if (gfx_alpha_select <= 2) + { + value = READ_VID32(RCDF_ALPHA_XPOS_1 + ((unsigned long)gfx_alpha_select << 5)); + *x = (unsigned short) (value & 0x000007FF); + *width = (unsigned short) ((value >> 16) & 0x000007FF) - *x; + value = READ_VID32(RCDF_ALPHA_YPOS_1 + ((unsigned long)gfx_alpha_select << 5)); + *y = (unsigned short) (value & 0x000007FF); + *height = (unsigned short) ((value >> 16) & 0x000007FF) - *y; + } + *x -= gfx_get_htotal() - gfx_get_hsync_end() - 2; + *y -= gfx_get_vtotal() - gfx_get_vsync_end() + 1; + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_value + * + * This routine returns the alpha value and increment/decrement value of + * the currently selected alpha region. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void redcloud_get_alpha_value(unsigned char *alpha, char *delta) +#else +void gfx_get_alpha_value(unsigned char *alpha, char *delta) +#endif +{ + unsigned long value = 0; + *alpha = 0; + *delta = 0; + if (gfx_alpha_select <= 2) + { + value = READ_VID32(RCDF_ALPHA_CONTROL_1 + ((unsigned long)gfx_alpha_select << 5)); + *alpha = (unsigned char) (value & 0x00FF); + *delta = (char) ((value >> 8) & 0x00FF); + } + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_priority + * + * This routine returns the priority of the currently selected alpha region. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void redcloud_get_alpha_priority(int *priority) +#else +void gfx_get_alpha_priority(int *priority) +#endif +{ + unsigned long pos = 0, value = 0; + *priority = 0; + if (gfx_alpha_select <= 2) + { + value = READ_VID32(RCDF_VID_ALPHA_CONTROL); + pos = 16 + (gfx_alpha_select << 1); + *priority = (int) ((value >> pos) & 3); + } + return; +} + +/*--------------------------------------------------------------------------- + * gfx_get_alpha_color + * + * This routine returns the color register value for the currently selected + * alpha region. Bit 24 is set if the color register is enabled. + *--------------------------------------------------------------------------- + */ +#if GFX_VIDEO_DYNAMIC +void redcloud_get_alpha_color(unsigned long *color) +#else +void gfx_get_alpha_color(unsigned long *color) +#endif +{ + *color = 0; + if (gfx_alpha_select <= 2) + { + *color = READ_VID32(RCDF_ALPHA_COLOR_1 + ((unsigned long)gfx_alpha_select << 5)); + } + return; +} + +#endif /* GFX_READ_ROUTINES */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_dga.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_dga.c 2005-07-13 13:16:49.000000000 -0600 @@ -0,0 +1,413 @@ +/* + * $Workfile: amd_lx_dga.c $ + * $Revision: #3 $ + * $Author: raymondd $ + * + * File contents: DGA(Direct Acess Graphics mode) is feature of + * XFree86 that allows the program to access directly to video + * memory on the graphics card.DGA supports the double + * flickering.This file has the functions to support the DGA + * modes. + * + * Project: Geode Xfree Frame buffer device driver. + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86_ansic.h" +#include "xf86Pci.h" +#include "xf86PciInfo.h" +#include "xaa.h" +#include "xaalocal.h" +#include "amd.h" +#include "dgaproc.h" + +/* forward declarations */ +Bool LXDGAInit(ScreenPtr pScrn); +static Bool LX_OpenFramebuffer(ScrnInfoPtr, char **, unsigned char **, + int *, int *, int *); +static void LX_CloseFramebuffer(ScrnInfoPtr pScrni); +static Bool LX_SetMode(ScrnInfoPtr, DGAModePtr); +static int LX_GetViewport(ScrnInfoPtr); +static void LX_SetViewport(ScrnInfoPtr, int, int, int); +static void LX_FillRect(ScrnInfoPtr, int, int, int, int, unsigned long); +static void LX_BlitRect(ScrnInfoPtr, int, int, int, int, int, int); + +extern void LXAdjustFrame(int, int, int, int); +extern Bool LXSwitchMode(int, DisplayModePtr, int); +extern void LXAccelSync(ScrnInfoPtr pScrni); + +static DGAFunctionRec LXDGAFuncs = { + LX_OpenFramebuffer, + LX_CloseFramebuffer, + LX_SetMode, + LX_SetViewport, + LX_GetViewport, + LXAccelSync, + LX_FillRect, + LX_BlitRect, + NULL +}; + +/*---------------------------------------------------------------------------- + * LXDGAInit. + * + * Description :This function is used to intiallize the DGA modes and sets the + viewport based on the screen mode. + * Parameters. + * pScreeen :Pointer to screen info structure. + * + * Returns :TRUE on success and FALSE on failure. + * + * Comments :This function prepares the DGA mode settings for + * other func reference. + * +*---------------------------------------------------------------------------- +*/ +Bool +LXDGAInit(ScreenPtr pScrn) +{ + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + GeodePtr pGeode = GEODEPTR(pScrni); + DGAModePtr modes = NULL, newmodes = NULL, currentMode; + DisplayModePtr pMode, firstMode; + int Bpp = pScrni->bitsPerPixel >> 3; + int num = 0; + Bool oneMore; + + pMode = firstMode = pScrni->modes; + DEBUGMSG(0, (0, X_NONE, "LXDGAInit %d\n", Bpp)); + while (pMode) { + + /* redundant but it can be used in future:if(0). */ + if (0) { /*pScrni->displayWidth != pMode->HDisplay */ + /* memory is allocated for dga to + *setup the viewport and mode parameters + */ + newmodes = xrealloc(modes, (num + 2) * sizeof(DGAModeRec)); + oneMore = TRUE; + } else { + /* one record is allocated here */ + newmodes = xrealloc(modes, (num + 1) * sizeof(DGAModeRec)); + oneMore = FALSE; + } + if (!newmodes) { + xfree(modes); + return FALSE; + } + modes = newmodes; + + SECOND_PASS: /* DGA mode flgas and viewport parametrs are set here. */ + + currentMode = modes + num; + num++; + currentMode->mode = pMode; + currentMode->flags = DGA_CONCURRENT_ACCESS | DGA_PIXMAP_AVAILABLE; + currentMode->flags |= DGA_FILL_RECT | DGA_BLIT_RECT; + if (pMode->Flags & V_DBLSCAN) + currentMode->flags |= DGA_DOUBLESCAN; + if (pMode->Flags & V_INTERLACE) + currentMode->flags |= DGA_INTERLACED; + currentMode->byteOrder = pScrni->imageByteOrder; + currentMode->depth = pScrni->depth; + currentMode->bitsPerPixel = pScrni->bitsPerPixel; + currentMode->red_mask = pScrni->mask.red; + currentMode->green_mask = pScrni->mask.green; + currentMode->blue_mask = pScrni->mask.blue; + currentMode->visualClass = (Bpp == 1) ? PseudoColor : TrueColor; + currentMode->viewportWidth = pMode->HDisplay; + currentMode->viewportHeight = pMode->VDisplay; + currentMode->xViewportStep = 1; + currentMode->yViewportStep = 1; + currentMode->viewportFlags = DGA_FLIP_RETRACE; + currentMode->offset = 0; + currentMode->address = pGeode->FBBase; + if (oneMore) { /* first one is narrow width */ + currentMode->bytesPerScanline = ((pMode->HDisplay * Bpp) + 3) & ~3L; + currentMode->imageWidth = pMode->HDisplay; + currentMode->imageHeight = pMode->VDisplay; + currentMode->pixmapWidth = currentMode->imageWidth; + currentMode->pixmapHeight = currentMode->imageHeight; + currentMode->maxViewportX = currentMode->imageWidth - + currentMode->viewportWidth; + /* this might need to get clamped to some maximum */ + currentMode->maxViewportY = currentMode->imageHeight - + currentMode->viewportHeight; + oneMore = FALSE; + goto SECOND_PASS; + } else { + currentMode->bytesPerScanline = + ((pScrni->displayWidth * Bpp) + 3) & ~3L; + currentMode->imageWidth = pScrni->displayWidth; + currentMode->imageHeight = pMode->VDisplay; + currentMode->pixmapWidth = currentMode->imageWidth; + currentMode->pixmapHeight = currentMode->imageHeight; + currentMode->maxViewportX = currentMode->imageWidth - + currentMode->viewportWidth; + /* this might need to get clamped to some maximum */ + currentMode->maxViewportY = currentMode->imageHeight - + currentMode->viewportHeight; + } + pMode = pMode->next; + if (pMode == firstMode) + break; + } + pGeode->numDGAModes = num; + pGeode->DGAModes = modes; + return DGAInit(pScrn, &LXDGAFuncs, modes, num); +} + +/*---------------------------------------------------------------------------- + * LX_SetMode. + * + * Description :This function is sets into the DGA mode. + *. + * Parameters. + * pScreeen :Pointer to screen info structure. + * pMode :Points to the DGAmode ptr data + * Returns :TRUE on success and FALSE on failure. + * + * Comments :none. + * + * +*---------------------------------------------------------------------------- +*/ +static Bool +LX_SetMode(ScrnInfoPtr pScrni, DGAModePtr pMode) +{ + static int OldDisplayWidth[MAXSCREENS]; + int index = pScrni->pScreen->myNum; + GeodePtr pGeode = GEODEPTR(pScrni); + + DEBUGMSG(0, (0, X_NONE, "LX_SetMode\n")); + + if (!pMode) { + /* restore the original mode + * * put the ScreenParameters back + */ + pScrni->displayWidth = OldDisplayWidth[index]; + DEBUGMSG(0, + (0, X_NONE, "LX_SetMode !pMode %d\n", pScrni->displayWidth)); + LXSwitchMode(index, pScrni->currentMode, 0); + pGeode->DGAactive = FALSE; + } else { + if (!pGeode->DGAactive) { /* save the old parameters */ + OldDisplayWidth[index] = pScrni->displayWidth; + pGeode->DGAactive = TRUE; + DEBUGMSG(0, + (0, X_NONE, "LX_SetMode pMode+ NA %d\n", + pScrni->displayWidth)); + } + pGeode->PrevDisplayOffset = vg_get_display_offset(); + + pScrni->displayWidth = pMode->bytesPerScanline / + (pMode->bitsPerPixel >> 3); + DEBUGMSG(0, + (0, X_NONE, "LX_SetMode pMode+ %d\n", pScrni->displayWidth)); + LXSwitchMode(index, pMode->mode, 0); + } + /* enable/disable Compression */ + if (pGeode->Compression) { + vg_set_compression_enable(!pGeode->DGAactive); + } + + /* enable/disable cursor */ + if (pGeode->HWCursor) { + vg_set_cursor_enable(!pGeode->DGAactive); + } + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LX_GetViewPort. + * + * Description :This function is Gets the viewport window memory. + *. + * Parameters. + * pScrni :Pointer to screen info structure. + * + * Returns :returns the viewport status. + * + * Comments :none. + * + * +*---------------------------------------------------------------------------- +*/ +static int +LX_GetViewport(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + return pGeode->DGAViewportStatus; +} + +/*---------------------------------------------------------------------------- + * LX_SetViewPort. + * + * Description :This function is Gets the viewport window memory. + * + * Parameters. + * pScrni :Pointer to screen info structure. + x :x-cordinate of viewport window + * y :y-codinate of the viewport window. + * flags :indicates the viewport to be flipped or not. + * Returns :returns the viewport status as zero. + * + * Comments :none. + * +*---------------------------------------------------------------------------- +*/ +static void +LX_SetViewport(ScrnInfoPtr pScrni, int x, int y, int flags) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + LXAdjustFrame(pScrni->pScreen->myNum, x, y, flags); + pGeode->DGAViewportStatus = 0; /*LXAdjustFrame loops until finished */ +} + +/*---------------------------------------------------------------------------- + * LX_FillRect. + * + * Description :This function is Gets the viewport window memory. + *. + * Parameters. + * pScrni :Pointer to screen info structure. + * x :x-cordinate of viewport window + * y :y-codinate of the viewport window. + * w :width of the rectangle + * h :height of the rectangle. + * color :color to be filled in rectangle. + * + * Returns :returns the viewport status as zero. + * + * Comments :This function is implemented by solidfill routines.. + * +*---------------------------------------------------------------------------- +*/ +static void +LX_FillRect(ScrnInfoPtr pScrni, int x, int y, + int w, int h, unsigned long color) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + if (pGeode->AccelInfoRec) { + (*pGeode->AccelInfoRec->SetupForSolidFill) (pScrni, color, GXcopy, ~0); + (*pGeode->AccelInfoRec->SubsequentSolidFillRect) (pScrni, x, y, w, h); + SET_SYNC_FLAG(pGeode->AccelInfoRec); + } +} + +/*---------------------------------------------------------------------------- + * LX_BlitRect. + * + * Description :This function implementing Blit and it moves a + * Rectangular block of data from one location to other + * Location. + * + * Parameters. + * pScrni :Pointer to screen info structure. + * srcx :x-cordinate of the src rectangle + * srcy :y-codinate of src rectangle. + * w :width of the rectangle + * h :height of the rectangle. + * dstx :x-cordinate of the dst rectangle. + * dsty :y -coordinates of the dst rectangle. + * Returns :none. + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static void +LX_BlitRect(ScrnInfoPtr pScrni, + int srcx, int srcy, int w, int h, int dstx, int dsty) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + if (pGeode->AccelInfoRec) { + int xdir = ((srcx < dstx) && (srcy == dsty)) ? -1 : 1; + int ydir = (srcy < dsty) ? -1 : 1; + + (*pGeode->AccelInfoRec->SetupForScreenToScreenCopy) + (pScrni, xdir, ydir, GXcopy, ~0, -1); + (*pGeode->AccelInfoRec->SubsequentScreenToScreenCopy) (pScrni, srcx, + srcy, dstx, dsty, + w, h); + SET_SYNC_FLAG(pGeode->AccelInfoRec); + } +} + +/*---------------------------------------------------------------------------- + * LX_OpenFramebuffer. + * + * Description :This function open the framebuffer driver for DGA. + * + * Parameters. + * pScrni :Pointer to screen info structure. + * srcx :x-cordinate of the src rectangle + * srcy :y-codinate of src rectangle. + * w :width of the rectangle + * h :height of the rectangle. + * dstx :x-cordinate of the dst rectangle. + * dsty :y -coordinates of the dst rectangle. + * Returns :none. + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static Bool +LX_OpenFramebuffer(ScrnInfoPtr pScrni, + char **name, unsigned char **mem, + int *size, int *offset, int *flags) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + *name = NULL; /* no special device */ + *mem = (unsigned char *)pGeode->FBLinearAddr; + *size = pGeode->FBAvail; + *offset = 0; + *flags = DGA_NEED_ROOT; + return TRUE; +} + +static void +LX_CloseFramebuffer(ScrnInfoPtr pScrni) +{ +} + +/* end of file */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_dga.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_dga.c 2005-07-13 13:16:48.000000000 -0600 @@ -0,0 +1,417 @@ +/* + * $Workfile: amd_gx_dga.c $ + * $Revision: #4 $ + * $Author: raymondd $ + * + * File contents: DGA(Direct Acess Graphics mode) is feature of + * XFree86 that allows the program to access directly to video + * memory on the graphics card.DGA supports the double + * flickering.This file has the functions to support the DGA + * modes. + * + * Project: Geode Xfree Frame buffer device driver. + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86_ansic.h" +#include "xf86Pci.h" +#include "xf86PciInfo.h" +#include "xaa.h" +#include "xaalocal.h" +#include "amd.h" +#include "dgaproc.h" + +/* forward declarations */ +Bool GXDGAInit(ScreenPtr pScrn); +static Bool GX_OpenFramebuffer(ScrnInfoPtr, char **, unsigned char **, + int *, int *, int *); +static void GX_CloseFramebuffer(ScrnInfoPtr pScrn); +static Bool GX_SetMode(ScrnInfoPtr, DGAModePtr); +static int GX_GetViewport(ScrnInfoPtr); +static void GX_SetViewport(ScrnInfoPtr, int, int, int); +static void GX_FillRect(ScrnInfoPtr, int, int, int, int, unsigned long); +static void GX_BlitRect(ScrnInfoPtr, int, int, int, int, int, int); + +extern void GXAdjustFrame(int, int, int, int); +extern Bool GXSwitchMode(int, DisplayModePtr, int); +extern void GXAccelSync(ScrnInfoPtr pScrni); + +static DGAFunctionRec GXDGAFuncs = { + GX_OpenFramebuffer, + GX_CloseFramebuffer, + GX_SetMode, + GX_SetViewport, + GX_GetViewport, + GXAccelSync, + GX_FillRect, + GX_BlitRect, + NULL +}; + +/*---------------------------------------------------------------------------- + * GXDGAInit. + * + * Description :This function is used to intiallize the DGA modes and sets the + viewport based on the screen mode. + * Parameters. + * pScreeen :Pointer to screen info structure. + * + * Returns :TRUE on success and FALSE on failure. + * + * Comments :This function prepares the DGA mode settings for + * other func reference. + * +*---------------------------------------------------------------------------- +*/ +Bool +GXDGAInit(ScreenPtr pScrn) +{ + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + GeodePtr pGeode = GEODEPTR(pScrni); + DGAModePtr modes = NULL, newmodes = NULL, currentMode; + DisplayModePtr pMode, firstMode; + int Bpp = pScrni->bitsPerPixel >> 3; + int num = 0; + Bool oneMore; + + pMode = firstMode = pScrni->modes; + DEBUGMSG(0, (0, X_NONE, "GXDGAInit %d\n", Bpp)); + while (pMode) { + + /* redundant but it can be used in future:if(0). */ + if (0) { /*pScrni->displayWidth != pMode->HDisplay */ + /* memory is allocated for dga to + *setup the viewport and mode parameters + */ + newmodes = xrealloc(modes, (num + 2) * sizeof(DGAModeRec)); + oneMore = TRUE; + } else { + /* one record is allocated here */ + newmodes = xrealloc(modes, (num + 1) * sizeof(DGAModeRec)); + oneMore = FALSE; + } + if (!newmodes) { + xfree(modes); + return FALSE; + } + modes = newmodes; + + SECOND_PASS: /* DGA mode flgas and viewport parametrs are set here. */ + + currentMode = modes + num; + num++; + currentMode->mode = pMode; + currentMode->flags = DGA_CONCURRENT_ACCESS | DGA_PIXMAP_AVAILABLE; + currentMode->flags |= DGA_FILL_RECT | DGA_BLIT_RECT; + if (pMode->Flags & V_DBLSCAN) + currentMode->flags |= DGA_DOUBLESCAN; + if (pMode->Flags & V_INTERLACE) + currentMode->flags |= DGA_INTERLACED; + currentMode->byteOrder = pScrni->imageByteOrder; + currentMode->depth = pScrni->depth; + currentMode->bitsPerPixel = pScrni->bitsPerPixel; + currentMode->red_mask = pScrni->mask.red; + currentMode->green_mask = pScrni->mask.green; + currentMode->blue_mask = pScrni->mask.blue; + currentMode->visualClass = (Bpp == 1) ? PseudoColor : TrueColor; + currentMode->viewportWidth = pMode->HDisplay; + currentMode->viewportHeight = pMode->VDisplay; + currentMode->xViewportStep = 1; + currentMode->yViewportStep = 1; + currentMode->viewportFlags = DGA_FLIP_RETRACE; + currentMode->offset = 0; + currentMode->address = pGeode->FBBase; + if (oneMore) { /* first one is narrow width */ + currentMode->bytesPerScanline = ((pMode->HDisplay * Bpp) + 3) & ~3L; + currentMode->imageWidth = pMode->HDisplay; + currentMode->imageHeight = pMode->VDisplay; + currentMode->pixmapWidth = currentMode->imageWidth; + currentMode->pixmapHeight = currentMode->imageHeight; + currentMode->maxViewportX = currentMode->imageWidth - + currentMode->viewportWidth; + /* this might need to get clamped to some maximum */ + currentMode->maxViewportY = currentMode->imageHeight - + currentMode->viewportHeight; + oneMore = FALSE; + goto SECOND_PASS; + } else { + currentMode->bytesPerScanline = + ((pScrni->displayWidth * Bpp) + 3) & ~3L; + currentMode->imageWidth = pScrni->displayWidth; + currentMode->imageHeight = pMode->VDisplay; + currentMode->pixmapWidth = currentMode->imageWidth; + currentMode->pixmapHeight = currentMode->imageHeight; + currentMode->maxViewportX = currentMode->imageWidth - + currentMode->viewportWidth; + /* this might need to get clamped to some maximum */ + currentMode->maxViewportY = currentMode->imageHeight - + currentMode->viewportHeight; + } + pMode = pMode->next; + if (pMode == firstMode) + break; + } + pGeode->numDGAModes = num; + pGeode->DGAModes = modes; + return DGAInit(pScrn, &GXDGAFuncs, modes, num); +} + +/*---------------------------------------------------------------------------- + * GX_SetMode. + * + * Description :This function is sets into the DGA mode. + *. + * Parameters. + * pScreeen :Pointer to screen info structure. + * pMode :Points to the DGAmode ptr data + * Returns :TRUE on success and FALSE on failure. + * + * Comments :none. + * + * +*---------------------------------------------------------------------------- +*/ +static Bool +GX_SetMode(ScrnInfoPtr pScrni, DGAModePtr pMode) +{ + static int OldDisplayWidth[MAXSCREENS]; + int index = pScrni->pScreen->myNum; + GeodePtr pGeode = GEODEPTR(pScrni); + + DEBUGMSG(0, (0, X_NONE, "GX_SetMode\n")); + + if (!pMode) { + /* restore the original mode + * * put the ScreenParameters back + */ + pScrni->displayWidth = OldDisplayWidth[index]; + DEBUGMSG(0, + (0, X_NONE, "GX_SetMode !pMode %d\n", pScrni->displayWidth)); + GXSwitchMode(index, pScrni->currentMode, 0); + pGeode->DGAactive = FALSE; + } else { + if (!pGeode->DGAactive) { /* save the old parameters */ + OldDisplayWidth[index] = pScrni->displayWidth; + pGeode->DGAactive = TRUE; + DEBUGMSG(0, + (0, X_NONE, "GX_SetMode pMode+ NA %d\n", + pScrni->displayWidth)); + } +#if defined(STB_X) + Gal_get_display_offset(&pGeode->PrevDisplayOffset); +#else + pGeode->PrevDisplayOffset = gfx_get_display_offset(); +#endif + + pScrni->displayWidth = pMode->bytesPerScanline / + (pMode->bitsPerPixel >> 3); + DEBUGMSG(0, + (0, X_NONE, "GX_SetMode pMode+ %d\n", pScrni->displayWidth)); + GXSwitchMode(index, pMode->mode, 0); + } + /* enable/disable Compression */ + if (pGeode->Compression) { + GFX(set_compression_enable(!pGeode->DGAactive)); + } + + /* enable/disable cursor */ + if (pGeode->HWCursor) { + GFX(set_cursor_enable(!pGeode->DGAactive)); + } + + return TRUE; +} + +/*---------------------------------------------------------------------------- + * GX_GetViewPort. + * + * Description :This function is Gets the viewport window memory. + *. + * Parameters. + * pScrni :Pointer to screen info structure. + * + * Returns :returns the viewport status. + * + * Comments :none. + * + * +*---------------------------------------------------------------------------- +*/ +static int +GX_GetViewport(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + return pGeode->DGAViewportStatus; +} + +/*---------------------------------------------------------------------------- + * GX_SetViewPort. + * + * Description :This function is Gets the viewport window memory. + * + * Parameters. + * pScrn :Pointer to screen info structure. + x :x-cordinate of viewport window + * y :y-codinate of the viewport window. + * flags :indicates the viewport to be flipped or not. + * Returns :returns the viewport status as zero. + * + * Comments :none. + * +*---------------------------------------------------------------------------- +*/ +static void +GX_SetViewport(ScrnInfoPtr pScrni, int x, int y, int flags) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + GXAdjustFrame(pScrni->pScreen->myNum, x, y, flags); + pGeode->DGAViewportStatus = 0; /*GXAdjustFrame loops until finished */ +} + +/*---------------------------------------------------------------------------- + * GX_FillRect. + * + * Description :This function is Gets the viewport window memory. + *. + * Parameters. + * pScrn :Pointer to screen info structure. + * x :x-cordinate of viewport window + * y :y-codinate of the viewport window. + * w :width of the rectangle + * h :height of the rectangle. + * color :color to be filled in rectangle. + * + * Returns :returns the viewport status as zero. + * + * Comments :This function is implemented by solidfill routines.. + * +*---------------------------------------------------------------------------- +*/ +static void +GX_FillRect(ScrnInfoPtr pScrn, int x, int y, + int w, int h, unsigned long color) +{ + GeodePtr pGeode = GEODEPTR(pScrn); + + if (pGeode->AccelInfoRec) { + (*pGeode->AccelInfoRec->SetupForSolidFill) (pScrn, color, GXcopy, ~0); + (*pGeode->AccelInfoRec->SubsequentSolidFillRect) (pScrn, x, y, w, h); + SET_SYNC_FLAG(pGeode->AccelInfoRec); + } +} + +/*---------------------------------------------------------------------------- + * GX_BlitRect. + * + * Description :This function implementing Blit and it moves a + * Rectangular block of data from one location to other + * Location. + * + * Parameters. + * pScrni :Pointer to screen info structure. + * srcx :x-cordinate of the src rectangle + * srcy :y-codinate of src rectangle. + * w :width of the rectangle + * h :height of the rectangle. + * dstx :x-cordinate of the dst rectangle. + * dsty :y -coordinates of the dst rectangle. + * Returns :none. + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static void +GX_BlitRect(ScrnInfoPtr pScrni, + int srcx, int srcy, int w, int h, int dstx, int dsty) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + if (pGeode->AccelInfoRec) { + int xdir = ((srcx < dstx) && (srcy == dsty)) ? -1 : 1; + int ydir = (srcy < dsty) ? -1 : 1; + + (*pGeode->AccelInfoRec->SetupForScreenToScreenCopy) + (pScrni, xdir, ydir, GXcopy, ~0, -1); + (*pGeode->AccelInfoRec->SubsequentScreenToScreenCopy) (pScrni, srcx, + srcy, dstx, dsty, + w, h); + SET_SYNC_FLAG(pGeode->AccelInfoRec); + } +} + +/*---------------------------------------------------------------------------- + * GX_OpenFramebuffer. + * + * Description :This function open the framebuffer driver for DGA. + * + * Parameters. + * pScrni :Pointer to screen info structure. + * srcx :x-cordinate of the src rectangle + * srcy :y-codinate of src rectangle. + * w :width of the rectangle + * h :height of the rectangle. + * dstx :x-cordinate of the dst rectangle. + * dsty :y -coordinates of the dst rectangle. + * Returns :none. + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static Bool +GX_OpenFramebuffer(ScrnInfoPtr pScrni, + char **name, unsigned char **mem, + int *size, int *offset, int *flags) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + *name = NULL; /* no special device */ + *mem = (unsigned char *)pGeode->FBLinearAddr; + *size = pGeode->FBSize; + *offset = 0; + *flags = DGA_NEED_ROOT; + return TRUE; +} + +static void +GX_CloseFramebuffer(ScrnInfoPtr pScrni) +{ +} + +/* end of file */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_vga.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_vga.c 2005-07-13 13:16:49.000000000 -0600 @@ -0,0 +1,56 @@ +/* + * $Workfile: amd_lx_vga.c $ + * $Revision: #3 $ + * $Author: raymondd $ + * + * This file contains routines to set modes using the VGA registers. + * Since this file is for the first generation graphics unit, it interfaces + * to SoftVGA registers. It works for both VSA1 and VSA2. + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +/* VGA STRUCTURE */ + +int gu3_get_vga_active(void); + +int +gu3_get_vga_active(void) +{ + int data = READ_REG32(DC3_GENERAL_CFG); + + if (data & DC3_GCFG_VGAE) + return 1; + return 0; +} + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_vga.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_vga.c 2005-07-13 13:16:48.000000000 -0600 @@ -0,0 +1,477 @@ +/* + * $Workfile: amd_gx_vga.c $ + * $Revision: #3 $ + * $Author: raymondd $ + * + * This file contains routines to set modes using the VGA registers. + * Since this file is for the first generation graphics unit, it interfaces + * to SoftVGA registers. It works for both VSA1 and VSA2. + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +/* VGA STRUCTURE */ + +#define GU2_STD_CRTC_REGS 25 +#define GU2_EXT_CRTC_REGS 15 +#define GU2_GDC_REGS 9 +#define GU2_SEQ_REGS 5 + +#define GU2_VGA_FLAG_MISC_OUTPUT 0x1 +#define GU2_VGA_FLAG_STD_CRTC 0x2 +#define GU2_VGA_FLAG_EXT_CRTC 0x4 +#define GU2_VGA_FLAG_GDC 0x10 +#define GU2_VGA_FLAG_SEQ 0x20 +#define GU2_VGA_FLAG_PALETTE 0x40 +#define GU2_VGA_FLAG_ATTR 0x80 + +static unsigned int GDCregs[10]; +static unsigned int SEQregs[10]; +static unsigned int palette[256]; +static unsigned int ATTRregs[32]; +static unsigned char *font_data = NULL; + +#define VGA_BLOCK 0x40000 /* 256 k */ + +void gu2_vga_extcrtc(char offset, int reset); +int gu2_get_vga_active(void); +void gu2_vga_font_data(int flag); +void gu2_set_vga(int reset); +int gu2_vga_seq_blanking(void); +int gu2_vga_attr_ctrl(int reset); +void gu2_vga_to_gfx(void); +void gu2_gfx_to_vga(int vga_mode); +int gu2_vga_seq_reset(int reset); +int gu2_vga_save(gfx_vga_struct * vga, int flags); +void gu2_vga_clear_extended(void); +int gu2_vga_restore(gfx_vga_struct * vga, int flags); + +int +gu2_get_vga_active(void) +{ + int data = gfx_read_reg32(MDC_GENERAL_CFG); + + if (data & MDC_GCFG_VGAE) + return 1; + return 0; +} + +void +gu2_vga_font_data(int flag) +{ + if (flag == 0) { + if (font_data == NULL) { + font_data = malloc(VGA_BLOCK); + } + DEBUGMSG(1, (0, X_NONE, "Saving VGA Data\n")); + memcpy(font_data, gfx_virt_fbptr, VGA_BLOCK); + } else { + if (font_data) { + DEBUGMSG(1, (0, X_NONE, "Restore VGA Data\n")); + memcpy(gfx_virt_fbptr, font_data, VGA_BLOCK); + free(font_data); + font_data = NULL; + } + } +} + +void +gu2_set_vga(int reset) +{ + int data = gfx_read_reg32(MDC_GENERAL_CFG); + + if (reset) + data |= MDC_GCFG_VGAE; + else + data &= ~MDC_GCFG_VGAE; + gfx_write_reg32(MDC_GENERAL_CFG, data); +} + +int +gu2_vga_seq_blanking(void) +{ + int tmp; + + gfx_outb(0x3C4, 1); + tmp = gfx_inb(0x3C5); + tmp |= 0x20; + tmp |= tmp << 8; + gfx_outw(0x3C4, tmp); + + gfx_delay_milliseconds(1); + return (GFX_STATUS_OK); +} + +int +gu2_vga_attr_ctrl(int reset) +{ + int tmp; + + tmp = gfx_inb(0x3DA); + gfx_outb(0x3C0, (unsigned char)(reset ? 0x00 : 0x20)); + if (reset) + tmp = gfx_inb(0x3DA); + return (GFX_STATUS_OK); +} + +void +gu2_vga_to_gfx(void) +{ + gu2_vga_attr_ctrl(0); + + gu2_vga_seq_blanking(); + gfx_delay_milliseconds(2); + + gu2_vga_extcrtc(0x3F, 1); +} + +void +gu2_gfx_to_vga(int vga_mode) +{ + int tmp; + char sequencer; + + gu2_vga_extcrtc(0x40, vga_mode); + + /* clear the display blanking bit */ + gfx_outb(MDC_SEQUENCER_INDEX, MDC_SEQUENCER_CLK_MODE); + sequencer = gfx_inb(MDC_SEQUENCER_DATA); + sequencer &= ~MDC_CLK_MODE_SCREEN_OFF; + sequencer |= 1; + gfx_outb(MDC_SEQUENCER_DATA, sequencer); + + gfx_delay_milliseconds(1); + + /*restart the sequencer */ + gfx_outw(0x3C4, 0x300); + + /* turn on the attribute controler */ + tmp = gfx_inb(0x3DA); + gfx_outb(0x3C0, 0x20); + tmp = gfx_inb(0x3DA); + + gu2_vga_extcrtc(0x3F, 0); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_seq_reset + * + * This routine enables or disables SoftVGA. It is used to make SoftVGA + * "be quiet" and not interfere with any of the direct hardware access from + * Durango. For VSA1, the sequencer is reset to stop text redraws. VSA2 may + * provide a better way to have SoftVGA sit in the background. + *----------------------------------------------------------------------------- + */ +int +gu2_vga_seq_reset(int reset) +{ + gfx_outb(0x3C4, 0); + gfx_outb(0x3C5, (unsigned char)(reset ? 0x00 : 0x03)); + return (GFX_STATUS_OK); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_save + * + * This routine saves the state of the VGA registers into the specified + * structure. Flags indicate what portions of the register state need to + * be saved. + *----------------------------------------------------------------------------- + */ +int +gu2_vga_save(gfx_vga_struct * vga, int flags) +{ + int i; + unsigned short crtcindex, crtcdata; + + crtcindex = (gfx_inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4; + crtcdata = crtcindex + 1; + + /* CHECK MISCELLANEOUS OUTPUT FLAG */ + + if (flags & GU2_VGA_FLAG_MISC_OUTPUT) { + /* SAVE MISCCELLANEOUS OUTPUT REGISTER */ + + vga->miscOutput = gfx_inb(0x3CC); + } + + /* CHECK SEQ */ + + if (flags & GU2_VGA_FLAG_SEQ) { + /* SAVE STANDARD CRTC REGISTERS */ + + for (i = 1; i < GU2_SEQ_REGS; i++) { + gfx_outb(0x3C4, (unsigned char)i); + SEQregs[i] = gfx_inb(0x3C5); + } + } + + /* CHECK STANDARD CRTC FLAG */ + + if (flags & GU2_VGA_FLAG_STD_CRTC) { + /* SAVE STANDARD CRTC REGISTERS */ + + for (i = 0; i < GU2_STD_CRTC_REGS; i++) { + gfx_outb(crtcindex, (unsigned char)i); + vga->stdCRTCregs[i] = gfx_inb(crtcdata); + } + } + + /* CHECK GDC */ + + if (flags & GU2_VGA_FLAG_GDC) { + /* SAVE STANDARD CRTC REGISTERS */ + + for (i = 0; i < GU2_GDC_REGS; i++) { + gfx_outb(0x3CE, (unsigned char)i); + GDCregs[i] = gfx_inb(0x3CF); + } + } + + /* CHECK EXTENDED CRTC FLAG */ + + if (flags & GU2_VGA_FLAG_EXT_CRTC) { + /* SAVE EXTENDED CRTC REGISTERS */ + + for (i = 0; i < GU2_EXT_CRTC_REGS; i++) { + gfx_outb(crtcindex, (unsigned char)(0x40 + i)); + vga->extCRTCregs[i] = gfx_inb(crtcdata); + } + } + + if (flags & GU2_VGA_FLAG_PALETTE) { + /* SAVE PALETTE DATA */ + + for (i = 0; i < 0x100; i++) { + gfx_outb(0x3C7, i); + palette[i] = gfx_inb(0x3C9); + } + } + + if (flags & GU2_VGA_FLAG_ATTR) { + /* SAVE Attribute DATA */ + + for (i = 0; i < 21; i++) { + gfx_inb(0x3DA); + gfx_outb(0x3C0, i); + ATTRregs[i] = gfx_inb(0x3C1); + } + } + /* save the VGA data */ + gu2_vga_font_data(0); + return (0); +} + +/*----------------------------------------------------------------------------- + * gfx_vga_clear_extended + * + * This routine clears the extended SoftVGA register values to have SoftVGA + * behave like standard VGA. + *----------------------------------------------------------------------------- + */ +void +gu2_vga_clear_extended(void) +{ + int i; + unsigned short crtcindex, crtcdata; + + crtcindex = (gfx_inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4; + crtcdata = crtcindex + 1; + + gfx_outb(crtcindex, 0x30); + gfx_outb(crtcdata, 0x57); + gfx_outb(crtcdata, 0x4C); + for (i = 0x41; i <= 0x4F; i++) { + gfx_outb(crtcindex, (unsigned char)i); + gfx_outb(crtcdata, 0); + } + gfx_outb(crtcindex, 0x30); + gfx_outb(crtcdata, 0x00); +} + +void +gu2_vga_extcrtc(char offset, int reset) +{ + unsigned short crtcindex, crtcdata; + + crtcindex = (gfx_inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4; + crtcdata = crtcindex + 1; + + /* UNLOCK EXTENDED CRTC REGISTERS */ + + gfx_outb(crtcindex, 0x30); + gfx_outb(crtcdata, 0x57); + gfx_outb(crtcdata, 0x4C); + + /* RESTORE EXTENDED CRTC REGISTERS */ + + gfx_outb(crtcindex, offset); + gfx_outb(crtcdata, reset); + +#if 0 + /* LOCK EXTENDED CRTC REGISTERS */ + + gfx_outb(crtcindex, 0x30); + gfx_outb(crtcdata, 0x00); +#endif +} + +/*----------------------------------------------------------------------------- + * gfx_vga_restore + * + * This routine restores the state of the VGA registers from the specified + * structure. Flags indicate what portions of the register state need to + * be saved. + *----------------------------------------------------------------------------- + */ +int +gu2_vga_restore(gfx_vga_struct * vga, int flags) +{ + int i; + unsigned short crtcindex, crtcdata; + + crtcindex = (gfx_inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4; + crtcdata = crtcindex + 1; + + /* CHECK MISCELLANEOUS OUTPUT FLAG */ + + if (flags & GU2_VGA_FLAG_MISC_OUTPUT) { + /* RESTORE MISCELLANEOUS OUTPUT REGISTER VALUE */ + + gfx_outb(0x3C2, vga->miscOutput); + } + + /* CHECK SEQ */ + + if (flags & GU2_VGA_FLAG_SEQ) { + /* RESTORE STANDARD CRTC REGISTERS */ + + for (i = 1; i < GU2_SEQ_REGS; i++) { + gfx_outb(0x3C4, (unsigned char)i); + gfx_outb(0x3C5, SEQregs[i]); + } + } + + /* CHECK STANDARD CRTC FLAG */ + + if (flags & GU2_VGA_FLAG_STD_CRTC) { + /* UNLOCK STANDARD CRTC REGISTERS */ + + gfx_outb(crtcindex, 0x11); + gfx_outb(crtcdata, 0); + + /* RESTORE STANDARD CRTC REGISTERS */ + + for (i = 0; i < GU2_STD_CRTC_REGS; i++) { + gfx_outb(crtcindex, (unsigned char)i); + gfx_outb(crtcdata, vga->stdCRTCregs[i]); + } + } + + /* CHECK GDC */ + + if (flags & GU2_VGA_FLAG_GDC) { + /* SAVE STANDARD CRTC REGISTERS */ + + for (i = 0; i < GU2_GDC_REGS; i++) { + gfx_outb(0x3CE, (unsigned char)i); + gfx_outb(0x3CF, GDCregs[i]); + } + } + + /* CHECK EXTENDED CRTC FLAG */ + + if (flags & GU2_VGA_FLAG_EXT_CRTC) { + /* UNLOCK EXTENDED CRTC REGISTERS */ + + gfx_outb(crtcindex, 0x30); + gfx_outb(crtcdata, 0x57); + gfx_outb(crtcdata, 0x4C); + + /* RESTORE EXTENDED CRTC REGISTERS */ + + for (i = 1; i < GU2_EXT_CRTC_REGS; i++) { + gfx_outb(crtcindex, (unsigned char)(0x40 + i)); + gfx_outb(crtcdata, vga->extCRTCregs[i]); + } + + /* LOCK EXTENDED CRTC REGISTERS */ + + gfx_outb(crtcindex, 0x30); + gfx_outb(crtcdata, 0x00); + + /* CHECK IF DIRECT FRAME BUFFER MODE (VESA MODE) */ + + if (vga->extCRTCregs[0x03] & 1) { + /* SET BORDER COLOR TO BLACK */ + /* This really should be another thing saved/restored, but */ + /* Durango currently doesn't do the attr controller registers. */ + + gfx_inb(0x3BA); /* Reset flip-flop */ + gfx_inb(0x3DA); + gfx_outb(0x3C0, 0x11); + gfx_outb(0x3C0, 0x00); + } + } + + if (flags & GU2_VGA_FLAG_PALETTE) { + /* RESTORE PALETTE DATA */ + + for (i = 0; i < 0x100; i++) { + gfx_outb(0x3C8, i); + gfx_outb(0x3C9, palette[i]); + } + } + + if (flags & GU2_VGA_FLAG_ATTR) { + /* RESTORE Attribute DATA */ + + for (i = 0; i < 21; i++) { + gfx_inb(0x3DA); + gfx_outb(0x3C0, i); + gfx_outb(0x3C0, ATTRregs[i]); + } + /* SAVE Attribute DATA */ + + for (i = 0; i < 21; i++) { + gfx_inb(0x3DA); + gfx_outb(0x3C0, i); + } + } + + /* restore the VGA data */ + gu2_vga_font_data(1); + + return (0); +} + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_cursor.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_cursor.c 2005-07-13 13:16:49.000000000 -0600 @@ -0,0 +1,303 @@ +/* + * $Workfile: amd_lx_cursor.c $ + * $Revision: #4 $ + * $Author: raymondd $ + * + * File Contents: Xfree cursor implementation routines + * for geode HWcursor init.setting cursor color,image etc + * are done here. + * Project: Geode Xfree Frame buffer device driver. + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86_ansic.h" +#include "xf86Pci.h" +#include "xf86PciInfo.h" +#include "amd.h" + +/* Forward declarations of the functions */ +Bool LXHWCursorInit(ScreenPtr pScrn); +static void LXSetCursorColors(ScrnInfoPtr pScrni, int bg, int fg); +static void LXSetCursorPosition(ScrnInfoPtr pScrni, int x, int y); +void LXLoadCursorImage(ScrnInfoPtr pScrni, unsigned char *src); +void LXHideCursor(ScrnInfoPtr pScrni); +void LXShowCursor(ScrnInfoPtr pScrni); +static Bool LXUseHWCursor(ScreenPtr pScrn, CursorPtr pCurs); +extern void LXSetVideoPosition(int x, int y, int width, int height, + short src_w, short src_h, short drw_w, + short drw_h, int id, int offset, + ScrnInfoPtr pScrni); + +/*---------------------------------------------------------------------------- + * LXHWCursorInit. + * + * Description :This function sets the cursor information by probing the + * hardware. + * + * Parameters. + * pScrn :Screeen pointer structure. + * + * Returns :TRUE on success and FALSE on Failure + * + * Comments :Geode supports the hardware_cursor,no need to enable SW + * cursor. +*---------------------------------------------------------------------------- +*/ +Bool +LXHWCursorInit(ScreenPtr pScrn) +{ + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + GeodePtr pGeode = GEODEPTR(pScrni); + xf86CursorInfoPtr infoPtr; + + infoPtr = xf86CreateCursorInfoRec(); + if (!infoPtr) + return FALSE; + /* the geode structure is intiallized with the cursor infoRec */ + pGeode->CursorInfo = infoPtr; + infoPtr->MaxWidth = 32; + infoPtr->MaxHeight = 32; + /* seeting up the cursor flags */ + infoPtr->Flags = HARDWARE_CURSOR_BIT_ORDER_MSBFIRST | + HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | + HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED; + /* cursor info ptr is intiallized with the values obtained from + * * durnago calls + */ + infoPtr->SetCursorColors = LXSetCursorColors; + infoPtr->SetCursorPosition = LXSetCursorPosition; + infoPtr->LoadCursorImage = LXLoadCursorImage; + infoPtr->HideCursor = LXHideCursor; + infoPtr->ShowCursor = LXShowCursor; + infoPtr->UseHWCursor = LXUseHWCursor; + return (xf86InitCursor(pScrn, infoPtr)); +} + +/*---------------------------------------------------------------------------- + * LXSetCursorColors. + * + * Description :This function sets the cursor foreground and background + * colors + * Parameters: + * pScrni: Screeen information pointer structure. + * bg: Specifies the color value of cursor background color. + * fg: Specifies the color value of cursor foreground color. + * Returns: none. + * + * Comments: The integer color value passed by this function is + * converted into * RGB value by the gfx_set_color routines. + *---------------------------------------------------------------------------- + */ +static void +LXSetCursorColors(ScrnInfoPtr pScrni, int bg, int fg) +{ + vg_set_mono_cursor_colors(bg, fg); +} + +/*---------------------------------------------------------------------------- + * LXSetCursorPosition. + * + * Description :This function sets the cursor co -ordinates and enable the + * cursor. + * + * Parameters: + * pScrni: Screeen information pointer structure. + * x: Specifies the x-cordinates of the cursor. + * y: Specifies the y co-ordinate of the cursor. + * Returns: none. + * + *---------------------------------------------------------------------------- + */ +static void +LXSetCursorPosition(ScrnInfoPtr pScrni, int x, int y) +{ + static unsigned long panOffset = 0; + GeodePtr pGeode = GEODEPTR(pScrni); + int newX, newY; + + (*pGeode->Rotation)(x,y,pGeode->HDisplay,pGeode->VDisplay,&newX,&newY); + (*pGeode->RBltXlat)(newX,newY,32,32,&newX,&newY); + if (newX < -31) newX = -31; + if (newY < -31) newY = -31; + + { VG_PANNING_COORDINATES panning; + vg_set_cursor_position(newX+31, newY+31, &panning); } + vg_set_cursor_enable(1); + +#ifndef AMD_V4L2_VIDEO + if ((pGeode->OverlayON) && (pGeode->EnabledOutput & LX_OT_FP)) { + pGeode->PrevDisplayOffset = vg_get_display_offset(); + if (pGeode->PrevDisplayOffset != panOffset) { + LXSetVideoPosition(pGeode->video_x, pGeode->video_y, + pGeode->video_w, pGeode->video_h, + pGeode->video_srcw, pGeode->video_srch, + pGeode->video_dstw, pGeode->video_dsth, + pGeode->video_id, pGeode->video_offset, + pGeode->video_scrnptr); + panOffset = pGeode->PrevDisplayOffset; + } + } +#endif +} + +/*---------------------------------------------------------------------------- + * LXLoadCursorImage + * + * Description :This function loads the 32x32 cursor pattern.The shape + * and color is set by AND and XOR masking of arrays of 32 + * DWORD. + * Parameters: + * pScrni: Screeen information pointer structure. + * src : Specifies cursor data. + * Returns : none + * + *---------------------------------------------------------------------------- +*/ +void +LXLoadCursorImage(ScrnInfoPtr pScrni, unsigned char *src) +{ + int i, n, x, y, newX, newY; + unsigned long andMask[32], xorMask[32]; + GeodePtr pGeode = GEODEPTR(pScrni); + unsigned long mskb, rowb; + unsigned char *rowp = &src[0]; + unsigned char *mskp = &src[128]; + + if( src != NULL ) { + mskb = rowb = 0; + for( y=32; --y>=0; ) + andMask[y] = xorMask[y] = 0; + for( y=0; y<32; ++y ) { + for( x=0; x<32; ++x ) { + if( (i=x&7) == 0 ) { + rowb = (*rowp & *mskp); + mskb = ~(*mskp); + ++rowp; ++mskp; + } + (*pGeode->Rotation)(x,y,32,32,&newX,&newY); + i = 7-i; n = 31-newX; + andMask[newY] |= (((mskb>>i)&1)<>i)&1)<=0; ) { + andMask[y] = ~0; + xorMask[y] = 0; + } + } + +#if 0 + andMask[31] = 0; + xorMask[31] = 0; + for( y=31; --y>0; ) { + andMask[y] &= ~0x80000001; + xorMask[y] &= ~0x80000001; + } + andMask[0] = 0; + xorMask[0] = 0; +#endif + + vg_set_mono_cursor_shape32(pGeode->CursorStartOffset,&andMask[0],&xorMask[0],31,31); +} + +/*---------------------------------------------------------------------------- + * LXHideCursor + * + * Description :This function will disable the cursor. + * + * Parameters: + * pScrni: Handles to the Screeen information pointer structure. + * + * Returns: none. + * + * Comments: gfx_set_cursor enable function is hardcoded to disable + * the cursor. + *---------------------------------------------------------------------------- + */ +void +LXHideCursor(ScrnInfoPtr pScrni) +{ + vg_set_cursor_enable(0); +} + +/*---------------------------------------------------------------------------- + * LXShowCursor + * + * Description :This function will enable the cursor. + * + * Parameters: + * pScrni :Handles to the Screeen information pointer structure. + * + * Returns :none + * + * Comments :gfx_set_cursor enable function is hardcoded to enable the + * cursor + *---------------------------------------------------------------------------- +*/ +void +LXShowCursor(ScrnInfoPtr pScrni) +{ + vg_set_cursor_enable(1); +} + +/*---------------------------------------------------------------------------- + * LXUseHwCursor. + * + * Description :This function will sets the hardware cursor flag in + * pscreen structure. + * + * Parameters. + * pScreen :Handles to the Screeen pointer structure. + * + * Returns :none + * + * Comments :none + * + *---------------------------------------------------------------------------- +*/ +static Bool +LXUseHWCursor(ScreenPtr pScrn, CursorPtr pCurs) +{ + ScrnInfoPtr pScrni = XF86SCRNINFO(pScrn); + + if (pScrni->currentMode->Flags & V_DBLSCAN) + return FALSE; + return TRUE; +} + +/* End of File */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_driver.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_driver.c 2005-08-30 10:36:03.000000000 -0600 @@ -0,0 +1,2906 @@ +/* + * $Workfile: amd_lx_driver.c $ + * $Revision: #6 $ + * $Author: raymondd $ + * + * File Contents: This is the main module configures the interfacing + * with the X server. The individual modules will be + * loaded based upon the options selected from the + * XF86Config. This file also has modules for finding + * supported modes, turning on the modes based on options. + * + * Project: Geode Xfree Frame buffer device driver. + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +/* Includes that are used by all drivers */ +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86_ansic.h" +#include "xf86_libc.h" +#include "xf86Resources.h" + +/* We may want inb() and outb() */ +#include "compiler.h" + +/* We may want to access the PCI config space */ +#include "xf86PciInfo.h" +#include "xf86Pci.h" + +/* Colormap handling stuff */ +#include "xf86cmap.h" + +#define RC_MAX_DEPTH 24 + +#include "amd.h" +#include "cim_defs.h" +#include "cim_regs.h" +#include "cim_dev.h" + +/* Frame buffer stuff */ +#if CFB +/* + * If using cfb, cfb.h is required. Select the others for the bpp values + * the driver supports. + */ +#define PSZ 8 /* needed for cfb.h */ +#include "cfb.h" +#undef PSZ +#include "cfb16.h" +#include "cfb24.h" +#include "cfb32.h" +#else +#include "fb.h" +#endif + +#include "shadowfb.h" + +/* Machine independent stuff */ +#include "mipointer.h" +#include "mibank.h" +#include "micmap.h" +/* All drivers implementing backing store need this */ +#include "mibstore.h" +#include "vgaHW.h" +#include "vbe.h" + +/* Check for some extensions */ +#ifdef XFreeXDGA +#define _XF86_DGA_SERVER_ +#include "extensions/xf86dgastr.h" +#endif /* XFreeXDGA */ + +#ifdef DPMSExtension +#include "globals.h" +#include "opaque.h" +#define DPMS_SERVER +#include "extensions/dpms.h" +#endif /* DPMSExtension */ + +#include "amd_lx_vga.c" + +extern SymTabRec GeodeChipsets[]; +extern OptionInfoRec LX_GeodeOptions[]; + +/* Forward definitions */ +static Bool LXPreInit(ScrnInfoPtr, int); +static Bool LXScreenInit(int, ScreenPtr, int, char **); +static Bool LXEnterVT(int, int); +static void LXLeaveVT(int, int); +static void LXFreeScreen(int, int); +void LXAdjustFrame(int, int, int, int); +Bool LXSwitchMode(int, DisplayModePtr, int); +static int LXValidMode(int, DisplayModePtr, Bool, int); +static void LXLoadPalette(ScrnInfoPtr pScrni, + int numColors, int *indizes, + LOCO * colors, VisualPtr pVisual); +static Bool LXMapMem(ScrnInfoPtr); +static Bool LXUnmapMem(ScrnInfoPtr); + +extern Bool LXAccelInit(ScreenPtr pScrn); +extern Bool LXHWCursorInit(ScreenPtr pScrn); +extern void LXHideCursor(ScrnInfoPtr pScrni); +extern void LXShowCursor(ScrnInfoPtr pScrni); +extern void LXLoadCursorImage(ScrnInfoPtr pScrni, unsigned char *src); +extern void LXPointerMoved(int index, int x, int y); +extern void LXRotationInit(ScrnInfoPtr pScrni); +extern void LXShadowFBInit(ScreenPtr pScrn,GeodePtr pGeode,int bytpp); +extern void LXInitVideo(ScreenPtr pScrn); +extern Bool LXDGAInit(ScreenPtr pScrn); + +unsigned char *XpressROMPtr; +unsigned long fb; + +/* List of symbols from other modules that this module references.The purpose +* is that to avoid unresolved symbol warnings +*/ +extern const char *amdVgahwSymbols[]; +extern const char *amdVbeSymbols[]; +extern const char *amdInt10Symbols[]; + +#if CFB +extern const char *amdCfbSymbols[]; +#else +extern const char *amdFbSymbols[]; +#endif +extern const char *amdXaaSymbols[]; +extern const char *amdRamdacSymbols[]; +extern const char *amdShadowSymbols[]; + +void LXSetupChipsetFPtr(ScrnInfoPtr pScrni); +GeodePtr LXGetRec(ScrnInfoPtr pScrni); +void lx_clear_screen(ScrnInfoPtr pScrni, int width, int height, int bpp); +void lx_clear_fb(ScrnInfoPtr pScrni); +void lx_disable_dac_power(ScrnInfoPtr pScrni,int option); +void lx_enable_dac_power(ScrnInfoPtr pScrni,int option); + +#if DEBUGLVL>0 +FILE *zdfp = NULL; +#endif + +/* Reference: Video Graphics Suite Specification: + * VG Config Register (0x00) page 16 + * VG FP Register (0x02) page 18 */ + +#define LX_READ_VG(reg) ( outw(0xAC1C,0xFC53), outw(0xAC1C,0x0200|(reg)), inw(0xAC1E) ) + +/* panel resolutiosn decode of FP config reg */ + +static struct sLXFpResolution { + int xres, yres; +} lx_fp_resolution[] = { + { 320, 240 }, { 640, 480 }, { 800, 600 }, { 1024, 768 }, + { 1152, 864 }, { 1280, 1024 }, { 1600, 1200 }, { 0, 0 } +}; + +/* Get the information from the BIOS regarding the panel */ + +static int +lx_get_panel_info(int *xres, int *yres) +{ + unsigned short reg = LX_READ_VG(0x02); + *xres = lx_fp_resolution[(reg>>3) & 0x07].xres; + *yres = lx_fp_resolution[(reg>>3) & 0x07].yres; + return 0; +} + +static int +lx_panel_configured(void) +{ + unsigned short reg = LX_READ_VG(0x00); + unsigned char ret = (reg >> 8) & 0x7; + return (ret == 1) || (ret == 5) ? 1 : 0; +} + +void +LXSetupChipsetFPtr(ScrnInfoPtr pScrni) +{ +#if DEBUGLVL>0 + if( zdfp == NULL ) { zdfp = fopen("/tmp/xwin.log","w"); setbuf(zdfp,NULL); } +#endif + DEBUGMSG(1,(0, X_INFO, "LXSetupChipsetFPtr!\n")); + pScrni->PreInit = LXPreInit; + pScrni->ScreenInit = LXScreenInit; + pScrni->SwitchMode = LXSwitchMode; + pScrni->AdjustFrame = LXAdjustFrame; + pScrni->EnterVT = LXEnterVT; + pScrni->LeaveVT = LXLeaveVT; + pScrni->FreeScreen = LXFreeScreen; + pScrni->ValidMode = LXValidMode; +} + +#ifdef AMD_V4L2_VIDEO +void +LXInitVideo(ScreenPtr pScrn) +{ + GeodePtr pGeode; + int num_adaptors; + XF86VideoAdaptorPtr *adaptors; + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + pGeode = GEODEPTR(pScrni); + if (!pGeode->NoAccel) { + num_adaptors = xf86XVListGenericAdaptors(pScrni, &adaptors); + if( num_adaptors > 0 ) + xf86XVScreenInit(pScrn,adaptors,num_adaptors); + } +} +#else +extern void LXInitVideo(ScreenPtr pScrn); +#endif + +/*---------------------------------------------------------------------------- + * LXGetRec. + * + * Description :This function allocate an GeodeRec and hooked into + * pScrni str driverPrivate member of ScreeenInfo + * structure. + * Parameters. + * pScrni :Pointer handle to the screenonfo structure. + * + * Returns :allocated driver structure. + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +GeodePtr +LXGetRec(ScrnInfoPtr pScrni) +{ + if (!pScrni->driverPrivate) { + GeodePtr pGeode; + + pGeode = pScrni->driverPrivate = xnfcalloc(sizeof(GeodeRec), 1); +#if INT10_SUPPORT + pGeode->vesa = xcalloc(sizeof(VESARec), 1); +#endif + } + return GEODEPTR(pScrni); +} + +/*---------------------------------------------------------------------------- + * LXFreeRec. + * + * Description :This function deallocate an GeodeRec and freed from + * pScrni str driverPrivate member of ScreeenInfo + * structure. + * Parameters. + * pScrni :Pointer handle to the screenonfo structure. + * + * Returns :none + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static void +LXFreeRec(ScrnInfoPtr pScrni) +{ + if (pScrni->driverPrivate == NULL) { + return; + } + xfree(pScrni->driverPrivate); + pScrni->driverPrivate = NULL; +} + +/*---------------------------------------------------------------------------- + * LXSaveScreen. + * + * Description :This is todo the screen blanking + * + * Parameters. + * pScrn :Handle to ScreenPtr structure. + * mode :mode is used by vgaHWSaveScren to check blnak os on. + * + * Returns :TRUE on success and FALSE on failure. + * + * Comments :none +*---------------------------------------------------------------------------- +*/ +static Bool +LXSaveScreen(ScreenPtr pScrn, int mode) +{ + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + DEBUGMSG(0,(0, X_INFO, "LXSaveScreen!\n")); + + if (!pScrni->vtSema) + return vgaHWSaveScreen(pScrn, mode); + + return TRUE; +} + +static xf86MonPtr +LXProbeDDC(ScrnInfoPtr pScrni, int index) +{ + vbeInfoPtr pVbe; + xf86MonPtr ddc = NULL; + + if (xf86LoadSubModule(pScrni, "vbe")) { + pVbe = VBEInit(NULL, index); + ddc = vbeDoEDID(pVbe, NULL); + vbeFree(pVbe); + } + return ddc; +} + +static void +LXDecodeDDC(ScrnInfoPtr pScrni,xf86MonPtr ddc) +{ + int i; + DEBUGMSG(1,(0, X_INFO, + "Detected monitor DDC (%4s) id %d serno %d week %d year %d nsects %d\n", + &ddc->vendor.name[0],ddc->vendor.prod_id,ddc->vendor.serial, + ddc->vendor.week,ddc->vendor.year,ddc->no_sections)); + for( i=0; idet_mon[i]; + switch( dp->type ) { + case DT: { + struct detailed_timings *r = &dp->section.d_timings; + DEBUGMSG(1,(0, X_INFO, " mon det timing %0.3f %dx%d\n", + r->clock/1000000.0, r->h_active, r->v_active)); + DEBUGMSG(1,(0, X_INFO, " mon border %d,%d laced %d stereo %d sync %d, misc %d\n", + r->h_border, r->v_border, r->interlaced, r->stereo, r->sync, r->misc)); + } break; + case DS_SERIAL: { + char *serial_no = (char*)&dp->section.serial[0]; + DEBUGMSG(1,(0, X_INFO, " mon serial %13s\n",serial_no)); + } break; + case DS_ASCII_STR: { + char *ascii = (char*)&dp->section.ascii_data[0]; + DEBUGMSG(1,(0, X_INFO, " mon ascii_str %13s\n",ascii)); + } break; + case DS_NAME: { + char *name = (char*)&dp->section.name[0]; + DEBUGMSG(1,(0, X_INFO, " mon name %13s\n",name)); + } break; + case DS_RANGES: { + struct monitor_ranges *r = &dp->section.ranges; + DEBUGMSG(1,(0, X_INFO, " mon ranges v %d-%d h %d-%d clk %d\n", + r->min_v, r->max_v, r->min_h, r->max_h, r->max_clock)); + } break; + case DS_WHITE_P: { + struct whitePoints *wp = &dp->section.wp[0]; + DEBUGMSG(1,(0, X_INFO, " mon whitept %f,%f %f,%f idx %d,%d gamma %f,%f\n", + wp[1].white_x, wp[1].white_y, wp[2].white_x, wp[2].white_y, + wp[1].index, wp[2].index, wp[1].white_gamma, wp[2].white_gamma)); + } break; + case DS_STD_TIMINGS: { + struct std_timings *t = &dp->section.std_t[0]; + DEBUGMSG(1,(0, X_INFO, " mon std_timing no size @rate, id\n")); + for( i=0; i<5; ++i ) + DEBUGMSG(1,(0, X_INFO, " %d %5dx%-5d @%-4d %d\n", + i, t[i].hsize, t[i].vsize, t[i].refresh, t[i].id)); + } break; + } + } +} + +static void +LXFBAlloc(int fd,unsigned int offset, unsigned int size) +{ + cim_mem_req_t req; + memset(&req,0,sizeof(req)); + strcpy(&req.owner[0],"XFree86"); + sprintf(&req.name[0],"%08lx",offset); + req.flags = CIM_F_PUBLIC; + req.size = size; + ioctl(fd,CIM_RESERVE_MEM,&req); +} + +/* check for "tv-" or "pnl-" in mode name, decode suffix */ +/* return -1 if mode name is not a known tv/pnl mode */ +static int +lx_tv_mode(DisplayModePtr pMode) +{ + int tv_mode = -1; + char *bp, *cp; + cp = pMode->name; + if( (*(bp=cp) == 't' && *++bp == 'v') || + (*(bp=cp) == 'p' && *++bp == 'n' && *++bp == 'l') ) { + if( *++bp == '-' ) { + if( xf86NameCmp("ntsc",++bp) == 0 ) tv_mode = VG_TVMODE_NTSC; + else if( xf86NameCmp("pal",bp) == 0 ) tv_mode = VG_TVMODE_PAL; + else if( xf86NameCmp("6x4_ntsc",bp) == 0 ) tv_mode = VG_TVMODE_6X4_NTSC; + else if( xf86NameCmp("8x6_ntsc",bp) == 0 ) tv_mode = VG_TVMODE_8X6_NTSC; + else if( xf86NameCmp("10x7_ntsc",bp) == 0 ) tv_mode = VG_TVMODE_10X7_NTSC; + else if( xf86NameCmp("6x4_pal",bp) == 0 ) tv_mode = VG_TVMODE_6X4_PAL; + else if( xf86NameCmp("8x6_pal",bp) == 0 ) tv_mode = VG_TVMODE_8X6_PAL; + else if( xf86NameCmp("10x7_pal",bp) == 0 ) tv_mode = VG_TVMODE_10X7_PAL; + else if( xf86NameCmp("480p",bp) == 0 ) tv_mode = VG_TVMODE_480P; + else if( xf86NameCmp("720p",bp) == 0 ) tv_mode = VG_TVMODE_720P; + else if( xf86NameCmp("1080i",bp) == 0 ) tv_mode = VG_TVMODE_1080I; + } + } + return tv_mode; +} + +static int +lx_tv_mode_interlaced(int tv_mode) +{ + switch( tv_mode ) { + case VG_TVMODE_NTSC: + case VG_TVMODE_PAL: + case VG_TVMODE_1080I: + return 1; + } + return 0; +} + +/*---------------------------------------------------------------------------- + * LXPreInit. + * + * Description :This function is called only once ate teh server startup + * + * Parameters. + * pScrni :Handle to ScreenPtr structure. + * options :may be used to check the probeed one with config. + * + * Returns :TRUE on success and FALSE on failure. + * + * Comments :none. + *---------------------------------------------------------------------------- + */ +static Bool +LXPreInit(ScrnInfoPtr pScrni, int options) +{ + ClockRangePtr GeodeClockRange; + MessageType from; + int i = 0; + GeodePtr pGeode; + char *mod = NULL; + xf86MonPtr ddc = NULL; + Q_WORD msrValue; +#if CFB + char *reqSymbol = NULL; +#endif /* CFB */ + unsigned long offset, length, fb_top; + char dev_name[64], dev_owner[64]; + FILE *fp; int fd; +#if INT10_SUPPORT + VESAPtr pVesa; +#endif + unsigned int PitchInc, minPitch, maxPitch; + unsigned int minHeight, maxHeight; + unsigned int flags, fmt, high, low; + int tv_encoder, tv_bus_fmt, tv_601_fmt; + int tv_conversion, tvox, tvoy, tv_flags; + int tv_601_flags, tv_vsync_shift, tv_vsync_select; + int tv_vsync_shift_count; + const char *s; + char **modes; + OptionInfoRec *GeodeOptions = &LX_GeodeOptions[0]; + + /* + * Setup the ClockRanges, which describe what clock ranges are + * available, and what sort of modes they can be used for. + */ + GeodeClockRange = (ClockRangePtr)xnfcalloc(sizeof(ClockRange), 1); + GeodeClockRange->next = NULL; + GeodeClockRange->minClock = 25175; + GeodeClockRange->maxClock = 341350; + GeodeClockRange->clockIndex = -1; /* programmable */ + GeodeClockRange->interlaceAllowed = TRUE; + GeodeClockRange->doubleScanAllowed = FALSE; /* XXX check this */ + + /* Select valid modes from those available */ + minPitch = 1024; maxPitch = 8192; /* Can support upto 1920x1440 32Bpp */ + minHeight = 400; maxHeight = 2048; /* Can support upto 1920x1440 32Bpp */ + /* need height >= maxWidth for rotate */ + + DEBUGMSG(1,(0, X_INFO, "LXPreInit!\n")); + /* Allocate driver private structure */ + if (!(pGeode = LXGetRec(pScrni))) + return FALSE; + + DEBUGMSG(1, (0, X_NONE, "pGeode = %p\n", (void*)pGeode)); + + /* This is the general case */ + for (i = 0; i < pScrni->numEntities; i++) { + pGeode->pEnt = xf86GetEntityInfo(pScrni->entityList[i]); + if (pGeode->pEnt->resources) + return FALSE; + pGeode->Chipset = pGeode->pEnt->chipset; + pScrni->chipset = (char *)xf86TokenToString(GeodeChipsets, + pGeode->pEnt->chipset); + } + + if( (options & PROBE_DETECT) != 0 ) { + ConfiguredMonitor = LXProbeDDC(pScrni, pGeode->pEnt->index); + return TRUE; + } + +#if INT10_SUPPORT + if (!xf86LoadSubModule(pScrni, "int10")) + return FALSE; + xf86LoaderReqSymLists(amdInt10Symbols, NULL); +#endif + + /* If the vgahw module would be needed it would be loaded here */ + if (!xf86LoadSubModule(pScrni, "vgahw")) { + return FALSE; + } + xf86LoaderReqSymLists(amdVgahwSymbols, NULL); + DEBUGMSG(1,(0, X_INFO, "LXPreInit(1)!\n")); + /* Do the cimarron hardware detection */ + init_detect_cpu(&pGeode->cpu_version,&pGeode->cpu_revision); + + /* find the base chipset core. Currently there can be only one + * chip active at any time. + */ + if ((pGeode->cpu_version & 0xFF) != CIM_CPU_GEODELX) { + ErrorF("Chipset not GEODELX !!!\n"); + return FALSE; + } + pGeode->DetectedChipSet = LX; + DEBUGMSG(1,(0, X_INFO, "Detected BaseChip (%d)\n", pGeode->DetectedChipSet)); + + /* LX : Can have CRT or PANEL/TVO only */ + msr_read64(MSR_DEVICE_GEODELX_DF, MSR_GEODELINK_CONFIG, &msrValue); + fmt = (msrValue.low>>3) & 0x07; + switch( fmt ) { + case 4: + case 2: + case 0: + flags = LX_OT_CRT; + break; + case 1: + case 3: + case 5: + flags = LX_OT_FP; + if( (msrValue.low & 0x8000) != 0 ) flags |= LX_OT_CRT; + break; + case 6: + flags = LX_OT_VOP; + break; + case 7: + flags = LX_OT_DRGB; + break; + } + + /* currently supported formats */ + flags &= (LX_OT_FP | LX_OT_CRT | LX_OT_VOP); + /* can switch from crt/pnl vop, but not the other way */ + flags |= LX_OT_VOP; + pGeode->EnabledOutput = flags; + + xf86DrvMsg(0, X_INFO, "AMD LX Output Formats -%sCRT,%sVOP,%sFP,%sDRGB\n", + ((flags & LX_OT_CRT) ? " " : " No "), ((flags & LX_OT_VOP) ? " " : " No "), + ((flags & LX_OT_FP) ? " " : " No "), ((flags & LX_OT_DRGB)? " " : " No ")); + + pGeode->vid_version = CIM_CPU_GEODELX; + DEBUGMSG(1,(0, X_INFO, "LXPreInit(1.2)!\n")); + init_read_base_addresses (&(pGeode->InitBaseAddress)); + DEBUGMSG(1,(0, X_INFO, "LXPreInit(1.4)!\n")); + + pGeode->FBLinearAddr = pGeode->InitBaseAddress.framebuffer_base; + fb_top = pGeode->InitBaseAddress.framebuffer_size; + + if (pGeode->pEnt->device->videoRam == 0) { + from = X_PROBED; + pScrni->videoRam = fb_top / 1024; + } else { + pScrni->videoRam = pGeode->pEnt->device->videoRam; + from = X_CONFIG; + fb_top = pScrni->videoRam << 10; + } + + DEBUGMSG(1, (pScrni->scrnIndex, from, "VideoRam: %lu kByte\n", + (unsigned long)pScrni->videoRam)); + + pGeode->CmdBfrOffset = 0; + pGeode->CmdBfrSize = 0; + + /* try to cause modules to load now, to reserve fb mem for other drivers */ + pGeode->cimFd = open("/dev/cimarron",O_RDONLY); + if( pGeode->cimFd < 0 ) + pGeode->cimFd = open("/dev/cim",O_RDONLY); + DEBUGMSG(1, (pScrni->scrnIndex, X_INFO, "/dev/cimarron: fd=%d\n",pGeode->cimFd)); + if( (fd=open("/dev/video",O_RDONLY)) >= 0 ) close(fd); + if( (fd=open("/dev/video0",O_RDONLY)) >= 0 ) close(fd); + if( (fd=open("/dev/video1",O_RDONLY)) >= 0 ) close(fd); + if( (fd=open("/dev/video2",O_RDONLY)) >= 0 ) close(fd); + if( (fd=open("/dev/video3",O_RDONLY)) >= 0 ) close(fd); + if( (fd=open("/dev/video/video0",O_RDONLY)) >= 0 ) close(fd); + if( (fd=open("/dev/video/video1",O_RDONLY)) >= 0 ) close(fd); + if( (fd=open("/dev/video/video2",O_RDONLY)) >= 0 ) close(fd); + if( (fd=open("/dev/video/video3",O_RDONLY)) >= 0 ) close(fd); + + DEBUGMSG(1, (pScrni->scrnIndex, X_INFO, "open cim map\n")); + if( (fp=fopen("/proc/driver/cimarron/map","r")) != NULL ) { + low = 0; + high = fb_top; + + DEBUGMSG(1, (pScrni->scrnIndex, X_INFO, "scan cim map\n")); + while( fscanf(fp,"%63s %63s %x %lx %lx\n", + &dev_owner[0],&dev_name[0],&flags,&offset,&length) == 5 ) { + if( offset < pGeode->FBLinearAddr ) continue; + offset -= pGeode->FBLinearAddr; + if( (flags & CIM_F_CMDBUF) != 0 ) { + pGeode->CmdBfrOffset = offset; + pGeode->CmdBfrSize = length; + } + if( offset >= fb_top ) continue; + if( (flags & CIM_F_PRIVATE) != 0 ) + if( offset < high ) high = offset; + if( offset+length >= fb_top ) + length = fb_top - offset; + if( (flags & CIM_F_PUBLIC) != 0 || (flags & CIM_F_FREE) != 0 ) + if( offset+length > low ) low = offset+length; + } + fclose(fp); + fb_top = high < low ? high : low; + } + + DEBUGMSG(1,(0, X_INFO, "fb_top = %08lx\n", fb_top)); + DEBUGMSG(1, (pScrni->scrnIndex, X_INFO, + "cmd bfr (map) %08lx/%08lx\n",pGeode->CmdBfrOffset,pGeode->CmdBfrSize)); + + /* if cimarron module not reporting, use default buffer parameters */ + if( pGeode->CmdBfrSize == 0 ) { + if( fb_top < CIM_CMD_BFR_SZ ) { + ErrorF("No memory for CMD_BFR !!!\n"); + return FALSE; + } + pGeode->CmdBfrSize = CIM_CMD_BFR_SZ; + fb_top -= pGeode->CmdBfrSize; + pGeode->CmdBfrOffset = fb_top; + } + + if( pGeode->CmdBfrSize < CIM_CMD_BFR_MIN ) { + ErrorF("Not enough memory for CMD_BFR !!!\n"); + return FALSE; + } + DEBUGMSG(1, (pScrni->scrnIndex, X_INFO, + "cmd bfr (actual) %08lx/%08lx\n",pGeode->CmdBfrOffset,pGeode->CmdBfrSize)); + + /* now soak up all of the usable framebuffer memory */ + if( pGeode->cimFd >= 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_INFO, "alloc cim map\n")); + for(;;) { + if( (fp=fopen("/proc/driver/cimarron/map","r")) == NULL ) break; + low = fb_top; + high = 0; + while( fscanf(fp,"%63s %63s %x %lx %lx\n", + &dev_owner[0],&dev_name[0],&flags,&offset,&length) == 5 ) { + if( offset < pGeode->FBLinearAddr ) continue; + offset -= pGeode->FBLinearAddr; + if( offset >= fb_top ) continue; + if( (flags & CIM_F_FREE) == 0 ) continue; + if( low < offset ) continue; + low = offset; + if( offset+length > fb_top ) + length = fb_top - offset; + high = length; + } + fclose(fp); + if( high == 0 ) break; + LXFBAlloc(pGeode->cimFd,low,high); + } + DEBUGMSG(1, (pScrni->scrnIndex, X_INFO, "check cim map\n")); + /* only shared memory allowed below fb_top */ + if( (fp=fopen("/proc/driver/cimarron/map","r")) != NULL ) { + low = 0; + while( fscanf(fp,"%63s %63s %x %lx %lx\n", + &dev_owner[0],&dev_name[0],&flags,&offset,&length) == 5 ) { + if( offset < pGeode->FBLinearAddr ) continue; + offset -= pGeode->FBLinearAddr; + if( offset >= fb_top ) continue; + if( (flags&CIM_F_PUBLIC) == 0 ) { + low = 1; break; + } + } + fclose(fp); + if( low != 0 ) { + ErrorF("Not able to claim free FB memory !!!\n"); + return FALSE; + } + } + } + + pGeode->FBTop = fb_top; + if( fb_top < GP3_SCRATCH_BUFFER_SIZE ) { + ErrorF("No available FB memory !!!\n"); + return FALSE; + } + + /* must remove cimarron scratch buffer from FB */ + pGeode->FBAvail = fb_top - GP3_SCRATCH_BUFFER_SIZE; + + DEBUGMSG(1, (pScrni->scrnIndex, X_INFO, "FBAvail = %08lx\n",pGeode->FBAvail)); + if (pGeode->DetectedChipSet & LX) { + pGeode->cpu_reg_size = 0x4000; + pGeode->gp_reg_size = 0x4000; + pGeode->vg_reg_size = 0x4000; + pGeode->vid_reg_size = 0x4000; + pGeode->vip_reg_size = 0x4000; + } else { + pGeode->cpu_reg_size = 0x9000; + pGeode->vid_reg_size = 0x1000; + } + + if (!LXMapMem(pScrni)) + return FALSE; + + /* KFB will Knock of VGA */ + /* check if VGA is active */ + pGeode->FBVGAActive = gu3_get_vga_active(); + + DEBUGMSG(1, (0, X_PROBED, "VGA = %d\n", pGeode->FBVGAActive)); + + /* Fill in the monitor field */ + pScrni->monitor = pScrni->confScreen->monitor; + DEBUGMSG(1,(0, X_INFO, "LXPreInit(2)!\n")); + /* Determine depth, bpp, etc. */ + if (!xf86SetDepthBpp(pScrni, 8, 8, 8, Support24bppFb|Support32bppFb)) + return FALSE; + + if( !((pScrni->depth == 8) || (pScrni->depth == 16) || + (pScrni->depth == 24) || (pScrni->depth == 32))) { + DEBUGMSG(1, (pScrni->scrnIndex, X_ERROR, + "Given depth (%d bpp) is not supported by this driver\n", + pScrni->depth)); + return FALSE; + } + + /*This must happen after pScrni->display has been set + * * because xf86SetWeight references it. + */ + if (pScrni->depth > 8) { + /* The defaults are OK for us */ + rgb BitsPerComponent = { 0, 0, 0 }; + rgb BitMask = { 0, 0, 0 }; + + if (pScrni->depth > 16) { + /* we are operating in 24 bpp, Redcloud */ + BitsPerComponent.red = 8; + BitsPerComponent.green = 8; + BitsPerComponent.blue = 8; + + BitMask.red = 0xFF0000; + BitMask.green = 0x00FF00; + BitMask.blue = 0x0000FF; + } + if( xf86SetWeight(pScrni, BitsPerComponent, BitMask) == 0 ) + return FALSE; + } + + + xf86PrintDepthBpp(pScrni); + + DEBUGMSG(1,(0, X_INFO, "LXPreInit(3)!\n")); + + if (!xf86SetDefaultVisual(pScrni, -1)) + return FALSE; + + DEBUGMSG(1,(0, X_INFO, "LXPreInit(4)!\n")); + + /* The new cmap layer needs this to be initialized */ + if (pScrni->depth > 1) { + Gamma zeros = { 0.0, 0.0, 0.0 }; + + if (!xf86SetGamma(pScrni, zeros)) { + return FALSE; + } + } + DEBUGMSG(1,(0, X_INFO, "LXPreInit(5)!\n")); + + /* We use a programmable clock */ + pScrni->progClock = TRUE; + + /*Collect all of the relevant option flags + * *(fill in pScrni->options) + */ + xf86CollectOptions(pScrni, NULL); + + /*Process the options */ + xf86ProcessOptions(pScrni->scrnIndex, pScrni->options, + GeodeOptions); + +#if INT10_SUPPORT + pVesa = pGeode->vesa; + /* Initialize Vesa record */ + + if ((pVesa->pInt = xf86InitInt10(pGeode->pEnt->index)) == NULL) { + xf86DrvMsg(0, X_ERROR, "Int10 initialization failed.\n"); + return (FALSE); + } +#endif + + /*Set the bits per RGB for 8bpp mode */ + if (pScrni->depth == 8) { + /* Default to 8 */ + pScrni->rgbBits = 8; + } + from = X_DEFAULT; + + pGeode->FPGeomDstSet = 0; + if( (s=xf86GetOptValString(GeodeOptions, LX_OPTION_FP_DEST_GEOM)) != NULL ) { + char *sp; + int xres = strtoul(s,&sp,0); + if( sp != NULL && *sp == 'x' ) { + int yres = strtoul(sp+1,&sp,0); + if( sp != NULL && *sp == 0 ) { + if( xres > 0 && xres <= maxPitch && + yres >= minHeight && yres <= maxHeight ) { + pGeode->FPGeomDstSet = 1; + pGeode->FPGeomDstX = xres; + pGeode->FPGeomDstY = yres; + } + else + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "FP_DEST_GEOM \"%dx%d\" out of range\n",xres,yres)); + } + } + if( pGeode->FPGeomDstSet == 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "FP_DEST_GEOM \"%s\" not recognized\n",s)); + return FALSE; + } + pGeode->EnabledOutput |= LX_OT_FP; + } + + pGeode->FPGeomActSet = 0; + if( (s=xf86GetOptValString(GeodeOptions, LX_OPTION_FP_ACTIVE_GEOM)) != NULL ) { + char *sp; + int xres = strtoul(s,&sp,0); + if( sp != NULL && *sp == 'x' ) { + int yres = strtoul(sp+1,&sp,0); + if( sp != NULL && *sp == 0 ) { + if( xres > 0 && xres <= maxPitch && + yres >= minHeight && yres <= maxHeight ) { + pGeode->FPGeomActSet = 1; + pGeode->FPGeomActX = xres; + pGeode->FPGeomActY = yres; + } + else + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "FP_ACTIVE_GEOM \"%s\" out of range\n",s)); + } + } + if( pGeode->FPGeomActSet == 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "FP_ACTIVE_GEOM \"%s\" not recognized\n",s)); + return FALSE; + } + pGeode->EnabledOutput |= LX_OT_FP; + } + + if( (pGeode->EnabledOutput & LX_OT_FP) !=0 ) { + if( pGeode->FPGeomDstSet == 0 ) { + if( lx_panel_configured() == 0 ) { + ErrorF("Panel configured and enabled but not configured in BIOS !!!\n"); + return FALSE; + } + lx_get_panel_info(&pGeode->FPBiosResX, &pGeode->FPBiosResY); + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "FP Bios panel configuation used\n")); + pGeode->FPGeomDstX = pGeode->FPBiosResX; + pGeode->FPGeomDstY = pGeode->FPBiosResY; + } + if( pGeode->FPGeomActSet == 0 ) { + pGeode->FPGeomActX = pGeode->FPGeomDstX; + pGeode->FPGeomActY = pGeode->FPGeomDstY; + } + if( pGeode->FPGeomActX > pGeode->FPGeomDstX || + pGeode->FPGeomActY > pGeode->FPGeomDstY ) { + ErrorF("FP Geom params Active %dx%d bigger than Dest %dx%d\n", + pGeode->FPGeomActX,pGeode->FPGeomActY,pGeode->FPGeomDstX, pGeode->FPGeomDstY); + return FALSE; + } + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "FP Geom params Dest %dx%d, Active %dx%d\n", + pGeode->FPGeomDstX, pGeode->FPGeomDstY,pGeode->FPGeomActX,pGeode->FPGeomActY)); + } + + if (xf86IsOptionSet(GeodeOptions,LX_OPTION_FLATPANEL)) { + if (xf86ReturnOptValBool(GeodeOptions, LX_OPTION_FLATPANEL, TRUE)) { + if( (pGeode->EnabledOutput & LX_OT_FP) != 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "FlatPanel Selected\n")); + } + else + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "FlatPanel Selected, but not available - ignored\n")); + } + else { + if( (pGeode->EnabledOutput & LX_OT_FP) != 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "FlatPanel configured, but not enabled\n")); + pGeode->EnabledOutput &= ~LX_OT_FP; + } + } + } + + /* + * *The preferred method is to use the "hw cursor" option as a tri-state + * *option, with the default set above. + */ + pGeode->HWCursor = TRUE; + if (xf86GetOptValBool(GeodeOptions, LX_OPTION_HW_CURSOR, &pGeode->HWCursor)) { + from = X_CONFIG; + } + /* For compatibility, accept this too (as an override) */ + if (xf86ReturnOptValBool(GeodeOptions, LX_OPTION_SW_CURSOR, FALSE)) { + from = X_CONFIG; + pGeode->HWCursor = FALSE; + } + DEBUGMSG(1, (pScrni->scrnIndex, from, "Using %s cursor\n", + pGeode->HWCursor ? "HW" : "SW")); + + pGeode->Compression = TRUE; + if (xf86ReturnOptValBool(GeodeOptions, LX_OPTION_NOCOMPRESSION, FALSE)) { + pGeode->Compression = FALSE; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "NoCompression\n")); + } + + pGeode->NoAccel = FALSE; + if (xf86ReturnOptValBool(GeodeOptions, LX_OPTION_NOACCEL, FALSE)) { + pGeode->NoAccel = TRUE; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "Acceleration disabled\n")); + } + + if (!xf86GetOptValInteger(GeodeOptions, LX_OPTION_OSM_IMG_BUFS, + &(pGeode->NoOfImgBuffers))) + pGeode->NoOfImgBuffers = DEFAULT_IMG_LINE_BUFS; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "NoOfImgBuffers = %d\n", pGeode->NoOfImgBuffers)); + if (!xf86GetOptValInteger(GeodeOptions, LX_OPTION_OSM_CLR_BUFS, + &(pGeode->NoOfColorExpandLines))) + pGeode->NoOfColorExpandLines = DEFAULT_CLR_LINE_BUFS; + if( pGeode->NoOfColorExpandLines <= 0 ) + pGeode->NoOfColorExpandLines = 0; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "NoOfColorExpandLines = %d\n", pGeode->NoOfColorExpandLines)); + + pGeode->CustomMode = FALSE; + if (xf86ReturnOptValBool(GeodeOptions, LX_OPTION_CUSTOM_MODE, FALSE)) { + pGeode->CustomMode = TRUE; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "Custom mode enabled\n")); + } + + if (xf86IsOptionSet(GeodeOptions,LX_OPTION_CRTENABLE)) { + if (xf86ReturnOptValBool(GeodeOptions, LX_OPTION_CRTENABLE, TRUE)) { + if( (pGeode->EnabledOutput & LX_OT_FP) != 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "CRT Output Selected\n")); + } + else + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "CRT Output Selected, but not available - ignored\n")); + } + else { + if( (pGeode->EnabledOutput & LX_OT_CRT) != 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "CRT output configured, but not enabled\n")); + pGeode->EnabledOutput &= ~LX_OT_CRT; + } + } + } + + pGeode->TVSupport = FALSE; + if( (s=xf86GetOptValString(GeodeOptions, LX_OPTION_TV_ENCODER)) != NULL ) { + tv_encoder = -1; + if( xf86NameCmp(s,"ADV7171") == 0 ) + tv_encoder = VG_ENCODER_ADV7171; + else if( xf86NameCmp(s,"SAA7127") == 0 ) + tv_encoder = VG_ENCODER_SAA7127; + else if( xf86NameCmp(s,"FS454") == 0 ) + tv_encoder = VG_ENCODER_FS454; + else if( xf86NameCmp(s,"ADV7300") == 0 ) + tv_encoder = VG_ENCODER_ADV7300; + if( tv_encoder < 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "VOP output configured, but no encoder specified, VOP diabled\n")); + pGeode->EnabledOutput &= ~LX_OT_VOP; + } + else + pGeode->TVSupport = TRUE; + pGeode->tv_encoder = tv_encoder; + } + + /* If TV Supported then check for TVO support */ + if( pGeode->TVSupport != FALSE ) { + tv_bus_fmt = -1; + tv_601_fmt = -1; + if( (s=xf86GetOptValString(GeodeOptions, LX_OPTION_TV_BUS_FMT)) != NULL ) { + if( xf86NameCmp(s,"disabled") == 0 ) + tv_bus_fmt = VOP_MODE_DISABLED; + else if( xf86NameCmp(s,"vip11") == 0 ) + tv_bus_fmt = VOP_MODE_VIP11; + else if( xf86NameCmp(s,"ccir656") == 0 ) + tv_bus_fmt = VOP_MODE_CCIR656; + else if( xf86NameCmp(s,"vip20_8bit") == 0 ) + tv_bus_fmt = VOP_MODE_VIP20_8BIT; + else if( xf86NameCmp(s,"vip20_16bit") == 0 ) + tv_bus_fmt = VOP_MODE_VIP20_16BIT; + else if( xf86NameCmp(s,"601_yuv_8bit") == 0 ) { + tv_601_fmt = VOP_601_YUV_8BIT; + tv_bus_fmt = VOP_MODE_601; + } else if( xf86NameCmp(s,"601_yuv_16bit") == 0 ) { + tv_601_fmt = VOP_601_YUV_16BIT; + tv_bus_fmt = VOP_MODE_601; + } else if( xf86NameCmp(s,"601_rgb_8_8_8") == 0 ) { + tv_601_fmt = VOP_601_RGB_8_8_8; + tv_bus_fmt = VOP_MODE_601; + } else if( xf86NameCmp(s,"601_yuv_4_4_4") == 0 ) { + tv_601_fmt = VOP_601_YUV_4_4_4; + tv_bus_fmt = VOP_MODE_601; + } + } + if( tv_bus_fmt < 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "VOP output configured, but no bus format specified,\n" + "VOP bus format will depend on SD/HD mode\n")); + } + pGeode->tv_bus_fmt = tv_bus_fmt; + pGeode->tv_601_fmt = tv_601_fmt; + tv_flags = 0; + if( (s=xf86GetOptValString(GeodeOptions, LX_OPTION_TV_FLAGS)) != NULL ) { + char *opt, *sp = strdup(s); + if( sp != NULL ) { + for( opt=strtok(sp,":"); opt!=NULL; opt=strtok(NULL,":") ) { + if( xf86NameCmp(opt,"singlechipcompat") == 0 ) + tv_flags |= VOP_FLAG_SINGLECHIPCOMPAT; + else if( xf86NameCmp(opt,"extendedsav") == 0 ) + tv_flags |= VOP_FLAG_EXTENDEDSAV; + else if( xf86NameCmp(opt,"vbi") == 0 ) + tv_flags |= VOP_FLAG_VBI; + else if( xf86NameCmp(opt,"task") == 0 ) + tv_flags |= VOP_FLAG_TASK; + else if( xf86NameCmp(opt,"swap_uv") == 0 ) + tv_flags |= VOP_FLAG_SWAP_UV; + else if( xf86NameCmp(opt,"swap_vbi") == 0 ) + tv_flags |= VOP_FLAG_SWAP_VBI; + else + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "VOP flag \"%s\" not recognized\n",opt)); + } + free(sp); + } + } + tv_vsync_shift_count = 0; + tv_601_flags = 0; + tv_vsync_shift = VOP_VSYNC_NOSHIFT; + if( (s=xf86GetOptValString(GeodeOptions, LX_OPTION_TV_601_FLAGS)) != NULL ) { + char *opt, *sp = strdup(s); + if( sp != NULL ) { + for( opt=strtok(sp,":"); opt!=NULL; opt=strtok(NULL,":") ) { + if( xf86NameCmp(opt,"inv_de_pol") == 0 ) + tv_601_flags |= VOP_601_INVERT_DISPE; + else if( xf86NameCmp(opt,"inv_hs_pol") == 0 ) + tv_601_flags |= VOP_601_INVERT_HSYNC; + else if( xf86NameCmp(opt,"inv_vs_pol") == 0 ) + tv_601_flags |= VOP_601_INVERT_VSYNC; + else if( xf86NameCmp(opt,"vsync-4") == 0 ) + tv_vsync_shift = VOP_VSYNC_EARLIER_BY4; + else if( xf86NameCmp(opt,"vsync-2") == 0 ) + tv_vsync_shift = VOP_VSYNC_EARLIER_BY2; + else if( xf86NameCmp(opt,"vsync+0") == 0 ) + tv_vsync_shift = VOP_VSYNC_NOSHIFT; + else if( xf86NameCmp(opt,"vsync+2") == 0 ) { + tv_vsync_shift = VOP_VSYNC_LATER_BY_X; + tv_vsync_shift_count = 2; + } + else if( xf86NameCmp(opt,"vsync+4") == 0 ) { + tv_vsync_shift = VOP_VSYNC_LATER_BY_X; + tv_vsync_shift_count = 4; + } + else + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "VOP 601_flag \"%s\" not recognized\n",opt)); + } + free(sp); + } + } + tv_vsync_select = VOP_MB_SYNCSEL_DISABLED; + if( (s=xf86GetOptValString(GeodeOptions, LX_OPTION_TV_VSYNC_SELECT)) != NULL ) { + char *opt, *sp = strdup(s); + if( sp != NULL ) { + for( opt=strtok(sp,":"); opt!=NULL; opt=strtok(NULL,":") ) { + if( xf86NameCmp(opt,"disabled") == 0 ) + tv_vsync_select = VOP_MB_SYNCSEL_DISABLED; + else if( xf86NameCmp(opt,"vg") == 0 ) + tv_vsync_select = VOP_MB_SYNCSEL_VG; + else if( xf86NameCmp(opt,"vg_inv") == 0 ) + tv_vsync_select = VOP_MB_SYNCSEL_VG_INV; + else if( xf86NameCmp(opt,"statreg17") == 0 ) + tv_vsync_select = VOP_MB_SYNCSEL_STATREG17; + else if( xf86NameCmp(opt,"statreg17_inv") == 0 ) + tv_vsync_select = VOP_MB_SYNCSEL_STATREG17_INV; + else + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "VOP vsync_select \"%s\" not recognized\n",opt)); + } + free(sp); + } + } + pGeode->tv_flags = tv_flags; + pGeode->tv_601_flags = tv_601_flags; + pGeode->tv_vsync_shift = tv_vsync_shift; + pGeode->tv_vsync_shift_count = tv_vsync_shift_count; + pGeode->tv_vsync_select = tv_vsync_select; + tv_conversion = -1; + if( (s=xf86GetOptValString(GeodeOptions, LX_OPTION_TV_CONVERSION)) != NULL ) { + if( xf86NameCmp(s,"cosited") == 0 ) + tv_conversion = VOP_422MODE_COSITED; + else if( xf86NameCmp(s,"interspersed") == 0 ) + tv_conversion = VOP_422MODE_INTERSPERSED; + else if( xf86NameCmp(s,"alternating") == 0 ) + tv_conversion = VOP_422MODE_ALTERNATING; + else { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "VOP conversion \"%s\" not recognized\n",s)); + } + } + if( tv_conversion < 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "VOP output configured, but no conversion specified,\n" + "VOP conversion will defaults to \"cosited\"\n")); + tv_conversion = VOP_422MODE_COSITED; + } + pGeode->tv_conversion = tv_conversion; + tvox = tvoy = 0; + if( (s=xf86GetOptValString(GeodeOptions,LX_OPTION_TV_OVERSCAN)) != NULL ) { + char *opt, *sp = strdup(s); + if( sp != NULL ) { + if( (opt=strtok(sp,":")) != NULL ) tvox = strtol(opt,NULL,0); + if( (opt=strtok(NULL, ":")) != NULL) tvoy = strtol(opt,NULL,0); + free(sp); + } + DEBUGMSG(1, (0, X_CONFIG, "TVO %d %d\n", tvox,tvoy)); + } + pGeode->tvox = tvox; pGeode->tvoy = tvoy; + } + else if( (pGeode->EnabledOutput & LX_OT_VOP) != 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "VOP output enabled, but not configured, VOP diabled\n")); + pGeode->EnabledOutput &= ~LX_OT_VOP; + } + + if( (pGeode->EnabledOutput & LX_OT_CRT) != 0 ) { + ddc = LXProbeDDC(pScrni, pGeode->pEnt->index); + } + + flags = pGeode->EnabledOutput; + xf86DrvMsg(0, X_INFO, "AMD LX Active Formats -%sCRT,%sVOP,%sFP,%sDRGB\n", + ((flags & LX_OT_CRT) ? " " : " No "), ((flags & LX_OT_VOP) ? " " : " No "), + ((flags & LX_OT_FP) ? " " : " No "), ((flags & LX_OT_DRGB)? " " : " No ")); + + if( (pGeode->EnabledOutput & (LX_OT_CRT|LX_OT_FP|LX_OT_VOP)) == 0 ) { + ErrorF("No output enabled !!!\n"); + return FALSE; + } + + pGeode->ShadowFB = FALSE; + if (xf86ReturnOptValBool(GeodeOptions, LX_OPTION_SHADOW_FB, FALSE)) { + pGeode->ShadowFB = TRUE; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "Using \"Shadow Framebuffer\"\n")); + } + + pGeode->Rotate = 0; + if ((s = xf86GetOptValString(GeodeOptions, LX_OPTION_ROTATE))) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "Rotating - %s\n", s)); + if (!xf86NameCmp(s, "CW")) { + pGeode->Rotate = 1; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "Rotating screen clockwise\n")); + } + else if (!xf86NameCmp(s, "INVERT")) { + pGeode->Rotate = 2; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "Rotating screen inverted\n")); + } + else if (!xf86NameCmp(s, "CCW")) { + pGeode->Rotate = 3; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "Rotating screen counter clockwise\n")); + } + if( pGeode->Rotate != 0 ) { + pGeode->ShadowFB = TRUE; + } + else { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "\"%s\" is not a valid value for Option \"Rotate\"\n", s)); + DEBUGMSG(1, (pScrni->scrnIndex, X_INFO, + "Valid options are \"CW\", \"INVERT\", or \"CCW\"\n")); + } + } + + /* XXX Init further private data here */ + + /* + * * This shouldn't happen because such problems should be caught in + * * GeodeProbe(), but check it just in case. + */ + if (pScrni->chipset == NULL) { + DEBUGMSG(1, (pScrni->scrnIndex, X_ERROR, + "ChipID 0x%04X is not recognised\n", pGeode->Chipset)); + return FALSE; + } + if (pGeode->Chipset < 0) { + DEBUGMSG(1, (pScrni->scrnIndex, X_ERROR, + "Chipset \"%s\" is not recognised\n", + pScrni->chipset)); + return FALSE; + } + DEBUGMSG(1,(0, X_INFO, "LXPreInit(6)!\n")); + + /* + * * Init the screen with some values + */ + DEBUGMSG(1, (pScrni->scrnIndex, from, + "Video I/O registers at 0x%08lX\n", + (unsigned long)VGAHW_GET_IOBASE())); + + if (pScrni->memPhysBase == 0) { + from = X_PROBED; + pScrni->memPhysBase = pGeode->FBLinearAddr; + } + pScrni->fbOffset = 0; + + DEBUGMSG(1, (pScrni->scrnIndex, from, + "Linear framebuffer at 0x%08lX\n", + (unsigned long)pScrni->memPhysBase)); + + DEBUGMSG(1,(0, X_INFO, "LXPreInit(7)!\n")); + + /* + * * xf86ValidateModes will check that the mode HTotal and VTotal values + * * don't exceed the chipset's limit if pScrni->maxHValue adn + * * pScrni->maxVValue are set. Since our LXValidMode() + * * already takes care of this, we don't worry about setting them here. + */ + if (pScrni->depth > 16) { + PitchInc = 4096; + } else if (pScrni->depth == 16) { + PitchInc = 2048; + } else { + PitchInc = 1024; + } + PitchInc <<= 3; /* in bits */ + + /* by default use what user sets in the XF86Config file */ + modes = pScrni->display->modes; + + if( ddc != NULL && pScrni->monitor != NULL && pScrni->monitor->DDC == NULL ) { + pScrni->monitor->DDC = ddc; + LXDecodeDDC(pScrni,ddc); + } + + i = xf86ValidateModes(pScrni, pScrni->monitor->Modes, modes, GeodeClockRange, + NULL, minPitch, maxPitch, PitchInc, minHeight, maxHeight, + pScrni->display->virtualX, pScrni->display->virtualY, + pGeode->FBAvail, LOOKUP_BEST_REFRESH); + + DEBUGMSG(1, (pScrni->scrnIndex, from, "xf86ValidateModes:%d %d %d %d\n", + i, pScrni->virtualX, pScrni->virtualY, pScrni->displayWidth)); + if( i == -1 ) { + LXFreeRec(pScrni); + return FALSE; + } + DEBUGMSG(1,(0, X_INFO, "LXPreInit(8)!\n")); + + /* Prune the modes marked as invalid */ + xf86PruneDriverModes(pScrni); + + DEBUGMSG(1,(0, X_INFO, "LXPreInit(9)!\n")); + if( i == 0 || pScrni->modes == NULL ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_ERROR, "No valid modes found\n")); + LXFreeRec(pScrni); + return FALSE; + } + DEBUGMSG(1,(0, X_INFO, "LXPreInit(10)!\n")); + + xf86SetCrtcForModes(pScrni, 0); + DEBUGMSG(1,(0, X_INFO, "LXPreInit(11)!\n")); + + /* Set the current mode to the first in the list */ + pScrni->currentMode = pScrni->modes; + DEBUGMSG(1,(0, X_INFO, "LXPreInit(12)!\n")); + + /* Print the list of modes being used */ + xf86PrintModes(pScrni); + DEBUGMSG(1,(0, X_INFO, "LXPreInit(13)!\n")); + + /* Set the display resolution */ + xf86SetDpi(pScrni, 0, 0); + DEBUGMSG(1,(0, X_INFO, "LXPreInit(14)!\n")); + + /* Load bpp-specific modules */ + mod = NULL; + +#if CFB + /* Load bpp-specific modules */ + switch (pScrni->bitsPerPixel) { + case 8: + mod = "cfb"; + reqSymbol = "cfbScreenInit"; + break; + case 16: + mod = "cfb16"; + reqSymbol = "cfb16ScreenInit"; + break; + case 24: + mod = "cfb24"; + reqSymbol = "cfb24ScreenInit"; + break; + case 32: + mod = "cfb32"; + reqSymbol = "cfb32ScreenInit"; + break; + default: + return FALSE; + } + if (mod && xf86LoadSubModule(pScrni, mod) == NULL) { + LXFreeRec(pScrni); + return FALSE; + } + + xf86LoaderReqSymbols(reqSymbol, NULL); +#else + if (xf86LoadSubModule(pScrni, "fb") == NULL) { + LXFreeRec(pScrni); + return FALSE; + } + + xf86LoaderReqSymLists(amdFbSymbols, NULL); +#endif + DEBUGMSG(1,(0, X_INFO, "LXPreInit(15)!\n")); + if (pGeode->NoAccel == FALSE) { + if (!xf86LoadSubModule(pScrni, "xaa")) { + LXFreeRec(pScrni); + return FALSE; + } + xf86LoaderReqSymLists(amdXaaSymbols, NULL); + } + DEBUGMSG(1,(0, X_INFO, "LXPreInit(16)!\n")); + if (pGeode->HWCursor == TRUE) { + if (!xf86LoadSubModule(pScrni, "ramdac")) { + LXFreeRec(pScrni); + return FALSE; + } + xf86LoaderReqSymLists(amdRamdacSymbols, NULL); + } + DEBUGMSG(1,(0, X_INFO, "LXPreInit(17)!\n")); + /* Load shadowfb if needed */ + if (pGeode->ShadowFB) { + if (!xf86LoadSubModule(pScrni, "shadowfb")) { + LXFreeRec(pScrni); + return FALSE; + } + xf86LoaderReqSymLists(amdShadowSymbols, NULL); + } + DEBUGMSG(1,(0, X_INFO, "LXPreInit(18)!\n")); + if (xf86RegisterResources(pGeode->pEnt->index, NULL, ResExclusive)) { + DEBUGMSG(1, (pScrni->scrnIndex, X_ERROR, + "xf86RegisterResources() found resource conflicts\n")); + LXFreeRec(pScrni); + return FALSE; + } + LXUnmapMem(pScrni); + DEBUGMSG(1,(0, X_INFO, "LXPreInit ... done successfully!\n")); + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LXRestore. + * + * Description :This function restores the mode that was saved on server + entry + * Parameters. + * pScrni :Handle to ScreenPtr structure. + * Pmode :poits to screen mode + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static void +LXRestore(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + DEBUGMSG(0,(0, X_INFO, "LXRestore!\n")); + if (pGeode->FBVGAActive) { + vgaHWPtr pvgaHW = VGAHWPTR(pScrni); + + vgaHWProtect(pScrni, TRUE); + vgaHWRestore(pScrni, &pvgaHW->SavedReg, VGA_SR_ALL); + vgaHWProtect(pScrni, FALSE); + } +} + +/*---------------------------------------------------------------------------- + * LXCalculatePitchBytes. + * + * Description :This function restores the mode that was saved on server + * + * Parameters. + * pScrni :Handle to ScreenPtr structure. + * Pmode :Points to screenmode + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static int +LXCalculatePitchBytes(unsigned int width, unsigned int bpp) +{ + int lineDelta = width * (bpp >> 3); + + if (width < 640) { + /* low resolutions have both pixel and line doubling */ + DEBUGMSG(1, (0, X_PROBED, "lower resolution %d %d\n", + width, lineDelta)); + lineDelta <<= 1; + } + /* needed in Rotate mode when in accel is turned off */ + if (1) { /*!pGeode->NoAccel */ + if (lineDelta > 4096) + lineDelta = 8192; + else if (lineDelta > 2048) + lineDelta = 4096; + else if (lineDelta > 1024) + lineDelta = 2048; + else + lineDelta = 1024; + } + + DEBUGMSG(0, (0, X_INFO, "pitch %d %d\n", width, lineDelta)); + + return lineDelta; +} + +/*---------------------------------------------------------------------------- + * LXGetRefreshRate. + * + * Description :This function restores the mode that saved on server + * + * Parameters. + * Pmode :Pointer to the screen modes + * + * Returns :It returns the selected refresh rate. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static int +LXGetRefreshRate(DisplayModePtr pMode) +{ +#define THRESHOLD 2 + unsigned int i; + static int validRates[] = { 56, 60, 70, 72, 75, 85, 90, 100 }; /* Hz */ + unsigned long dotClock; + int refreshRate; + int selectedRate; + + dotClock = pMode->SynthClock * 1000; + refreshRate = dotClock / (pMode->CrtcHTotal * pMode->CrtcVTotal); + + if ((pMode->CrtcHTotal < 640) && (pMode->CrtcVTotal < 480)) + refreshRate >>= 2; /* double pixel and double scan */ + + DEBUGMSG(0, (0, X_INFO, "dotclock %lu %d\n", dotClock, refreshRate)); + + selectedRate = validRates[0]; + + for (i = 0; i < (sizeof(validRates) / sizeof(validRates[0])); i++) { + if (validRates[i] < (refreshRate + THRESHOLD)) { + selectedRate = validRates[i]; + } + } + return selectedRate; +} + +void +lx_clear_screen(ScrnInfoPtr pScrni, int width, int height, int bpp) +{ + /* no accels, mode is not yet set */ + GeodePtr pGeode = GEODEPTR(pScrni); + unsigned long offset = vg_get_display_offset(); + unsigned long pitch = vg_get_display_pitch(); + unsigned long n = width * ((bpp+7)>>3); + DEBUGMSG(0, (0, X_INFO, "clear screen %lx %d %d %d %lu %lu\n", offset,width,height,bpp,pitch,n)); + while( height > 0 ) { + memset(pGeode->FBBase+offset,0,n); + offset += pitch; + --height; + } +} + +void +lx_clear_fb(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + unsigned char *fb = pGeode->FBBase+pGeode->FBOffset; + memset(fb,0,pGeode->FBSize); + if( pGeode->ShadowPtr != NULL && pGeode->ShadowPtr != fb ) + memset(pGeode->ShadowPtr,0,pGeode->ShadowSize); +} + +static int +lx_set_tv_mode(ScrnInfoPtr pScrni,int tv_mode) +{ + int ret, bpp, flags; + int tv_conversion, tv_bus_fmt, tv_flags; + int tv_601_fmt, tv_601_flags; + int tv_vsync_shift, tv_vsync_shift_count, tv_vsync_select; + unsigned long src_width, src_height; + char *bp, *cp, *dp; + GeodePtr pGeode = GEODEPTR(pScrni); + VOPCONFIGURATIONBUFFER vopc; + bpp = pScrni->bitsPerPixel; + if( bpp == 32 ) bpp = 24; + flags = lx_tv_mode_interlaced(tv_mode) != 0 ? VG_MODEFLAG_INTERLACED : 0; + src_width = src_height = 0; + ret = vg_set_tv_mode(&src_width,&src_height, + pGeode->tv_encoder,tv_mode,bpp,flags,0,0); + DEBUGMSG(1, (0, X_INFO, + "Setting TV mode %lux%lu encoder=%d,bpp=%d,flags=%d,overscan %d,%d\n", + src_width,src_height,pGeode->tv_encoder,bpp,flags, + pGeode->tvox,pGeode->tvoy)); + ret = vg_set_tv_mode(&src_width,&src_height, + pGeode->tv_encoder,tv_mode,bpp,flags,pGeode->tvox,pGeode->tvoy); + + DEBUGMSG(1, (0, X_INFO, "Set TV mode ret=%d\n", ret)); + if( ret == 0 ) { + memset(&vopc,0,sizeof(vopc)); + tv_flags = pGeode->tv_flags; + tv_bus_fmt = pGeode->tv_bus_fmt; + tv_601_fmt = pGeode->tv_601_fmt; + tv_601_flags = pGeode->tv_601_flags; + tv_vsync_shift = pGeode->tv_vsync_shift; + tv_vsync_shift_count = pGeode->tv_vsync_shift_count; + tv_vsync_select = pGeode->tv_vsync_select; + tv_conversion = pGeode->tv_conversion; + if( tv_bus_fmt < 0 ) { + dp = "defaults"; + switch( tv_mode ) { + case VG_TVMODE_NTSC: case VG_TVMODE_6X4_NTSC: + case VG_TVMODE_8X6_NTSC: case VG_TVMODE_10X7_NTSC: + case VG_TVMODE_PAL: case VG_TVMODE_6X4_PAL: + case VG_TVMODE_8X6_PAL: case VG_TVMODE_10X7_PAL: + tv_bus_fmt = VOP_MODE_VIP11; + break; + default: + tv_bus_fmt = VOP_MODE_VIP20_16BIT; + break; + } + } + else + dp = "set"; + switch( tv_bus_fmt ) { + case VOP_MODE_VIP11: bp = "vop11"; break; + case VOP_MODE_CCIR656: bp = "ccir656"; break; + case VOP_MODE_VIP20_8BIT: bp = "vip20_8bit"; break; + case VOP_MODE_VIP20_16BIT: bp = "vip20_16bit"; break; + case VOP_MODE_601: + switch( tv_601_fmt ) { + default: tv_601_fmt = VOP_601_YUV_8BIT; + case VOP_601_YUV_8BIT: bp = "601_yuv_8bit"; break; + case VOP_601_YUV_16BIT: bp = "601_yuv_16bit"; break; + case VOP_601_RGB_8_8_8: bp = "601_rgb_8_8_8"; break; + case VOP_601_YUV_4_4_4: bp = "601_yuv_4_4_4"; break; + } + break; + default: tv_bus_fmt = VOP_MODE_DISABLED; + case VOP_MODE_DISABLED: bp = "disabled"; break; + } + switch( tv_conversion ) { + default: tv_conversion = VOP_422MODE_COSITED; + case VOP_422MODE_COSITED: cp = "cosited"; break; + case VOP_422MODE_INTERSPERSED: cp = "interspersed"; break; + case VOP_422MODE_ALTERNATING: cp = "alternating"; break; + } + vopc.flags = tv_flags; + vopc.mode = tv_bus_fmt; + vopc.conversion_mode = tv_conversion; + vopc.vsync_out = tv_vsync_select; + vopc.vop601.flags = tv_601_flags; + vopc.vop601.vsync_shift = tv_vsync_shift; + vopc.vop601.vsync_shift_count = tv_vsync_shift_count; + vopc.vop601.output_mode = tv_601_fmt; + DEBUGMSG(1, (0, X_INFO, + "Set TV mode %s to %s, conv %s, flags %x\n", + dp,bp,cp,tv_flags)); + DEBUGMSG(1, (0, X_INFO, + "Set TV 601 mode %x flags %x vsync shift %x/%x\n", + tv_601_fmt,tv_601_flags,tv_vsync_shift,tv_vsync_shift_count)); + vop_set_configuration(&vopc); + } + return ret; +} + +static int +lx_set_custom_mode(unsigned long bpp, unsigned long flags, + unsigned long hactive, unsigned long hblankstart, + unsigned long hsyncstart, unsigned long hsyncend, + unsigned long hblankend, unsigned long htotal, + unsigned long vactive, unsigned long vblankstart, + unsigned long vsyncstart, unsigned long vsyncend, + unsigned long vblankend, unsigned long vtotal, + unsigned long frequency) + +{ + VG_DISPLAY_MODE mode; + memset(&mode,0,sizeof(mode)); + mode.flags = flags; + mode.src_width = hactive; + mode.src_height = vactive; + mode.mode_width = hactive; + mode.mode_height = vactive; + mode.hactive = hactive; + mode.hblankstart = hblankstart; + mode.hsyncstart = hsyncstart; + mode.hsyncend = hsyncend; + mode.hblankend = hblankend; + mode.htotal = htotal; + mode.vactive = vactive; + mode.vblankstart = vblankstart; + mode.vsyncstart = vsyncstart; + mode.vsyncend = vsyncend; + mode.vblankend = vblankend; + mode.vtotal = vtotal; + mode.vactive_even = vactive; + mode.vblankstart_even = vblankstart; + mode.vsyncstart_even = vsyncstart; + mode.vsyncend_even = vsyncend; + mode.vblankend_even = vblankend; + mode.vtotal_even = vtotal; + mode.frequency = frequency; + return vg_set_custom_mode(&mode,bpp); +} + +/*---------------------------------------------------------------------------- + * LXSetMode. + * + * Description :This function sets parametrs for screen mode + * + * Parameters. + * pScrni :Pointer to the screenInfo structure. + * Pmode :Pointer to the screen modes + * + * Returns :TRUE on success and FALSE on Failure. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ + +static Bool +LXSetMode(ScrnInfoPtr pScrni, DisplayModePtr pMode) +{ + int bpp, bppx, rate, video_enable, tv_mode, opath; + unsigned long flags, srcw,srch, actw,acth, dstw,dsth, video_flags; + + GeodePtr pGeode = GEODEPTR(pScrni); + DF_VIDEO_SOURCE_PARAMS vs_odd, vs_even; + gp_wait_until_idle(); + /* disable video */ + df_get_video_enable(&video_enable,&video_flags); + if( video_enable != 0 ) df_set_video_enable(0,0); + df_get_video_source_configuration(&vs_odd, &vs_even); + lx_disable_dac_power(pScrni,DF_CRT_DISABLE); + + DEBUGMSG(1, (0, X_NONE, "LXSetMode! %p %p %p\n", + cim_gp_ptr, cim_vid_ptr, cim_fb_ptr)); + + /* Set the VT semaphore */ + pScrni->vtSema = TRUE; + + srcw = pMode->CrtcHDisplay; + srch = pMode->CrtcVDisplay; + bpp = pScrni->bitsPerPixel; + rate = LXGetRefreshRate(pMode); + /* otherwise color/chroma keying doesnt work */ + bppx = bpp == 32 ? 24 : bpp; + + /* The timing will be adjusted later */ + DEBUGMSG(1, (0, X_PROBED, + "Setting mode %dx%d %0.3f %d %d %d %d %d %d %d %d\n", + pMode->CrtcHDisplay, pMode->CrtcVDisplay, pMode->SynthClock/1000.0, + pMode->CrtcHDisplay, pMode->CrtcHSyncStart, pMode->CrtcHSyncEnd, pMode->CrtcHTotal, + pMode->CrtcVDisplay, pMode->CrtcVSyncStart, pMode->CrtcVSyncEnd, pMode->CrtcVTotal)); + DEBUGMSG(1,(0, X_INFO, "Set display mode: %lux%lu-%d (%dHz) Pitch %d/%d\n", + srcw,srch, bpp, rate, pGeode->Pitch,pGeode->AccelPitch)); + + opath = DF_DISPLAY_CRT; + if( (pGeode->EnabledOutput&LX_OT_FP) != 0 ) { + if( (pGeode->EnabledOutput&LX_OT_CRT) != 0 ) + opath = DF_DISPLAY_CRT_FP; + else + opath = DF_DISPLAY_FP; + } + + if( pGeode->TVSupport && (tv_mode=lx_tv_mode(pMode)) >= 0 ) { + DEBUGMSG(1, (0, X_INFO, "Set TV mode %d\n",tv_mode)); + lx_set_tv_mode(pScrni,tv_mode); + opath = DF_DISPLAY_VOP; + } + else if( pGeode->CustomMode != 0 ) { + DEBUGMSG(1, (0, X_PROBED, "Setting Custom mode\n")); + flags = 0; + if( (pMode->Flags & V_NHSYNC) != 0 ) flags |= VG_MODEFLAG_NEG_HSYNC; + if( (pMode->Flags & V_NVSYNC) != 0 ) flags |= VG_MODEFLAG_NEG_VSYNC; + lx_set_custom_mode(bppx, flags, + pMode->CrtcHDisplay, pMode->CrtcHBlankStart, pMode->CrtcHSyncStart, + pMode->CrtcHSyncEnd, pMode->CrtcHBlankEnd, pMode->CrtcHTotal, + pMode->CrtcVDisplay, pMode->CrtcVBlankStart, pMode->CrtcVSyncStart, + pMode->CrtcVSyncEnd, pMode->CrtcVBlankEnd, pMode->CrtcVTotal, + (int)((pMode->SynthClock/1000.0)*0x10000)); + } + else if( (pGeode->EnabledOutput&LX_OT_FP) != 0 ) { + /* display is fp */ + actw = pGeode->FPGeomActX; dstw = pGeode->FPGeomDstX; + acth = pGeode->FPGeomActY; dsth = pGeode->FPGeomDstY; + flags = (pGeode->EnabledOutput&LX_OT_CRT) != 0 ? VG_MODEFLAG_CRT_AND_FP : 0; + /* cant do scaling if width > 1024 (hw bfr size limitation) */ + if( srcw > 1024 ) { + if( srcw != actw ) + DEBUGMSG(1, (0, X_PROBED, "FPGeomSrcX > 1024, scaling disabled\n")); + actw = srcw; acth = srch; + vg_set_border_color(0); + } + DEBUGMSG(1, (0, X_PROBED, "Setting Display for TFT %lux%lu %lux%lu %lux%lu %d\n", + srcw,srch, actw,acth, dstw,dsth, pScrni->bitsPerPixel)); + vg_set_panel_mode(srcw,srch, actw,acth, dstw,dsth, bppx, flags); + } + else { + /* display is crt */ + DEBUGMSG(1, (0, X_PROBED, "Setting Display for CRT %lux%lu-%d@%d\n", + srcw, srch, bppx, LXGetRefreshRate(pMode))); + vg_set_display_mode(srcw,srch, srcw,srch, bppx, LXGetRefreshRate(pMode),0); + } + + df_set_output_path(opath); + vg_set_display_pitch(pGeode->Pitch); + gp_set_bpp(pScrni->bitsPerPixel); + + vg_set_display_offset(0L); + vg_wait_vertical_blank(); + + DEBUGMSG(1, (0, X_PROBED, "Display mode set\n")); + /* enable compression if option selected */ + if( pGeode->Compression != 0 ) { + DEBUGMSG(1, (0, X_PROBED, "Compression mode set %d\n", pGeode->Compression)); + /* set the compression parameters,and it will be turned on later. */ + vg_configure_compression(&(pGeode->CBData)); + + /* set the compression buffer, all parameters already set */ + vg_set_compression_enable(1); + } + + if( pGeode->HWCursor != 0 ) { + VG_PANNING_COORDINATES panning; + /* Load blank cursor */ + LXLoadCursorImage(pScrni, NULL); + vg_set_cursor_position(0, 0, &panning); + LXShowCursor(pScrni); + } + + DEBUGMSG(1,(0, X_INFO, "setting mode done.\n")); + + vg_set_display_offset(pGeode->PrevDisplayOffset); + + /* Restore the contents in the screen info */ + DEBUGMSG(1,(0, X_INFO, "After setting the mode\n")); + switch( pGeode->Rotate ) { + case 1: + case 3: + pGeode->HDisplay = pMode->VDisplay; + pGeode->VDisplay = pMode->HDisplay; + break; + default: + pGeode->HDisplay = pMode->HDisplay; + pGeode->VDisplay = pMode->VDisplay; + break; + } + + df_configure_video_source(&vs_odd,&vs_even); + if( video_enable != 0 ) + df_set_video_enable(video_enable,video_flags); + lx_enable_dac_power(pScrni,1); + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LXEnterGraphics. + * + * Description :This function will intiallize the displaytiming + structure for nextmode and switch to VGA mode. + * + * Parameters. + * pScrn :Screen information will be stored in this structure. + * pScrni :Pointer to the screenInfo structure. + * + * Returns :TRUE on success and FALSE on Failure. + * + * Comments :gfx_vga_mode_switch() will start and end the + * switching based on the arguments 0 or 1.soft_vga + * is disabled in this function. +*---------------------------------------------------------------------------- +*/ +static Bool +LXEnterGraphics(ScreenPtr pScrn, ScrnInfoPtr pScrni) +{ + int bpp; + unsigned long cmd_bfr_phys; + GeodePtr pGeode = GEODEPTR(pScrni); + vgaHWPtr pvgaHW = VGAHWPTR(pScrni); + + DEBUGMSG(1,(0, X_INFO, "LXEnterGraphics.\n")); + + gp_wait_until_idle(); + cmd_bfr_phys = pGeode->InitBaseAddress.framebuffer_base + pGeode->CmdBfrOffset; + cim_cmd_base_ptr = cim_fb_ptr + pGeode->CmdBfrOffset; + gp_set_frame_buffer_base(pGeode->InitBaseAddress.framebuffer_base,pGeode->FBTop); + gp_set_command_buffer_base(cmd_bfr_phys,0,pGeode->CmdBfrSize); + + lx_disable_dac_power(pScrni,DF_CRT_DISABLE); + /* Save CRT State */ + vg_get_current_display_mode(&pGeode->FBcimdisplaytiming.vgDisplayMode, &bpp); + pGeode->FBcimdisplaytiming.wBpp = bpp; + + pGeode->FBcimdisplaytiming.wPitch = vg_get_display_pitch(); + + /* Save Display offset */ + pGeode->FBDisplayOffset = vg_get_display_offset(); + pGeode->FBBIOSMode = pvgaHW->readCrtc(pvgaHW, 0x040); + DEBUGMSG(1,(0, X_INFO, "FBBIOSMode %d\n", pGeode->FBBIOSMode)); + + /* Save the current Compression state */ + pGeode->FBCompressionEnable = vg_get_compression_enable(); + + vg_get_compression_info (&(pGeode->FBCBData)); + + /* Save Cursor offset */ + vg_get_cursor_info(&pGeode->FBCursor); + + /* only if comming from VGA */ + if (pGeode->FBVGAActive) { + unsigned short sequencer; + vgaHWPtr pvgaHW = VGAHWPTR(pScrni); + + /* Map VGA aperture */ + if (!vgaHWMapMem(pScrni)) + return FALSE; + + /* Unlock VGA registers */ + vgaHWUnlock(pvgaHW); + + /* Save the current state and setup the current mode */ + vgaHWSave(pScrni, &VGAHWPTR(pScrni)->SavedReg, VGA_SR_ALL); + + /* DISABLE VGA SEQUENCER */ + /* This allows the VGA state machine to terminate. We must delay */ + /* such that there are no pending MBUS requests. */ + + cim_outb(DC3_SEQUENCER_INDEX, DC3_SEQUENCER_CLK_MODE); + sequencer = cim_inb(DC3_SEQUENCER_DATA); + sequencer |= DC3_CLK_MODE_SCREEN_OFF; + cim_outb(DC3_SEQUENCER_DATA, sequencer); + + vg_delay_milliseconds(1); + + /* BLANK THE VGA DISPLAY */ + cim_outw(DC3_SEQUENCER_INDEX, DC3_SEQUENCER_RESET); + sequencer = cim_inb(DC3_SEQUENCER_DATA); + sequencer &= ~DC3_RESET_VGA_DISP_ENABLE; + cim_outb(DC3_SEQUENCER_DATA, sequencer); + + vg_delay_milliseconds(1); + } + + lx_clear_fb(pScrni); + + if (!LXSetMode(pScrni, pScrni->currentMode)) { + return FALSE; + } + + lx_enable_dac_power(pScrni,1); + return TRUE; +} + +void +lx_disable_dac_power(ScrnInfoPtr pScrni,int option) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + if( (pGeode->EnabledOutput&LX_OT_FP) != 0 ) + df_set_panel_enable(0); + if( (pGeode->EnabledOutput&LX_OT_CRT) != 0 ) { + if( (pGeode->EnabledOutput&LX_OT_FP) != 0 ) + /* wait for the panel to be fully powered off */ + while( (READ_VID32(DF_POWER_MANAGEMENT) & 2) == 0 ); + df_set_crt_enable(option); + } +} + +void +lx_enable_dac_power(ScrnInfoPtr pScrni, int option) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + df_set_crt_enable(DF_CRT_ENABLE); + if( option != 0 && (pGeode->EnabledOutput&LX_OT_CRT) == 0 ) { + unsigned int misc = READ_VID32(DF_VID_MISC); + misc |= DF_DAC_POWER_DOWN; + WRITE_VID32(DF_VID_MISC, misc); + } + if( (pGeode->EnabledOutput&LX_OT_FP) != 0 ) + df_set_panel_enable(1); +} + +/*---------------------------------------------------------------------------- + * LXLeaveGraphics: + * + * Description :This function will restore the displaymode parameters + * and switches the VGA mode + * + * Parameters. + * pScrni :Pointer to the screenInfo structure. + * + * Returns :none. +*---------------------------------------------------------------------------- +*/ +static void +LXLeaveGraphics(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + gp_wait_until_idle(); + + /* Restore VG registers */ + lx_disable_dac_power(pScrni,DF_CRT_DISABLE); + vg_set_custom_mode(&(pGeode->FBcimdisplaytiming.vgDisplayMode), + pGeode->FBcimdisplaytiming.wBpp); + + vg_set_compression_enable(0); + + /* Restore the previous Compression state */ + if (pGeode->FBCompressionEnable) { + vg_configure_compression(&(pGeode->FBCBData)); + vg_set_compression_enable(1); + } + + vg_set_display_pitch(pGeode->FBcimdisplaytiming.wPitch); + + vg_set_display_offset(pGeode->FBDisplayOffset); + + /* Restore Cursor */ + { VG_PANNING_COORDINATES panning; + vg_set_cursor_position(pGeode->FBCursor.cursor_x,pGeode->FBCursor.cursor_y,&panning); } + + /* For the moment, always do an int 10 */ + +#if INT10_SUPPORT + pGeode->vesa->pInt->num = 0x10; + pGeode->vesa->pInt->ax = 0x0 | pGeode->FBBIOSMode; + pGeode->vesa->pInt->bx = 0; + xf86ExecX86int10(pGeode->vesa->pInt); +#endif + vg_delay_milliseconds(3); + LXRestore(pScrni); + + lx_enable_dac_power(pScrni,0); +} + +/*---------------------------------------------------------------------------- + * LXCloseScreen. + * + * Description :This function will restore the original mode + * and also it unmap video memory + * + * Parameters. + * ScrnIndex :Screen index value of the screen will be closed. + * pScrn :Pointer to the screen structure. + * + * + * Returns :TRUE on success and FALSE on Failure. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static Bool +LXCloseScreen(int scrnIndex, ScreenPtr pScrn) +{ + ScrnInfoPtr pScrni = xf86Screens[scrnIndex]; + GeodePtr pGeode = GEODEPTR(pScrni); + + if( pGeode->ShadowPtr && !pGeode->ShadowInFBMem ) + xfree(pGeode->ShadowPtr); + + DEBUGMSG(1, (scrnIndex, X_PROBED, "LXCloseScreen %d\n", + pScrni->vtSema)); + if (pScrni->vtSema) + LXLeaveGraphics(pScrni); + + if (pGeode->AccelInfoRec) + XAADestroyInfoRec(pGeode->AccelInfoRec); + + if (pGeode->AccelImageWriteBuffers) { +#if LX_USE_OFFSCRN_MEM + xfree(pGeode->AccelImageWriteBuffers[0]); +#endif + xfree(pGeode->AccelImageWriteBuffers); + pGeode->AccelImageWriteBuffers = NULL; + } + if (pGeode->AccelColorExpandBuffers) { + xfree(pGeode->AccelColorExpandBuffers[0]); + xfree(pGeode->AccelColorExpandBuffers); + pGeode->AccelColorExpandBuffers = NULL; + } + pScrni->vtSema = FALSE; + + LXUnmapMem(pScrni); + + if (pGeode && (pScrn->CloseScreen = pGeode->CloseScreen)) { + pGeode->CloseScreen = NULL; + return ((*pScrn->CloseScreen)(scrnIndex,pScrn)); + } + return TRUE; +} + +#ifdef DPMSExtension +/*---------------------------------------------------------------------------- + * LXDPMSSet. + * + * Description :This function sets geode into Power Management + * Signalling mode. + * + * Parameters. + * pScrni :Pointer to screen info strucrure. + * mode :Specifies the power management mode. + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static void +LXDPMSSet(ScrnInfoPtr pScrni, int mode, int flags) +{ + GeodePtr pGeode; + + pGeode = GEODEPTR(pScrni); + + DEBUGMSG(1,(0, X_INFO, "LXDPMSSet!\n")); + + /* Check if we are actively controlling the display */ + if (!pScrni->vtSema) { + ErrorF("LXDPMSSet called when we not controlling the VT!\n"); + return; + } + switch (mode) { + case DPMSModeOn: /* Screen: On; HSync: On; VSync: On */ + lx_enable_dac_power(pScrni,1); + break; + + case DPMSModeStandby: /* Screen: Off; HSync: Off; VSync: On */ + lx_disable_dac_power(pScrni,DF_CRT_STANDBY); + break; + + case DPMSModeSuspend: /* Screen: Off; HSync: On; VSync: Off */ + lx_disable_dac_power(pScrni,DF_CRT_SUSPEND); + break; + case DPMSModeOff: /* Screen: Off; HSync: Off; VSync: Off */ + lx_disable_dac_power(pScrni,DF_CRT_DISABLE); + break; + } +} +#endif + +/*---------------------------------------------------------------------------- + * LXScreenInit. + * + * Description :This function will be called at the each ofserver + * generation. + * + * Parameters. + * scrnIndex :Specfies the screenindex value during generation. + * pScrn :Pointer to screen strucrure. + * argc :parameters for command line arguments count + * argv :command line arguments if any it is not used. + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static Bool +LXScreenInit(int scrnIndex, ScreenPtr pScrn, int argc, char **argv) +{ + int i, bytpp, size, fbsize, fboffset, fbavail; + int pitch, displayWidth, virtualX, virtualY; + int HDisplay, VDisplay, maxHDisplay, maxVDisplay, maxX, maxY; + unsigned char *FBStart, **ap, *bp; + DisplayModePtr p; + GeodePtr pGeode; + VisualPtr visual; + BoxRec AvailBox; + RegionRec OffscreenRegion; + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + Bool Inited = FALSE; + + DEBUGMSG(1,(0, X_INFO, "LXScreenInit!\n")); + /* Get driver private */ + pGeode = LXGetRec(pScrni); + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(0)!\n")); + /* + * * Allocate a vgaHWRec + */ + + if (!vgaHWGetHWRec(pScrni)) + return FALSE; + if (!vgaHWMapMem(pScrni)) + return FALSE; + + vgaHWGetIOBase(VGAHWPTR(pScrni)); + + if (!LXMapMem(pScrni)) + return FALSE; + + pGeode->Pitch = LXCalculatePitchBytes(pScrni->virtualX, + pScrni->bitsPerPixel); + pGeode->AccelPitch = pGeode->Pitch; + bytpp = (pScrni->bitsPerPixel+7)/8; + + /* start of framebuffer for accels */ + fboffset = 0; + fbavail = pGeode->FBAvail; + + /* allocate display frame buffer at zero offset */ + fbsize = pScrni->virtualY * pGeode->Pitch; + pGeode->FBSize = fbsize; + + pGeode->CursorSize = (HW_CURSOR_W*HW_CURSOR_H)/8*2; + pGeode->CursorStartOffset = 0; + + DEBUGMSG(1, (scrnIndex, X_PROBED,"%d %d %d\n", + pScrni->virtualX, pScrni->bitsPerPixel, pGeode->Pitch)); + + HDisplay = pScrni->currentMode->HDisplay; + VDisplay = pScrni->currentMode->VDisplay; + pGeode->orig_virtX = pScrni->virtualX; + pGeode->orig_virtY = pScrni->virtualY; + + p = pScrni->modes; + maxHDisplay = p->HDisplay; + maxVDisplay = p->VDisplay; + while( (p=p->next)!=pScrni->modes ) { + if( maxHDisplay < p->HDisplay ) maxHDisplay = p->HDisplay; + if( maxVDisplay < p->VDisplay ) maxVDisplay = p->VDisplay; + } + DEBUGMSG(1, (scrnIndex, X_PROBED,"maxHDisplay %d maxVDisplay %d\n",maxHDisplay,maxVDisplay)); + + switch( pGeode->Rotate ) { + case 1: + case 3: + pGeode->HDisplay = VDisplay; + pGeode->VDisplay = HDisplay; + virtualX = pScrni->virtualY; + virtualY = pScrni->virtualX; + maxX = maxVDisplay; + maxY = maxHDisplay; + break; + default: + pGeode->HDisplay = HDisplay; + pGeode->VDisplay = VDisplay; + virtualX = pScrni->virtualX; + virtualY = pScrni->virtualY; + maxX = maxHDisplay; + maxY = maxVDisplay; + break; + } + + /* shadow may be first in FB, since accels render there */ + + pGeode->ShadowPtr = NULL; + if( pGeode->ShadowFB ) { + if( !pGeode->PointerMoved ) { + pGeode->PointerMoved = pScrni->PointerMoved; + pScrni->PointerMoved = LXPointerMoved; + } + if( !pGeode->NoAccel ) { + pGeode->ShadowPitch = LXCalculatePitchBytes(virtualX,pScrni->bitsPerPixel); + size = pGeode->ShadowPitch * virtualY; + if( size <= fbavail-fbsize ) { + pGeode->ShadowPtr = (unsigned char *)pGeode->FBBase + fboffset; + pGeode->AccelPitch = pGeode->ShadowPitch; + pGeode->ShadowSize = size; + pGeode->ShadowInFBMem = TRUE; + fboffset += size; + fbavail -= size; + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Shadow FB, No FB Memory, trying offscreen\n"); + } + } + if( pGeode->ShadowPtr == NULL ) { + pGeode->ShadowPitch = BitmapBytePad(pScrni->bitsPerPixel*virtualX); + size = pGeode->ShadowPitch * virtualY; + pGeode->ShadowPtr = xalloc(size); + if( pGeode->ShadowPtr != NULL ) { + pGeode->ShadowSize = size; + pGeode->ShadowInFBMem = FALSE; + if( !pGeode->NoAccel ) { + pGeode->NoAccel = TRUE; + pGeode->HWCursor = FALSE; + xf86DrvMsg(scrnIndex, X_ERROR, "Shadow FB offscreen, All Accels disabled\n"); + } + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Shadow FB, No offscreen Memory, disabled\n"); + pGeode->ShadowFB = FALSE; + pGeode->Rotate = 0; + pGeode->HDisplay = HDisplay; + pGeode->VDisplay = VDisplay; + virtualX = pScrni->virtualX; + virtualY = pScrni->virtualY; + } + } + } + + if( pGeode->ShadowPtr != NULL ) { + displayWidth = pGeode->ShadowPitch / bytpp; + FBStart = pGeode->ShadowPtr; + DEBUGMSG(1, (0, X_PROBED, "Shadow %p \n", FBStart)); + } + else { + displayWidth = pGeode->Pitch / bytpp; + FBStart = pGeode->FBBase; + DEBUGMSG(1, (0, X_PROBED, "FBStart %p \n", FBStart)); + } + + DEBUGMSG(1, (0, X_PROBED, "FB display %X size %X \n",fboffset,fbsize)); + pGeode->FBOffset = fboffset; /* offset of display framebuffer */ + pScrni->fbOffset = fboffset; + fboffset += fbsize; + fbavail -= fbsize; + + if( pGeode->Compression ) { /* Compression enabled */ + pGeode->CBData.size = 512+32; + pGeode->CBData.pitch = 512+32; + size = maxY*pGeode->CBData.pitch; + DEBUGMSG(1, (0, X_PROBED, "CB %#x size %#x (%d*%lu)\n",fboffset,size,maxY,pGeode->CBData.pitch)); + if( size <= fbavail ) { + pGeode->CBData.compression_offset = fboffset; + fboffset += size; + fbavail -= size; + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Compression, No FB Memory, disabled\n"); + pGeode->Compression = FALSE; + } + } + + if( pGeode->HWCursor ) { /* HWCursor enabled */ + size = pGeode->CursorSize; + if( size <= fbavail ) { + pGeode->CursorStartOffset = fboffset; + fboffset += size; + fbavail -= size; + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "HWCursor, No FB Memory, disabled\n"); + pGeode->HWCursor = FALSE; + } + } + + if( !pGeode->NoAccel ) { /* Acceleration enabled */ + if( pGeode->NoOfImgBuffers > 0 ) { + pGeode->AccelImageWriteBuffers = NULL; + pitch = pGeode->AccelPitch; + size = pitch * pGeode->NoOfImgBuffers; +#if !LX_USE_OFFSCRN_MEM + if( size <= fbavail ) { + bp = (unsigned char *)pGeode->FBBase + fboffset; + ap = xalloc(sizeof(pGeode->AccelImageWriteBuffers[0]) * pGeode->NoOfImgBuffers); + if( ap != NULL ) { + for( i=0; iNoOfImgBuffers; ++i ) { + ap[i] = bp; + bp += pitch; + } + pGeode->AccelImageWriteBuffers = ap; + fboffset += size; + fbavail -= size; + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Image Write, No Memory\n"); + } + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Image Write, No FB Memory\n"); + } +#else + if( (bp=(unsigned char *)xalloc(size)) != NULL ) { + ap = xalloc(sizeof(pGeode->AccelImageWriteBuffers[0]) * pGeode->NoOfImgBuffers); + if( ap != NULL ) { + for( i=0; iNoOfImgBuffers; ++i ) { + ap[i] = bp; + bp += pitch; + } + pGeode->AccelImageWriteBuffers = ap; + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Image Write, No Memory\n"); + } + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Image Write, No offscreen Memory\n"); + } +#endif + if( pGeode->AccelImageWriteBuffers == NULL ) { + xf86DrvMsg(scrnIndex, X_ERROR, "Accel Image Write disabled\n"); + pGeode->NoOfImgBuffers = 0; + } + } + + if (pGeode->NoOfColorExpandLines > 0) { + pGeode->AccelColorExpandBuffers = NULL; + pitch = ((pGeode->AccelPitch+31) >> 5) << 2; + size = pitch * pGeode->NoOfColorExpandLines; + if( (bp=(unsigned char *)xalloc(size)) != NULL ) { + ap = xalloc(sizeof(pGeode->AccelColorExpandBuffers[0]) * pGeode->NoOfColorExpandLines); + if( ap != NULL ) { + for( i=0; iNoOfColorExpandLines; ++i ) { + ap[i] = bp; + bp += pitch; + } + pGeode->AccelColorExpandBuffers = ap; + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Color Expansion, No Memory\n"); + } + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Color Expansion, No offscreen Memory\n"); + } + if( pGeode->AccelColorExpandBuffers == NULL ) { + xf86DrvMsg(scrnIndex, X_ERROR, "Accel Color Expansion disabled\n"); + pGeode->NoOfColorExpandLines = 0; + } + } + } + else { + pGeode->NoOfImgBuffers = 0; + pGeode->AccelImageWriteBuffers = NULL; + pGeode->NoOfColorExpandLines = 0; + pGeode->AccelColorExpandBuffers = NULL; + } + + /* Initialise graphics mode */ + if (!LXEnterGraphics(pScrn, pScrni)) + return FALSE; + + pScrni->virtualX = virtualX; + pScrni->virtualY = virtualY; + + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(1)!\n")); + + /* Reset visual list */ + miClearVisualTypes(); + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(2)!\n")); + + /* Setup the visual we support */ + if (pScrni->bitsPerPixel > 8) { + DEBUGMSG(1, (scrnIndex, X_PROBED, + "miSetVisualTypes %d %X %X %X\n", + pScrni->depth, + TrueColorMask, + pScrni->rgbBits, pScrni->defaultVisual)); + + if (!miSetVisualTypes(pScrni->depth, + TrueColorMask, + pScrni->rgbBits, + pScrni->defaultVisual)) { + return FALSE; + } + } else { + if (!miSetVisualTypes(pScrni->depth, + miGetDefaultVisualMask(pScrni->depth), + pScrni->rgbBits, + pScrni->defaultVisual)) { + return FALSE; + } + } + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(3)!\n")); + + /* Set for RENDER extensions */ + miSetPixmapDepths(); + + /* Call the framebuffer layer's ScreenInit function, and fill in other + * * pScrn fields. + */ + switch (pScrni->bitsPerPixel) { +#if CFB + case 8: + Inited = cfbScreenInit(pScrn, FBStart, virtualX, virtualY, + pScrni->xDpi, pScrni->yDpi, + displayWidth); + break; + case 16: + Inited = cfb16ScreenInit(pScrn, FBStart, virtualX, virtualY, + pScrni->xDpi, pScrni->yDpi, + displayWidth); + break; + case 24: + case 32: + Inited = cfb32ScreenInit(pScrn, FBStart, virtualX, virtualY, + pScrni->xDpi, pScrni->yDpi, + displayWidth); + break; +#else + case 8: + case 16: + case 24: + case 32: + Inited = fbScreenInit(pScrn, FBStart, virtualX, virtualY, + pScrni->xDpi, pScrni->yDpi, + displayWidth, pScrni->bitsPerPixel); + break; +#endif + default: + xf86DrvMsg(scrnIndex, X_ERROR, + "Internal error: invalid bpp (%d) in ScreenInit\n", + pScrni->bitsPerPixel); + Inited = FALSE; + break; + } + if (!Inited) + return FALSE; + + LXRotationInit(pScrni); + LXAdjustFrame(scrnIndex, pScrni->frameX0, pScrni->frameY0, 0); + + /* SET UP GRAPHICS MEMORY AVAILABLE FOR PIXMAP CACHE */ + AvailBox.x1 = 0; + AvailBox.y1 = (fboffset + pGeode->AccelPitch-1) / pGeode->AccelPitch; + AvailBox.x2 = displayWidth; + AvailBox.y2 = (pGeode->FBAvail - pGeode->AccelPitch+1) / pGeode->AccelPitch; + + if( AvailBox.y1 < AvailBox.y2 ) { + xf86DrvMsg(scrnIndex, X_INFO, + "Initializing Memory manager to (%d,%d) (%d,%d)\n", + AvailBox.x1, AvailBox.y1, AvailBox.x2, AvailBox.y2); + REGION_INIT(pScrn, &OffscreenRegion, &AvailBox, 2); + if( !xf86InitFBManagerRegion(pScrn, &OffscreenRegion) ) { + xf86DrvMsg(scrnIndex, X_ERROR, + "Memory manager initialization failed, Cache Diabled\n"); + } + REGION_UNINIT(pScrn, &OffscreenRegion); + } + else { + xf86DrvMsg(scrnIndex, X_INFO, + "No Off Screen Memory, Cache Disabled (%d,%d) (%d,%d)\n", + AvailBox.x1, AvailBox.y1, AvailBox.x2, AvailBox.y2); + } + + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(4)!\n")); + xf86SetBlackWhitePixels(pScrn); + + if( !pGeode->ShadowFB ) { + LXDGAInit(pScrn); + } + + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(5)!\n")); + if (pScrni->bitsPerPixel > 8) { + /* Fixup RGB ordering */ + visual = pScrn->visuals + pScrn->numVisuals; + while (--visual >= pScrn->visuals) { + if ((visual->class | DynamicClass) == DirectColor) { + visual->offsetRed = pScrni->offset.red; + visual->offsetGreen = pScrni->offset.green; + visual->offsetBlue = pScrni->offset.blue; + visual->redMask = pScrni->mask.red; + visual->greenMask = pScrni->mask.green; + visual->blueMask = pScrni->mask.blue; + } + } + } +#if CFB +#else + /* must be after RGB ordering fixed */ + fbPictureInit(pScrn, 0, 0); +#endif + + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(6)!\n")); + if (!pGeode->NoAccel) { + LXAccelInit(pScrn); + } + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(7)!\n")); + miInitializeBackingStore(pScrn); + xf86SetBackingStore(pScrn); + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(8)!\n")); + /* Initialise software cursor */ + miDCInitialize(pScrn, xf86GetPointerScreenFuncs()); + /* Initialize HW cursor layer. + * * Must follow software cursor initialization + */ + if (pGeode->HWCursor) { + if (!LXHWCursorInit(pScrn)) + xf86DrvMsg(pScrni->scrnIndex, X_ERROR, + "Hardware cursor initialization failed\n"); + } + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(9)!\n")); + /* Setup default colourmap */ + if (!miCreateDefColormap(pScrn)) { + return FALSE; + } + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(10)!\n")); + if( pScrni->bitsPerPixel == 8 ) { + /* Initialize colormap layer. + * * Must follow initialization of the default colormap + */ + if (!xf86HandleColormaps(pScrn, 256, 8, + LXLoadPalette, NULL, + CMAP_PALETTED_TRUECOLOR | + CMAP_RELOAD_ON_MODE_SWITCH)) { + return FALSE; + } + } + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(11)!\n")); + + if (pGeode->ShadowFB) { + DEBUGMSG(1,(0, X_INFO, "Shadowed, Rotate=%d, NoAccel=%d\n",pGeode->Rotate,pGeode->NoAccel)); + LXShadowFBInit(pScrn,pGeode,bytpp); + } +#ifdef DPMSExtension + xf86DPMSInit(pScrn, LXDPMSSet, 0); +#endif + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(12)!\n")); + + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(13)!\n")); + LXInitVideo(pScrn); /* needed for video */ + /* Wrap the screen's CloseScreen vector and set its + * SaveScreen vector + */ + pGeode->CloseScreen = pScrn->CloseScreen; + pScrn->CloseScreen = LXCloseScreen; + + pScrn->SaveScreen = LXSaveScreen; + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(14)!\n")); + + /* Report any unused options */ + if (serverGeneration == 1) { + xf86ShowUnusedOptions(pScrni->scrnIndex, pScrni->options); + } + DEBUGMSG(1,(0, X_INFO, "LXScreenInit(15)!\n")); + return TRUE; +} + +/*---------------------------------------------------------------------------- + * LXSwitchMode. + * + * Description :This function will switches the screen mode + * + * Parameters: + * scrnIndex :Specfies the screen index value. + * pMode :pointer to the mode structure. + * flags :may be used for status check?. + * + * Returns :Returns TRUE on success and FALSE on failure. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +Bool +LXSwitchMode(int scrnIndex, DisplayModePtr pMode, int flags) +{ + DEBUGMSG(1,(0, X_INFO, "LXSwitchMode!\n")); + return LXSetMode(xf86Screens[scrnIndex], pMode); +} + +/*---------------------------------------------------------------------------- + * LXAdjustFrame. + * + * Description :This function is used to intiallize the start + * address of the memory. + * Parameters. + * scrnIndex :Specfies the screen index value. + * x :x co-ordinate value interms of pixels. + * y :y co-ordinate value interms of pixels. + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +void +LXAdjustFrame(int scrnIndex, int x, int y, int flags) +{ + ScrnInfoPtr pScrni = xf86Screens[scrnIndex]; + GeodePtr pGeode = GEODEPTR(pScrni); + int newX, newY; + unsigned long offset; + if( x+pGeode->HDisplay >= pScrni->virtualX ) + x = pScrni->virtualX-pGeode->HDisplay; + if( x < 0 ) x = 0; + if( y+pGeode->VDisplay >= pScrni->virtualY ) + y = pScrni->virtualY-pGeode->VDisplay; + if( y < 0 ) y = 0; + pScrni->frameX0 = x; + pScrni->frameY0 = y; + pScrni->frameX1 = x + pGeode->HDisplay-1; + pScrni->frameY1 = y + pGeode->VDisplay-1; + (*pGeode->Rotation)(x,y,pScrni->virtualX,pScrni->virtualY,&newX,&newY); + (*pGeode->RBltXlat)(newX,newY,pGeode->HDisplay,pGeode->VDisplay,&newX,&newY); + offset = pGeode->FBOffset + newY*pGeode->Pitch + newX*(pScrni->bitsPerPixel>>3); + vg_set_display_offset(offset); +} + +/*---------------------------------------------------------------------------- + * LXEnterVT. + * + * Description :This is called when VT switching back to the X server + * + * Parameters. + * scrnIndex :Specfies the screen index value. + * flags :Not used inside the function. + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static Bool +LXEnterVT(int scrnIndex, int flags) +{ + DEBUGMSG(1,(0, X_INFO, "LXEnterVT!\n")); + return LXEnterGraphics(NULL, xf86Screens[scrnIndex]); +} + +/*---------------------------------------------------------------------------- + * LXLeaveVT. + * + * Description :This is called when VT switching X server text mode. + * + * Parameters. + * scrnIndex :Specfies the screen index value. + * flags :Not used inside the function. + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static void +LXLeaveVT(int scrnIndex, int flags) +{ + ScrnInfoPtr pScrni = xf86Screens[scrnIndex]; + GeodePtr pGeode = GEODEPTR(pScrni); + + pGeode->PrevDisplayOffset = vg_get_display_offset(); + DEBUGMSG(1,(0, X_INFO, "LXLeaveVT!\n")); + LXLeaveGraphics(xf86Screens[scrnIndex]); +} + +/*---------------------------------------------------------------------------- + * LXFreeScreen. + * + * Description :This is called to free any persistent data structures. + * + * Parameters. + * scrnIndex :Specfies the screen index value. + * flags :Not used inside the function. + * + * Returns :none. + * + * Comments :This will be called only when screen being deleted.. +*---------------------------------------------------------------------------- +*/ +static void +LXFreeScreen(int scrnIndex, int flags) +{ + DEBUGMSG(1,(0, X_INFO, "LXFreeScreen!\n")); + if (xf86LoaderCheckSymbol("vgaHWFreeHWRec")) + vgaHWFreeHWRec(xf86Screens[scrnIndex]); + LXFreeRec(xf86Screens[scrnIndex]); +} + +/*---------------------------------------------------------------------------- + * LXValidMode. + * + * Description :This function checks if a mode is suitable for selected + * chipset. + * Parameters. + * scrnIndex :Specfies the screen index value. + * pMode :Pointer to the screen mode structure.. + * verbose :not used for implementation. + * flags :not used for implementation + * + * Returns :MODE_OK if the specified mode is supported or + * MODE_NO_INTERLACE. + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static int +LXValidMode(int scrnIndex, DisplayModePtr pMode, Bool Verbose, int flags) +{ + unsigned int total_memory_required; + ScrnInfoPtr pScrni = xf86Screens[scrnIndex]; + int ret = -1; + GeodePtr pGeode = GEODEPTR(pScrni); + + DEBUGMSG(0, (0, X_NONE, "GeodeValidateMode: %dx%d %d %d\n", + pMode->CrtcHDisplay, pMode->CrtcVDisplay, + pScrni->bitsPerPixel, LXGetRefreshRate(pMode))); + if( pGeode->CustomMode == 0 ) { + int tv_mode; + VG_QUERY_MODE vgQueryMode; + unsigned long flags; + + if (pMode->Flags & V_INTERLACE) + return MODE_NO_INTERLACE; + + flags = VG_QUERYFLAG_REFRESH | VG_QUERYFLAG_BPP | + VG_QUERYFLAG_ACTIVEWIDTH | VG_QUERYFLAG_ACTIVEHEIGHT; + + if( (pGeode->EnabledOutput&LX_OT_FP) != 0 ) { + /* scaling required, but too big to scale */ + if( pGeode->FPGeomDstX != pMode->CrtcHDisplay && pMode->CrtcHDisplay > 1024 ) + return MODE_NOMODE; + flags = VG_QUERYFLAG_PANELWIDTH | VG_QUERYFLAG_PANELHEIGHT | + VG_QUERYFLAG_PANEL; + vgQueryMode.panel_width = pGeode->FPGeomDstX; + vgQueryMode.panel_height = pGeode->FPGeomDstY; + } + + vgQueryMode.active_width = pMode->CrtcHDisplay; + vgQueryMode.active_height = pMode->CrtcVDisplay; + vgQueryMode.bpp = pScrni->bitsPerPixel; + vgQueryMode.hz = LXGetRefreshRate(pMode); + vgQueryMode.query_flags = VG_QUERYFLAG_REFRESH | VG_QUERYFLAG_BPP | + VG_QUERYFLAG_ACTIVEWIDTH | VG_QUERYFLAG_ACTIVEHEIGHT; + if( (tv_mode=lx_tv_mode(pMode)) >= 0 ) { + vgQueryMode.encoder = pGeode->tv_encoder; + vgQueryMode.tvmode = tv_mode; + vgQueryMode.query_flags |= VG_QUERYFLAG_TVMODE | VG_QUERYFLAG_ENCODER; + vgQueryMode.query_flags &= ~VG_QUERYFLAG_REFRESH; + if( lx_tv_mode_interlaced(tv_mode) != 0 ) { + vgQueryMode.query_flags |= VG_QUERYFLAG_INTERLACED; + vgQueryMode.active_height /= 2; + } + } + ret = vg_get_display_mode_index(&vgQueryMode); + if (ret < 0) + return MODE_NOMODE; + } + + total_memory_required = LXCalculatePitchBytes(pMode->CrtcHDisplay, + pScrni->bitsPerPixel) * pMode->CrtcVDisplay; + + DEBUGMSG(0, (0, X_NONE, "Total Mem %x %lx\n", + total_memory_required, pGeode->FBAvail)); + + if (total_memory_required > pGeode->FBAvail) + return MODE_MEM; + + return MODE_OK; +} + +/*---------------------------------------------------------------------------- + * LXLoadPalette. + * + * Description :This function sets the palette entry used for graphics data + * + * Parameters. + * pScrni:Points the screeninfo structure. + * numColors:Specifies the no of colors it supported. + * indizes :This is used get index value . + * LOCO :to be added. + * pVisual :to be added. + * + * Returns :MODE_OK if the specified mode is supported or + * MODE_NO_INTERLACE. + * Comments :none. +*---------------------------------------------------------------------------- +*/ + +static void +LXLoadPalette(ScrnInfoPtr pScrni, + int numColors, int *indizes, LOCO * colors, VisualPtr pVisual) +{ + int i, index, color; + + for (i = 0; i < numColors; i++) { + index = indizes[i] & 0xFF; + color = (((unsigned long)(colors[index].red & 0xFF)) << 16) | + (((unsigned long)(colors[index].green & 0xFF)) << 8) | + ((unsigned long)(colors[index].blue & 0xFF)); + vg_set_display_palette_entry(index, color); + } +} + +static Bool +LXMapMem(ScrnInfoPtr pScrni) +{ + unsigned long cmd_bfr_phys; + GeodePtr pGeode = GEODEPTR(pScrni); + DEBUGMSG(1, (0, X_NONE, "LXMapMem\n")); + + cim_gp_ptr = (unsigned char *)xf86MapVidMem(pScrni->scrnIndex, + VIDMEM_MMIO, + pGeode->InitBaseAddress.gp_register_base, + pGeode->gp_reg_size); + cim_vg_ptr = (unsigned char *)xf86MapVidMem(pScrni->scrnIndex, + VIDMEM_MMIO, + pGeode->InitBaseAddress.vg_register_base, + pGeode->vg_reg_size); + cim_vid_ptr = (unsigned char *)xf86MapVidMem(pScrni->scrnIndex, + VIDMEM_MMIO, + pGeode->InitBaseAddress.df_register_base, + pGeode->vid_reg_size); + + cim_vip_ptr = (unsigned char *)xf86MapVidMem(pScrni->scrnIndex, + VIDMEM_MMIO, + pGeode->InitBaseAddress.vip_register_base, + pGeode->vip_reg_size); + + cim_fb_ptr = (unsigned char *)xf86MapVidMem(pScrni->scrnIndex, + VIDMEM_FRAMEBUFFER, + pGeode->InitBaseAddress.framebuffer_base, + pGeode->InitBaseAddress.framebuffer_size); + pGeode->FBBase = cim_fb_ptr; + + DEBUGMSG(1, (0, X_NONE, "cim ptrs %p %p %p %p %p\n", + cim_gp_ptr, cim_vg_ptr, cim_vid_ptr, + cim_vip_ptr, cim_fb_ptr)); + + /* CHECK IF REGISTERS WERE MAPPED SUCCESSFULLY */ + if ((!cim_gp_ptr) || (!cim_vid_ptr) || (!cim_fb_ptr)) { + DEBUGMSG(1, (0, X_NONE, "Could not map hardware registers.\n")); + return (FALSE); + } + + cmd_bfr_phys = pGeode->InitBaseAddress.framebuffer_base + pGeode->CmdBfrOffset; + cim_cmd_base_ptr = cim_fb_ptr + pGeode->CmdBfrOffset; + + /* map the top of the frame buffer as the scratch buffer (GP3_SCRATCH_BUFFER_SIZE) */ + gp_set_frame_buffer_base(pGeode->InitBaseAddress.framebuffer_base,pGeode->FBTop); + gp_set_command_buffer_base(cmd_bfr_phys,0,pGeode->CmdBfrSize); + DEBUGMSG(1, (0, X_NONE, "cim cmd %p %lx %lx %lx\n", + cim_cmd_base_ptr, pGeode->CmdBfrSize, cmd_bfr_phys, pGeode->FBTop)); + + /* Map the XpressROM ptr to read what platform are we on */ + XpressROMPtr = (unsigned char *)xf86MapVidMem(pScrni->scrnIndex, + VIDMEM_FRAMEBUFFER, 0xF0000, + 0x10000); + + DEBUGMSG(1, (0, X_NONE, "adapter info %lx %lx %lx %lx %p, %p\n", + pGeode->cpu_version, + pGeode->vid_version, pGeode->FBLinearAddr, + pGeode->FBAvail, pGeode->FBBase, XpressROMPtr)); + + return TRUE; +} + +/* + * Unmap the framebuffer and MMIO memory. + */ + +static Bool +LXUnmapMem(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + DEBUGMSG(1, (0, X_NONE, "LXUnMapMem\n")); + + /* unmap all the memory map's */ + xf86UnMapVidMem(pScrni->scrnIndex, + cim_gp_ptr, pGeode->gp_reg_size); + xf86UnMapVidMem(pScrni->scrnIndex, + cim_vg_ptr, pGeode->vg_reg_size); + xf86UnMapVidMem(pScrni->scrnIndex, + cim_vid_ptr, pGeode->vid_reg_size); + xf86UnMapVidMem(pScrni->scrnIndex, + cim_vip_ptr, pGeode->vip_reg_size); + xf86UnMapVidMem(pScrni->scrnIndex, + cim_fb_ptr, pGeode->InitBaseAddress.framebuffer_size); + xf86UnMapVidMem(pScrni->scrnIndex, XpressROMPtr, 0x10000); + return TRUE; +} + +/* End of file */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd.h 2005-08-03 16:15:04.000000000 -0600 @@ -0,0 +1,477 @@ +/* + * $Workfile: amd.h $ + * $Revision: #4 $ + * $Author: raymondd $ + * + * File Contents: This file contains the data structures Geode driver. + * + * Project: Geode Xfree Frame buffer device driver. + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +#ifndef _AMD_GEODE_H_ +#define _AMD_GEODE_H_ + +#include "xaa.h" +#include "xf86Cursor.h" +#include "vgaHW.h" +#include "xf86int10.h" +#include "xf86xv.h" + +#define CFB 0 +#define INT10_SUPPORT 1 +/* Existing Processor Models */ +#define GX1 0x1 +#define GX2 0x10 +#define GX2_CRT 0x11 +#define GX2_TFT 0x12 +#define LX 0x20 +#define LX_CRT 0x21 +#define LX_TFT 0x22 + +#define PCI_VENDOR_ID_CYRIX 0x1078 +#define PCI_VENDOR_ID_NS 0x100B +#define PCI_VENDOR_ID_AMD 0x1022 + +#define PCI_CHIP_5530 0x0104 +#define PCI_CHIP_SC1200 0x0504 +#define PCI_CHIP_SC1400 0x0104 +#define PCI_CHIP_REDCLOUD 0x0030 +#define PCI_CHIP_GEODELX 0x2081 +#define GFX_CPU_GEODELX 4 + +#ifdef HAVE_GX +#define GX_FILL_RECT_SUPPORT 1 +#define GX_BRES_LINE_SUPPORT 1 +#define GX_DASH_LINE_SUPPORT 0 /* does not do dashed lines */ +#define GX_MONO_8X8_PAT_SUPPORT 1 +#define GX_CLREXP_8X8_PAT_SUPPORT 1 +#define GX_SCR2SCREXP_SUPPORT 1 +#define GX_SCR2SCRCPY_SUPPORT 1 +#define GX_CPU2SCREXP_SUPPORT 1 +#define GX_SCANLINE_SUPPORT 1 +#define GX_USE_OFFSCRN_MEM 0 +#define GX_ONE_LINE_AT_A_TIME 1 +#define GX_WRITE_PIXMAP_SUPPORT 1 + +#define GFX(func) gfx_##func +#define GFX2(func) gfx2_##func +#endif + +#ifdef HAVE_LX +#define LX_FILL_RECT_SUPPORT 1 +#define LX_BRES_LINE_SUPPORT 1 +#define LX_DASH_LINE_SUPPORT 1 +#define LX_MONO_8X8_PAT_SUPPORT 1 +#define LX_CLREXP_8X8_PAT_SUPPORT 1 +#define LX_SCR2SCREXP_SUPPORT 1 +#define LX_SCR2SCRCPY_SUPPORT 1 +#define LX_CPU2SCREXP_SUPPORT 1 +#define LX_SCANLINE_SUPPORT 1 +#define LX_USE_OFFSCRN_MEM 1 +#define LX_WRITE_PIXMAP_SUPPORT 1 +#endif + +#define DEBUGTIM 0 +#define DEBUGLVL 0 + +#ifndef DEBUGTIM +#define DEBUGTIM 0 +#endif +#ifndef DEBUGLVL +#define DEBUGLVL 0 +#endif + +#define GEODEPTR(p) ((GeodePtr)((p)->driverPrivate)) + +#define DEFAULT_IMG_LINE_BUFS 20 +#define DEFAULT_CLR_LINE_BUFS 20 +/* 64x64 cursor used as 32x32 */ +#define HW_CURSOR_W 64 +#define HW_CURSOR_H 64 + +#define MYDBG 1 +#if defined(MYDBG) +#define DEBUGMSG(cond, drv_msg) if((cond)) xf86DrvMsg drv_msg +#else +#define DEBUGMSG(cond, drv_msg) +#endif + +#ifdef HAVE_LX +extern unsigned char cim_inb(unsigned short port); +extern void cim_outb(unsigned short port, unsigned char data); +extern unsigned short cim_inw(unsigned short port); +extern void cim_outw(unsigned short port, unsigned short data); +extern unsigned long cim_ind(unsigned short port); +extern void cim_outd(unsigned short port, unsigned long data); + +#include "cim_rtns.h" + +#define CIM_CMD_BFR_SZ 0x200000L +#define CIM_CMD_BFR_MIN 0x20000L + +typedef struct tag_CIM_DISPLAYTIMING +{ + unsigned short wPitch; + unsigned short wBpp; + + VG_DISPLAY_MODE vgDisplayMode; +} +CIM_DISPLAYTIMING, *CIM_PDISPLAYTIMING; +#endif + +#ifdef HAVE_GX +extern void gfx_write_reg32(int offset, int data); +extern void gfx_write_reg16(int offset, short data); +extern void gfx_write_reg8(int offset, char data); +extern int gfx_read_reg32(int offset); +extern short gfx_read_reg16(int offset); +extern void gfx_write_vid32(int offset, int data); +extern int gfx_read_vid32(int offset); +extern unsigned char gfx_inb(unsigned short port); +extern void gfx_outb(unsigned short port, unsigned char data); +extern unsigned short gfx_inw(unsigned short port); +extern void gfx_outw(unsigned short port, unsigned short data); +extern unsigned long gfx_ind(unsigned short port); +extern void gfx_outd(unsigned short port, unsigned long data); + +#define Q_WORD QQ_WORD +#include "gfx_rtns.h" +#undef Q_WORD +#include "panel.h" + +typedef struct __TVPARAMS +{ + unsigned int dwFlags; + unsigned short wWidth; + unsigned short wHeight; + unsigned short wStandard; + unsigned short wType; + unsigned short wOutput; + unsigned short wResolution; + Bool bState; +} +TVPARAMS, *PTVPARAMS; + +typedef struct tag_GFX_DISPLAYTIMING +{ + unsigned int dwDotClock; + unsigned short wPitch; + unsigned short wBpp; + unsigned short wHTotal; + unsigned short wHActive; + unsigned short wHSyncStart; + unsigned short wHSyncEnd; + unsigned short wHBlankStart; + unsigned short wHBlankEnd; + unsigned short wVTotal; + unsigned short wVActive; + unsigned short wVSyncStart; + unsigned short wVSyncEnd; + unsigned short wVBlankStart; + unsigned short wVBlankEnd; + unsigned short wPolarity; +} +GFX_DISPLAYTIMING, *GFX_PDISPLAYTIMING; + +/* TV Timings */ +typedef struct __TVTIMING +{ + unsigned long HorzTim; + unsigned long HorzSync; + unsigned long VertSync; + unsigned long LineEnd; + unsigned long VertDownscale; + unsigned long HorzScaling; + unsigned long TimCtrl1; + unsigned long TimCtrl2; + unsigned long Subfreq; + unsigned long DispPos; + unsigned long DispSize; + unsigned long Debug; + unsigned long DacCtrl; + unsigned int DotClock; +} +TVTIMING, *PTVTIMING; +#endif + + +typedef struct _VESARec +{ + xf86Int10InfoPtr pInt; +} +VESARec, *VESAPtr; + +/* output enable types */ +#define LX_OT_CRT 0x0001 +#define LX_OT_FP 0x0002 +#define LX_OT_VOP 0x0004 +#define LX_OT_DRGB 0x0008 + +typedef struct +{ + /* Private struct for the server */ + unsigned long cpu_version; + unsigned long cpu_revision; + unsigned long vid_version; + INIT_BASE_ADDRESSES InitBaseAddress; + + EntityInfoPtr pEnt; + ScreenBlockHandlerProcPtr BlockHandler; /* needed for video */ + int DetectedChipSet; + int Chipset; +#ifdef HAVE_LX + int cimFd; + unsigned long CmdBfrOffset; + unsigned long CmdBfrSize; + unsigned int EnabledOutput; + unsigned long FBTop; +#endif + unsigned long FBLinearAddr; + unsigned char *FBBase; + unsigned long FBAvail; + unsigned long FBOffset; + unsigned long FBSize; + unsigned int cpu_reg_size; + unsigned int gp_reg_size; + unsigned int vid_reg_size; +#ifdef HAVE_LX + unsigned int vg_reg_size; + unsigned int vip_reg_size; +#endif + int Pitch; /* display FB pitch */ + int AccelPitch; /* accel pitch (may be ShadowPitch) */ + Bool HWCursor; + Bool NoAccel; + Bool CustomMode; + unsigned long VideoKey; + + Bool TVSupport; +#ifdef HAVE_LX + int tv_encoder; + int tv_bus_fmt; + int tv_flags; + int tv_601_fmt; + int tv_601_flags; + int tv_conversion; + int tv_vsync_shift; + int tv_vsync_shift_count; + int tv_vsync_select; + int tvox, tvoy; + + int FPBiosResX, FPBiosResY; + int FPGeomDstSet, FPGeomDstX, FPGeomDstY; + int FPGeomActSet, FPGeomActX, FPGeomActY; +#endif +#ifdef HAVE_GX + TVPARAMS TvParam; + + int TVOx, TVOy, TVOw, TVOh; + Bool TV_Overscan_On; + + Bool Panel; + + /* Flatpanel support from Bios */ + int FPBX; /* xres */ + int FPBY; /* yres */ + int FPBB; /* bpp */ + int FPBF; /* freq */ +#endif + + int Rotate; + void (*Rotation)(int x,int y,int w,int h,int *newX,int *newY); + void (*RBltXlat)(int x,int y,int w,int h,int *newX,int *newY); + +#ifdef HAVE_GX + void (*WritePixmap)(ScrnInfoPtr pScrni, int x, int y, int w, int h, + unsigned char *src, int srcwidth, int rop, + unsigned int planemask, int trans, int bpp, int depth); +#endif + + Bool ShadowFB; + unsigned char *ShadowPtr; + int ShadowSize; + int ShadowPitch; + int ShadowInFBMem; + + int orig_virtX; /* original */ + int orig_virtY; + int HDisplay; /* rotated */ + int VDisplay; + + void (*PointerMoved) (int index, int x, int y); + /* CloseScreen function. */ + CloseScreenProcPtr CloseScreen; + + Bool Compression; +#ifdef HAVE_LX + VG_COMPRESSION_DATA CBData; +#endif +#ifdef HAVE_GX + unsigned int CBOffset; + unsigned int CBPitch; + unsigned int CBSize; +#endif + unsigned long CursorStartOffset; + unsigned int CursorSize; + xf86CursorInfoPtr CursorInfo; + int CursorXHot; + int CursorYHot; + unsigned long OffscreenStartOffset; + unsigned int OffscreenSize; + + /***Image Write structures ***/ + + /* offset in video memory for ImageWrite Buffers */ + unsigned char **AccelImageWriteBuffers; + int NoOfImgBuffers; + unsigned char **AccelColorExpandBuffers; + int NoOfColorExpandLines; + +/*****************************************/ +/* Saved Console State */ +#ifdef HAVE_GX + gfx_vga_struct FBgfxVgaRegs; + TVTIMING FBtvtiming; + GFX_DISPLAYTIMING FBgfxdisplaytiming; +#endif +#ifdef HAVE_LX + CIM_DISPLAYTIMING FBcimdisplaytiming; +#endif + int FBVGAActive; + unsigned int FBTVActive; + unsigned int FBSupport; + unsigned long FBDisplayOffset; + unsigned long PrevDisplayOffset; + + VESAPtr vesa; + + /* compression */ + int FBCompressionEnable; +#ifdef HAVE_LX + VG_COMPRESSION_DATA FBCBData; + VG_CURSOR_DATA FBCursor; +#endif +#ifdef HAVE_GX + unsigned long FBCompressionOffset; + unsigned short FBCompressionPitch; + unsigned short FBCompressionSize; + + /* Save the Cursor offset of the FB */ + unsigned long FBCursorOffset; +#endif + unsigned char FBBIOSMode; +/*****************************************/ + + XAAInfoRecPtr AccelInfoRec; + + DGAModePtr DGAModes; + int numDGAModes; + Bool DGAactive; + int DGAViewportStatus; +/*****************************************/ + int video_x; + int video_y; + short video_w; + short video_h; + short video_srcw; + short video_srch; + short video_dstw; + short video_dsth; + int video_id; + int video_offset; + ScrnInfoPtr video_scrnptr; + BOOL OverlayON; + + int videoKey; + XF86VideoAdaptorPtr adaptor; +} +GeodeRec, *GeodePtr; + +/* option flags are self-explanatory */ +#ifdef HAVE_LX +enum +{ + LX_OPTION_SW_CURSOR, + LX_OPTION_HW_CURSOR, + LX_OPTION_NOCOMPRESSION, + LX_OPTION_NOACCEL, + LX_OPTION_TV_ENCODER, + LX_OPTION_TV_BUS_FMT, + LX_OPTION_TV_FLAGS, + LX_OPTION_TV_601_FLAGS, + LX_OPTION_TV_VSYNC_SELECT, + LX_OPTION_TV_CONVERSION, + LX_OPTION_TV_OVERSCAN, + LX_OPTION_SHADOW_FB, + LX_OPTION_ROTATE, + LX_OPTION_FLATPANEL, + LX_OPTION_CRTENABLE, + LX_OPTION_COLOR_KEY, + LX_OPTION_OSM_IMG_BUFS, + LX_OPTION_OSM_CLR_BUFS, + LX_OPTION_CUSTOM_MODE, + LX_OPTION_FP_DEST_GEOM, + LX_OPTION_FP_ACTIVE_GEOM, + LX_OPTION_DONT_PROGRAM +} +LX_GeodeOpts; +#endif + +#ifdef HAVE_GX +enum +{ + GX_OPTION_SW_CURSOR, + GX_OPTION_HW_CURSOR, + GX_OPTION_NOCOMPRESSION, + GX_OPTION_NOACCEL, + GX_OPTION_TV_SUPPORT, + GX_OPTION_TV_OUTPUT, + GX_OPTION_TV_OVERSCAN, + GX_OPTION_SHADOW_FB, + GX_OPTION_ROTATE, + GX_OPTION_FLATPANEL, + GX_OPTION_FLATPANEL_INFO, + GX_OPTION_FLATPANEL_IN_BIOS, + GX_OPTION_COLOR_KEY, + GX_OPTION_OSM, + GX_OPTION_OSM_IMG_BUFS, + GX_OPTION_OSM_CLR_BUFS, + GX_OPTION_CUSTOM_MODE, + GX_OPTION_DONT_PROGRAM +} +GX_GeodeOpts; +#endif + +#endif /* _AMD_GEODE_H_ */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/platform.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/platform.c 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This file contains platform dependent functions + * which provide interface to that platform. + * + * + * SubModule: Geode FlatPanel library + * */ + + + +#define LINUX_ROM_SEGMENT 0x000F +#define SEGMENT_LENGTH 0xFFFF +#define PAGE_LENGTH 0x1000 +#define SYS_BOARD_NAME_LEN 24 + +#define PLT_UNKNOWN 0xFFFF + +typedef struct +{ + char sys_board_name[SYS_BOARD_NAME_LEN]; + SYS_BOARD sys_board; +} +SYS_BOARD_INFO; + +static SYS_BOARD_INFO Sys_info; + +/* + * The names in the sys_board_name string must exactly match the names in the + * BIOS header. These names are used by FindStringInSeg() to find the names + * in the BIOS header space. The BIOS does not use OTHER; it is a dummy value + * for program useonly. + * + */ + +SYS_BOARD_INFO Sys_board_info_array[] = { + {"Marmot", MARMOT_PLATFORM}, + {"Unicorn", UNICORN_PLATFORM}, + {"Centaurus", CENTAURUS_PLATFORM}, + {"Aries", ARIES_PLATFORM}, + {"Carmel", CARMEL_PLATFORM}, + {"Hyrda", HYDRA_PLATFORM}, + {"Dorado", DORADO_PLATFORM}, + {"Redcloud", REDCLOUD_PLATFORM}, + {"Other", OTHER_PLATFORM} +}; + +#define NUM_SYS_BOARD_TYPES sizeof(Sys_board_info_array)/sizeof(SYS_BOARD_INFO) + +static int Num_sys_board_type = NUM_SYS_BOARD_TYPES; +SYS_BOARD_INFO *Sys_board_array_base = Sys_board_info_array; +int FindStringInSeg(unsigned int, char *); +static unsigned char get_sys_board_type(SYS_BOARD_INFO *, SYS_BOARD_INFO *); + +/* Detect the Platform */ +int +Detect_Platform(void) +{ + /* See if we can find the board name using Xpressrom */ + if (get_sys_board_type(&Sys_info, Sys_board_array_base) == TRUE) { +#if 0 + if (Sys_info.sys_board == CENTAURUS_PLATFORM) { + printk("CENTAURUS Platform Found\n"); + } else if (Sys_info.sys_board == DORADO_PLATFORM) { + printk("DORADO Platform Found \n"); + } else { + printk("UNKNOWN Platform Found \n"); + } +#endif + } + return (Sys_info.sys_board); +} + +static int +Strncmp(char *str1, char *str2, int len) +{ + int i; + + if ((str1 == 0x0) || (str2 == 0x0) || (len == 0)) + return (1); + for (i = 0; i < len; i++) { + if (*(str1 + i) > *(str2 + i)) { + return 1; + } else if (*(str1 + i) < *(str2 + i)) { + return -1; + } + } + return 0; +} + +static char * +Strcpy(char *dst, char *src) +{ + int i; + + if ((dst == 0x0) || (src == 0x0)) + return (0); + for (i = 0; src[i] != 0x0; i++) { + dst[i] = src[i]; + } + dst[i] = 0x0; /* NULL termination */ + return dst; +} + +static int +Strlen(char *str) +{ + int i; + + if (str == 0x0) + return 0; + for (i = 0; str[i] != 0x0; i++) ; + return i; +} + +/***********************************************************************/ + +/* Platform Detection Code */ + +/***********************************************************************/ + +/************************************************************************ + * int FindStringInSeg( unsigned int segment_address, char *string_ptr ) + * Returns the offset where the NULL terminated string pointed to by + * string_ptr is located in the segment passed in segment_address. + * Segment_address must be of the form 0xXXXX (i.e 0xf000 for segment f). + * Returns NULL if the string is not found. + ************************************************************************ + */ +int +FindStringInSeg(unsigned int segment_address, char *string_ptr) +{ + int string_length = Strlen(string_ptr); + char *psegment_buf; + unsigned long mem_ptr = (unsigned long)segment_address << 16; + unsigned int i; + + /* silence compiler */ + (void)mem_ptr; + +#if defined(linux) && !defined(XFree86Server) + XpressROMPtr = (unsigned char *)ioremap(mem_ptr, SEGMENT_LENGTH + 1); + psegment_buf = (char *)XpressROMPtr; +#elif defined (XFree86Server) + psegment_buf = (char *)XpressROMPtr; +#elif defined(_WIN32) /* Windows */ + psegment_buf = XpressROMPtr; +#endif + + /* Now search for the first character of the string_ptr */ + for (i = 0; i < SEGMENT_LENGTH + 1; i++) { + if (*(psegment_buf + i) == *string_ptr) { + + /* If we match the first character, do a + * string compare. + */ + + if (!Strncmp(string_ptr, (psegment_buf + i), string_length)) { + /* They match! */ + return (1); + } + } + } + /* if we got this far we didn't find anything. Return NULL. */ + return (0); + +}/* end FindStringInSeg() */ + +/********************************************************************** + + * TRUE_FALSE get_sys_board_type( SYS_BOARD_INFO *sys_info, + * SYS_BOARD_INFO *sys_board_array_base) Checks the system + * BIOS area for Xpressrom information. If found, searches the BIOS + * area for one of names in the array pointed to by sys_board_array_ptr. + * If a match is found, sets the SYS_INFO system_board_name string + * and the system_board variable to the board name and returns TRUE. + * If Xpressrom or a board is not found, sets the variables to + * their default values and returns FALSE. + * Uses the global string pointer *xpress_rom_string_ptr. + * + *********************************************************************** + */ + +static unsigned char +get_sys_board_type(SYS_BOARD_INFO * sys_info, + SYS_BOARD_INFO * sys_board_array_base) +{ + int index; + char *xpress_rom_string_ptr = "XpressStart"; + unsigned int segment = LINUX_ROM_SEGMENT; + + /* See if XpressStart is present in the BIOS area. + * If it is, search for a board string. If not, Xpressrom is + * not present, set system_board information to UNKNOWN and + * return FALSE. + */ + + if (!FindStringInSeg(segment, xpress_rom_string_ptr)) { + sys_info->sys_board = PLT_UNKNOWN; + Strcpy(sys_info->sys_board_name, "Unknown"); + return (FALSE); + } else { + + /* we have Xpressrom, so look for a board */ + for (index = 0; index < Num_sys_board_type; index++) { + if (!FindStringInSeg(segment, (sys_board_array_base + + index)->sys_board_name)) { + continue; + } else { + + /* a match!! */ + sys_info->sys_board = (sys_board_array_base + index)->sys_board; + Strcpy(sys_info->sys_board_name, + (sys_board_array_base + index)->sys_board_name); + return (TRUE); + } + } /* end for() */ + } /* end else */ + + /* if we are here we have failed */ + sys_info->sys_board = PLT_UNKNOWN; + Strcpy(sys_info->sys_board_name, "Unknown"); + return (FALSE); +}/* end get_sys_board_type() */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/readme.txt 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/readme.txt 2003-11-20 19:35:18.000000000 -0700 @@ -0,0 +1,448 @@ +Panel Library +Release 1.3.6 +OS - Can be used in all OS's. +May 19, 2003 +Developer - Sarma Kolluru + +----------------------------------------------------------------------------- +PRODUCT INFORMATION +----------------------------------------------------------------------------- +Panel library is set of functions enabling the driver to give panel support. +The panel library is supported on Centaurus and Dorado. +The panel library can detect the panel support by the jumper settings +selected on the board. The platform can be detected too. + + \readme.txt This file + +----------------------------------------------------------------------------- +BUILD INSTRUCTIONS +----------------------------------------------------------------------------- +Panel library is a set of files which has support for flatpanel. The panel +subdirectory needs to be copied in the driver directory. +----------------------------------------------------------------------------- +INSTALLATION INSTRUCTIONS +----------------------------------------------------------------------------- +These is no instalation and to be treaded as a driver source code extension. +----------------------------------------------------------------------------- +UNIT TEST +Panel library when compiled is a part of the driver and cannot be unit tested. +----------------------------------------------------------------------------- + +----------------------------------------------------------------------------- +REVISION HISTORY +----------------------------------------------------------------------------- +Version changes v1.3.6 05/19/03 +----------------------------------------------------------------------------- +Dependencies: + - None +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +- None. +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +Removed the code which is not being used in linux env. The allocation of +segment buffer in stack was the cause of instability. +----------------------------------------------------------------------------- +FILE CHANGES + platform.c +----------------------------------------------------------------------------- +Version changes v1.3.5 02/28/03 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1o +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Added National Copyright header which replaced the GPL and BSD.. +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None. +----------------------------------------------------------------------------- +FILE CHANGES + 92xx.h + cen9211.c + cen9211.h + dora9211.c + dora9211.h + drac9210.c + drac9210.h + gx2_9211.c + gx2_9211.h + panel.h + panel.c + platform.c + pnl_bios.c + pnl_defs.h + pnl_init.c +----------------------------------------------------------------------------- +Version changes v1.3.4 12/30/02 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1o +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +- Added special GX2_READ and GX2_WRITE instead of READ/WRITE supplied by + system. +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None. +----------------------------------------------------------------------------- +FILE CHANGES + gx2_9211.c + gx2_9211.h + panel.c + panel.h + platform.c + pnl_bios.c +----------------------------------------------------------------------------- +Version changes v1.3.3 12/17/02 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1o +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +- None +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- 125.10 Panel code no longer compiles under WinCE with latest change. +----------------------------------------------------------------------------- +FILE CHANGES + drac9210.c +----------------------------------------------------------------------------- +Version changes v1.3.2 12/10/02 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1o +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +- Did code indentation for XFree release. +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None. +----------------------------------------------------------------------------- +FILE CHANGES + 92xx.h + cen9211.c + cen9211.h + dora9211.c + dora9211.h + drac9210.c + drac9210.h + gx2_9211.c + gx2_9211.h + panel.h + panel.c + platform.c + pnl_bios.c + pnl_defs.h + pnl_init.c +----------------------------------------------------------------------------- +Version changes v1.3.1 12/06/02 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1o +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +- Added function protoype. +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None. +----------------------------------------------------------------------------- +FILE CHANGES + cen9211.h + dora9211.h + gx2_9211.h +----------------------------------------------------------------------------- +Version changes v1.3.0 11/29/02 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1o +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +- None. +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- cursor variable not defined for XFree when not as a module. +----------------------------------------------------------------------------- +FILE CHANGES + platform.c +----------------------------------------------------------------------------- +Version changes v1.2.9 7/31/02 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1o +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Added FP setup from user input. +Added Redcloud Panel initialization. +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- +FILE CHANGES + pnl_init.c + panel.c + platform.c + gx2_9211.c + gx2_9211.h +----------------------------------------------------------------------------- +Version changes v1.2.8 5/16/02 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1o +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Added FP detection with BIOS for GX2. +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- +FILE CHANGES + pnl_bios.c +----------------------------------------------------------------------------- +Version changes v1.2.7 1/20/02 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1o +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Added the protoype for gfx_detect_video. +Durango dependency removed. +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- +FILE CHANGES + panel.c +----------------------------------------------------------------------------- +Version changes v1.2.6 12/1/01 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1o + - Durango 2.35.01 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Toggle 5530/scx200/RC FlatPanel Power and Data accordingly during +power up/down. + +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- +FILE CHANGES + pnl_init.c +----------------------------------------------------------------------------- +Version changes v1.2.5 11/1/01 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1o + - Durango 2.35.01 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Re-Enabled the Draco platform support. + +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- +FILE CHANGES + panel_defs.h + pnl_init.c +----------------------------------------------------------------------------- +Version changes v1.2.4 08/12/01 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1 + - Durango 2.33.01 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Added 2 functions to get the FP setting details from BIOS. + +int Pnl_IsPanelEnabledInBIOS(void); +void Pnl_GetPanelInfoFromBIOS(int *xres, int *yres, int *bpp, int *hz); + +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- +FILE CHANGES + panel.h + pnl_bios.c +----------------------------------------------------------------------------- +Version changes v1.2.3 06/05/01 +----------------------------------------------------------------------------- +Dependencies: + - crlf v1.0.1 + - Durango 2.31.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Code cleanup and documentation. + +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- +FILE CHANGES + panel.h + cen9211.c + cen9211.h + dora9211.c + dora9211.h + panel.h + pnl_init.c +----------------------------------------------------------------------------- +Version changes v1.2.2 04/11/01 +----------------------------------------------------------------------------- +Dependencies: + - Durango 2.27.00 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Added Pnl_PowerUp and Pnl_PowerDown Functions. + +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- +FILE CHANGES + panel.h + cen9211.c + cen9211.h + dora9211.c + dora9211.h + panel.h + pnl_init.c +----------------------------------------------------------------------------- +Version changes v1.2.1 03/29/01 +----------------------------------------------------------------------------- +Dependencies: + - Durango 2.25 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Added Pnl_SavePanelState and Pnl_RestorePanelState Functions. + +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- +FILE CHANGES + panel.h + 92xx.h + cen9211.c + cen9211.h + dora9211.c + dora9211.h + platform.c + pnl_init.c +----------------------------------------------------------------------------- +Version changes v1.2.0 03/04/01 +----------------------------------------------------------------------------- +Dependencies: + - Durango 2.23 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Use inb/out routines from durango directly. +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- +FILE CHANGES + panel.h -inb/outb deleted. +============================================================================= +Version changes v1.0.1 02/02/01 +----------------------------------------------------------------------------- +Dependencies: + - Durango 2.19 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Added 9211 Rev. C on Centaurus platform. + +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- +FILE CHANGES + 92xx.h -9211 Rev.C. + cen9211.c - centaurus 9211_C support file. + cen9211.h - centaurus 9211_C support file. + platform.c - Support for detection of platform in which driver runs. +============================================================================= +Version changes v1.0.0 01/21/01 +----------------------------------------------------------------------------- +Dependencies: + - Durango 2.16 + +----------------------------------------------------------------------------- +FUNCTIONAL CHANGES +----------------------------------------------------------------------------- +Detection of platform +Detection of 92x chip with version and the panel sected by jumper settings. +initialization of the h/w. +----------------------------------------------------------------------------- +DEFECTS CORRECTED +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- +FILE CHANGES + 92xx.h -common file with all 9211/9210 definitions. + cen9211.c - centaurus 9211_A support file. + cen9211.h - centaurus 9211_A support file. + dora9211.c - dorado 9211_A support file. + dora9211.h - dorado 9211_C support file. + drac9210.c - draco 9210 support file. + drac9210.h - draco 9210 support file. + panel.c - This is the confiuration file to enable support for platforms. + panel.h - centaurus 9211_A support file. + platform.c - Support for detection of platform in which driver runs. + pnl_defs.h - common definitions for panel. + pnl_init.c - configurationto call appropriate platform calls. + readme.txt - this file. +----------------------------------------------------------------------------- +----------------------------------------------------------------------------- +KNOWN ERRATA +----------------------------------------------------------------------------- +- None listed +----------------------------------------------------------------------------- + --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/drac9210.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/drac9210.c 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,713 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This file contains the panel library files to the + * platforms with 9210, and 9211 support. + * SubModule: Geode FlatPanel library + * */ + + +#include "drac9210.h" + +#define CS9210 0x40 /* Chip select pin */ + +/* 9210 on Draco */ +#define CLOCK9210 0x04 /* Clock pin */ +#define DATAIN9210 0x20 /* Data from 9210 */ +#define DATAOUT9210 0x80 /* Data to 9210 */ + +static void DracoWriteData(unsigned char data); +static void DracoReadData(unsigned char *data); +static void Draco9210GpioInit(); +static void Draco9210SetCS(void); +static unsigned char Draco9210ReadReg(unsigned char index); +static void Draco9210WriteReg(unsigned char index, unsigned char data); +static void Draco9210ClearCS(void); +static void Draco9210SetDataOut(void); +static void Draco9210ClearDataOut(void); +static unsigned char Draco9210ReadDataIn(void); +static void Draco9210ToggleClock(void); + +void +Draco9210Init(Pnl_PanelStat * pstat) +{ + unsigned char panelvalues[] = { + 0x2, 0x80, + 0x2, 0x24, + 0x03, 0x00, + 0xc0, 0x00, + 0xc1, 0x00, + 0xc2, 0x00, + 0xc3, 0x00, + 0xc4, 0x00, + 0xc5, 0x01, + 0xc6, 0xff, + 0xc7, 0xff, + 0xc8, 0x3, + 0xc9, 0xfe, + 0xca, 0x0, + 0xcb, 0x3f, + 0xcc, 0xc, + 0xcd, 0x1, + 0xce, 0xff, + 0xcf, 0xc1, + 0xd0, 0x0, + 0xd1, 0x7e, + 0xd2, 0x3, + 0xd3, 0xfe, + 0xd4, 0x3, + 0xd5, 0x81, + 0xd6, 0xfc, + 0xd7, 0x3f, + 0xd8, 0x14, + 0xd9, 0x1e, + 0xda, 0x0f, + 0xdb, 0xc7, + 0xdc, 0x29, + 0xdd, 0xe1, + 0xde, 0xf1, + 0xdf, 0xf9, + 0xe0, 0x2, + 0xe1, 0xe, + 0xe2, 0x1e, + 0xe3, 0x3e, + 0xe4, 0x04, + 0xe5, 0x71, + 0xe6, 0xe3, + 0xe7, 0xcf, + 0xe8, 0x1, + 0xe9, 0x86, + 0xea, 0x3c, + 0xeb, 0xf3, + 0xec, 0xa, + 0xed, 0x39, + 0xee, 0xc7, + 0xef, 0x3d, + + 0xf0, 0x14, + 0xf1, 0xc6, + 0xf2, 0x39, + 0xf3, 0xce, + 0xf4, 0x3, + 0xf5, 0x19, + 0xf6, 0xce, + 0xf7, 0x77, + 0xf8, 0x0, + 0xf9, 0x66, + 0xfa, 0x33, + 0xfb, 0xbb, + 0xfc, 0x2d, + 0xfd, 0x99, + 0xfe, 0xdd, + 0xff, 0xdd, + + 0x3, 0x1, + 0xc0, 0x2, + 0xc1, 0x22, + 0xc2, 0x66, + 0xc3, 0x66, + 0xc4, 0x0, + 0xc5, 0xcd, + 0xc6, 0x99, + 0xc7, 0xbb, + 0xc8, 0x5, + 0xc9, 0x32, + 0xca, 0x66, + 0xcb, 0xdd, + 0xcc, 0x1a, + 0xcd, 0x4d, + 0xce, 0x9b, + 0xcf, 0x6f, + 0xd0, 0x0, + 0xd1, 0x92, + 0xd2, 0x6d, + 0xd3, 0xb6, + 0xd4, 0x5, + 0xd5, 0x25, + 0xd6, 0xb6, + 0xd7, 0xdb, + 0xd8, 0x2, + 0xd9, 0x5a, + 0xda, 0x4b, + 0xdb, 0x6d, + 0xdc, 0x29, + 0xdd, 0xa5, + 0xde, 0xb5, + 0xdf, 0xb7, + 0xe0, 0x4, + 0xe1, 0x4a, + 0xe2, 0x5a, + 0xe3, 0xda, + 0xe4, 0x12, + 0xe5, 0x95, + 0xe6, 0xad, + 0xe7, 0x6f, + 0xe8, 0x1, + 0xe9, 0x2a, + 0xea, 0x56, + 0xeb, 0xb5, + 0xec, 0xe, + 0xed, 0x55, + 0xee, 0xab, + 0xef, 0x5f, + 0xf0, 0x0, + 0xf1, 0xaa, + 0xf2, 0x55, + 0xf3, 0xea, + 0xf4, 0x1, + 0xf5, 0x55, + 0xf6, 0xaa, + 0xf7, 0xbf, + 0xf8, 0x6, + 0xf9, 0xaa, + 0xfa, 0x55, + 0xfb, 0x55, + 0xfc, 0x39, + 0xfd, 0x55, + 0xfe, 0xff, + 0xff, 0xff, + + 0x3, 0x2, + 0xc0, 0x0, + 0xc1, 0x0, + 0xc2, 0xaa, + 0xc3, 0xaa, + 0xc4, 0x6, + 0xc5, 0xab, + 0xc6, 0x55, + 0xc7, 0x55, + 0xc8, 0x01, + 0xc9, 0x54, + 0xca, 0xaa, + 0xcb, 0xbf, + 0xcc, 0x8, + 0xcd, 0xab, + 0xce, 0x55, + 0xcf, 0xeb, + 0xd0, 0x6, + 0xd1, 0x54, + 0xd2, 0xab, + 0xd3, 0x5e, + 0xd4, 0x1, + 0xd5, 0x2b, + 0xd6, 0x56, + 0xd7, 0xb5, + 0xd8, 0x12, + 0xd9, 0x94, + 0xda, 0xad, + 0xdb, 0x6f, + 0xdc, 0x2d, + 0xdd, 0x4b, + 0xde, 0x5b, + 0xdf, 0xdb, + 0xe0, 0x0, + 0xe1, 0xa4, + 0xe2, 0xb4, + 0xe3, 0xb6, + 0xe4, 0x2, + 0xe5, 0x5b, + 0xe6, 0x4b, + 0xe7, 0x6d, + 0xe8, 0x5, + 0xe9, 0x24, + 0xea, 0xb6, + 0xeb, 0xdb, + 0xec, 0x8, + 0xed, 0x93, + 0xee, 0x6d, + 0xef, 0xb7, + 0xf0, 0x12, + 0xf1, 0x4c, + 0xf2, 0x9b, + 0xf3, 0x6e, + 0xf4, 0x5, + 0xf5, 0x33, + 0xf6, 0x66, + 0xf7, 0xdd, + 0xf8, 0x0, + 0xf9, 0xcc, + 0xfa, 0x99, + 0xfb, 0xbb, + 0xfc, 0x2b, + 0xfd, 0x33, + 0xfe, 0x77, + 0xff, 0x77, + + 0x3, 0x3, + 0xc0, 0x4, + 0xc1, 0x88, + 0xc2, 0xcc, + 0xc3, 0xcc, + 0xc4, 0x0, + 0xc5, 0x67, + 0xc6, 0x33, + 0xc7, 0xbb, + 0xc8, 0x3, + 0xc9, 0x18, + 0xca, 0xce, + 0xcb, 0x77, + 0xcc, 0x1c, + 0xcd, 0xc7, + 0xce, 0x39, + 0xcf, 0xcf, + + 0xd0, 0x2, + 0xd1, 0x38, + 0xd2, 0xc7, + 0xd3, 0x3c, + 0xd4, 0x1, + 0xd5, 0x87, + 0xd6, 0x3c, + 0xd7, 0xf3, + 0xd8, 0x4, + 0xd9, 0x70, + 0xda, 0xe3, + 0xdb, 0xcf, + 0xdc, 0x2b, + 0xdd, 0xf, + 0xde, 0x1f, + 0xdf, 0x3f, + 0xe0, 0x00, + 0xe1, 0xe0, + 0xe2, 0xf0, + 0xe3, 0xf8, + 0xe4, 0x14, + 0xe5, 0x1f, + 0xe6, 0xf, + 0xe7, 0xc7, + 0xe8, 0x3, + 0xe9, 0x80, + 0xea, 0xfc, + 0xeb, 0x3f, + 0xec, 0x8, + 0xed, 0x7f, + 0xee, 0x3, + 0xef, 0xff, + 0xf0, 0x4, + 0xf1, 0x0, + 0xf2, 0xff, + 0xf3, 0xc0, + 0xf4, 0x3, + 0xf5, 0xff, + 0xf6, 0x0, + 0xf7, 0x3f, + 0xf8, 0x0, + 0xf9, 0x0, + 0xfa, 0xff, + 0xfb, 0xff, + 0xfc, 0x3f, + 0xfd, 0xff, + 0xfe, 0xff, + 0xff, 0xff, + 0x3, 0x4, + + /* Setup the Diter to Pattern33 */ + 0x80, 0xdd, + 0x81, 0xdd, + 0x82, 0x33, + 0x83, 0x33, + 0x84, 0xdd, + 0x85, 0xdd, + 0x86, 0x33, + 0x87, 0x33, + 0x88, 0x33, + 0x89, 0x33, + 0x8a, 0x77, + 0x8b, 0x77, + 0x8c, 0x33, + 0x8d, 0x33, + 0x8e, 0x77, + 0x8f, 0x77, + 0x90, 0xdd, + 0x91, 0xdd, + 0x92, 0x33, + 0x93, 0x33, + 0x94, 0xdd, + 0x95, 0xdd, + 0x96, 0x33, + 0x97, 0x33, + 0x98, 0x33, + 0x99, 0x33, + 0x9a, 0x77, + 0x9b, 0x77, + 0x9c, 0x33, + 0x9d, 0x33, + 0x9e, 0x77, + 0x9f, 0x77, + + 0x4, 0x20, + 0x5, 0x3, + 0x6, 0x56, + 0x7, 0x2, + 0x8, 0x1c, + 0x9, 0x0, + 0xa, 0x26, + 0xb, 0x0, + 0xc, 0x15, + 0xd, 0x4, + 0xe, 0x50, + 0xf, 0x4, + 0x10, 0xfa, + 0x11, 0x0, + 0x12, 0xc8, + 0x13, 0x0, + 0x14, 0x31, + 0x15, 0x23, + 0x16, 0x0, + + /* Enable DSTN panel */ + 0x2, 0x64 + }; + unsigned char index, data; + int i; + + gfx_delay_milliseconds(100); + Draco9210GpioInit(); + Draco9210SetCS(); + Draco9210ToggleClock(); + Draco9210ToggleClock(); + Draco9210ToggleClock(); + Draco9210ToggleClock(); + Draco9210ClearCS(); + +#if defined(_WIN32) /* For Windows */ + for (i = 0; i < 10; i++) { + _asm { + out 0EDh, al} + } + +#elif defined(linux) /* Linux */ + +#endif + + for (i = 0; i < 630; i += 2) { + index = panelvalues[i]; + data = panelvalues[i + 1]; + Draco9210WriteReg(index, data); + } + +} + +static void +DracoWriteData(unsigned char data) +{ + int i; + unsigned char mask = 0x80, databit; + + for (i = 0; i < 8; i++) { + + databit = data & mask; + if (data & mask) { + Draco9210SetDataOut(); + } else { + Draco9210ClearDataOut(); + } + mask >>= 1; + Draco9210ToggleClock(); + } +} + +static void +DracoReadData(unsigned char *data) +{ + int i; + unsigned char tmp = 0, readbit; + + Draco9210ClearDataOut(); + Draco9210ToggleClock(); + for (i = 0; i < 7; i++) { + readbit = Draco9210ReadDataIn(); + tmp |= (readbit & 0x1); + tmp <<= 1; + Draco9210ToggleClock(); + } + readbit = Draco9210ReadDataIn(); + tmp |= (readbit & 0x1); + *data = tmp; +} + +#if defined(_WIN32) /* For Windows */ + +void +Draco9210GpioInit() +{ + _asm { + pushf + cli + mov dx, 0CF8h + mov eax, CX55x0_ID + 090h + out dx, eax + mov dx, 0CFCh + mov al, 0CFh + mov ah, 00h + out dx, ax + popf + } +} + +void +Draco9210SetCS() +{ + _asm { + pushf + ;Point to PCI address register + mov dx, 0CF8h + ;55 XX GPIO data register + mov eax, CX55x0_ID + 090h + out dx, eax + ;Point to PCI data register (CFCh) + mov dx, 0CFCh + + in ax, dx + and ah, 30h + mov ah, c92DataReg + or ah, CS9210 + mov c92DataReg, ah + out dx, ax + popf + } +} + +void +Draco9210ClearCS() +{ + _asm { + pushf + ;Point to PCI address register + mov dx, 0CF8h + ;55 XX GPIO data register + mov eax, CX55x0_ID + 090h + out dx, eax + ;Point to PCI data register (CFCh) + mov dx, 0CFCh + ;Set CS LOW + in ax, dx + mov ah, c92DataReg + and ah, NOT CS9210 + mov c92DataReg, ah + out dx, ax + popf + } +} + +void +Draco9210SetDataOut() +{ + _asm { + pushf + ;Point to PCI address register + mov dx, 0CF8h + ;55 XX GPIO data register + mov eax, CX55x0_ID + 090h + out dx, eax + ;Point to PCI data register (CFCh) + mov dx, 0CFCh + ;Set DATA HIGH + in ax, dx + mov ah, c92DataReg + or ah, DATAOUT9210 + mov c92DataReg, ah + out dx, ax + popf + } +} + +void +Draco9210ClearDataOut() +{ + _asm { + pushf + ;Point to PCI address register + mov dx, 0CF8h + mov eax, CX55x0_ID + 090h; + ;55 XX GPIO data register + out dx, eax + ;Point to PCI data register (CFCh) + mov dx, 0CFCh + ;Set Data LOW + in ax, dx + mov ah, c92DataReg + and ah, NOT DATAOUT9210 + mov c92DataReg, ah + out dx, ax + popf + } +} + +unsigned char +Draco9210ReadDataIn() +{ + unsigned char readdata; + + _asm { + pushf + ;Point to PCI address register + mov dx, 0CF8h + ;55 XX GPIO data register + mov eax, CX55x0_ID + 090h + out dx, eax + ;Point to PCI data register (CFCh) + mov dx, 0FCh + + in ax, dx + ;Preserve just Data IN bit + and ah, DATAIN9210 + mov al, ah + cmp al, 0 + ;Is it LOW ? + je readDataLow + ;must be HIGH + mov al, 1 + readDataLow: + mov readdata, al + popf + } + return (readdata); +} + +void +Draco9210ToggleClock() +{ + _asm { + pushf + ;Point to PCI address register + mov dx, 0CF8h + ;55 XX GPIO data register + mov eax, CX55x0_ID + 090h + ;Point to PCI data register (CFCh) + out dx, eax + mov dx, 0CFCh + ;SET CLOCK + in ax, dx + mov ah, c92DataReg + or ah, CLOCK9210 + mov c92DataReg, ah + out dx, ax + out 0EDh, al /* IOPAUSE */ + ;Point to PCI address register + mov dx, 0CF8h + ;55 XX GPIO data register + mov eax, CX55x0_ID + 090h + out dx, eax + ;Point to PCI data register (CFCh) + mov dx, 0CFCh; + ;CLEAR CLOCK + in ax, dx + mov ah, c92DataReg + and ah, NOT CLOCK9210 + mov c92DataReg, ah + out dx, ax + popf + } +} + +#elif defined(linux) /* Linux */ + +void +Draco9210GpioInit() +{ +} +void +Draco9210SetCS() +{ +} +void +Draco9210ClearCS() +{ +} +void +Draco9210SetDataOut() +{ +} +void +Draco9210ClearDataOut() +{ +} +unsigned char +Draco9210ReadDataIn() +{ +} +void +Draco9210ToggleClock() +{ +} + +#endif + +unsigned char +Draco9210ReadReg(unsigned char index) +{ + unsigned char data; + + Draco9210SetCS(); + Draco9210ToggleClock(); + Draco9210SetDataOut(); + Draco9210ToggleClock(); + Draco9210ClearDataOut(); + Draco9210ToggleClock(); + Draco9210ClearDataOut(); + Draco9210ToggleClock(); + Draco9210ClearDataOut(); + Draco9210ToggleClock(); + + DracoWriteData(index); + DracoReadData(&data); + + return (data); +} + +void +Draco9210WriteReg(unsigned char index, unsigned char data) +{ + + Draco9210SetCS(); + Draco9210ToggleClock(); + + Draco9210SetDataOut(); + Draco9210ToggleClock(); + + Draco9210ClearDataOut(); + Draco9210ToggleClock(); + + Draco9210ClearDataOut(); + Draco9210ToggleClock(); + + Draco9210SetDataOut(); + Draco9210ToggleClock(); + + DracoWriteData(index); + DracoWriteData(data); + + Draco9210ClearDataOut(); + Draco9210ToggleClock(); + + Draco9210ClearCS(); + Draco9210ToggleClock(); + Draco9210ToggleClock(); + +} --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/drac9210.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/drac9210.h 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This file contains the panel header file and definition + * for the platform with 9210 support. + * + * SubModule: Geode FlatPanel library + * */ + + + +#include "panel.h" + +#ifndef _DRAC9210_h +#define _DRAC9210_h +#define CX55x0_ID 0x80009000 +static unsigned char c92DataReg = 0; +#endif /* !_DRAC9210_h */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/cen9211.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/cen9211.c 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,871 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This file contains panel functions to interface with + * the centaraus platform. + * + * SubModule: Geode FlatPanel library + * */ + + +#include "cen9211.h" + +static unsigned char sioc2_orig_val; +static unsigned char must_restore_97317 = FALSE; + +/******************************************************************** + * + * PASS_FAIL init_GPIO(void); + * Initializes the GPIO pins in the Cx5530 or the National PC97317 + * for use with a 9211 on a Marmot or Centaurus board. Uses + * the global variables RdPCIVal and sioc2_orig_val. + * + *********************************************************************/ + +unsigned char +init_Centaurus_GPIO(void) +{ + unsigned char reg_val; + static unsigned char first_time = TRUE; + + /* The Centaurus board uses ports 1 and 2 of the 97317 for GPIO. + * These ports require bank 0 to be active. The first thing we will + * do is verify that bank 0 is active and set it if it is not. + */ + + /* set the index for access to the configuration register */ + gfx_outb(CENT_CONFIG_INDEX, CENT_SIOC2); + reg_val = gfx_inb(CENT_CONFIG_DATA); + + /* set to bank 0 */ + if (reg_val & CENT_GPIO_BANK_SELECT) { + gfx_outb(CENT_CONFIG_DATA, + (unsigned char)(reg_val & ~CENT_GPIO_BANK_SELECT)); + } + + /* If this is the first time we have modified sioc2, we must + * save the current value (set by the BIOS) for restoration by + * the calling program, set the global flag must_restore_97317, and set + * first_time to FALSE. + */ + + if (first_time == TRUE) { + sioc2_orig_val = reg_val; + must_restore_97317 = TRUE; + first_time = FALSE; + } + + /* set port 1 direction */ + reg_val = gfx_inb(CENT_PORT1_DIRECTION); + + /* make GPIO 14 and 17 outputs */ + reg_val |= CENT_97317_CLOCK_MASK | CENT_97317_DATA_OUT_MASK; + gfx_outb(CENT_PORT1_DIRECTION, reg_val); + + /* set port 2 direction */ + reg_val = gfx_inb(CENT_PORT2_DIRECTION); + + /* make GPIO 20 an output */ + + reg_val |= CENT_97317_CHIP_SEL_MASK; + + /* make GPIO 21 an input */ + + reg_val &= ~CENT_97317_DATA_IN_MASK; + gfx_outb(CENT_PORT2_DIRECTION, reg_val); + + /* make GPIO 14 and 17 push-pull */ + + reg_val = gfx_inb(CENT_PORT1_OUTPUT_TYPE); + reg_val |= CENT_97317_CLOCK_MASK | CENT_97317_DATA_OUT_MASK; + gfx_outb(CENT_PORT1_OUTPUT_TYPE, reg_val); + + /* make GPIO 20 and 21 push-pull */ + reg_val = gfx_inb(CENT_PORT2_OUTPUT_TYPE); + reg_val |= CENT_97317_CHIP_SEL_MASK | CENT_97317_DATA_IN_MASK; + gfx_outb(CENT_PORT2_OUTPUT_TYPE, reg_val); + return CENT_PASS; + +} /* end init_GPIO() */ + +/********************************************************************* + * + * PASS_FAIL init_9211(void); + * Initializes (sets to 0) the clock, chip select, and data pins + * of the Cx9211 on a Marmot or Centaurus board. + * + **********************************************************************/ + +unsigned char +init_Centaurus_9211(void) +{ + unsigned char ReadData; + + /* Uses the 97317 for GPIO. + * we will use the clock port define for port 1 + */ + ReadData = gfx_inb(CENT_97317_CLOCK_PORT); + ReadData &= ~CENT_97317_CLOCK_MASK & ~CENT_97317_DATA_OUT_MASK; + gfx_outb(CENT_97317_CLOCK_PORT, ReadData); + /* we will use the chip select port define for port 2 */ + ReadData = gfx_inb(CENT_97317_CHIP_SELECT); + ReadData &= ~CENT_97317_CHIP_SEL_MASK & ~CENT_97317_DATA_IN_MASK; + gfx_outb(CENT_97317_CHIP_SELECT, ReadData); + return (CENT_PASS); + +} /*end init_9211() */ + +/****************************************************************** + * + * PASS_FAIL restore_97317_SIOC2(void); + * Restores the original value to the 97317 SIOC2 register using + * the global variable sioc2_orig_val. Returns PASS if the value + * was written, FAIL if not. + * + *******************************************************************/ + +unsigned char +restore_Centaurus_97317_SIOC2(void) +{ + /* set the global flag */ + if (must_restore_97317 == TRUE) { + unsigned char cfg; + + /* set the index for access to the configuration register */ + gfx_outb(CENT_CONFIG_INDEX, CENT_SIOC2); + + /* restore the value */ + gfx_outb(CENT_CONFIG_DATA, sioc2_orig_val); + + /* now read and verify */ + cfg = gfx_inb(CENT_CONFIG_DATA); + if (cfg == sioc2_orig_val) + return (CENT_PASS); + else + return (CENT_FAIL); + + } /* end if() */ + return (CENT_FAIL); + +} /* end restore_97317_SIOC2bank() */ + +/* ----------------------------------------------------------------------- + * + * SET_FLAT_PANEL_MODE + * + * This routine sets the specified flat panel moden parameters in + * the 9211. + * Returns PASS if successful, FAIL if the mode parameters could + * not be set. + * + *------------------------------------------------------------------------*/ + +unsigned char +set_Centaurus_92xx_mode(Pnl_PanelStat * pstat) +{ + int mode; + + /* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */ + + for (mode = 0; mode < NUM_92XX_MODES; mode++) { + if ((FPModeParams[mode].xres == pstat->XRes) && + (FPModeParams[mode].yres == pstat->YRes) && + (FPModeParams[mode].bpp == pstat->Depth) && + (FPModeParams[mode].panel_type == pstat->Type) && + (FPModeParams[mode].color_type == pstat->MonoColor)) { + + /* SET THE 92xx FOR THE SELECTED MODE */ + set_Centaurus_92xx_mode_params(mode); + return (CENT_PASS); + } /* end if() */ + } /* end for() */ + return (CENT_FAIL); + +} /* end set_Centaurus_92xx_mode() */ + +/*------------------------------------------------------------------- + * + * SET_92XX_MODE_PARAMS + * This routine sets the 9211 mode parameters. + * + *-------------------------------------------------------------------*/ + +void +set_Centaurus_92xx_mode_params(int mode) +{ + CS92xx_MODE *pMode = &FPModeParams[mode]; + unsigned long off_data = 0; + + /* Turn the 92xx power off before setting any new parameters. + * Since we are going to reset all the power bit positions, we will + * force the power register to 0. + */ + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_LCD_PWR_MAN, off_data); + + /* set 9211 registers using the desired panel settings */ + + Centaurus_write_gpio(FOUR_BYTES, + CS92xx_LCD_PAN_TIMING1, pMode->panel_timing1); + + Centaurus_write_gpio(FOUR_BYTES, + CS92xx_LCD_PAN_TIMING2, pMode->panel_timing2); + + if (Pnl_Rev_ID == PNL_9211_C) { + + /* load the LSFR seeds */ + Centaurus_write_gpio(FOUR_BYTES, + CS92xx_LCD_DITH_FR_CNTRL, pMode->rev_C_dither_frc); + + Centaurus_write_gpio(FOUR_BYTES, + CS92xx_BLUE_LSFR_SEED, pMode->blue_lsfr_seed); + + Centaurus_write_gpio(FOUR_BYTES, + CS92xx_RED_GREEN_LSFR_SEED, + pMode->red_green_lsfr_seed); + } else { + + Centaurus_write_gpio(FOUR_BYTES, + CS92xx_LCD_DITH_FR_CNTRL, pMode->pre_C_dither_frc); + + Centaurus_write_gpio(FOUR_BYTES, + CS92xx_LCD_BLOCK_SEL1, pMode->block_select1); + + Centaurus_write_gpio(FOUR_BYTES, + CS92xx_LCD_BLOCK_SEL2, pMode->block_select2); + + Centaurus_write_gpio(FOUR_BYTES, + CS92xx_LCD_DISPER1, pMode->dispersion1); + + Centaurus_write_gpio(FOUR_BYTES, + CS92xx_LCD_DISPER2, pMode->dispersion2); + + CentaurusProgramFRMload(); + } + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_LCD_MEM_CNTRL, + pMode->memory_control); + + /* Set the power register last. This will turn the panel on at the 9211. */ + + Centaurus_write_gpio(FOUR_BYTES, + CS92xx_LCD_PWR_MAN, pMode->power_management); + +} /* end set_Centaurus_92xx_mode_params() */ + +void +Centaurus_write_gpio(int width, ULONG address, unsigned long data) +{ + int num_clock_toggles; + int count; + unsigned long Addr = address; + + enable_Centaurus_9211_chip_select(); + + /* Write 1 Clock period of no valid transfer */ + write_Centaurus_CX9211_GPIO(CENT_NO_DATA); + + /* Write 1 control bit (the data book calls this the control bar write) */ + write_Centaurus_CX9211_GPIO(0x1); + + /* Write the 12-bit address */ + for (count = 0; count < 12; count++) { + write_Centaurus_CX9211_GPIO((unsigned char)(Addr & 0x01)); + /*the 9211 expects data LSB->MSB */ + Addr = Addr >> 1; + } + + /* write */ + write_Centaurus_CX9211_DWdata(data); + + /* a write will require four toggles after disabling CS */ + num_clock_toggles = CENT_NUM_WRITE_CLOCK_TOGGLES; + disable_Centaurus_9211_chip_select(); + + /* now toggle the clock */ + for (count = 0; count < num_clock_toggles; count++) { + toggle_Centaurus_9211_clock(); + } + return; + +} /* end Centaurus_write_gpio() */ + +unsigned long +Centaurus_read_gpio(int width, unsigned long address) +{ + int num_clock_toggles; + int count; + unsigned long Addr = address; + unsigned long data; + + enable_Centaurus_9211_chip_select(); + + /* Write 1 Clock period of no valid transfer */ + write_Centaurus_CX9211_GPIO(CENT_NO_DATA); + + /* Write 1 control bit (the data book calls this the control bar write) */ + write_Centaurus_CX9211_GPIO(0x1); + + /* Write the 12-bit address */ + for (count = 0; count < 12; count++) { + write_Centaurus_CX9211_GPIO((unsigned char)(Addr & 0x01)); + + /*the 9211 expects data LSB->MSB */ + Addr = Addr >> 1; + } + + data = read_Centaurus_CX9211_DWdata(); + + /* a read will require one toggle after disabling CS */ + num_clock_toggles = CENT_NUM_READ_CLOCK_TOGGLES; + disable_Centaurus_9211_chip_select(); + + /* now toggle the clock */ + for (count = 0; count < num_clock_toggles; count++) { + toggle_Centaurus_9211_clock(); + } + return data; + +} /* end Centaurus_read_gpio() */ + +/******************************************************************* + * + * void enable_Centaurus_9211_chip_select(void); + * Enables the chip select of the CX9211 using the National 97317 + * on a Centaurus board. + * + *******************************************************************/ + +void +enable_Centaurus_9211_chip_select(void) +{ + unsigned char cs_port_val; + + /* Set the chip select (GPIO20) high */ + cs_port_val = gfx_inb(CENT_97317_CHIP_SELECT); + gfx_outb(CENT_97317_CHIP_SELECT, + (unsigned char)(cs_port_val | CENT_97317_CHIP_SEL_MASK)); + return; + +} /* end enable_Centaurus_9211_chip_select() */ + +/******************************************************************** + * + * void disable_Centaurus_9211_chip_select(void); + * Disables the chip select of the CX9211 using the National 97317 + * on a Centaurus board. + * + *******************************************************************/ + +void +disable_Centaurus_9211_chip_select(void) +{ + unsigned char cs_port_val; + + /* Set the chip select (GPIO20) low */ + cs_port_val = gfx_inb(CENT_97317_CHIP_SELECT); + gfx_outb(CENT_97317_CHIP_SELECT, + (unsigned char)(cs_port_val & ~CENT_97317_CHIP_SEL_MASK)); + return; + +} /* end disable_Centaurus_9211_chip_select() */ + +/********************************************************************** + * + * void toggle_Centaurus_9211_clock(void); + * Toggles the clock bit of the CX9211 using the National 97317 on a + * Centaurus board. Assumes the 9211 clock bit has previously been + * initialized to 0 (this way we do not have to waste GPIO cycles + * windowing the clock pulse). + * + **********************************************************************/ + +void +toggle_Centaurus_9211_clock(void) +{ + unsigned char port_val; + + /* get the 97317 GPIO port contents for the 9211 clock */ + + port_val = gfx_inb(CENT_97317_CLOCK_PORT); + /* set the clock bit high */ + gfx_outb(CENT_97317_CLOCK_PORT, + (unsigned char)(port_val | CENT_97317_CLOCK_MASK)); + + /* set the clock bit low */ + gfx_outb(CENT_97317_CLOCK_PORT, + (unsigned char)(port_val & ~CENT_97317_CLOCK_MASK)); + +} /* end toggle_Centaurus_9211_clock() */ + +/******************************************************************** + * + * void write_Centaurus_CX9211_GPIO(unsigned char databit); + * Writes the value in bit 0 of the value passed in databit to + * the 9211 through the GPIO interface of the National 97317 on a + * Centaurus board. + * NOTE: This function does not set or reset the chip select line! + * + *******************************************************************/ + +void +write_Centaurus_CX9211_GPIO(unsigned char databit) +{ + unsigned char data_port_val; + + /* Set the data bit for (GPIO17) */ + databit <<= 7; + + /* read the value of the other bits in the 97317 data port */ + data_port_val = gfx_inb(CENT_97317_DATA_OUTPORT); + + /* set the bit accordingly */ + data_port_val &= ~CENT_97317_DATA_OUT_MASK; + data_port_val |= databit; + gfx_outb(CENT_97317_DATA_OUTPORT, data_port_val); + + /* clock the data */ + toggle_Centaurus_9211_clock(); + return; + +} /* end write_Centaurus_CX9211_GPIO() */ + +/***************************************************************** + * + * void write_Centaurus_CX9211_DWdata(unsigned long data); + * Writes the doubleword value passed in data to the CX9211 + * using GPIO Pins of the National 97317 on a Centaurus board. + * This function assumes the Direction register of the 97317 + * and the address register of the CX9211 have been previously set. + * Uses the global variable count. + * NOTE: This function does not set or reset the chip select line! + * + ******************************************************************/ + +void +write_Centaurus_CX9211_DWdata(unsigned long data) +{ + int count; + + /* Send the read/write command to the 9211 first. */ + + write_Centaurus_CX9211_GPIO(CENT_WRITE); + + /* Now write the 32-bit Data */ + for (count = 0; count < 32; count++) { + write_Centaurus_CX9211_GPIO((unsigned char)(data & 0x01)); + + /* the 9211 expects the data LSB->MSB */ + data >>= 1; + } + return; + +} /* end write_Centaurus_CX9211_DWdata() */ + +/********************************************************************* + * + * unsigned char read_Centaurus_CX9211_GPIO(void); + * Returns the current value of the databit of the 9211 in bit 0 + * using the GPIO interface of the National 97317 on a Centaurus board. + * NOTE: This function does not set or reset the chip select line! + * + *********************************************************************/ + +unsigned char +read_Centaurus_CX9211_GPIO(void) +{ + unsigned char data_port_val; + + toggle_Centaurus_9211_clock(); + + /* read the data */ + data_port_val = gfx_inb(CENT_97317_DATA_INPORT); + + /* Save the data from (GPIO21) as bit 0 */ + data_port_val >>= 1; + return (data_port_val & 0x1); + +} /* end read_Centaurus_CX9211_GPIO() */ + +/********************************************************************** + * + * void read_Centaurus_CX9211_DWdata(unsigned long *data); + * Reads a doubleword value from the CX9211 using GPIO Pins of + * the National 97317 on a Centaurus board. + * This function assumes the Direction register of the 97317 and + * the address register of the CX9211 have been previously set. + * NOTE: This function does not set or reset the chip select line! + * + ***********************************************************************/ + +unsigned long +read_Centaurus_CX9211_DWdata(void) +{ + unsigned char ReadData; + int count; + unsigned long Data; + + /* Send read/write command word to the 9211 first. */ + write_Centaurus_CX9211_GPIO(CENT_READ); + + /* The data book (revision 0.1) states 8 clock periods of no valid data. + * However, the data becomes valid on the eighth clock, making the eighth + * clock valid. Since read_Centaurus_GPIO() toggles the clock before + * reading, we will only toggle the clock 7 times here. + */ + for (count = 0; count < 7; count++) /* works */ + toggle_Centaurus_9211_clock(); + + /* Now read the 32-bit Data, bit by bit in a single loop. */ + Data = 0; + for (count = 0; count < 32; count++) { + ReadData = read_Centaurus_CX9211_GPIO(); + /* 9211 sends data LSB->MSB */ + Data = Data | (((unsigned long)ReadData) << count); + } /* end for() */ + + return Data; + +} /* end read_Centaurus_CX9211_DWdata() */ + +void +Centaurus_Get_9211_Details(unsigned long flags, PPnl_PanelParams pParam) +{ + unsigned long PanelType; + int i; + + for (i = 0; i < 0x7fff; i++) { + } + + init_Centaurus_GPIO(); + + for (i = 0; i < 5; i++) + toggle_Centaurus_9211_clock(); + + if (flags & PNL_PANELCHIP) { + + PanelType = Centaurus_read_gpio(FOUR_BYTES, 0x430); + PanelType = Centaurus_read_gpio(FOUR_BYTES, 0x430); + if ((PanelType & 0xFFFF0000) == 0x92110000) { + + /* found 9211 */ + /* check the values for revision ID */ + if (PanelType >= 0x92110301) + pParam->PanelChip = PNL_9211_C; + else if ((PanelType >= 0x92110101) && (PanelType < 0x92110301)) + pParam->PanelChip = PNL_9211_A; + else + pParam->PanelChip = PNL_UNKNOWN_CHIP; + } else { /* no 9211 present */ + pParam->PanelChip = PNL_UNKNOWN_CHIP; + } + Pnl_Rev_ID = pParam->PanelChip; + } + /* if end */ + if ((pParam->PanelChip != PNL_UNKNOWN_CHIP) && (flags & PNL_PANELSTAT)) { + PanelType = Centaurus_read_gpio(FOUR_BYTES, 0x438); + PanelType &= 0x00f8f8f8; + PanelType |= 0x00070000; + Centaurus_write_gpio(FOUR_BYTES, 0x438, PanelType); + PanelType = 0; + PanelType = Centaurus_read_gpio(FOUR_BYTES, 0x434); + PanelType = (PanelType >> 8); + PanelType &= 0x7; + + switch (PanelType) { + case 0: + pParam->PanelStat.XRes = 800; + pParam->PanelStat.YRes = 600; + pParam->PanelStat.Depth = 18; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_TFT; + break; + case 1: + pParam->PanelStat.XRes = 640; + pParam->PanelStat.YRes = 480; + pParam->PanelStat.Depth = 8; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_SSTN; + break; + case 2: + pParam->PanelStat.XRes = 1024; + pParam->PanelStat.YRes = 768; + pParam->PanelStat.Depth = 18; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_TFT; + break; + case 3: + pParam->PanelStat.XRes = 640; + pParam->PanelStat.YRes = 480; + pParam->PanelStat.Depth = 16; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_DSTN; + break; + case 4: + pParam->PanelStat.XRes = 640; + pParam->PanelStat.YRes = 480; + pParam->PanelStat.Depth = 18; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_TFT; + break; + case 5: + pParam->PanelStat.XRes = 1024; + pParam->PanelStat.YRes = 768; + pParam->PanelStat.Depth = 24; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_DSTN; + break; + case 6: + pParam->PanelStat.XRes = 640; + pParam->PanelStat.YRes = 480; + pParam->PanelStat.Depth = 8; + pParam->PanelStat.MonoColor = PNL_MONO_PANEL; + pParam->PanelStat.Type = PNL_DSTN; + break; + case 7: + pParam->PanelStat.XRes = 800; + pParam->PanelStat.YRes = 600; + pParam->PanelStat.Depth = 16; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_DSTN; + break; + default: + break; + } + } + +} + +void +CentaurusProgramFRMload(void) +{ + unsigned long CentaurusFRMtable[] = { + 0x00000000, + 0x00000000, + 0x01000100, + 0x01000100, + 0x01010101, + 0x01010101, + 0x02081041, + 0x02081041, + 0x10111111, + 0x11111101, + 0x49249241, + 0x12412492, + 0x92244891, + 0x92244891, + 0x22252525, + 0x22252525, + 0x528294a5, + 0x2528494a, + 0x294a5295, + 0x294a5295, + 0x54a54a95, + 0x2952a52a, + 0x2a552a55, + 0x2a552a55, + 0x554aa955, + 0x2a9552aa, + 0x2aaa5555, + 0x2aaa5555, + 0x55555555, + 0x2aaaaaaa, + 0x55555555, + 0x55555555, + 0xaaaaaaab, + 0x55555555, + 0x5555aaab, + 0x5555aaab, + 0xaab556ab, + 0x556aad55, + 0x55ab55ab, + 0x55ab55ab, + 0xab5ab56b, + 0x56ad5ad5, + 0x56b5ad6b, + 0x56b5ad6b, + 0xad6d6b5b, + 0x5ad6b6b6, + 0x5b5b5b5b, + 0x5b5b5b5b, + 0x5F6db6db, + 0x5F6db6db, + 0xF776F776, + 0xF776F776, + 0xFBDEFBDE, + 0xFBDEFBDE, + 0x7eFFBFF7, + 0x7eFFBFF7, + 0xFF7FF7F7, + 0xFF7FF7F7, + 0xFF7FFF7F, + 0xFF7FFF7F, + 0xFFF7FFFF, + 0xFFF7FFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + }; + + unsigned char i; + unsigned short index; + unsigned long data; + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_FRM_MEMORY_INDEX, 0); + index = CS92xx_FRM_MEMORY_DATA; + for (i = 0; i < 64; i += 2) { + data = CentaurusFRMtable[i]; + Centaurus_write_gpio(FOUR_BYTES, CS92xx_FRM_MEMORY_DATA, data); + data = CentaurusFRMtable[i + 1]; + Centaurus_write_gpio(FOUR_BYTES, CS92xx_FRM_MEMORY_DATA, data); + } + + /* + * The first FRM location (64 bits) does not program correctly. + * This location always reads back with the last value programmed. + * ie. If 32 64-bit values are programmed, location 0 reads + * back as the 32nd If 30 locations are programmed, location 0 + * reads back as the 30th, etc. + * Fix this by re-writing location 0 after programming all 64 in + * the writeFRM loop in RevCFrmload() in CS9211. + */ + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_FRM_MEMORY_INDEX, 0); + Centaurus_write_gpio(FOUR_BYTES, CS92xx_FRM_MEMORY_DATA, 0); + Centaurus_write_gpio(FOUR_BYTES, CS92xx_FRM_MEMORY_DATA, 0); +} + +/******************************************************************** + * + * void Centaurus_Enable_Power((void); + * Enables the power of the CX9211 using the National 97317 on + * a Centaurus board. + * + ********************************************************************/ + +void +Centaurus_Power_Up(void) +{ + unsigned long off_data = 0x01000000; + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_LCD_PWR_MAN, off_data); + return; + +} /* Centaurus_Disable_Power */ + +/*********************************************************************** + * + * void Centaurus_Disable_Power((void); + * Disables the power of the CX9211 using the National 97317 + * on a Centaurus board. + * + **********************************************************************/ + +void +Centaurus_Power_Down(void) +{ + unsigned long off_data = 0; + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_LCD_PWR_MAN, off_data); + return; + +} /* Centaurus_Disable_Power */ + +void +Centaurus_9211init(Pnl_PanelStat * pstat) +{ + init_Centaurus_GPIO(); + init_Centaurus_9211(); + set_Centaurus_92xx_mode(pstat); + restore_Centaurus_97317_SIOC2(); +} + +void +Centaurus_Save_Panel_State(void) +{ + /* set 9211 registers using the desired panel settings */ + + cs9211_regs.panel_timing1 = + Centaurus_read_gpio(FOUR_BYTES, CS92xx_LCD_PAN_TIMING1); + cs9211_regs.panel_timing2 = + Centaurus_read_gpio(FOUR_BYTES, CS92xx_LCD_PAN_TIMING2); + cs9211_regs.dither_frc_ctrl = + Centaurus_read_gpio(FOUR_BYTES, CS92xx_LCD_DITH_FR_CNTRL); + cs9211_regs.blue_lsfr_seed = + Centaurus_read_gpio(FOUR_BYTES, CS92xx_BLUE_LSFR_SEED); + + cs9211_regs.red_green_lsfr_seed = + Centaurus_read_gpio(FOUR_BYTES, CS92xx_RED_GREEN_LSFR_SEED); + /* CentaurusProgramFRMload(); */ + + cs9211_regs.memory_control = + Centaurus_read_gpio(FOUR_BYTES, CS92xx_LCD_MEM_CNTRL); + + /* Set the power register last. + * This will turn the panel on at the 9211. + */ + cs9211_regs.power_management = + Centaurus_read_gpio(FOUR_BYTES, CS92xx_LCD_PWR_MAN); +} + +void +Centaurus_Restore_Panel_State(void) +{ + + unsigned long off_data = 0; + + /* Before restoring the 9211 registers, power off the 9211. */ + Centaurus_write_gpio(FOUR_BYTES, CS92xx_LCD_PWR_MAN, off_data); + + /* set 9211 registers using the desired panel settings */ + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_LCD_PAN_TIMING1, + cs9211_regs.panel_timing1); + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_LCD_PAN_TIMING2, + cs9211_regs.panel_timing2); + + /* load the LSFR seeds */ + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_LCD_DITH_FR_CNTRL, + cs9211_regs.dither_frc_ctrl); + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_BLUE_LSFR_SEED, + cs9211_regs.blue_lsfr_seed); + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_RED_GREEN_LSFR_SEED, + cs9211_regs.red_green_lsfr_seed); + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_LCD_MEM_CNTRL, + cs9211_regs.memory_control); + + /* Set the power register last. This will turn the panel on at the 9211. */ + + Centaurus_write_gpio(FOUR_BYTES, CS92xx_LCD_PWR_MAN, + cs9211_regs.power_management); + +} --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/cen9211.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/cen9211.h 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This header file defines the Durango routines and + * variables used to access the memory mapped regions. + * + * SubModule: Geode FlatPanel library + * */ + + +#include "92xx.h" +#include "panel.h" + +#ifndef _CEN9211_h +#define _CEN9211_h + +/* Centaurus/97317 GPIO PORT defines */ + +#define CENT_97317_CLOCK_PORT 0xE0 +#define CENT_97317_DATA_OUTPORT 0xE0 +#define CENT_97317_CHIP_SELECT 0xE4 +#define CENT_97317_DATA_INPORT 0xE4 +#define CENT_PORT1_DIRECTION 0xE1 +#define CENT_PORT2_DIRECTION 0xE5 +#define CENT_PORT1_OUTPUT_TYPE 0xE2 +#define CENT_PORT2_OUTPUT_TYPE 0xE6 + +/* + * Centaurus/97317 GPIO bit masks. + * In and out are with respect to the 97317. + */ + +#define CENT_97317_CLOCK_MASK 0x10 +#define CENT_97317_CHIP_SEL_MASK 0x01 +#define CENT_97317_DATA_IN_MASK 0x02 +#define CENT_97317_DATA_OUT_MASK 0x80 + +#define CENT_PASS 1 +#define CENT_FAIL 0 +#define CENT_READ 0x0000 +#define CENT_WRITE 0x0001 +#define CENT_NO_DATA 0 + +#define CENT_CONFIG_INDEX 0x2E +#define CENT_SIOC2 0x22 +#define CENT_CONFIG_DATA 0x2F +#define CENT_GPIO_BANK_SELECT 0x80 + +#define CENT_NUM_READ_CLOCK_TOGGLES 1 +#define CENT_NUM_WRITE_CLOCK_TOGGLES 4 + +/* local functions */ +void set_Centaurus_92xx_mode_params(int mode); +void enable_Centaurus_9211_chip_select(void); +void disable_Centaurus_9211_chip_select(void); +void toggle_Centaurus_9211_clock(void); +void write_Centaurus_CX9211_GPIO(unsigned char databit); +void write_Centaurus_CX9211_DWdata(unsigned long data); +void Centaurus_write_gpio(int width, unsigned long address, + unsigned long data); +void Centaurus_Power_Up(void); +void Centaurus_Power_Down(void); +unsigned long Centaurus_read_gpio(int width, unsigned long address); +unsigned char read_Centaurus_CX9211_GPIO(void); +unsigned long read_Centaurus_CX9211_DWdata(void); +unsigned char restore_Centaurus_97317_SIOC2(void); +unsigned char init_Centaurus_GPIO(void); +unsigned char init_Centaurus_9211(void); +unsigned char set_Centaurus_92xx_mode(Pnl_PanelStat * pstat); +void CentaurusProgramFRMload(void); +void Centaurus_Get_9211_Details(unsigned long flags, PPnl_PanelParams pParam); +void Centaurus_Save_Panel_State(void); +void Centaurus_Restore_Panel_State(void); +void Centaurus_9211init(Pnl_PanelStat * pstat); + +#endif /* !_CEN9211_h */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/dora9211.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/dora9211.c 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,607 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This file contains the panel functions to interface + * the dorado platform. + * + * SubModule: Geode FlatPanel library + * */ + + +#include "dora9211.h" + +void +Dorado_Get_9211_Details(unsigned long flags, PPnl_PanelParams pParam) +{ + unsigned long DPanelType; + int i; + + for (i = 0; i < 0x7fff; i++) { + } + + Dorado9211GpioInit(); + + for (i = 0; i < 5; i++) + toggle_Centaurus_9211_clock(); + + if (flags & PNL_PANELCHIP) { + DPanelType = Dorado9211ReadReg(0x430); + + if ((DPanelType & 0xFFFF0000) == 0x92110000) { /* found 9211 */ + /* check the values for revision ID */ + if (DPanelType >= 0x92110301) + pParam->PanelChip = PNL_9211_C; + else if ((DPanelType >= 0x92110101) && (DPanelType < 0x92110301)) + pParam->PanelChip = PNL_9211_A; + else + pParam->PanelChip = PNL_UNKNOWN_CHIP; + } else { /* no 9211 present */ + pParam->PanelChip = PNL_UNKNOWN_CHIP; + } + } + + if ((pParam->PanelChip != PNL_UNKNOWN_CHIP) && (flags & PNL_PANELSTAT)) { + unsigned long PanelTypeOrg; + unsigned char Panel_2Byte; + + DPanelType = Dorado9211ReadReg(0x438); + DPanelType &= 0x00e8e8e8; + DPanelType |= 0x00170000; + Dorado9211WriteReg(0x438, DPanelType); + DPanelType = 0; + + DPanelType = Dorado9211ReadReg(0x434); + DPanelType = (DPanelType >> (DRD_LCDRESGPIO1 + 1)); + PanelTypeOrg = DPanelType >> 8; + Panel_2Byte = (unsigned char)PanelTypeOrg; + Panel_2Byte = (Panel_2Byte >> (DRD_LCDRESGPIO2 - DRD_LCDRESGPIO1 - 1)); + DPanelType = (DPanelType | ((unsigned int)Panel_2Byte << 8)); + DPanelType = DPanelType >> 1; + PanelTypeOrg = DPanelType >> 8; + Panel_2Byte = (unsigned char)PanelTypeOrg; + Panel_2Byte = (Panel_2Byte >> (DRD_LCDRESGPIO3 - DRD_LCDRESGPIO2 - 1)); + DPanelType = (DPanelType | ((unsigned int)Panel_2Byte << 8)); + DPanelType = DPanelType >> 1; + PanelTypeOrg = DPanelType >> 8; + Panel_2Byte = (unsigned char)PanelTypeOrg; + Panel_2Byte = (Panel_2Byte >> (DRD_LCDRESGPIO4 - DRD_LCDRESGPIO3 - 1)); + DPanelType = (DPanelType | ((unsigned int)Panel_2Byte << 8)); + DPanelType = DPanelType >> 5; + DPanelType &= 0xf; + + switch (DPanelType) { + case 8: + pParam->PanelStat.XRes = 800; + pParam->PanelStat.YRes = 600; + pParam->PanelStat.Depth = 18; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_TFT; + break; + + case 9: + pParam->PanelStat.XRes = 640; + pParam->PanelStat.YRes = 480; + pParam->PanelStat.Depth = 8; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_SSTN; + break; + + case 10: + pParam->PanelStat.XRes = 1024; + pParam->PanelStat.YRes = 768; + pParam->PanelStat.Depth = 18; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_TFT; + break; + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + case 11: + pParam->PanelStat.XRes = 640; + pParam->PanelStat.YRes = 480; + pParam->PanelStat.Depth = 16; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_DSTN; + break; + case 12: + pParam->PanelStat.XRes = 640; + pParam->PanelStat.YRes = 480; + pParam->PanelStat.Depth = 18; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_TFT; + break; + case 13: + pParam->PanelStat.XRes = 1024; + pParam->PanelStat.YRes = 768; + pParam->PanelStat.Depth = 24; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_DSTN; + break; + case 14: + pParam->PanelStat.XRes = 640; + pParam->PanelStat.YRes = 480; + pParam->PanelStat.Depth = 8; + pParam->PanelStat.MonoColor = PNL_MONO_PANEL; + pParam->PanelStat.Type = PNL_DSTN; + break; + case 15: + pParam->PanelStat.XRes = 800; + pParam->PanelStat.YRes = 600; + pParam->PanelStat.Depth = 16; + pParam->PanelStat.MonoColor = PNL_COLOR_PANEL; + pParam->PanelStat.Type = PNL_DSTN; + break; + default: + break; + } + } + /* if block end */ +} + +void +Dorado9211Init(Pnl_PanelStat * pstat) +{ + int mode; + unsigned long orig_value, pm_value; + + gfx_delay_milliseconds(100); + Dorado9211GpioInit(); + + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + + gfx_delay_milliseconds(100); + + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + + Dorado9211WriteReg(CS92xx_LCD_PWR_MAN, 0x0); + + gfx_delay_milliseconds(100); + gfx_delay_milliseconds(100); + + /* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */ + for (mode = 0; mode < NUM_92XX_MODES; mode++) { + if ((FPModeParams[mode].xres == pstat->XRes) && + (FPModeParams[mode].yres == pstat->YRes) && + (FPModeParams[mode].bpp == pstat->Depth) && + (FPModeParams[mode].panel_type == pstat->Type) && + (FPModeParams[mode].color_type == pstat->MonoColor)) { + + /* SET THE 92xx FOR THE SELECTED MODE */ + CS92xx_MODE *pMode = &FPModeParams[mode]; + + Dorado9211WriteReg(CS92xx_LCD_PAN_TIMING1, pMode->panel_timing1); + Dorado9211WriteReg(CS92xx_LCD_PAN_TIMING2, pMode->panel_timing2); + Dorado9211WriteReg(CS92xx_LCD_DITH_FR_CNTRL, + pMode->rev_C_dither_frc); + Dorado9211WriteReg(CS92xx_BLUE_LSFR_SEED, pMode->blue_lsfr_seed); + Dorado9211WriteReg(CS92xx_RED_GREEN_LSFR_SEED, + pMode->red_green_lsfr_seed); + DoradoProgramFRMload(); + Dorado9211WriteReg(CS92xx_LCD_MEM_CNTRL, pMode->memory_control); + Dorado9211WriteReg(CS92xx_LCD_PWR_MAN, pMode->power_management); + gfx_delay_milliseconds(100); + gfx_delay_milliseconds(100); + Dorado9211ClearCS(); + + /* This code is added to take care of Panel initialization. + * Irrespective of Xpressrom is enabling the panel or not. + */ + orig_value = READ_VID32(0X04); + WRITE_VID32(0x04, 0x00200141); + gfx_delay_milliseconds(21); + pm_value = gfx_ind(0x9030); + + pm_value |= 0x400; + gfx_outd(0x9030, pm_value); + gfx_delay_milliseconds(4); + orig_value &= 0xfff1ffff; + WRITE_VID32(0X4, orig_value); + return; + } /*end if() */ + } /*end for() */ + +} + +void +Dorado9211SetCS(void) +{ + unsigned long value; + + value = gfx_ind(DRD_CSP9211IN); + gfx_outd(DRD_CSP9211OUT, value | DRD_CS9211); +} + +void +Dorado9211ClearCS(void) +{ + unsigned long value; + + value = gfx_ind(DRD_CSP9211IN); + gfx_outd(DRD_CSP9211OUT, value & (~DRD_CS9211)); +} + +void +Dorado9211SetDataOut(void) +{ + unsigned long value; + + value = gfx_ind(DRD_DATAOUTP9211IN); + gfx_outd(DRD_DATAOUTP9211OUT, value | DRD_DATAIN9211); +} + +void +Dorado9211ClearDataOut(void) +{ + unsigned long value; + + value = gfx_ind(DRD_DATAOUTP9211IN); + gfx_outd(DRD_DATAOUTP9211OUT, value & (~DRD_DATAIN9211)); +} + +unsigned char +Dorado9211ReadDataIn(void) +{ + unsigned char readdata = 0; + unsigned long value; + + /* why to read 4 times ??? */ + value = gfx_ind(DRD_DATAINP9211IN); + value = gfx_ind(DRD_DATAINP9211IN); + value = gfx_ind(DRD_DATAINP9211IN); + value = gfx_ind(DRD_DATAINP9211IN); + if (value & DRD_DATAOUT9211) + readdata = 1; + return (readdata); +} + +void +Dorado9211ToggleClock(void) +{ + Dorado9211SetClock(); + Dorado9211ClearClock(); +} + +void +Dorado9211SetClock(void) +{ + unsigned long value; + + value = gfx_ind(DRD_CLOCKP9211IN); + gfx_outd(DRD_CLOCKP9211OUT, value | DRD_CLOCK9211); +} + +void +Dorado9211ClearClock(void) +{ + unsigned long value; + + value = gfx_ind(DRD_CLOCKP9211IN); + gfx_outd(DRD_CLOCKP9211OUT, value & (~DRD_CLOCK9211)); +} + +void +Dorado9211GpioInit(void) +{ + unsigned long value; + + /* set output enable on gpio 7, 9, 11 */ + gfx_outd((DRD_GEODE_GPIO_BASE + DRD_GEODE_GPPIN_SEL), DRD_CLOCK9211CFG); + gfx_outd((DRD_GEODE_GPIO_BASE + DRD_GEODE_GPPIN_CFG), 3); + /* set output enable on gpio 7, 9, 11 */ + gfx_outd((DRD_GEODE_GPIO_BASE + DRD_GEODE_GPPIN_SEL), DRD_CS9211CFG); + gfx_outd((DRD_GEODE_GPIO_BASE + DRD_GEODE_GPPIN_CFG), 3); + /* set output enable on gpio 7, 9, 18 */ + gfx_outd((DRD_GEODE_GPIO_BASE + DRD_GEODE_GPPIN_SEL), DRD_DATAIN9211CFG); + gfx_outd((DRD_GEODE_GPIO_BASE + DRD_GEODE_GPPIN_CFG), 3); + /* disable on gpio 11 - This is the output from the 9211 */ + gfx_outd((DRD_GEODE_GPIO_BASE + DRD_GEODE_GPPIN_SEL), DRD_DATAOUT9211CFG); + gfx_outd((DRD_GEODE_GPIO_BASE + DRD_GEODE_GPPIN_CFG), 0); + /* Set all PINS low */ + value = gfx_ind(DRD_GEODE_GPIO_BASE + DRD_GEODE_GPDI0); + value &= ~(DRD_CS9211 | DRD_CLOCK9211 | DRD_DATAIN9211); + gfx_outd((DRD_GEODE_GPIO_BASE + DRD_GEODE_GPDO0), value); +} + +unsigned long +Dorado9211ReadReg(unsigned short index) +{ + + unsigned char i, readbit; + unsigned long data; + + Dorado9211ClearDataOut(); + + Dorado9211SetCS(); + Dorado9211ToggleClock(); + + Dorado9211SetDataOut(); + Dorado9211ToggleClock(); + + for (i = 0; i < 12; i++) { + if (index & 0x1) { + Dorado9211SetDataOut(); + } else { + Dorado9211ClearDataOut(); + } + Dorado9211ToggleClock(); + index >>= 1; + } + + Dorado9211ClearDataOut(); + Dorado9211ToggleClock(); + + /* Idle clock, 7 clocks, no data set */ + + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + + data = 0; + for (i = 0; i < 32; i++) { + Dorado9211ToggleClock(); + readbit = Dorado9211ReadDataIn(); + data |= (((unsigned long)readbit) << i); + } + + Dorado9211ClearCS(); + Dorado9211ToggleClock(); + return (data); + +} + +void +Dorado9211WriteReg(unsigned short index, unsigned long data) +{ + + unsigned char i; + + Dorado9211ClearDataOut(); + Dorado9211SetDataOut(); + Dorado9211SetCS(); + Dorado9211ToggleClock(); + Dorado9211SetDataOut(); + Dorado9211ToggleClock(); + + for (i = 0; i < 12; i++) { + if (index & 0x1) { + Dorado9211SetDataOut(); + } else { + Dorado9211ClearDataOut(); + } + Dorado9211ToggleClock(); + index >>= 1; + } + + Dorado9211SetDataOut(); + Dorado9211ToggleClock(); + + for (i = 0; i < 32; i++) { + if (data & 0x1) { + Dorado9211SetDataOut(); + } else { + Dorado9211ClearDataOut(); + } + Dorado9211ToggleClock(); + data >>= 1; + } + + Dorado9211ClearCS(); + + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); + Dorado9211ToggleClock(); +} + +void +DoradoProgramFRMload(void) +{ + unsigned long DoradoFRMtable[] = { + + 0x00000000, + 0x00000000, + 0x01000100, + 0x01000100, + 0x01010101, + 0x01010101, + 0x02081041, + 0x02081041, + 0x10111111, + 0x11111101, + 0x49249241, + 0x12412492, + 0x92244891, + 0x92244891, + 0x22252525, + 0x22252525, + 0x528294a5, + 0x2528494a, + 0x294a5295, + 0x294a5295, + 0x54a54a95, + 0x2952a52a, + 0x2a552a55, + 0x2a552a55, + 0x554aa955, + 0x2a9552aa, + 0x2aaa5555, + 0x2aaa5555, + 0x55555555, + 0x2aaaaaaa, + 0x55555555, + 0x55555555, + 0xaaaaaaab, + 0x55555555, + 0x5555aaab, + 0x5555aaab, + 0xaab556ab, + 0x556aad55, + 0x55ab55ab, + 0x55ab55ab, + 0xab5ab56b, + 0x56ad5ad5, + 0x56b5ad6b, + 0x56b5ad6b, + 0xad6d6b5b, + 0x5ad6b6b6, + 0x5b5b5b5b, + 0x5b5b5b5b, + 0x5F6db6db, + 0x5F6db6db, + 0xF776F776, + 0xF776F776, + 0xFBDEFBDE, + 0xFBDEFBDE, + 0x7eFFBFF7, + 0x7eFFBFF7, + 0xFF7FF7F7, + 0xFF7FF7F7, + 0xFF7FFF7F, + 0xFF7FFF7F, + 0xFFF7FFFF, + 0xFFF7FFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + }; + + unsigned char i; + unsigned short index; + unsigned long data; + + Dorado9211WriteReg(CS92xx_FRM_MEMORY_INDEX, 0); + index = CS92xx_FRM_MEMORY_DATA; + for (i = 0; i < 64; i += 2) { + data = DoradoFRMtable[i]; + Dorado9211WriteReg(index, data); + data = DoradoFRMtable[i + 1]; + Dorado9211WriteReg(index, data); + } + +/* + * The first FRM location (64 bits) does not program correctly. + * This location always reads back with the last value programmed. + * ie. If 32 64-bit values are programmed, location 0 reads back as the 32nd + * If 30 locations are programmed, location 0 reads back as the 30th, etc. + * Fix this by re-writing location 0 after programming all 64 in the writeFRM + * loop in RevCFrmload() in CS9211. + */ + + Dorado9211WriteReg(CS92xx_FRM_MEMORY_INDEX, 0); + Dorado9211WriteReg(CS92xx_FRM_MEMORY_DATA, 0); + Dorado9211WriteReg(CS92xx_FRM_MEMORY_DATA, 0); + +} + +/****************************************************************************** + * void Dorado_Enable_Power((void); + * Enables the power of the CX9211 on Dorado board. + ****************************************************************************** + */ + +void +Dorado_Power_Up(void) +{ + Dorado9211WriteReg(CS92xx_LCD_PWR_MAN, 0x01000000); + return; + +} /* disable_Centaurus_Power */ + +/****************************************************************************** + * void Dorado_Disable_Power((void); + * Disables the power of the CX9211 on Dorado board. + ***************************************************************************** + */ + +void +Dorado_Power_Down(void) +{ + Dorado9211WriteReg(CS92xx_LCD_PWR_MAN, 0x0); + return; + +} /* disable_Centaurus_Power */ + +void +Dorado_Save_Panel_State(void) +{ + + /* set 9211 registers using the desired panel settings */ + cs9211_regs.panel_timing1 = Dorado9211ReadReg(CS92xx_LCD_PAN_TIMING1); + cs9211_regs.panel_timing2 = Dorado9211ReadReg(CS92xx_LCD_PAN_TIMING2); + + cs9211_regs.dither_frc_ctrl = Dorado9211ReadReg(CS92xx_LCD_DITH_FR_CNTRL); + cs9211_regs.blue_lsfr_seed = Dorado9211ReadReg(CS92xx_BLUE_LSFR_SEED); + cs9211_regs.red_green_lsfr_seed = + Dorado9211ReadReg(CS92xx_RED_GREEN_LSFR_SEED); + + /* CentaurusProgramFRMload(); */ + cs9211_regs.memory_control = Dorado9211ReadReg(CS92xx_LCD_MEM_CNTRL); + + /* Set the power register last. This will turn the panel on at the 9211. */ + cs9211_regs.power_management = Dorado9211ReadReg(CS92xx_LCD_PWR_MAN); + cs9211_regs.panel_state = cs9211_regs.power_management; +} + +void +Dorado_Restore_Panel_State(void) +{ + unsigned long off_data = 0; + + /* Before restoring the 9211 registers, power off the 9211. */ + + Dorado9211WriteReg(CS92xx_LCD_PWR_MAN, off_data); + + /* set 9211 registers using the desired panel settings */ + Dorado9211WriteReg(CS92xx_LCD_PAN_TIMING1, cs9211_regs.panel_timing1); + Dorado9211WriteReg(CS92xx_LCD_PAN_TIMING2, cs9211_regs.panel_timing2); + /* load the LSFR seeds */ + Dorado9211WriteReg(CS92xx_LCD_DITH_FR_CNTRL, cs9211_regs.dither_frc_ctrl); + Dorado9211WriteReg(CS92xx_BLUE_LSFR_SEED, cs9211_regs.blue_lsfr_seed); + Dorado9211WriteReg(CS92xx_RED_GREEN_LSFR_SEED, + cs9211_regs.red_green_lsfr_seed); + + Dorado9211WriteReg(CS92xx_LCD_MEM_CNTRL, cs9211_regs.memory_control); + /* Set the power register last. This will turn the panel on at the 9211. */ + Dorado9211WriteReg(CS92xx_LCD_PWR_MAN, cs9211_regs.power_management); +} --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/dora9211.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/dora9211.h 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This header file defines the Durango routines and + * variables used to access the memory mapped regions. + * + * SubModule: Geode FlatPanel library + * */ + + +#include "panel.h" +#include "92xx.h" + +#ifndef _DORA9211_h +#define _DORA9211_h + +/* 9211 Rev.C3 Dorado */ + +/* GPIO Pin Configuration Registers */ + +#define DRD_GEODE_GPPIN_SEL 0x20 /* GPIO Pin Configuration Select */ +#define DRD_GEODE_GPPIN_CFG 0x24 /* GPIO Pin Configuration Access */ +#define DRD_GEODE_GPPIN_RESET 0x28 /* GPIO Pin Reset */ + +#define DRD_GEODE_GPIO_BASE 0x6400 /* F0 GPIO, IO mapped */ +#define DRD_GEODE_GPDI0 0x04 /* GPIO Data In 0 */ +#define DRD_GEODE_GPDO0 0x00 /* GPIO Data Out 0 */ + +/* Data Ports in */ +#define DRD_CLOCKP9211IN DRD_GEODE_GPIO_BASE + DRD_GEODE_GPDI0 +#define DRD_DATAINP9211IN DRD_GEODE_GPIO_BASE + DRD_GEODE_GPDI0 +#define DRD_DATAOUTP9211IN DRD_GEODE_GPIO_BASE + DRD_GEODE_GPDI0 +#define DRD_CSP9211IN DRD_GEODE_GPIO_BASE + DRD_GEODE_GPDI0 + +/* Data Ports out */ +#define DRD_CLOCKP9211OUT DRD_GEODE_GPIO_BASE + DRD_GEODE_GPDO0 +#define DRD_DATAINP9211OUT DRD_GEODE_GPIO_BASE + DRD_GEODE_GPDO0 +#define DRD_DATAOUTP9211OUT DRD_GEODE_GPIO_BASE + DRD_GEODE_GPDO0 +#define DRD_CSP9211OUT DRD_GEODE_GPIO_BASE + DRD_GEODE_GPDO0 + +/* Pin MASKS */ +#define DRD_CLOCK9211 0x00000080 /*;gpio 7, clock output to 9211 */ +#define DRD_DATAIN9211 0x00040000 /*;gpio 18, data output to 9211 */ +#define DRD_DATAOUT9211 0x00000800 /*;gpio 11, data input from 9211 */ +#define DRD_CS9211 0x00000200 /*;gpio 9, chip select output to 9211 */ + +/* Gpio CFG values to select in */ +#define DRD_CLOCK9211CFG 0x00000007 /* ;gpio 7 */ +#define DRD_DATAIN9211CFG 0x00000012 /* ;gpio 18 */ +#define DRD_DATAOUT9211CFG 0x0000000B /* ;gpio 11 */ +#define DRD_CS9211CFG 0x00000009 /* ;gpio 9 */ + +#define DRD_LCDRESGPIO1 0x00 +#define DRD_LCDRESGPIO2 0x01 +#define DRD_LCDRESGPIO3 0x02 +#define DRD_LCDRESGPIO4 0x04 + +void Dorado9211SetCS(void); +void Dorado9211ClearCS(void); +void Dorado9211SetDataOut(void); +void Dorado9211ClearDataOut(void); +unsigned char Dorado9211ReadDataIn(void); +void Dorado9211ToggleClock(void); +void Dorado9211SetClock(void); +void Dorado9211ClearClock(void); +void Dorado9211GpioInit(void); +unsigned long Dorado9211ReadReg(unsigned short index); +void Dorado9211WriteReg(unsigned short index, unsigned long data); +void DoradoProgramFRMload(void); +void Dorado_Get_9211_Details(unsigned long flags, PPnl_PanelParams pParam); +void Dorado_Power_Up(void); +void Dorado_Power_Down(void); +void Dorado_Save_Panel_State(void); +void Dorado_Restore_Panel_State(void); +void Dorado9211Init(Pnl_PanelStat * pstat); + +#endif /* !_DORA9211_h */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/panel.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/panel.c 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This file contains the file inclusions, macro definitions + * for the panel. + * + * SubModule: Geode FlatPanel library + * */ + + + +#if defined(linux) /* Linux */ + +#ifdef __KERNEL__ + +#include +#include + +#elif !defined(XFree86Server) + +#include +#include + +#endif /* __KERNEL__ */ +#elif defined(_WIN32) /* windows */ + +#include + +#endif + +#include "panel.h" +#include "gfx_defs.h" + +extern unsigned char *gfx_virt_regptr; +extern unsigned char *gfx_virt_fbptr; +extern unsigned char *gfx_virt_vidptr; +extern unsigned char *gfx_virt_vipptr; +extern unsigned long gfx_detect_video(void); + +#define PLATFORM_DYNAMIC 1 /* runtime selection */ +#define PLATFORM_DRACO 1 /* Draco + 9210 */ +#define PLATFORM_CENTAURUS 1 /* Centaurus + 9211 RevA */ +#define PLATFORM_DORADO 1 /* Dorado + 9211 RevC */ +#define PLATFORM_REDCLOUD 1 /* GX2 */ + +unsigned char *XpressROMPtr; + +#include "pnl_init.c" +#include "pnl_bios.c" --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/panel.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/panel.h 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This file contains the Geode frame buffer panel + * functions prototypes and it includes panel + * definitions header file. + * + * SubModule: Geode FlatPanel library + * */ + + + +/* COMPILER OPTION FOR C++ PROGRAMS */ + +#ifndef _panel_h +#define _panel_h + +#include "pnl_defs.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* CLOSE BRACKET FOR C++ COMPLILATION */ + + void Pnl_SetPlatform(int platform); + int Pnl_GetPlatform(void); + int Pnl_IsPanelPresent(void); + void Pnl_SetPanelPresent(int present); + void Pnl_SetPanelChip(int panelChip); + int Pnl_GetPanelChip(void); + void Pnl_SetPanelParam(PPnl_PanelParams pParam); + void Pnl_GetPanelParam(PPnl_PanelParams pParam); + int Pnl_InitPanel(PPnl_PanelParams pParam); + int Detect_Platform(void); + void Pnl_SavePanelState(void); + void Pnl_RestorePanelState(void); + void Pnl_PowerUp(void); + void Pnl_PowerDown(void); + + int Pnl_IsPanelEnabledInBIOS(void); + void Pnl_GetPanelInfoFromBIOS(int *xres, int *yres, int *bpp, int *hz); +/* from durango */ + +#if defined(_WIN32) /* windows */ + extern void gfx_delay_milliseconds(unsigned long milliseconds); + extern unsigned long gfx_ind(unsigned short port); + extern void gfx_outd(unsigned short port, unsigned long data); + extern unsigned char gfx_inb(unsigned short port); + extern void gfx_outb(unsigned short port, unsigned char data); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !_panel_h */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/gx2_9211.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/gx2_9211.c 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This file contains the panel library files to the + * GX2 platforms with 9211 support. + * + * SubModule: Geode FlatPanel library + * */ + + + +#include "92xx.h" +#include "gx2_9211.h" +#include "pnl_defs.h" + +#if defined(_WIN32) /*windows */ +#include "gfx_defs.h" + +extern DEV_STATUS gfx_msr_read(unsigned int device, unsigned int msrRegister, + Q_WORD * msrValue); +extern DEV_STATUS gfx_msr_write(unsigned int device, unsigned int msrRegister, + Q_WORD * msrValue); +#endif + +static unsigned long FPBaseAddr; + +void +SetFPBaseAddr(unsigned long addr) +{ + + FPBaseAddr = addr; +} + +/**************************************************************************** + * protected_mode_access( unsigned long mode, unsigned long width, + * unsigned long addr, unsigned char* pdata ) + * This function provides access to physical memory at the requested address. + * mode is: + * GX2_READ or GX2_WRITE (accesses a single byte, word or double + * word depending on the value of "width". Only 1, 2 or 4 supported). + * READ_BYTES, WRITE_BYTES accesses "width" number of bytes (8 bits) + * READ_WORDS, WRITE_WORDS accesses "width" number of words (16 bits) + * READ_DWORDS, WRITE_DWORDS accesses "width" number of dwords (32 bits) + * width is: The size of the access. For READ or WRITE, only 1, 2 and 4 are + * supported. For other modes, width is not limited but will cause + * paging if the block traverses page boundaries. + * addr is: The physical address being accessed + * pdata is: A pointer to the data to be read or written into. + * NOTE! WORD or DWORD accesses can only be made on WORD or DWORD boundaries! + ****************************************************************************/ +void +protected_mode_access(unsigned long mode, + unsigned long width, + unsigned long addr, char *pdata) +{ + void *ptr = (void *)(FPBaseAddr + addr); + + /* type specific buffer pointers */ + char *byte_data = (char *)pdata; + unsigned long *word_data = (unsigned long *)pdata; + unsigned long *dword_data = (unsigned long *)pdata; + + if (mode == GX2_READ) { + switch (width) { + case FOUR_BYTES: + *(dword_data) = (unsigned long)(*(unsigned long *)ptr); + break; + case TWO_BYTES: + *(word_data) = (unsigned long)(*(unsigned long *)ptr); + break; + default: + *(byte_data) = (char)(*(char *)ptr); + break; + } + } /* end GX2_READ */ + else if (mode == GX2_WRITE) { + switch (width) { + case FOUR_BYTES: + *(unsigned long *)ptr = *dword_data; + break; + case TWO_BYTES: + *(unsigned long *)ptr = *word_data; + break; + default: + *(char *)ptr = *byte_data; + break; + } /* end switch(mode) */ + } + /* end case GX2_WRITE */ + return; + +} /* End of protected_mode_access. */ + +/************************************************************************* + * void write_video_reg64_low( unsigned long offset, unsigned long value ) + * Writes value to the low 32 bits of the 64 bit memory mapped video + * register indicated by offset. + * This function uses Sys_info.video_reg_base as the base address, so + * the value of offset should be with respect to this base. + *************************************************************************/ +void +write_video_reg64_low(unsigned long offset, unsigned long value) +{ + protected_mode_access(GX2_WRITE, FOUR_BYTES, + FPBaseAddr + offset, (char *)&value); +} /*end write_video_reg64_low() */ + +/************************************************************************* + * unsigned long read_video_reg64_low( unsigned long offset ) + * Returns the contents of the low 32 bits of the 64 bit memory mapped + * video register indicated by offset. + * This function uses Sys_info.video_reg_base as the base address, so + * the value of offset should be with respect to this base. + *************************************************************************/ +unsigned long +read_video_reg64_low(unsigned long offset) +{ + unsigned long data; + + protected_mode_access(GX2_READ, FOUR_BYTES, + FPBaseAddr + offset, (char *)&data); + return (data); +} /*end read_video_reg64_low() */ + +/******************************************************************************* + * void Redcloud_fp_reg( int mode, unsigned long address, unsigned long *data ) + * + * Writes and reads dwords to the Redcloud flat panel registers in the Redcloud + * Display Filter. There's no clock control, chip select or timing to deal with. + * This routine expects the actual GX2 macro definitions for the address. + * + * Parameters: + * mode: An integer value for a GX2_READ or GX2_WRITE operation + * 0 = GX2_Read and 1 = GX2_Write + * address: A dword value representing the offset of the register. + * data: A pointer to a dword value that is to be written in to + * the required register. In case of a Read operation this + * will point to the result of the Read operation. + * + *******************************************************************************/ +void +Redcloud_fp_reg(int mode, unsigned long address, unsigned long *data) +{ + if (mode == GX2_READ) { + *data = read_video_reg64_low(address); + } else { + write_video_reg64_low(address, *data); + } + +} /* End of Redcloud_fp_reg() */ + +/*------------------------------------------------------------------- + * + * SET_92XX_MODE_PARAMS + * This routine sets the 9211 mode parameters. + * + *-------------------------------------------------------------------*/ + +void +set_Redcloud_92xx_mode_params(int mode) +{ + CS92xx_MODE *pMode = &FPModeParams[mode]; + unsigned long temp_data = 0; + unsigned long base_data; + Q_WORD msrValue; + + /* on a Redcloud, we need to set up the DF pad select MSR */ + if (gfx_msr_read(RC_ID_DF, GX2_VP_MSR_PAD_SELECT, &msrValue) == FOUND) { + msrValue.low &= ~GX2_VP_PAD_SELECT_MASK; + if (pMode->panel_type == PNL_TFT || pMode->panel_type == PNL_TWOP) { + msrValue.low = GX2_VP_PAD_SELECT_TFT; + } else { + msrValue.low = GX2_VP_PAD_SELECT_DSTN; + } + gfx_msr_write(RC_ID_DF, GX2_VP_MSR_PAD_SELECT, &msrValue); + } + + /* Turn the 92xx power off before setting any new parameters. */ + temp_data = pMode->power_management & ~GX2_FP_PM_PWR_ON; + Redcloud_fp_reg(GX2_WRITE, GX2_FP_PWR_MAN, (unsigned long *)&temp_data); + + /* Set 9211 registers using the desired panel settings */ + + Redcloud_fp_reg(GX2_WRITE, GX2_FP_PAN_TIMING1, + (unsigned long *)&pMode->panel_timing1); + + /* On Redcloud, bit 31 is now reserved. */ + temp_data = pMode->panel_timing2 & 0x7FFFFFFF; + Redcloud_fp_reg(GX2_WRITE, GX2_FP_PAN_TIMING2, (unsigned long *)&temp_data); + + /* On Redcloud TFT parts, set this to 0x70 so all 8 bits per color run + * thru fp crc but only non-TFT parts. Otherwise, set it to be 0x50. + * (source: Larry G.). + */ + if (pMode->panel_type == PNL_TFT || pMode->panel_type == PNL_TWOP) { + temp_data = GX2_FP_CRC_PASS_THRU_MASK; + } else { + temp_data = pMode->rev_C_dither_frc; + } + Redcloud_fp_reg(GX2_WRITE, GX2_FP_DITH_FR_CNTRL, (unsigned long *)&temp_data); + Redcloud_fp_reg(GX2_WRITE, GX2_FP_BLFSR, + (unsigned long *)&pMode->blue_lsfr_seed); + Redcloud_fp_reg(GX2_WRITE, GX2_FP_RLFSR, + (unsigned long *)&pMode->red_green_lsfr_seed); + + /* Set the memory information, then the power register last. + * This will turn the panel on at the 9211. + */ + + Redcloud_fp_reg(GX2_READ, GX2_FP_FBB, (unsigned long *)&base_data); + if (base_data != 0x41780000) { + base_data = 0x41780000; + Redcloud_fp_reg(GX2_WRITE, GX2_FP_FBB, (unsigned long *)&base_data); + } + + Redcloud_fp_reg(GX2_WRITE, GX2_FP_PWR_MAN, + (unsigned long *)&pMode->power_management); + +} /*end set_92xx_mode_params() */ + +/* ----------------------------------------------------------------------- + * + * SET_FLAT_PANEL_MODE + * + * This routine sets the specified flat panel moden parameters in + * the 9211. + * Returns PASS if successful, FAIL if the mode parameters could + * not be set. + * + *------------------------------------------------------------------------*/ + +unsigned char +set_Redcloud_92xx_mode(Pnl_PanelStat * pstat) +{ + int mode; + + /* LOOP THROUGH THE AVAILABLE MODES TO FIND A MATCH */ + + for (mode = 0; mode < NUM_92XX_MODES; mode++) { + if ((FPModeParams[mode].xres == pstat->XRes) && + (FPModeParams[mode].yres == pstat->YRes) && + (FPModeParams[mode].bpp == pstat->Depth) && + (FPModeParams[mode].panel_type == pstat->Type) && + (FPModeParams[mode].color_type == pstat->MonoColor)) { + + /* SET THE 92xx FOR THE SELECTED MODE */ + set_Redcloud_92xx_mode_params(mode); + return TRUE; + } /* end if() */ + } /* end for() */ + return FALSE; + +} /* end set_Centaurus_92xx_mode() */ + +void +Redcloud_9211init(Pnl_PanelStat * pstat) +{ + + set_Redcloud_92xx_mode(pstat); + +} --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/gx2_9211.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/gx2_9211.h 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This file contains the panel library files to the + * GX2 platforms with 9211 support. + * + * SubModule: Geode FlatPanel library + * */ + + +/* ----------------------------------------------------------- + * GX2 FLAT PANEL CONTROLLER REGISTER DEFINITIONS + *----------------------------------------------------------- + */ + +#define GX2_VP_MSR_PAD_SELECT 0x2011 +#define GX2_VP_PAD_SELECT_MASK 0x3FFFFFFF +#define GX2_VP_PAD_SELECT_TFT 0x1FFFFFFF +#define GX2_VP_PAD_SELECT_DSTN 0x00000000 + +/* This is useful for generating addresses incrementally + * (ie, vidtest register display code). + */ + +#define GX2_FP_LCD_OFFSET 0x00000400 +#define CS9211_REDCLOUD 0x0400 /* Moved 9211 Rev C3 up to next major no. */ + +#define GX2_FP_PAN_TIMING1 0x0400 /* FP timings 1 */ +#define GX2_FP_PAN_TIMING2 0x0408 /* FP timings 2 */ +#define GX2_FP_PWR_MAN 0x0410 /* FP power management */ +#define GX2_FP_DITH_FR_CNTRL 0x0418 /* FP dither and frame rate */ +#define GX2_FP_BLFSR 0x0420 /* Blue LFSR seed */ +#define GX2_FP_RLFSR 0x0428 /* Red and Green LFSR seed */ +#define GX2_FP_FMI 0x0430 /* FRM Memory Index */ +#define GX2_FP_FMD 0x0438 /* FRM Memory Data */ +#define GX2_FP_DCA 0x0448 /* Dither ram control and address */ +#define GX2_FP_DMD 0x0450 /* Dither memory data */ +#define GX2_FP_PAN_CRC_SIG 0x0458 /* FP CRC signature */ +#define GX2_FP_FBB 0x0460 /* Frame Buffer Base Address */ + +/* GX2_FP_PAN_TIMING2 bits */ + +#define GX2_FP_TFT_PASS_THRU 0x40000000 /* TFT pass through enable */ +#define GX2_FP_PT2_PIX_OUT_MASK 0xFFF8FFFF /* panel output bit formats */ +#define GX2_FP_PT2_PIX_OUT_TFT 0x00000000 /* 8 BIT DSTN or TFT panel */ +#define GX2_FP_PT2_COLOR_MONO 0x00080000 /* color or monochrome */ +#define GX2_FP_PT2_DSTN_TFT_MASK 0xFFCFFFFF /* panel type bits */ +#define GX2_FP_PT2_DSTN_TFT_TFT 0x00100000 /* TFT panel */ +#define GX2_FP_PT2_PSH_CLK_CTL 0x08000000 /* shift clock retrace activity control */ + +/* GX2_FP_PWR_MAN bits */ + +#define GX2_FP_PM_SHFCLK_INVERT 0x00002000 /* Invert shfclk to panel */ +#define GX2_FP_PM_VSYNC_DELAY 0x0000C000 /* Vert Sync delay */ +#define GX2_FP_PM_HSYNC_DELAY 0x00030000 /* Horiz Sync delay */ +#define GX2_FP_PM_PWRDN_PHASE_BIT0 0x00040000 /* panel power down phase bit 0 */ +#define GX2_FP_PM_PWRDN_PHASE_BIT1 0x00080000 /* panel power down phase bit 1 */ +#define GX2_FP_PM_PWRDN_PHASE_BIT2 0x00100000 /* panel power down phase bit 2 */ +#define GX2_FP_PM_PWRUP_PHASE_BIT0 0x00200000 /* panel power up phase bit 0 */ +#define GX2_FP_PM_PWRUP_PHASE_BIT1 0x00400000 /* panel power up phase bit 1 */ +#define GX2_FP_PM_PWRUP_PHASE_BIT2 0x00800000 /* panel power up phase bit 2 */ +#define GX2_FP_PM_PWR_ON 0x01000000 /* panel power ON */ +#define GX2_FP_PM_DIS_OFF_CTL 0x02000000 /* disable the panel back light */ +#define GX2_FP_PM_EXT_PWR_SEQ 0x08000000 /* external power sequence */ + +/* GX2_FP_PAN_CRC_SIG bits */ + +#define GX2_FP_PAN_CRC_SIGE 0x00000001 /* CRC Sig Enable */ +#define GX2_FP_PAN_CRC_SFR 0x00000002 /* CRC Sig Free Run */ + +/* This define is used by the hardware CRC mechanism */ +#define GX2_FP_CRC_PASS_THRU_MASK 0x00000070 + +#define GX2_READ 0 +#define GX2_WRITE 1 + +void SetFPBaseAddr(unsigned long); +void Redcloud_9211init(Pnl_PanelStat *); +void protected_mode_access(unsigned long mode, + unsigned long width, + unsigned long addr, char *pdata); +void write_video_reg64_low(unsigned long offset, unsigned long value); +unsigned long read_video_reg64_low(unsigned long offset); +void Redcloud_fp_reg(int mode, unsigned long address, unsigned long *data); +void set_Redcloud_92xx_mode_params(int mode); +unsigned char set_Redcloud_92xx_mode(Pnl_PanelStat * pstat); --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/92xx.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/92xx.h 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This header file defines the Durango routines and + * variables used to access the memory mapped regions. + * + * SubModule: Geode FlatPanel library + * */ + + +#ifndef _92XX_h +#define _92XX_h + +typedef unsigned long ULONG; +typedef unsigned char UCHAR; + +#define FALSE 0 +#define TRUE 1 +#define NUM_92XX_MODES 13 +#define ONE_BYTE 1 +#define TWO_BYTES 2 +#define FOUR_BYTES 4 + +/* LCD Registers + * The LCD memory area is shared by both TV and LCD. + * This offset is for LCD access. + */ + +#define CS92xx_LCD_OFFSET 0x00000400 + +/* LCD CONTROL REGISTERS */ + +#define CS92xx_LCD_PAN_TIMING1 CS92xx_LCD_OFFSET + 0x00 + +/* flat panel(FP) timings */ +#define CS92xx_LCD_PAN_TIMING2 CS92xx_LCD_OFFSET + 0x04 + +/* FP panel timings */ +#define CS92xx_LCD_PWR_MAN CS92xx_LCD_OFFSET + 0x08 + +/* FP power management */ +#define CS92xx_LCD_DITH_FR_CNTRL CS92xx_LCD_OFFSET + 0x0C + +/* FP dither and frame rate + * these defines are in revisions prior to C + */ +#define CS92xx_LCD_BLOCK_SEL1 CS92xx_LCD_OFFSET + 0x10 + +/* FRM register */ +#define CS92xx_LCD_BLOCK_SEL2 CS92xx_LCD_OFFSET + 0x14 + +/* FRM register */ +#define CS92xx_LCD_DISPER1 CS92xx_LCD_OFFSET + 0x18 + +/* FRM register */ +#define CS92xx_LCD_DISPER2 CS92xx_LCD_OFFSET + 0x1C + +/* FRM register + * these defines are revision C + */ +#define CS92xx_BLUE_LSFR_SEED CS92xx_LCD_OFFSET + 0x10 + +/* FRM register */ +#define CS92xx_RED_GREEN_LSFR_SEED CS92xx_LCD_OFFSET + 0x14 + +/* FRM register */ +#define CS92xx_FRM_MEMORY_INDEX CS92xx_LCD_OFFSET + 0x18 + +/* FRM register */ +#define CS92xx_FRM_MEMORY_DATA CS92xx_LCD_OFFSET + 0x1C + +/* FRM register */ +#define CS92xx_LCD_MEM_CNTRL CS92xx_LCD_OFFSET + 0x20 + +/* memory PLL register */ +#define CS92xx_LCD_RAM_CNTRL CS92xx_LCD_OFFSET + 0x24 + +/* ram control */ + +#define CS92xx_LCD_RAM_DATA CS92xx_LCD_OFFSET + 0x28 /* ram data */ + +#define CS92xx_LCD_PAN_CRC_SIG CS92xx_LCD_OFFSET + 0x2C + +/* FP CRC signature */ +#define CS92xx_DEV_REV_ID CS92xx_LCD_OFFSET + 0x30 + +/* Device and revision id */ +#define CS92xx_LCD_GPIO_DATA CS92xx_LCD_OFFSET + 0x34 /* GPIO Data */ + +#define CS92xx_LCD_GPIO_CNTRL CS92xx_LCD_OFFSET + 0x38 + +/* GPIO Control */ +int Pnl_Rev_ID; + +typedef struct +{ + /* DISPLAY MODE PARAMETERS */ + int xres; + int yres; + int bpp; + int panel_type; + int color_type; + /* VALUES USED TO SET THE FLAT PANEL DISPLAY CONTROLLER */ + unsigned long panel_timing1; + unsigned long panel_timing2; + unsigned long power_management; + /* the following 5 registers are prior to revision C */ + unsigned long pre_C_dither_frc; + unsigned long block_select1; + unsigned long block_select2; + unsigned long dispersion1; + unsigned long dispersion2; + /* the following 4 registers are revision C only */ + unsigned long rev_C_dither_frc; + unsigned long blue_lsfr_seed; + unsigned long red_green_lsfr_seed; + unsigned long frm_memory_index; + unsigned long frm_memory_data; + unsigned long memory_control; + +} +CS92xx_MODE; + +/* VALUES USED TO SAVE AND RESTORE 9211 REGISTERS. */ +typedef struct +{ + unsigned long panel_state; + /* VALUES USED TO SET THE FLAT PANEL DISPLAY CONTROLLER */ + unsigned long panel_timing1; + unsigned long panel_timing2; + unsigned long power_management; + unsigned long dither_frc_ctrl; + unsigned long blue_lsfr_seed; + unsigned long red_green_lsfr_seed; + unsigned long frm_memory_index; + unsigned long frm_memory_data; + unsigned long memory_control; +} +CS92xx_REGS; + +CS92xx_REGS cs9211_regs; + +/* + *------------------------------------------------------------------------ + * PANEL MODE TABLES: + * GLOBAL ARRAY OF FLAT PANEL MODE STRUCTURES + *------------------------------------------------------------------------ + */ +CS92xx_MODE FPModeParams[] = { + + {640, 480, 8, PNL_SSTN, PNL_COLOR_PANEL, /* display parameters */ + 0x01e00000, 0x00034000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /* The next 5 values are prior to revision C */ + 0x00000050, /* dither and frame rate control */ + 0x25cf3096, 0xad47b81e, /* block select 1, block select 2 */ + 0x21446450, 0x21446450, /* dispersion 1, dispersion 2 */ + /* The next 5 values are for revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000000, /* memory control */ + }, + + {640, 480, 12, PNL_TFT, PNL_COLOR_PANEL, /* display parameters */ + 0x01e00000, 0x0f100000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /* The next 5 values are prior to revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* block select 1, block select 2 */ + 0x00000000, 0x00000000, /* dispersion 1, dispersion 2 */ + /* The next 5 values are for revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000000, /* memory control */ + }, + + {640, 480, 18, PNL_TFT, PNL_COLOR_PANEL, /* display parameters */ + 0x01e00000, 0x0f100000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /* The next 5 values are prior to revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* block select 1, block select 2 */ + 0x00000000, 0x00000000, /* dispersion 1, dispersion 2 */ + /* The next 5 values are for revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000000, /* memory control */ + }, + + {640, 480, 16, PNL_DSTN, PNL_COLOR_PANEL, /* display parameters */ + 0x01e00000, 0x00014000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /* The next 5 values are prior to revision C */ + 0x00000050, /* dither and frame rate control */ + 0x048c26ae, 0x048c26ae, /* block select 1, block select 2 */ + 0x02468ace, 0x13579bdf, /* dispersion 1, dispersion 2 */ + /* The next 5 values are for revision C */ + 0x0000004b, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000007, /* memory control */ + }, + + {640, 480, 8, PNL_DSTN, PNL_MONO_PANEL, /* display parameters */ + 0x01e00000, 0x00084000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /* The next 5 values are prior to revision C */ + 0x0000004b, /* dither and frame rate control */ + 0x25cf3096, 0xad47b81e, /* block select 1, block select 2 */ + 0x21446450, 0x21446450, /* dispersion 1, dispersion 2 */ + /* The next 5 values are for revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000007, /* memory control */ + }, + + {640, 480, 16, PNL_DSTN, PNL_MONO_PANEL, /* display parameters */ + 0x01e00000, 0x00094000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /* The next 5 values are prior to revision C */ + 0x00000050, /* dither and frame rate control */ + 0x25cf3096, 0xad47b81e, /* block select 1, block select 2 */ + 0x81a5d470, 0x29cfb63e, /* dispersion 1, dispersion 2 */ + /* The next 5 values are for revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000007, /* memory control */ + }, + + {800, 600, 12, PNL_TFT, PNL_COLOR_PANEL, /* display parameters */ + 0x02580000, 0x0f100000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /* The next 5 values are prior to revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* block select 1, block select 2 */ + 0x00000000, 0x00000000, /* dispersion 1, dispersion 2 */ + /* The next 5 values are for revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000000, /* memory control */ + }, + + {800, 600, 18, PNL_TFT, PNL_COLOR_PANEL, /* display parameters */ + 0x02580000, 0x0f100000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /* The next 5 values are prior to revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* block select 1, block select 2 */ + 0x00000000, 0x00000000, /* dispersion 1, dispersion 2 */ + /* The next 5 values are for revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000000, /* memory control */ + }, + + {800, 600, 16, PNL_DSTN, PNL_COLOR_PANEL, /* display parameters */ + 0x02580000, 0x00014000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /* The next 5 values are prior to revision C */ + 0x00000050, /* dither and frame rate control */ + 0x048c26ae, 0x048c26ae, /* block select 1, block select 2 */ + 0x02468ace, 0x13579bdf, /* dispersion 1, dispersion 2 */ + /* The next 5 values are for revision C */ + 0x0000004b, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000007, /* memory control */ + }, + + {800, 600, 8, PNL_DSTN, PNL_MONO_PANEL, /* display parameters */ + 0x02580000, 0x00084000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /* The next 5 values are prior to revision C */ + 0x00000050, /* dither and frame rate control */ + 0x25cf3096, 0xad47b81e, /* block select 1, block select 2 */ + 0x21446450, 0x21446450, /* dispersion 1, dispersion 2 */ + /* The next 5 values are for revision C */ + 0x0000004b, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000007, /* memory control */ + }, + + {800, 600, 16, PNL_DSTN, PNL_MONO_PANEL, /* display parameters */ + 0x02580000, 0x00094000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /* The next 5 values are prior to revision C */ + 0x00000050, /* dither and frame rate control */ + 0x25cf3096, 0xad47b81e, /* block select 1, block select 2 */ + 0x81a5d470, 0x29cfb63e, /* dispersion 1, dispersion 2 */ + /* The next 5 values are for revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000007, /* memory control */ + }, + + {1024, 768, 18, PNL_TFT, PNL_COLOR_PANEL, /* display parameters */ + 0x03000000, 0x0f100000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /*The next 5 values are prior to revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* block select 1, block select 2 */ + 0x00000000, 0x00000000, /* dispersion 1, dispersion 2 */ + /*The next 5 values are for revision C */ + 0x00000050, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000000, /* memory control */ + }, + + {1024, 768, 24, PNL_DSTN, PNL_COLOR_PANEL, /* display parameters */ + 0x03000000, 0x80024000, /* panel timing reg 1, panel timing reg 2 */ + 0x01000000, /* power management */ + /*The next 5 values are prior to revision C */ + 0x00000050, /* dither and frame rate control */ + 0x048c26ae, 0x048c26ae, /* block select 1, block select 2 */ + 0x02468ace, 0x13579bdf, /* dispersion 1, dispersion 2 */ + /*The next 5 values are for revision C */ + 0x0000004b, /* dither and frame rate control */ + 0x00000000, 0x00000000, /* blue LSFR, red and green LSFR */ + 0x00000000, 0x00000000, /* FRM memory index, FRM memory data */ + 0x00000005, /* memory control */ + } +}; + +#endif /* !_92XX_h */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/pnl_bios.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/pnl_bios.c 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This file panel functions which query for the BIOS for current FP + * Paramters. + * + * SubModule: Geode FlatPanel library + * */ + + + +#include "panel.h" + +#if defined(_WIN32) /* windows */ +extern unsigned long gfx_cpu_version; +extern void gfx_outw(unsigned short port, unsigned short data); +extern unsigned short gfx_inw(unsigned short port); +#endif + +#define SOFTVGA_DISPLAY_ENABLE 0x50 +#define SOFTVGA_FPRESOLUTION 0x52 +#define SOFTVGA_FPCLOCKFREQUENCY 0x54 + +/* SOFTVG VIRTUAL REGISTER DEFINITIONS */ + +#define VR_INDEX 0xAC1C +#define VR_DATA 0xAC1E +#define VR_UNLOCK 0xFC53 +#define VRC_VG 0x0002 /* SoftVG Virtual Register Class */ +#define VG_MEM_SIZE 0x0000 /* MemSize Virtual Register */ +#define FP_DETECT_MASK 0x8000 + +#define VG_FP_TYPE 0x0002 /* Flat Panel Info Virtual Register */ + +#define FP_DEV_MASK 0x0003 /* Flat Panel type */ +#define FP_TYPE_SSTN 0x0000 /* SSTN panel type value */ +#define FP_TYPE_DSTN 0x0001 /* DSTN panel type value */ +#define FP_TYPE_TFT 0x0002 /* TFT panel type value */ +#define FP_TYPE_LVDS 0x0003 /* LVDS panel type value */ + +#define FP_RESOLUTION_MASK 0x0038 +#define FP_RES_6X4 0x0000 /* 640x480 resolution value */ +#define FP_RES_8X6 0x0008 /* 800x600 resolution value */ +#define FP_RES_10X7 0x0010 /* 1024x768 resolution value */ +#define FP_RES_11X8 0x0018 /* 1152x864 resolution value */ +#define FP_RES_12X10 0x0020 /* 1280x1024 resolution value */ +#define FP_RES_16X12 0x0028 /* 1600x1200 resolution value */ + +#define FP_WIDTH_MASK 0x01C0 +#define FP_WIDTH_8 0x0000 /* 8 bit data bus width */ +#define FP_WIDTH_9 0x0040 /* 9 bit data bus width */ +#define FP_WIDTH_12 0x0080 /* 12 bit data bus width */ +#define FP_WIDTH_18 0x00C0 /* 18 bit data bus width */ +#define FP_WIDTH_24 0x0100 /* 24 bit data bus width */ +#define FP_WIDTH_16 0x0140 /* 16 bit data bus width - 16 bit Mono DSTN only */ + +#define FP_COLOR_MASK 0x0200 +#define FP_COLOR_COLOR 0x0000 /* Color panel */ +#define FP_COLOR_MONO 0x0200 /* Mono Panel */ + +#define FP_PPC_MASK 0x0400 +#define FP_PPC_1PPC 0x0000 /* One pixel per clock */ +#define FP_PPC_2PPC 0x0400 /* Two pixels per clock */ + +#define FP_HPOL_MASK 0x0800 +#define FP_H_POL_LGH 0x0000 /* HSync at panel, normally low, active high */ +#define FP_H_POL_HGL 0x0800 /* HSync at panel, normally high, active low */ + +#define FP_VPOL_MASK 0x1000 +#define FP_V_POL_LGH 0x0000 /* VSync at panel, normally low, active high */ +#define FP_V_POL_HGL 0x1000 /* VSync at panel, normally high, active low */ + +#define FP_REF_MASK 0xE000 +#define FP_REF_60 0x0000 /* 60Hz refresh rate */ +#define FP_REF_70 0x2000 /* 70Hz refresh rate */ +#define FP_REF_72 0x4000 /* 72Hz refresh rate */ +#define FP_REF_75 0x6000 /* 75Hz refresh rate */ +#define FP_REF_85 0x8000 /* 85Hz refresh rate */ +#define FP_REF_90 0xA000 /* 90Hz refresh rate */ +#define FP_REF_100 0xC000 /* 100Hz refresh rate */ + +/*----------------------------------------------------------------- + * Pnl_IsPanelEnabledInBIOS + * + * Description: This function specifies whether the panel is enabled + * by the BIOS or not. + * parameters: none. + * return: 1 - Enabled, 0 - Disabled + *-----------------------------------------------------------------*/ +int +Pnl_IsPanelEnabledInBIOS(void) +{ + unsigned char ret = 0; + + if ((gfx_cpu_version & 0xFF) == GFX_CPU_REDCLOUD) { + unsigned short data; + + gfx_outw(VR_INDEX, VR_UNLOCK); + gfx_outw(VR_INDEX, (VRC_VG << 8) | VG_MEM_SIZE); + data = gfx_inw(VR_DATA); + if (data & FP_DETECT_MASK) + ret = 1; + } else { + unsigned short crtcindex, crtcdata; + + crtcindex = (gfx_inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4; + crtcdata = crtcindex + 1; + + /* CHECK DisplayEnable Reg in SoftVGA */ + + gfx_outb(crtcindex, (unsigned char)SOFTVGA_DISPLAY_ENABLE); + ret = gfx_inb(crtcdata); + } + + return (ret & 0x1); +} + +/*----------------------------------------------------------------- + * Pnl_GetPanelInfoFromBIOS + * + * Description: This function queries the panel information from + * the BIOS. + * parameters: + * xres: width of the panel configured + * yres: height of the panel configured + * bpp: depth of the panel configured + * hz: vertical frequency of the panel configured + * return: none + *-----------------------------------------------------------------*/ +void +Pnl_GetPanelInfoFromBIOS(int *xres, int *yres, int *bpp, int *hz) +{ + unsigned short crtcindex, crtcdata; + unsigned short ret; + + if ((gfx_cpu_version & 0xFF) == GFX_CPU_REDCLOUD) { + gfx_outw(VR_INDEX, VR_UNLOCK); + gfx_outw(VR_INDEX, (VRC_VG << 8) | VG_FP_TYPE); + ret = gfx_inw(VR_DATA); + switch (ret & FP_RESOLUTION_MASK) { + case FP_RES_6X4: + *xres = 640; + *yres = 480; + break; + case FP_RES_8X6: + *xres = 800; + *yres = 600; + break; + case FP_RES_10X7: + *xres = 1024; + *yres = 768; + break; + case FP_RES_11X8: + *xres = 1152; + *yres = 864; + break; + case FP_RES_12X10: + *xres = 1280; + *yres = 1024; + break; + case FP_RES_16X12: + *xres = 1600; + *yres = 1200; + break; + } + + switch (ret & FP_WIDTH_MASK) { + case FP_WIDTH_8: + *bpp = 8; + break; + case FP_WIDTH_9: + *bpp = 9; + break; + case FP_WIDTH_12: + *bpp = 12; + break; + case FP_WIDTH_18: + *bpp = 18; + break; + case FP_WIDTH_24: + *bpp = 24; + break; + case FP_WIDTH_16: + *bpp = 16; + break; + } + + switch (ret & FP_REF_MASK) { + case FP_REF_60: + *hz = 60; + break; + case FP_REF_70: + *hz = 70; + break; + case FP_REF_72: + *hz = 72; + break; + case FP_REF_75: + *hz = 75; + break; + case FP_REF_85: + *hz = 85; + break; + case FP_REF_90: + *hz = 90; + break; + case FP_REF_100: + *hz = 100; + break; + } + + } else { + crtcindex = (gfx_inb(0x3CC) & 0x01) ? 0x3D4 : 0x3B4; + crtcdata = crtcindex + 1; + + /* CHECK FPResolution Reg in SoftVGA */ + + gfx_outb(crtcindex, (unsigned char)SOFTVGA_FPRESOLUTION); + ret = gfx_inb(crtcdata); + + switch (ret & 0x3) { + case 0: + *xres = 640; + *yres = 480; + break; + case 1: + *xres = 800; + *yres = 600; + break; + case 2: + *xres = 1024; + *yres = 768; + break; + } + + switch ((ret >> 4) & 0x3) { + case 0: + *bpp = 12; + break; + case 1: + *bpp = 18; + break; + case 2: + *bpp = 16; + break; + case 3: + *bpp = 8; + break; + } + + /* CHECK FPClockFrequency Reg in SoftVGA */ + + gfx_outb(crtcindex, (unsigned char)SOFTVGA_FPCLOCKFREQUENCY); + *hz = gfx_inb(crtcdata); + } +} --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/pnl_defs.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/pnl_defs.h 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This file contains definitions of the Geode + * frame buffer panel data structures. + * + * SubModule: Geode FlatPanel library + * */ + + + +#ifndef _pnl_defs_h +#define _pnl_defs_h + +typedef enum +{ + MARMOT_PLATFORM = 0, + UNICORN_PLATFORM, + CENTAURUS_PLATFORM, + ARIES_PLATFORM, + CARMEL_PLATFORM, + HYDRA_PLATFORM, + DORADO_PLATFORM, + DRACO_PLATFORM, + REDCLOUD_PLATFORM, + OTHER_PLATFORM +} +SYS_BOARD; + +#define PNL_9210 0x01 +#define PNL_9211_A 0x02 +#define PNL_9211_C 0x04 +#define PNL_UNKNOWN_CHIP 0x08 + +#define PNL_TFT 0x01 +#define PNL_SSTN 0x02 +#define PNL_DSTN 0x04 +#define PNL_TWOP 0x08 +#define PNL_UNKNOWN_PANEL 0x10 + +#define PNL_MONO_PANEL 0x01 +#define PNL_COLOR_PANEL 0x02 +#define PNL_UNKNOWN_COLOR 0x08 + +#define PNL_PANELPRESENT 0x01 +#define PNL_PLATFORM 0x02 +#define PNL_PANELCHIP 0x04 +#define PNL_PANELSTAT 0x08 +#define PNL_OVERRIDE_STAT 0x10 +#define PNL_OVERRIDE_ALL 0x1F + +typedef struct _Pnl_PanelStat_ +{ + int Type; + int XRes; + int YRes; + int Depth; + int MonoColor; +} +Pnl_PanelStat; + +typedef struct _Pnl_Params_ +{ + unsigned long Flags; + int PanelPresent; + int Platform; + int PanelChip; + Pnl_PanelStat PanelStat; +} +Pnl_PanelParams, *PPnl_PanelParams; + +#endif /* _pnl_defs_h */ + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel/pnl_init.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel/pnl_init.c 2005-12-14 11:25:10.000000000 -0700 @@ -0,0 +1,507 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * File Contents: This file contains the Geode frame buffer panel + * intialization functions. + * + * SubModule: Geode FlatPanel library + * */ + + +#include "panel.h" +#include "gfx_regs.h" +#include "gfx_type.h" + +/* defaults +Panel : Enabled +Platform : Centaurus +92xx Chip : 9211 Rev. A +PanelType : DSTN +XResxYRes : 800x600 +Depth : 16 +Mono_Color : Color +*/ +static Pnl_PanelParams sPanelParam = { + 0, 1, CENTAURUS_PLATFORM, PNL_9211_A, + {PNL_DSTN, 800, 600, 16, PNL_COLOR_PANEL} +}; + +#if PLATFORM_DRACO +#include "drac9210.c" +#endif + +#if PLATFORM_CENTAURUS +#include "cen9211.c" +#endif + +#if PLATFORM_DORADO +#include "dora9211.c" +#endif + +#if PLATFORM_GX2BASED +#include "gx2_9211.c" +#endif +#include "platform.c" + +/* + * return -1 - UnKnown + * 0 - Draco has 9210 + * 1 - Centaurus has 9211 Rev. A + * 2 - Dorado has 9211 Rev. C + */ + +/*----------------------------------------------------------------- + * Pnl_SetPlatform + * + * Description: This function sets the panel with hardware platform. + * parameters: + * platform: It specify the platform. + * return: none. + *-----------------------------------------------------------------*/ +void +Pnl_SetPlatform(int platform) +{ + /* To Be Implemented */ + sPanelParam.Platform = platform; + +} + +/*----------------------------------------------------------------- + * Pnl_GetPlatform + * + * Description: This function returns the panel platform. + * parameters: none. + * return: On success it returns the panel platform. + *-----------------------------------------------------------------*/ +int +Pnl_GetPlatform(void) +{ + sPanelParam.Platform = Detect_Platform(); + + return sPanelParam.Platform; + +} + +/*----------------------------------------------------------------- + * Pnl_IsPanelPresent + * + * Description: This function specifies whether the panel is prsent + * or not. + * parameters: none. + * return: On success it returns an integer panel present value. + *-----------------------------------------------------------------*/ +int +Pnl_IsPanelPresent(void) +{ + /* To Be Implemented */ + return sPanelParam.PanelPresent; +} + +/*----------------------------------------------------------------- + * Pnl_SetPanelPresent + * + * Description: This function sets the panel_present parameter. + * parameters: + * present: It specifies the panel present value. + * return: none. + *-----------------------------------------------------------------*/ +void +Pnl_SetPanelPresent(int present) +{ + /* To Be Implemented */ + sPanelParam.PanelPresent = present; +} + +/*----------------------------------------------------------------- + * Pnl_SetPanelParam + * + * Description: This function sets the panel parameters + * parameters: + * pParam: It specifies the elements of the panel parameter + * structure. + * return: none. + *-----------------------------------------------------------------*/ +void +Pnl_SetPanelParam(PPnl_PanelParams pParam) +{ + if (pParam->Flags & PNL_PANELPRESENT) { + Pnl_SetPanelPresent(pParam->PanelPresent); + } + if (pParam->Flags & PNL_PLATFORM) { + Pnl_SetPlatform(pParam->Platform); + } + if (pParam->Flags & PNL_PANELCHIP) { + Pnl_SetPanelChip(pParam->PanelChip); + } + if (pParam->Flags & PNL_PANELSTAT) { + sPanelParam.PanelStat.XRes = pParam->PanelStat.XRes; + sPanelParam.PanelStat.YRes = pParam->PanelStat.YRes; + sPanelParam.PanelStat.Depth = pParam->PanelStat.Depth; + sPanelParam.PanelStat.MonoColor = pParam->PanelStat.MonoColor; + sPanelParam.PanelStat.Type = pParam->PanelStat.Type; + } +} + +/*----------------------------------------------------------------- + * Pnl_PowerUp + * + * Description: This function sets the power based on the + * hardware platforms dorado or centaraus. + * parameters: none. + * return: none. + *-----------------------------------------------------------------*/ +void +Pnl_PowerUp(void) +{ + int Platform; + unsigned long dcfg, hw_video; + + Platform = Pnl_GetPlatform(); + +#if PLATFORM_CENTAURUS + if (Platform == CENTAURUS_PLATFORM) { + Centaurus_Power_Up(); + return; + } +#endif + +#if PLATFORM_DORADO + if (Platform == DORADO_PLATFORM) { + Dorado_Power_Up(); + return; + } +#endif + +#if PLATFORM_GX2BASED + if (Platform == REDCLOUD_PLATFORM) { + } +#endif + + hw_video = gfx_detect_video(); + + if (hw_video == GFX_VID_CS5530) { + /* READ DISPLAY CONFIG FROM CX5530 */ + dcfg = READ_VID32(CS5530_DISPLAY_CONFIG); + + /* SET RELEVANT FIELDS */ + dcfg |= (CS5530_DCFG_FP_PWR_EN | CS5530_DCFG_FP_DATA_EN); + /* Enable the flatpanel power and data */ + WRITE_VID32(CS5530_DISPLAY_CONFIG, dcfg); + } else if (hw_video == GFX_VID_SC1200) { + /* READ DISPLAY CONFIG FROM SC1200 */ + dcfg = READ_VID32(SC1200_DISPLAY_CONFIG); + + /* SET RELEVANT FIELDS */ + dcfg |= (SC1200_DCFG_FP_PWR_EN | SC1200_DCFG_FP_DATA_EN); + /* Enable the flatpanel power and data */ + WRITE_VID32(SC1200_DISPLAY_CONFIG, dcfg); + } else if (hw_video == GFX_VID_REDCLOUD) { + /* READ DISPLAY CONFIG FROM REDCLOUD */ + dcfg = READ_VID32(RCDF_DISPLAY_CONFIG); + + /* SET RELEVANT FIELDS */ + dcfg |= (RCDF_DCFG_FP_PWR_EN | RCDF_DCFG_FP_DATA_EN); + /* Enable the flatpanel power and data */ + WRITE_VID32(RCDF_DISPLAY_CONFIG, dcfg); + } + +} + +/*----------------------------------------------------------------- + * Pnl_PowerDown + * + * Description: This function make power down based on the + * hardware platforms dorado or centaraus. + * parameters: none. + * return: none. + *-----------------------------------------------------------------*/ +void +Pnl_PowerDown(void) +{ + int Platform; + unsigned long dcfg, hw_video; + + Platform = Pnl_GetPlatform(); + +#if PLATFORM_CENTAURUS + if (Platform == CENTAURUS_PLATFORM) { + Centaurus_Power_Down(); + return; + } +#endif +#if PLATFORM_DORADO + if (Platform == DORADO_PLATFORM) { + Dorado_Power_Down(); + return; + } +#endif + +#if PLATFORM_GX2BASED + if (Platform == REDCLOUD_PLATFORM) { + } +#endif + + hw_video = gfx_detect_video(); + + if (hw_video == GFX_VID_CS5530) { + /* READ DISPLAY CONFIG FROM CX5530 */ + dcfg = READ_VID32(CS5530_DISPLAY_CONFIG); + + /* CLEAR RELEVANT FIELDS */ + dcfg &= ~(CS5530_DCFG_FP_PWR_EN | CS5530_DCFG_FP_DATA_EN); + /* Disable the flatpanel power and data */ + WRITE_VID32(CS5530_DISPLAY_CONFIG, dcfg); + } else if (hw_video == GFX_VID_SC1200) { + /* READ DISPLAY CONFIG FROM SC1200 */ + dcfg = READ_VID32(SC1200_DISPLAY_CONFIG); + + /* CLEAR RELEVANT FIELDS */ + dcfg &= ~(SC1200_DCFG_FP_PWR_EN | SC1200_DCFG_FP_DATA_EN); + /* Disable the flatpanel power and data */ + WRITE_VID32(SC1200_DISPLAY_CONFIG, dcfg); + } else if (hw_video == GFX_VID_REDCLOUD) { + /* READ DISPLAY CONFIG FROM REDCLOUD */ + dcfg = READ_VID32(RCDF_DISPLAY_CONFIG); + + /* CLEAR RELEVANT FIELDS */ + dcfg &= ~(RCDF_DCFG_FP_PWR_EN | RCDF_DCFG_FP_DATA_EN); + /* Disable the flatpanel power and data */ + WRITE_VID32(RCDF_DISPLAY_CONFIG, dcfg); + } +} + +/*----------------------------------------------------------------- + * Pnl_SavePanelState + * + * Description: This function saves the panel state based on the + * hardware platforms dorado or centaraus. + * parameters: none. + * return: none. + *-----------------------------------------------------------------*/ +void +Pnl_SavePanelState(void) +{ + int Platform; + + Platform = Pnl_GetPlatform(); + +#if PLATFORM_CENTAURUS + if (Platform == CENTAURUS_PLATFORM) { + Centaurus_Save_Panel_State(); + return; + } +#endif + +#if PLATFORM_DORADO + if (Platform == DORADO_PLATFORM) { + Dorado_Save_Panel_State(); + return; + } +#endif + +#if PLATFORM_GX2BASED + if (Platform == REDCLOUD_PLATFORM) { + } +#endif +} + +/*----------------------------------------------------------------- + * Pnl_RestorePanelState + * + * Description: This function restore the panel state based on the + * hardware platforms dorado or centaraus. + * parameters: none. + * return: none. + *-----------------------------------------------------------------*/ +void +Pnl_RestorePanelState(void) +{ + int Platform; + + Platform = Pnl_GetPlatform(); +#if PLATFORM_CENTAURUS + if (Platform == CENTAURUS_PLATFORM) { + Centaurus_Restore_Panel_State(); + return; + } +#endif + +#if PLATFORM_DORADO + if (Platform == DORADO_PLATFORM) { + Dorado_Restore_Panel_State(); + return; + } +#endif + +#if PLATFORM_GX2BASED + if (Platform == REDCLOUD_PLATFORM) { + } +#endif +} + +/*----------------------------------------------------------------- + * Pnl_GetPanelParam + * + * Description: This function gets the panel parameters from the + * hardware platforms dorado or centaraus. + * parameters: + * pParam: It specifies the elements of the panel parameter + * structure. + * return: none. + *-----------------------------------------------------------------*/ +void +Pnl_GetPanelParam(PPnl_PanelParams pParam) +{ + if (pParam->Flags & PNL_PANELPRESENT) { + pParam->PanelPresent = Pnl_IsPanelPresent(); + } + if (pParam->Flags & PNL_PLATFORM) { + pParam->Platform = Pnl_GetPlatform(); + } + if ((pParam->Flags & PNL_PANELCHIP) || (pParam->Flags & PNL_PANELSTAT)) { +#if PLATFORM_CENTAURUS + if (pParam->Platform == CENTAURUS_PLATFORM) { + Centaurus_Get_9211_Details(pParam->Flags, pParam); + return; + } +#endif + +#if PLATFORM_DORADO + if (pParam->Platform == DORADO_PLATFORM) { + Dorado_Get_9211_Details(pParam->Flags, pParam); + return; + } +#endif + +#if PLATFORM_GX2BASED + if (pParam->Platform == REDCLOUD_PLATFORM) { + } +#endif + + /* if unknown platform put unknown */ + if (pParam->Flags & PNL_PANELCHIP) + pParam->PanelChip = PNL_UNKNOWN_CHIP; + + if (pParam->Flags & PNL_PANELSTAT) { + pParam->PanelStat.XRes = 0; + pParam->PanelStat.YRes = 0; + pParam->PanelStat.Depth = 0; + pParam->PanelStat.MonoColor = PNL_UNKNOWN_COLOR; + pParam->PanelStat.Type = PNL_UNKNOWN_PANEL; + } + } +} + +/*----------------------------------------------------------------- + * Pnl_SetPanelChip + * + * Description: This function sets the panelchip parameter of panel + * structure. + * parameters: + * panelChip: It specifies the panelChip value. + * return: none. + *-----------------------------------------------------------------*/ + +void +Pnl_SetPanelChip(int panelChip) +{ + /* To Be Implemented */ + sPanelParam.PanelChip = panelChip; + +} + +/*----------------------------------------------------------------- + * Pnl_GetPanelChip + * + * Description: This function gets the panelchip parameter of panel + * structure. + * parameters: + * return: On success it returns the panelchip. + *-----------------------------------------------------------------*/ +int +Pnl_GetPanelChip(void) +{ + /* To Be Implemented */ + return sPanelParam.PanelChip; +} + +/*----------------------------------------------------------------- + * Pnl_InitPanel + * + * Description: This function initializes the panel with + * hardware platforms dorado or centaraus. + * parameters: + * pParam: It specifies the elements of the panel parameter + * structure. + * return: none. + *-----------------------------------------------------------------*/ +int +Pnl_InitPanel(PPnl_PanelParams pParam) +{ + PPnl_PanelParams pPtr; + + if (pParam == 0x0) /* NULL use the static table */ + pPtr = &sPanelParam; + else + pPtr = pParam; + + if (!pPtr->PanelPresent) { + return -1; /* error */ + } else { + if ((pPtr->PanelChip < 0) || (pPtr->Platform < 0)) + return -1; /* error */ + +#if PLATFORM_DRACO + /* check we are init. the right one */ + if ((pPtr->Platform == DRACO_PLATFORM) && (pPtr->PanelChip == PNL_9210)) { + Draco9210Init(&(pPtr->PanelStat)); + } +#endif + +#if PLATFORM_CENTAURUS + /* check we are init. the right one */ + if (pPtr->Platform == CENTAURUS_PLATFORM) { + Centaurus_9211init(&(pPtr->PanelStat)); + } +#endif + +#if PLATFORM_DORADO + /* check we are init. the right one */ + if ((pPtr->Platform == DORADO_PLATFORM) && + (pPtr->PanelChip == PNL_9211_C)) { + Dorado9211Init(&(pPtr->PanelStat)); + } +#endif +#if PLATFORM_GX2BASED + if (pPtr->Platform == REDCLOUD_PLATFORM) { + Redcloud_9211init(&(pPtr->PanelStat)); + } +#endif + } /* else end */ + return 1; +} --- xc/programs/Xserver/hw/xfree86/drivers/amd/z4l.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/z4l.c 2005-07-14 14:01:57.000000000 -0600 @@ -0,0 +1,1423 @@ +/* prototype Xv interface for lxv4l2 driver */ + +#include +#include +#include +#include + +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86Resources.h" +#include "xf86_ansic.h" +#include "compiler.h" +#include "Xv.h" +#include "xf86xv.h" +#include "fourcc.h" + +#include + +#define __s64 __s_64 +typedef long long __s64; +#define __u64 __u_64 +typedef unsigned long long __u64; + +#include "linux/videodev.h" +#define __user +#include "linux/videodev2.h" + +typedef signed long long s64; +typedef unsigned long long u64; + +int debuglvl = 0; +#define NONBLK_IO +#undef HAVE_SELECT + +#define DEBUG 1 +#ifdef DEBUG +#define DBLOG(n,s...) do { if ( debuglvl >= (n) ) xf86Msg(X_INFO, "z4l: " s); } while(0) +#else +#define DBLOG(n,s...) do {} while(0) +#endif + +#define DEFAULT_COLORKEY 0x010203 +#define DEFAULT_KEYMODE 0 + +#define MAX_BUFFERS 4 +#define MAX_OVLY_WIDTH 2048 +#define MAX_OVLY_HEIGHT 2048 + +static char *z4l_dev_paths[] = { + "/dev/videox", NULL +}; + +#define ATTR_ENCODING "encoding" +#define ATTR_ENCODING_ID -1 +#define ATTR_KEYMODE "keymode" +#define ATTR_KEYMODE_ID -2 +#define ATTR_COLORKEY "colorkey" +#define ATTR_COLORKEY_ID -3 +#define ATTR_MAX_ID 3 + +#ifdef XvExtension + +static XF86VideoFormatRec Formats[] = { + {8, PseudoColor}, + {15, TrueColor}, + {16, TrueColor}, + {24, TrueColor} +}; +#define NUM_FORMATS (sizeof(Formats)/sizeof(Formats[0])) + +#define FOURCC_Y800 0x30303859 +#define XVIMAGE_Y800 \ + { \ + FOURCC_Y800, \ + XvYUV, \ + LSBFirst, \ + {'Y','8','0','0', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 8, \ + XvPacked, \ + 1, \ + 0, 0, 0, 0, \ + 8, 0, 0, \ + 1, 0, 0, \ + 1, 0, 0, \ + {'Y','8','0','0', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +static XF86ImageRec pixfmts[] = { + XVIMAGE_UYVY, XVIMAGE_YUY2, + XVIMAGE_I420, XVIMAGE_YV12, + XVIMAGE_Y800, +}; +#define NUM_PIXFMTS (sizeof(pixfmts)/sizeof(pixfmts[0])) + +typedef struct s_std_data { + int inp; + v4l2_std_id std; + unsigned int fmt; +} t_std_data; + +typedef struct s_ovly_bfrs { + void *start; + unsigned long offset; + size_t length; +} t_ovly_bfrs; + +typedef struct { + int fd; + int run; + int dir; + int nbfrs; + int bufno; + int bufsz; + int last; + int width, height; + int keymode, colorkey; + int src_is_set, src_x, src_y, src_w, src_h; + int drw_is_set, drw_x, drw_y, drw_w, drw_h; + unsigned int pixfmt; + char dev_path[32]; + t_ovly_bfrs bfrs[MAX_BUFFERS]; + XF86VideoAdaptorPtr adpt; + XF86VideoEncodingPtr enc; + RegionRec clips; + int attrIds[1]; +} Z4lPortPrivRec, *Z4lPortPrivPtr; + +static int z4l_x_offset = 0; +static int z4l_y_offset = 0; +static int Z4l_nAdaptors = 0; +static XF86VideoAdaptorPtr *Z4l_pAdaptors = NULL; + +static int +IoCtl(int fd,unsigned int fn,void *arg,int flag) +{ + int ret; + errno = 0; + ret = ioctl(fd,fn,arg); + if( ret != 0 && flag != 0 ) + DBLOG(0,"ioctl(%08x)=%d\n",fn,ret); + return ret; +} + +static void +z4l_ovly_unmap(Z4lPortPrivPtr pPriv) +{ +#ifdef LINUX_2_6 + int i, nbfrs; + nbfrs = pPriv->nbfrs; + for( i=0; ibfrs[i].start != NULL ) { + munmap(pPriv->bfrs[i].start,pPriv->bfrs[i].length); + pPriv->bfrs[i].start = NULL; + } + } +#else + if( pPriv->bfrs[0].start != NULL ) { + munmap((void *)pPriv->bfrs[0].start,pPriv->bufsz); + pPriv->bfrs[0].start = NULL; + } +#endif + pPriv->nbfrs = -1; + pPriv->bufsz = -1; + pPriv->last = -1; +} + +static void +z4l_ovly_map(Z4lPortPrivPtr pPriv,int dir) +{ + long offset, bsz; + int i, fd; + struct v4l2_buffer bfr; + struct v4l2_requestbuffers req; + int type = dir >= 0 ? + V4L2_BUF_TYPE_VIDEO_CAPTURE : V4L2_BUF_TYPE_VIDEO_OVERLAY; + if( pPriv->run > 0 ) { + DBLOG(1,"busy\n"); + return; + } + fd = pPriv->fd; + memset(&req,0,sizeof(req)); + req.type = type; + req.memory = V4L2_MEMORY_MMAP; + req.count = MAX_BUFFERS; + if( ioctl(fd,VIDIOC_REQBUFS,&req) < 0 ) goto xit; + pPriv->nbfrs = req.count; + if( pPriv->nbfrs <= 0 ) { + DBLOG(1,"no vidmem\n"); + return; + } + memset(&pPriv->bfrs,0,sizeof(pPriv->bfrs)); + + for( i=0; inbfrs; ++i ) { + memset(&bfr,0,sizeof(bfr)); + bfr.type = type; + bfr.index = i; + if( ioctl(fd,VIDIOC_QUERYBUF,&bfr) < 0 ) goto xit; + offset = bfr.m.offset; + pPriv->bfrs[i].offset = offset; + pPriv->bfrs[i].length = bfr.length; + bsz = offset+bfr.length; + if( pPriv->bufsz < bsz ) pPriv->bufsz = bsz; + } + +#ifdef LINUX_2_6 + for( i=0; inbfrs; ++i ) { + pPriv->bfrs[i].start = + mmap(NULL, bfr.length, PROT_READ | PROT_WRITE, + MAP_SHARED, fd, pPriv->bfrs[i].offset); + if( pPriv->bfrs[i].start == MAP_FAILED ) goto xit; + } +#else + pPriv->bfrs[0].offset = 0; + pPriv->bfrs[0].start = + mmap(NULL, pPriv->bufsz, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); + + if( pPriv->bfrs[0].start == MAP_FAILED ) { + pPriv->bfrs[0].start = NULL; + goto xit; + } + + + offset = (unsigned long)pPriv->bfrs[0].start; + for( i=1; inbfrs; ++i ) + pPriv->bfrs[i].start = (void*)(offset + pPriv->bfrs[i].offset); +#endif + + for( i=0; inbfrs; ++i ) { + DBLOG(3,"bfr %d ofs %#lx adr %p sz %lu\n",i, + pPriv->bfrs[i].offset,pPriv->bfrs[i].start, + (unsigned long)pPriv->bfrs[i].length); + memset(pPriv->bfrs[i].start,0x80,pPriv->bfrs[i].length); + } + + pPriv->last = 0; + while( pPriv->last < pPriv->nbfrs-1 ) { + bfr.index = pPriv->last++; + bfr.type = type; + if( ioctl(fd,VIDIOC_QBUF,&bfr) < 0 ) goto xit; + } + return; + +xit: + z4l_ovly_unmap(pPriv); +} + +static int +z4l_ovly_dqbuf(Z4lPortPrivPtr pPriv) +{ + int stat; + struct v4l2_buffer bfr; + int fd = pPriv->fd; +#ifdef HAVE_SELECT + struct timeval tmo; + fd_set dqset; + FD_ZERO(&dqset); + FD_SET(pPriv->fd,&dqset); + tmo.tv_sec = 0; tmo.tv_usec = 0; + if( select(fd+1,&dqset,NULL,NULL,&tmo) <= 0 ) return -1; +#endif + memset(&bfr,0,sizeof(bfr)); + bfr.type = V4L2_BUF_TYPE_VIDEO_OVERLAY; + stat = ioctl(fd,VIDIOC_DQBUF,&bfr); + DBLOG(3,"dqbuf %d,%d,%d,%d\n",stat,bfr.index,pPriv->last,errno); + return stat==0 ? bfr.index : -1; +} + +static int +z4l_open_device(Z4lPortPrivPtr pPriv) +{ + int enable; + if( pPriv->fd < 0 ) { + pPriv->fd = open(&pPriv->dev_path[0], O_RDWR, 0); + DBLOG(1,"open(%s)=%d\n",&pPriv->dev_path[0],pPriv->fd); + enable = 1; +#ifdef NONBLK_IO + if( IoCtl(pPriv->fd,FIONBIO,&enable,1) != 0 ) { + DBLOG(1,"open cant enable nonblocking\n"); + close(pPriv->fd); + pPriv->fd = -1; + } +#endif + } + return pPriv->fd; +} + +static int +z4l_close_device(Z4lPortPrivPtr pPriv) +{ + int ret = 0; + if( pPriv->fd >= 0 ) { + ret = close(pPriv->fd); + pPriv->fd = -1; + DBLOG(1,"close()=%d\n",ret); + } + if( pPriv->run > 0 ) { + z4l_ovly_unmap(pPriv); + pPriv->run = -1; + } + return ret; +} + +static int +z4l_ovly_reset(Z4lPortPrivPtr pPriv) +{ + int ret = 0; + if( pPriv->run > 0 ) { + z4l_close_device(pPriv); + ret = z4l_open_device(pPriv); + } + return ret; +} + +static unsigned int +z4l_fourcc_pixfmt(int fourcc) +{ + unsigned int pixfmt = -1; + switch( fourcc ) { + case FOURCC_UYVY: + pixfmt = V4L2_PIX_FMT_UYVY; + break; + case FOURCC_YV12: + pixfmt = V4L2_PIX_FMT_YVU420; + break; + case FOURCC_Y800: + case FOURCC_I420: + pixfmt = V4L2_PIX_FMT_YUV420; + break; + case FOURCC_YUY2: + pixfmt = V4L2_PIX_FMT_YUYV; + break; + } + return pixfmt; +} +static void +z4l_ovly_pixfmt(Z4lPortPrivPtr pPriv,unsigned int pixfmt) +{ + struct v4l2_framebuffer fbuf; + DBLOG(1,"pixfmt %4.4s %4.4s\n",(char*)&pPriv->pixfmt,(char*)&pixfmt); + memset(&fbuf,0,sizeof(fbuf)); + IoCtl(pPriv->fd,VIDIOC_G_FBUF,&fbuf,1); + fbuf.fmt.pixelformat = pixfmt; + fbuf.base = NULL; + IoCtl(pPriv->fd,VIDIOC_S_FBUF,&fbuf,1); + pPriv->pixfmt = pixfmt; +} + +static void +z4l_ovly_bfr(Z4lPortPrivPtr pPriv,int width,int height) +{ + struct v4l2_format fmt; + DBLOG(1,"sfmt ovly %dx%d\n",width,height); + memset(&fmt,0,sizeof(fmt)); + fmt.type = 0x102; + IoCtl(pPriv->fd,VIDIOC_G_FMT,&fmt,1); + fmt.fmt.win.field = V4L2_FIELD_NONE; + fmt.fmt.win.w.width = pPriv->width = width; + fmt.fmt.win.w.height = pPriv->height = height; + IoCtl(pPriv->fd,VIDIOC_S_FMT,&fmt,1); +} + +static void +z4l_ovly_rect(Z4lPortPrivPtr pPriv, + int src_x,int src_y,int src_w,int src_h, + int drw_x,int drw_y,int drw_w,int drw_h) +{ + int x, dx, w, y, dy, h; + struct v4l2_format fmt; + pPriv->src_x = src_x; pPriv->src_y = src_y; + pPriv->src_w = src_w; pPriv->src_h = src_h; + pPriv->drw_x = drw_x; pPriv->drw_y = drw_y; + pPriv->drw_w = drw_w; pPriv->drw_h = drw_h; + if( (drw_x-=z4l_x_offset) < 0 ) { + if( (w=pPriv->drw_w) <= 0 ) w = 1; + x = -drw_x; + dx = x*pPriv->src_w / w; + src_x = pPriv->src_x + dx; + src_w = pPriv->src_w - dx; + drw_w = pPriv->drw_w - x; + drw_x = 0; + } + if( (drw_y-=z4l_y_offset) < 0 ) { + if( (h=pPriv->drw_h) <= 0 ) h = 1; + y = -drw_y; + dy = y * pPriv->src_h / h; + src_y = pPriv->src_y + dy; + src_h = pPriv->src_h - dy; + drw_h = pPriv->drw_h - y; + drw_y = 0; + } + memset(&fmt,0,sizeof(fmt)); + fmt.type = 0x100; + IoCtl(pPriv->fd,VIDIOC_G_FMT,&fmt,1); + if( pPriv->src_is_set != 0 ) { + if( src_x != fmt.fmt.win.w.left || src_y != fmt.fmt.win.w.top || + src_w != fmt.fmt.win.w.width || src_h != fmt.fmt.win.w.height ) + pPriv->src_is_set = 0; + } + if( pPriv->src_is_set == 0 ) { + pPriv->src_is_set = 1; + fmt.fmt.win.w.left = src_x; fmt.fmt.win.w.top = src_y; + fmt.fmt.win.w.width = src_w; fmt.fmt.win.w.height = src_h; + IoCtl(pPriv->fd,VIDIOC_S_FMT,&fmt,1); + DBLOG(3," set src %d,%d %dx%d\n",src_x,src_y,src_w,src_h); + } + memset(&fmt,0,sizeof(fmt)); + fmt.type = 0x101; + IoCtl(pPriv->fd,VIDIOC_G_FMT,&fmt,1); + if( pPriv->drw_is_set != 0 ) { + if( drw_x != fmt.fmt.win.w.left || drw_y != fmt.fmt.win.w.top || + drw_w != fmt.fmt.win.w.width || drw_h != fmt.fmt.win.w.height ) + pPriv->drw_is_set = 0; + } + if( pPriv->drw_is_set == 0 ) { + pPriv->drw_is_set = 1; + fmt.fmt.win.w.left = drw_x; fmt.fmt.win.w.top = drw_y; + fmt.fmt.win.w.width = drw_w; fmt.fmt.win.w.height = drw_h; + IoCtl(pPriv->fd,VIDIOC_S_FMT,&fmt,1); + DBLOG(3," set drw %d,%d %dx%d\n",drw_x,drw_y,drw_w,drw_h); + } +} + +static void +z4l_ovly_pitch(unsigned int pixfmt,int w,int h,int *py_pitch,int *puv_pitch, + int *poffset1,int *poffset2,int *psize) +{ + int y_pitch, uv_pitch; + int offset1, offset2; + int size, is_420; + switch( pixfmt ) { + case V4L2_PIX_FMT_YVU420: + case V4L2_PIX_FMT_YUV420: + is_420 = 1; + y_pitch = ((w+1)/2)*2; + uv_pitch = (w+1)/2; + break; + default: + is_420 = 0; + y_pitch = ((w+1)/2)*4; + uv_pitch = 0; + break; + } + offset1 = y_pitch * h; + offset2 = uv_pitch * h; + if( is_420 != 0 ) + offset2 /= 2; + size = offset1 + 2*offset2; + *py_pitch = y_pitch; + *puv_pitch = uv_pitch; + *poffset1 = offset1; + *poffset2 = offset2; + *psize = size; +} + +static int +z4l_ovly_set_colorkey(Z4lPortPrivPtr pPriv,int key) +{ + struct v4l2_format fmt; + memset(&fmt,0,sizeof(fmt)); + fmt.type = V4L2_BUF_TYPE_VIDEO_OVERLAY; + if( IoCtl(pPriv->fd,VIDIOC_G_FMT,&fmt,1) < 0 ) return 0; + fmt.fmt.win.chromakey = key; + if( IoCtl(pPriv->fd,VIDIOC_S_FMT,&fmt,1) < 0 ) return 0; + pPriv->colorkey = key; + return 1; +} + +static int +z4l_ovly_get_colorkey(Z4lPortPrivPtr pPriv,int *key) +{ + struct v4l2_format fmt; + memset(&fmt,0,sizeof(fmt)); + fmt.type = V4L2_BUF_TYPE_VIDEO_OVERLAY; + if( IoCtl(pPriv->fd,VIDIOC_G_FMT,&fmt,1) < 0 ) return 0; + *key = fmt.fmt.win.chromakey; + return 1; +} + +static int +z4l_ovly_set_keymode(Z4lPortPrivPtr pPriv,int enable) +{ + struct v4l2_framebuffer fbuf; + memset(&fbuf,0,sizeof(fbuf)); + if( IoCtl(pPriv->fd,VIDIOC_G_FBUF,&fbuf,1) < 0 ) return 0; + if( enable != 0 ) + fbuf.flags |= V4L2_FBUF_FLAG_CHROMAKEY; + else + fbuf.flags &= ~V4L2_FBUF_FLAG_CHROMAKEY; + fbuf.base = NULL; + if( IoCtl(pPriv->fd,VIDIOC_S_FBUF,&fbuf,1) < 0 ) return 0; + pPriv->keymode = enable; + return 1; +} + +static int +z4l_ovly_get_keymode(Z4lPortPrivPtr pPriv,int *enable) +{ + struct v4l2_framebuffer fbuf; + memset(&fbuf,0,sizeof(fbuf)); + if( IoCtl(pPriv->fd,VIDIOC_G_FBUF,&fbuf,1) < 0 ) return 0; + *enable = (fbuf.flags & V4L2_FBUF_FLAG_CHROMAKEY) != 0 ? 1 : 0; + return 1; +} + +static int +z4l_ovly_set_encoding(Z4lPortPrivPtr pPriv,int id) +{ + int l, n, inp; + char *cp; + t_std_data *sp; + XF86VideoEncodingPtr enc; + XF86VideoAdaptorPtr adpt; + v4l2_std_id std; + struct v4l2_format fmt; + struct v4l2_framebuffer fbuf; + adpt = pPriv->adpt; + DBLOG(1,"z4l_ovly_set_encoding(%d)\n",id); + if( id < 0 || id >= adpt->nEncodings ) return 0; + enc = &adpt->pEncodings[id]; + cp = &enc->name[0]; + n = sizeof(int)-1; + l = strlen(cp)+1; + l = (l+n) & ~n; + sp = (t_std_data *)(cp+l); + inp = sp->inp; + DBLOG(1," nm %s fmt %4.4s inp %d std %llx\n", + cp,(char*)&sp->fmt,sp->inp,sp->std); + if( IoCtl(pPriv->fd,VIDIOC_S_INPUT,&inp,1) < 0 ) return 0; + std = sp->std; + if( IoCtl(pPriv->fd,VIDIOC_S_STD,&std,1) < 0 ) return 0; + memset(&fmt,0,sizeof(fmt)); + fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + if( IoCtl(pPriv->fd,VIDIOC_G_FMT,&fmt,1) < 0 ) return 0; + fmt.fmt.pix.pixelformat = sp->fmt; + if( IoCtl(pPriv->fd,VIDIOC_S_FMT,&fmt,1) < 0 ) return 0; + memset(&fbuf,0,sizeof(fbuf)); + if( IoCtl(pPriv->fd,VIDIOC_G_FBUF,&fbuf,1) < 0 ) return 0; + fbuf.fmt.pixelformat = sp->fmt; + fbuf.base = NULL; + if( IoCtl(pPriv->fd,VIDIOC_S_FBUF,&fbuf,1) < 0 ) return 0; + pPriv->pixfmt = sp->fmt; + pPriv->enc = enc; + pPriv->src_is_set = pPriv->drw_is_set = 0; + return 1; +} + +static int +z4l_ovly_get_encoding(Z4lPortPrivPtr pPriv,int *id) +{ + XF86VideoEncodingPtr enc = pPriv->enc; + *id = enc->id; + return 1; +} + +static void +z4l_ovly_stop(Z4lPortPrivPtr pPriv) +{ + int type, enable, fd; + if( pPriv->run < 0 ) return; + fd = pPriv->fd; + if( pPriv->dir > 0 ) { + type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + ioctl(fd,VIDIOC_STREAMOFF,&type); + } + if( pPriv->dir <= 0 ) { + enable = 0; + ioctl(fd,VIDIOC_OVERLAY,&enable); + } + if( pPriv->dir != 0 ) + z4l_ovly_unmap(pPriv); + pPriv->run = -1; + z4l_close_device(pPriv); +} + +static void +z4l_ovly_start(Z4lPortPrivPtr pPriv,int dir) +{ + int enable; + if( pPriv->run >= 0 ) + return; + if( (pPriv->dir=dir) != 0 ) + z4l_ovly_map(pPriv,dir); + enable = 1; + if( IoCtl(pPriv->fd,VIDIOC_OVERLAY,&enable,1) != 0 ) { + z4l_ovly_stop(pPriv); + return; + } + pPriv->run = 1; +} + +static int +z4l_region_equal(RegionPtr ap, RegionPtr bp) +{ + int nboxes; + BoxPtr abox, bbox; + if( ap == NULL && bp == NULL ) return 1; + if( ap == NULL || bp == NULL ) return 0; + + if( (nboxes=REGION_NUM_RECTS(ap)) != REGION_NUM_RECTS(bp) || + ap->extents.x1 != bp->extents.x1 || ap->extents.x2 != bp->extents.x2 || + ap->extents.y1 != bp->extents.y1 || ap->extents.y2 != bp->extents.y2 ) + return 0; + + abox = REGION_RECTS(ap); bbox = REGION_RECTS(bp); + while( --nboxes >= 0 ) { + if( abox->x1 != bbox->x1 || abox->y1 != bbox->y1 || + abox->x2 != bbox->x2 || abox->y2 != bbox->y2 ) + return 0; + ++abox; ++bbox; + } + + return 1; +} + +static void +z4l_setup_colorkey(Z4lPortPrivPtr pPriv,ScreenPtr pScrn,RegionPtr clipBoxes) +{ + if( pPriv->run > 0 && pPriv->dir <= 0 && pPriv->keymode != 0 && + z4l_region_equal(&pPriv->clips,clipBoxes) == 0 ) { + xf86XVFillKeyHelper(pScrn,pPriv->colorkey,clipBoxes); + REGION_COPY(pScrn,&pPriv->clips,clipBoxes); + } +} + +static void +Z4lStopVideo(ScrnInfoPtr pScrni,pointer data,Bool exit) +{ + Z4lPortPrivPtr pPriv = (Z4lPortPrivPtr)data; + DBLOG(1,"Z4lStopVideo()\n"); + if( exit != 0 ) + z4l_ovly_stop(pPriv); + else + pPriv->src_is_set = pPriv->drw_is_set = 0; + REGION_EMPTY(pScrni->pScreen,&pPriv->clips); +} + +static void +Z4lQueryBestSize(ScrnInfoPtr pScrni, Bool motion, + short vid_w, short vid_h, short drw_w, short drw_h, + unsigned int *p_w, unsigned int *p_h, pointer data) +{ + if( drw_w > MAX_OVLY_WIDTH ) drw_w = MAX_OVLY_WIDTH; + if( drw_h > MAX_OVLY_HEIGHT ) drw_h = MAX_OVLY_HEIGHT; + *p_w = drw_w; *p_h = drw_h; + DBLOG(1,"Z4lQueryBestSize(%d, src %dx%d dst %dx%d)\n",motion,vid_w,vid_h,drw_w,drw_h); +} + +static int +Z4lPutImage(ScrnInfoPtr pScrni, + short src_x, short src_y, short drw_x, short drw_y, + short src_w, short src_h, short drw_w, short drw_h, + int id, unsigned char *buf, short width, short height, + Bool sync, RegionPtr clipBoxes, pointer data) +{ + int fd, size; + int y_pitch, uv_pitch, offset1, offset2; + unsigned char *src, *dst; + unsigned int pixfmt; + struct v4l2_buffer bfr; + Z4lPortPrivPtr pPriv = (Z4lPortPrivPtr)data; + if( pPriv->run > 0 && pPriv->dir >= 0 ) + return BadMatch; + if( pPriv->fd < 0 ) { + z4l_open_device(pPriv); + if( pPriv->fd < 0 ) + return BadValue; + } + fd = pPriv->fd; + if( pPriv->run < 0 ) { + DBLOG(2,"PutImg id %#x src %d,%d %dx%d drw %d,%d %dx%d bfr %p %dx%d data %p\n", + id,src_x,src_y,src_w,src_h,drw_x,drw_y,drw_w,drw_h,buf,width,height,data); + pPriv->pixfmt = pPriv->height = -1; + pPriv->src_is_set = pPriv->drw_is_set = 0; + } + pixfmt = z4l_fourcc_pixfmt(id); + if( pixfmt != pPriv->pixfmt ) { + z4l_ovly_reset(pPriv); + z4l_ovly_pixfmt(pPriv,pixfmt); + } + if( pPriv->width != width || pPriv->height != height ) { + z4l_ovly_reset(pPriv); + z4l_ovly_bfr(pPriv,width,height); + } + if( pPriv->src_is_set == 0 || pPriv->drw_is_set == 0 || + pPriv->src_x != src_x || pPriv->src_y != src_y || + pPriv->src_w != src_w || pPriv->src_h != src_h || + pPriv->drw_x != drw_x || pPriv->drw_y != drw_y || + pPriv->drw_w != drw_w || pPriv->drw_h != drw_h ) + z4l_ovly_rect(pPriv,src_x,src_y,src_w,src_h,drw_x,drw_y,drw_w,drw_h); + if( pPriv->run < 0 ) { + z4l_ovly_start(pPriv,-1); + if( pPriv->run < 0 ) + return BadValue; + } + if( pPriv->last < 0 && (pPriv->last=z4l_ovly_dqbuf(pPriv)) < 0 ) + return BadAlloc; + z4l_ovly_pitch(pixfmt,width,height,&y_pitch,&uv_pitch, + &offset1,&offset2,&size); + src = buf; + dst = (unsigned char *)pPriv->bfrs[pPriv->last].start; + DBLOG(3,"cpy %4.4s src %p dst %p yp %d uvp %d o1 %d o2 %d sz %d\n", + (char*)&id,src,dst,y_pitch,uv_pitch,offset1,offset2,size); + if( id == FOURCC_Y800 ) { + memcpy(dst,src,offset1); + src += offset1; dst += offset1; + memset(dst,0x80,2*offset2); + } + else + memcpy(dst,src,size); + memset(&bfr,0,sizeof(bfr)); + bfr.type = V4L2_BUF_TYPE_VIDEO_OVERLAY; + bfr.index = pPriv->last; + bfr.timestamp.tv_sec = 0; + bfr.timestamp.tv_usec = 0; + bfr.flags |= V4L2_BUF_FLAG_TIMECODE; + if( IoCtl(fd,VIDIOC_QBUF,&bfr,1) != 0 ) + return BadAccess; + pPriv->last = z4l_ovly_dqbuf(pPriv); + z4l_setup_colorkey(pPriv,pScrni->pScreen,clipBoxes); + return Success; +} + +static int +Z4lQueryImageAttributes(ScrnInfoPtr pScrni, int id, + unsigned short *width, unsigned short *height, + int *pitches, int *offsets) +{ + int w, h, size; + int y_pitch, uv_pitch, offset1, offset2; + unsigned int pixfmt = z4l_fourcc_pixfmt(id); + w = *width; h = *height; + if( w > MAX_OVLY_WIDTH ) w = MAX_OVLY_WIDTH; + if( h > MAX_OVLY_HEIGHT ) h = MAX_OVLY_HEIGHT; + z4l_ovly_pitch(pixfmt,w,h,&y_pitch,&uv_pitch, + &offset1,&offset2,&size); + + if( offsets != NULL ) + offsets[0] = 0; + if( pitches != NULL ) + pitches[0] = y_pitch; + + switch( pixfmt ) { + case V4L2_PIX_FMT_YVU420: + case V4L2_PIX_FMT_YUV420: + if( offsets != NULL ) { + offsets[1] = offset1; + offsets[2] = offset1+offset2; + } + if( pitches != NULL ) + pitches[1] = pitches[2] = uv_pitch; + h = (h+1) & ~1; + break; + } + w = (w+1) & ~1; + *width = w; + *height = h; + DBLOG(1,"Z4lQueryImageAttributes(%4.4s) = %d, %dx%d %d/%d %d/%d\n", + (char*)&id,size,w,h,y_pitch,uv_pitch,offset1,offset2); + return size; +} + +static int +Z4lPutVideo(ScrnInfoPtr pScrni, + short src_x, short src_y, short drw_x, short drw_y, + short src_w, short src_h, short drw_w, short drw_h, + RegionPtr clipBoxes, pointer data) +{ + int id; + Z4lPortPrivPtr pPriv = (Z4lPortPrivPtr)data; + DBLOG(2,"PutVid src %d,%d %dx%d drw %d,%d %dx%d data %p\n", + src_x,src_y,src_w,src_h,drw_x,drw_y,drw_w,drw_h,data); + if( z4l_open_device(pPriv) >= 0 ) { + if( pPriv->run < 0 ) { + DBLOG(2,"PutVid start\n"); + z4l_ovly_get_encoding(pPriv,&id); + z4l_ovly_set_encoding(pPriv,id); + } + DBLOG(2,"PutVid priv %d,%d %dx%d drw %d,%d %dx%d\n", + pPriv->src_x,pPriv->src_y,pPriv->src_w,pPriv->src_h, + pPriv->drw_x,pPriv->drw_y,pPriv->drw_w,pPriv->drw_h); + if( pPriv->src_is_set == 0 || pPriv->drw_is_set == 0 || + pPriv->src_w != src_w || pPriv->src_h != src_h || + pPriv->drw_x != drw_x || pPriv->drw_y != drw_y || + pPriv->drw_w != drw_w || pPriv->drw_h != drw_h ) + z4l_ovly_rect(pPriv,src_x,src_y,src_w,src_h,drw_x,drw_y,drw_w,drw_h); + if( pPriv->run < 0 ) + z4l_ovly_start(pPriv,0); + z4l_setup_colorkey(pPriv,pScrni->pScreen,clipBoxes); + } + return Success; +} + +static XF86VideoEncodingPtr +Z4lNewEncoding(XF86VideoEncodingPtr *encs,int *nencs) +{ + XF86VideoEncodingPtr enc; + XF86VideoEncodingPtr tencs = + (XF86VideoEncodingPtr)xrealloc(*encs,sizeof(*tencs)*(*nencs+1)); + if( tencs == NULL ) return NULL; + *encs = tencs; + enc = &tencs[*nencs]; + ++*nencs; + memset(enc,0,sizeof(*enc)); + return enc; +} + +static void +Z4lEncodingName(char *ename,int l,char *inp_name,char *std_name,char *fmt) +{ + int i, ch; + while( (ch=*inp_name++) != 0 ) { + if( isalnum(ch) == 0 ) continue; + if( --l <= 0 ) goto xit; + *ename++ = ch; + } + if( --l <= 0 ) goto xit; + *ename++ = '-'; + while( (ch=*std_name++) != 0 ) { + if( isalnum(ch) == 0 ) continue; + if( --l <= 0 ) goto xit; + *ename++ = ch; + } + if( --l <= 0 ) goto xit; + *ename++ = '-'; + i = 4; + while( --i >= 0 && (ch=*fmt++) != 0 ) { + if( isalnum(ch) == 0 ) continue; + if( --l <= 0 ) goto xit; + *ename++ = ch; + } +xit: + *ename = 0; +} + +static int +Z4lAddEncoding(XF86VideoEncodingPtr enc,char *name, + int id,int width,int height,int numer,int denom, + int inp, v4l2_std_id std, unsigned int fmt) +{ + int l, n; + t_std_data *sp; + char *cp; + n = sizeof(int)-1; + l = strlen(&name[0])+1; + l = (l+n) & ~n; + n = l + sizeof(*sp); + cp = (char*)xalloc(n); + if( cp == NULL ) return 0; + sp = (t_std_data *)(cp+l); + enc->id = id; + strcpy(cp,&name[0]); + enc->name = cp; + enc->width = width; + enc->height = height; + enc->rate.numerator = numer; + enc->rate.denominator = denom; + sp->inp = inp; + sp->std = std; + sp->fmt = fmt; + DBLOG(1,"enc %s\n",&name[0]); + return 1; +} + +static XF86ImagePtr +Z4lNewImage(XF86ImagePtr *imgs,int *nimgs) +{ + XF86ImagePtr img; + XF86ImagePtr timgs = + (XF86ImagePtr)xrealloc(*imgs,sizeof(*timgs)*(*nimgs+1)); + if( timgs == NULL ) return NULL; + *imgs = timgs; + img = &timgs[*nimgs]; + ++*nimgs; + memset(img,0,sizeof(*img)); + return img; +} + +static int +Z4lAddImage(XF86ImagePtr img,XF86ImagePtr ip) +{ + *img = *ip; + DBLOG(1,"img %4.4s\n",(char*)&img->id); + return 1; +} + +static XF86AttributePtr +Z4lNewAttribute(XF86AttributePtr *attrs,int *nattrs) +{ + XF86AttributePtr attr; + XF86AttributePtr tattrs = + (XF86AttributePtr)xrealloc(*attrs,sizeof(*tattrs)*(*nattrs+1)); + if( tattrs == NULL ) return NULL; + *attrs = tattrs; + attr = &tattrs[*nattrs]; + ++*nattrs; + memset(attr,0,sizeof(*attr)); + return attr; +} + +static void +Z4lAttributeName(char *bp,int l,char *cp) +{ + int ch; char *atomNm = bp; + if( l > 0 ) { *bp++ = 'X'; --l; } + if( l > 0 ) { *bp++ = 'V'; --l; } + if( l > 0 ) { *bp++ = '_'; --l; } + while( l > 0 && (ch=*cp++) != 0 ) { + if( isalnum(ch) == 0 ) continue; + *bp++ = toupper(ch); + } + *bp = 0; + MakeAtom(&atomNm[0],strlen(&atomNm[0]),TRUE); +} + +static int +Z4lAddAttribute(XF86AttributePtr attr,char *name, + int min,int max,int flags) +{ + char *cp = (char*)xalloc(strlen((char*)&name[0])+1); + if( cp == NULL ) return 0; + attr->name = cp; + strcpy(&attr->name[0],name); + attr->min_value = min; + attr->max_value = max; + attr->flags = flags; + DBLOG(1,"attr %s\n",attr->name); + return 1; +} + +static XF86VideoAdaptorPtr +Z4lNewAdaptor(XF86VideoAdaptorPtr **adpts,int *nadpts,int nattrs) +{ + int n; + Z4lPortPrivPtr pPriv; + XF86VideoAdaptorPtr adpt, *tadpts; + tadpts = (XF86VideoAdaptorPtr*)xrealloc(*adpts,sizeof(*tadpts)*(*nadpts+1)); + if( tadpts == NULL ) return NULL; + *adpts = tadpts; + n = sizeof(*adpt) + sizeof(*pPriv) + 1*sizeof(*adpt->pPortPrivates); + n += (nattrs-1) * sizeof(pPriv->attrIds[0]); + adpt = (XF86VideoAdaptorPtr)xalloc(n); + if( adpt == NULL ) return NULL; + memset(adpt,0,n); + tadpts[*nadpts] = adpt; + ++*nadpts; + adpt->pPortPrivates = (DevUnion *)&adpt[1]; + pPriv = (Z4lPortPrivPtr) &adpt->pPortPrivates[1]; + adpt->pPortPrivates[0].ptr = (pointer)pPriv; + pPriv->adpt = adpt; + adpt->nPorts = 1; + return adpt; +} + +static int +Z4lSetPortAttribute(ScrnInfoPtr pScrni, + Atom attribute, INT32 value, pointer data) +{ + Z4lPortPrivPtr pPriv = (Z4lPortPrivPtr)data; + XF86VideoAdaptorPtr adpt; + XF86AttributePtr attr; + struct v4l2_control ctrl; + int i, nattrs, attrId, val; + char *name = NameForAtom(attribute); + int old_fd = pPriv->fd; + DBLOG(1,"Z4lSetPortAttribute(%#lx,%d) '%s'\n", + (unsigned long)attribute,(int)value,name!=NULL?name:"_null_"); + if( name == NULL ) return BadImplementation; + if( old_fd < 0 && z4l_open_device(pPriv) < 0 ) + return BadAccess; + adpt = pPriv->adpt; + attr = adpt->pAttributes; + nattrs = adpt->nAttributes; + for( i=0; iname,name) == 0 ) break; + if( i >= nattrs ) return BadMatch; + attrId = pPriv->attrIds[i]; + val = value; + switch( attrId ) { + case ATTR_ENCODING_ID: + z4l_ovly_set_encoding(pPriv,val); + break; + case ATTR_KEYMODE_ID: + z4l_ovly_set_keymode(pPriv,val); + REGION_EMPTY(pScrni->pScreen,&pPriv->clips); + z4l_setup_colorkey(pPriv,pScrni->pScreen,&pPriv->clips); + break; + case ATTR_COLORKEY_ID: + z4l_ovly_set_colorkey(pPriv,val); + break; + default: + memset(&ctrl,0,sizeof(ctrl)); + ctrl.id = attrId + V4L2_CID_BASE; + ctrl.value = val; + if( IoCtl(pPriv->fd,VIDIOC_S_CTRL,&ctrl,1) != 0 ) + return BadMatch; + break; + } + if( old_fd < 0 ) + z4l_close_device(pPriv); + return Success; +} + +static int +Z4lGetPortAttribute(ScrnInfoPtr pScrni, + Atom attribute, INT32 *value, pointer data) +{ + Z4lPortPrivPtr pPriv = (Z4lPortPrivPtr)data; + XF86VideoAdaptorPtr adpt; + XF86AttributePtr attr; + struct v4l2_control ctrl; + int i, nattrs, attrId, val; + char *name = NameForAtom(attribute); + int old_fd = pPriv->fd; + DBLOG(1,"Z4lGetPortAttribute(%#lx) '%s'\n", + (unsigned long)attribute,name!=NULL?name:"_null_"); + if( name == NULL ) return BadImplementation; + if( old_fd < 0 && z4l_open_device(pPriv) < 0 ) + return BadAccess; + adpt = pPriv->adpt; + attr = adpt->pAttributes; + nattrs = adpt->nAttributes; + for( i=0; iname,name) == 0 ) break; + if( i >= nattrs ) return BadMatch; + attrId = pPriv->attrIds[i]; + val = 0; + switch( attrId ) { + case ATTR_ENCODING_ID: + z4l_ovly_get_encoding(pPriv,&val); + *value = val; + break; + case ATTR_KEYMODE_ID: + z4l_ovly_get_keymode(pPriv,&val); + *value = val; + break; + case ATTR_COLORKEY_ID: + z4l_ovly_get_colorkey(pPriv,&val); + break; + default: + memset(&ctrl,0,sizeof(ctrl)); + ctrl.id = attrId + V4L2_CID_BASE; + if( IoCtl(pPriv->fd,VIDIOC_G_CTRL,&ctrl,1) != 0 ) + return BadMatch; + val = ctrl.value; + break; + } + if( old_fd < 0 ) + z4l_close_device(pPriv); + *value = val; + return Success; +} + +static void (*oldAdjustFrame)(int scrnIndex, int x, int y, int flags) = NULL; + +static void Z4lAdjustFrame(int scrnIndex,int x,int y,int flags) +{ + int i; + XF86VideoAdaptorPtr adpt; + Z4lPortPrivPtr pPriv; + DBLOG(3,"Z4lAdjustFrame(%d,%d,%d)\n",x,y,flags); + z4l_x_offset = x; z4l_y_offset = y; + oldAdjustFrame(scrnIndex,x,y,flags); + /* xv adjust does not handle putvideo case */ + for( i=0; ipPortPrivates[0].ptr; + if( pPriv->run > 0 ) { + pPriv->drw_is_set = 0; + z4l_ovly_rect(pPriv, + pPriv->src_x,pPriv->src_y,pPriv->src_w,pPriv->src_h, + pPriv->drw_x,pPriv->drw_y,pPriv->drw_w,pPriv->drw_h); + } + } +} + +static int +Z4lInit(ScrnInfoPtr pScrni, XF86VideoAdaptorPtr **adaptors) +{ + int i, id, fd, dev, enable, has_video, has_colorkey; + int ctl, cinp, inp, std, fmt, has_image; + int nadpts, nattrs, nencs, cenc, nimgs; + int numer, denom, width, height; + unsigned int pixfmt, cpixfmt, opixfmt; + XF86VideoAdaptorPtr *adpts, adpt; + XF86AttributePtr attrs, attr; + XF86VideoEncodingPtr encs, enc; + XF86ImagePtr ip, img, imgs; + Z4lPortPrivPtr pPriv; + char *dp, *msg; + char enc_name[256],attr_name[256]; + int attrIds[V4L2_CID_LASTP1-V4L2_CID_BASE+ATTR_MAX_ID]; + struct v4l2_capability capability; + v4l2_std_id cstd_id, std_id; + struct v4l2_standard standard; + struct v4l2_format format, cfmt; + struct v4l2_input input; + struct v4l2_fmtdesc fmtdesc; + struct v4l2_queryctrl queryctrl; + struct v4l2_framebuffer fbuf; + DBLOG(1,"Init\n"); + if( oldAdjustFrame == NULL ) { + oldAdjustFrame = pScrni->AdjustFrame; + pScrni->AdjustFrame = Z4lAdjustFrame; + } + + fd = -1; + enc = NULL; encs = NULL; nencs = 0; + img = NULL; imgs = NULL; nimgs = 0; + attr = NULL; attrs = NULL; nattrs = 0; + adpt = NULL; adpts = NULL; nadpts = 0; + has_video = has_image = has_colorkey = 0; + + for( dev=0; z4l_dev_paths[dev]!= NULL; ++dev ) { + fd = open(z4l_dev_paths[dev], O_RDWR, 0); + if( fd < 0 ) continue; + DBLOG(1,"%s open ok\n",z4l_dev_paths[dev]); + msg = NULL; enable = 1; + if( IoCtl(fd,VIDIOC_QUERYCAP,&capability,1) < 0 ) + msg = "bad querycap"; + else if( (capability.capabilities&V4L2_CAP_VIDEO_OVERLAY) == 0 ) + msg = "no overlay"; + else if( (capability.capabilities&V4L2_CAP_STREAMING) == 0 ) + msg = "no streaming"; +#ifdef NONBLK_IO + else if( IoCtl(fd,FIONBIO,&enable,1) != 0 ) + msg = "cant enable non-blocking io"; +#endif + if( msg == NULL ) { + memset(&format,0,sizeof(format)); + format.type = 0x100; + if( IoCtl(fd,VIDIOC_G_FMT,&format,1) != 0 ) + msg = "no src/dst ovly fmt"; + } + if( msg != NULL ) { + DBLOG(0,"%s %s\n",z4l_dev_paths[dev],msg); + close(fd); continue; + } + + memset(&cfmt,0,sizeof(cfmt)); + cfmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + if( IoCtl(fd,VIDIOC_G_FMT,&cfmt,1) < 0 ) goto fail; + if( IoCtl(fd,VIDIOC_G_STD,&cstd_id,1) < 0 ) goto fail; + if( IoCtl(fd,VIDIOC_G_INPUT,&cinp,1) < 0 ) goto fail; + cpixfmt = cfmt.fmt.pix.pixelformat; + cenc = 0; + for( inp=0; ; ++inp ) { + memset(&input,0,sizeof(input)); + input.index = inp; + if( IoCtl(fd,VIDIOC_ENUMINPUT,&input,0) < 0 ) break; + id = inp; + if( IoCtl(fd,VIDIOC_S_INPUT,&id,1) < 0 ) goto fail; + for( std=0; ; ++std ) { + memset(&standard,0,sizeof(standard)); + standard.index = std; + if( IoCtl(fd,VIDIOC_ENUMSTD,&standard,0) < 0 ) break; + std_id = standard.id; + denom = standard.frameperiod.denominator; + numer = standard.frameperiod.numerator; + if( IoCtl(fd,VIDIOC_S_STD,&std_id,1) < 0 ) continue; + memset(&format,0,sizeof(format)); + format.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + if( IoCtl(fd,VIDIOC_G_FMT,&format,1) < 0 ) continue; + width = format.fmt.pix.width; + height = format.fmt.pix.height; + for( fmt=0; ; ++fmt ) { + memset(&fmtdesc,0,sizeof(fmtdesc)); + fmtdesc.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + fmtdesc.index = fmt; + if( IoCtl(fd,VIDIOC_ENUM_FMT,&fmtdesc,0) < 0 ) break; + pixfmt = fmtdesc.pixelformat; + ip = &pixfmts[0]; + for( i=sizeof(pixfmts)/sizeof(pixfmts[0]); --i>=0; ++ip ) + if( z4l_fourcc_pixfmt(ip->id) == pixfmt ) break; + if( i >= 0 ) { + id = nencs; has_video = 1; + if( (enc=Z4lNewEncoding(&encs,&nencs)) == NULL ) goto fail; + Z4lEncodingName(&enc_name[0],sizeof(enc_name), + (char*)&input.name[0],(char*)&standard.name[0],(char*)&pixfmt); + if( Z4lAddEncoding(enc,&enc_name[0],id,width,height, + denom,numer,inp,std_id,pixfmt) == 0 ) goto fail; + if( std_id == cstd_id && inp == cinp && pixfmt == cpixfmt ) + cenc = id; + } + } + } + } + if( IoCtl(fd,VIDIOC_S_INPUT,&cinp,1) < 0 ) goto fail; + if( IoCtl(fd,VIDIOC_S_STD,&cstd_id,1) < 0 ) goto fail; + if( IoCtl(fd,VIDIOC_S_FMT,&cfmt,1) < 0 ) goto fail; + + if( encs == NULL ) { + DBLOG(0,"no encodings\n"); + goto fail; + } + + for( fmt=0; ; ++fmt ) { + memset(&fmtdesc,0,sizeof(fmtdesc)); + fmtdesc.type = V4L2_BUF_TYPE_VIDEO_OVERLAY; + fmtdesc.index = fmt; + if( IoCtl(fd,VIDIOC_ENUM_FMT,&fmtdesc,0) < 0 ) break; + pixfmt = fmtdesc.pixelformat; + ip = &pixfmts[0]; + for( i=sizeof(pixfmts)/sizeof(pixfmts[0]); --i>=0; ++ip ) + if( z4l_fourcc_pixfmt(ip->id) == pixfmt ) break; + if( i >= 0 ) { + has_image = 1; + if( (img=Z4lNewImage(&imgs,&nimgs)) == NULL ) goto fail; + if( Z4lAddImage(img,ip) == 0 ) goto fail; + } + } + + if( nimgs > 0 ) { + id = nencs; + if( (enc=Z4lNewEncoding(&encs,&nencs)) == NULL ) goto fail; + if( Z4lAddEncoding(enc,"XV_IMAGE",id,MAX_OVLY_WIDTH, + MAX_OVLY_HEIGHT, 0,0,0,0,pixfmt) == 0 ) goto fail; + } + + ctl = 0; + for( ctl=0; ctl<(V4L2_CID_LASTP1-V4L2_CID_BASE); ++ctl ) { + memset(&queryctrl,0,sizeof(queryctrl)); + queryctrl.id = V4L2_CID_BASE+ctl; + if( IoCtl(fd,VIDIOC_QUERYCTRL,&queryctrl,0) < 0 ) continue; + if( queryctrl.type != V4L2_CTRL_TYPE_INTEGER && + queryctrl.type != V4L2_CTRL_TYPE_BOOLEAN ) continue; + attrIds[nattrs] = ctl; + if( (attr=Z4lNewAttribute(&attrs,&nattrs)) == NULL ) goto fail; + Z4lAttributeName(&attr_name[0],sizeof(attr_name), + (char*)&queryctrl.name[0]); + if( Z4lAddAttribute(attr,&attr_name[0], + queryctrl.minimum,queryctrl.maximum, + XvSettable|XvGettable) == 0 ) goto fail; + } + attrIds[nattrs] = ATTR_ENCODING_ID; + if( (attr=Z4lNewAttribute(&attrs,&nattrs)) == NULL ) goto fail; + Z4lAttributeName(&attr_name[0],sizeof(attr_name),ATTR_ENCODING); + if( Z4lAddAttribute(attr,&attr_name[0],0,nencs-1, + XvSettable|XvGettable) == 0 ) goto fail; + memset(&fbuf,0,sizeof(fbuf)); + if( IoCtl(fd,VIDIOC_G_FBUF,&fbuf,1) < 0 ) goto fail; + opixfmt = fbuf.fmt.pixelformat; + if( (fbuf.capability & V4L2_FBUF_CAP_CHROMAKEY) != 0 ) { + attrIds[nattrs] = ATTR_KEYMODE_ID; + if( (attr=Z4lNewAttribute(&attrs,&nattrs)) == NULL ) goto fail; + Z4lAttributeName(&attr_name[0],sizeof(attr_name),ATTR_KEYMODE); + if( Z4lAddAttribute(attr,&attr_name[0],0,1, + XvSettable|XvGettable) == 0 ) goto fail; + attrIds[nattrs] = ATTR_COLORKEY_ID; + if( (attr=Z4lNewAttribute(&attrs,&nattrs)) == NULL ) goto fail; + Z4lAttributeName(&attr_name[0],sizeof(attr_name),ATTR_COLORKEY); + if( Z4lAddAttribute(attr,&attr_name[0],0,0xffffff, + XvSettable|XvGettable) == 0 ) goto fail; + has_colorkey = 1; + } + dp = xalloc(strlen((char*)&capability.card[0])+1); + if( dp == NULL ) goto fail; + strcpy(dp,(char*)&capability.card[0]); + if( (adpt=Z4lNewAdaptor(&adpts,&nadpts,nattrs)) == NULL ) goto fail; + adpt->type = XvWindowMask | XvInputMask; + if( has_video != 0 ) adpt->type |= XvVideoMask; + if( has_image != 0 ) adpt->type |= XvImageMask; + adpt->flags = VIDEO_OVERLAID_IMAGES | VIDEO_CLIP_TO_VIEWPORT; + adpt->name = dp; + adpt->type = XvInputMask | XvWindowMask | XvVideoMask | XvImageMask; + adpt->pEncodings = encs; + adpt->nEncodings = nencs; + adpt->pFormats = &Formats[0]; + adpt->nFormats = sizeof(Formats)/sizeof(Formats[0]); + adpt->pAttributes = attrs; + adpt->nAttributes = nattrs; + attrs = NULL; nattrs = 0; + adpt->pImages = imgs; + adpt->nImages = nimgs; + imgs = NULL; nimgs = 0; + adpt->PutVideo = Z4lPutVideo; + adpt->StopVideo = Z4lStopVideo; + adpt->SetPortAttribute = Z4lSetPortAttribute; + adpt->GetPortAttribute = Z4lGetPortAttribute; + adpt->QueryBestSize = Z4lQueryBestSize; + adpt->PutImage = Z4lPutImage; + adpt->QueryImageAttributes = Z4lQueryImageAttributes; + pPriv = (Z4lPortPrivPtr) adpt->pPortPrivates[0].ptr; + pPriv->fd = fd; + pPriv->run = -1; + pPriv->dir = 0; + pPriv->nbfrs = -1; + pPriv->bufsz = -1; + pPriv->last = -1; + pPriv->pixfmt = opixfmt; +#if defined(REGION_NULL) + REGION_NULL(pScrni->pScreen,&pPriv->clips); +#else + REGION_INIT(pScrni->pScreen,&pPriv->clips,NullBox,0); +#endif + strncpy(&pPriv->dev_path[0],z4l_dev_paths[dev],sizeof(pPriv->dev_path)); + pPriv->enc = &encs[cenc]; + for( i=0; inAttributes; ++i ) + pPriv->attrIds[i] = attrIds[i]; + DBLOG(1,"adpt %s\n",dp); + if( has_colorkey != 0 ) { + z4l_ovly_set_colorkey(pPriv,DEFAULT_COLORKEY); + z4l_ovly_set_keymode(pPriv,DEFAULT_KEYMODE); + } + close(fd); + pPriv->fd = -1; + adpt = NULL; cenc = 0; + encs = NULL; nencs = 0; + } + + DBLOG(0,"init done, %d device(s) found\n",nadpts); + Z4l_nAdaptors = nadpts; + Z4l_pAdaptors = adpts; + *adaptors = adpts; + return nadpts; + +fail: + if( attrs != NULL ) { + for( i=0; iname != NULL ) free(adpt->name); + if( (attrs=adpt->pAttributes) != NULL ) { + for( i=0; inAttributes; ++i ) + if( attrs[i].name != NULL ) free(attrs[i].name); + free(attrs); + } + if( (encs=adpt->pEncodings) != NULL ) { + for( i=0; inEncodings; ++i,++enc ) + if( encs[i].name != NULL ) free(encs[i].name); + free(encs); + } + if( (imgs=adpt->pImages) != NULL ) free(imgs); + xfree(adpt); + } + } + free(adpts); + } + if( fd >= 0 ) close(fd); + return 0; +} + +static Bool +Z4lProbe(DriverPtr drv, int flags) +{ + DBLOG(1,"Probe\n"); + if (flags & PROBE_DETECT) return TRUE; + xf86XVRegisterGenericAdaptorDriver(Z4lInit); + drv->refCount++; + return TRUE; +} + +static const OptionInfoRec * +Z4lAvailableOptions(int chipid, int busid) +{ + return NULL; +} + +static void +Z4lIdentify(int flags) +{ + xf86Msg(X_INFO, "z4l driver for Video4Linux\n"); +} + +DriverRec Z4l = { + 40001, + "z4l", + Z4lIdentify, + Z4lProbe, + Z4lAvailableOptions, + NULL, + 0 +}; + +#ifdef XFree86LOADER + +static MODULESETUPPROTO(z4lSetup); + +static XF86ModuleVersionInfo z4lVersRec = { + "z4l", + MODULEVENDORSTRING, MODINFOSTRING1, MODINFOSTRING2, + XF86_VERSION_CURRENT, 0, 0, 1, + ABI_CLASS_VIDEODRV, ABI_VIDEODRV_VERSION, MOD_CLASS_NONE, + {0,0,0,0} +}; + +XF86ModuleData z4lModuleData = { &z4lVersRec, z4lSetup, NULL }; + +static pointer +z4lSetup(pointer module, pointer opts, int *errmaj, int *errmin) +{ + const char *osname; + static Bool setupDone = FALSE; + if( setupDone != FALSE ) { + if( errmaj != NULL ) *errmaj = LDR_ONCEONLY; + return NULL; + } + setupDone = TRUE; + LoaderGetOS(&osname, NULL, NULL, NULL); + if( osname == NULL || strcmp(osname,"linux") != 0 ) { + if (errmaj) *errmaj = LDR_BADOS; + if (errmin) *errmin = 0; + return NULL; + } + xf86AddDriver(&Z4l,module,0); + return (pointer)1; +} + +#endif +#endif /* !XvExtension */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/Imakefile 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/Imakefile 2005-09-27 17:30:05.000000000 -0600 @@ -0,0 +1,261 @@ +XCOMM $XFree86: xc/programs/Xserver/hw/xfree86/drivers/amd/Imakefile,v 1.4 2003/01/13 20:50:46 tsi Exp $ +XCOMM Imakefile for the Advanced Micro Devices XFree86 display driver +XCOMM that is based on the durango code. +XCOMM +XCOMM +XCOMM Copyright (c) 2003-2005 Advanced Micro Devices, Inc. +XCOMM +XCOMM Permission is hereby granted, free of charge, to any person obtaining a copy +XCOMM of this software and associated documentation files (the "Software"), to +XCOMM deal in the Software without restriction, including without limitation the +XCOMM rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +XCOMM sell copies of the Software, and to permit persons to whom the Software is +XCOMM furnished to do so, subject to the following conditions: +XCOMM +XCOMM The above copyright notice and this permission notice shall be included in +XCOMM all copies or substantial portions of the Software. +XCOMM +XCOMM THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +XCOMM IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +XCOMM FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +XCOMM AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +XCOMM LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +XCOMM FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +XCOMM IN THE SOFTWARE. +XCOMM +XCOMM Neither the name of the Advanced Micro Devices, Inc. nor the names of its +XCOMM contributors may be used to endorse or promote products derived from this +XCOMM software without specific prior written permission. +XCOMM +XCOMM +XCOMM +XCOMM +XCOMM +XCOMM +XCOMM +XCOMM +#define IHaveModules +#include + +XCOMM the AMD linux kernel frame buffer driver interface. + + +#define LINUX_2_6 +#define HAVE_LX +#define HAVE_GX + +#if defined(HAVE_GX) +GX_SRCS = amd_gx_driver.c\ + amd_gx_accel.c \ + amd_gx_cursor.c \ + amd_gx_dga.c \ + amd_gx_video.c \ + amd_gx_shadow.c \ + amd_gx_regacc.c \ + durango.c \ + panel.c + +GX_OBJS = amd_gx_driver.o \ + amd_gx_accel.o \ + amd_gx_cursor.o \ + amd_gx_dga.o \ + amd_gx_video.o \ + amd_gx_shadow.o \ + amd_gx_regacc.o \ + durango.o \ + panel.o + +GX_DEFINES = -DHAVE_GX -DOPT_ACCEL -DPNL_SUP +GX_EXTINCLUDES = -I./gfx -I./panel +#endif + +#if defined(HAVE_LX) +LX_SRCS = amd_lx_driver.c \ + amd_lx_accel.c \ + amd_lx_cursor.c \ + amd_lx_dga.c \ + amd_lx_video.c \ + amd_lx_shadow.c \ + amd_lx_regacc.c \ + cimarron.c + +LX_OBJS = amd_lx_driver.o \ + amd_lx_accel.o \ + amd_lx_cursor.o \ + amd_lx_dga.o \ + amd_lx_video.o \ + amd_lx_shadow.o \ + amd_lx_regacc.o \ + cimarron.o + +SRCZ = z4l.c +OBJZ = z4l.o + +#if defined(LINUX_2_6) +LX_DEFINES = -DHAVE_LX -DLINUX_2_6 +LX_EXTINCLUDES = -I./cim -Ilinux_v26 -DAMD_V4L2_VIDEO +#else +LX_DEFINES = -DHAVE_LX +LX_EXTINCLUDES = -I./cim +#endif +#endif + +SRCS = amd_driver.c $(LX_SRCS) $(GX_SRCS) +OBJS = amd_driver.o $(LX_OBJS) $(GX_OBJS) +DEFINES = $(LX_DEFINES) $(GX_DEFINES) +EXTINCLUDES = $(LX_EXTINCLUDES) $(GX_EXTINCLUDES) + +#if defined(XF86DriverSDK) +INCLUDES = -I. -I../../include +#else +INCLUDES = -I. -I$(XF86COMSRC) -I$(XF86OSSRC) -I$(SERVERSRC)/Xext \ + -I$(SERVERSRC)/mfb -I$(SERVERSRC)/mi \ + -I$(SERVERSRC)/cfb -I$(SERVERSRC)/fb -I$(XF86SRC)/xaa \ + -I$(XF86SRC)/vgahw -I$(XF86SRC)/ramdac \ + -I$(XF86SRC)/ddc -I$(XF86SRC)/i2c \ + -I$(XF86SRC)/rac -I$(XF86SRC)/int10 \ + -I$(XF86SRC)/xf24_32bpp -I$(FONTINCSRC) \ + -I$(XF86SRC)/xf8_32bpp -I$(XF86SRC)/xf1bpp \ + -I$(XF86SRC)/xf4bpp -I$(SERVERSRC)/include -I$(XINCLUDESRC) \ + -I$(XF86SRC)/ddc -I$(XF86SRC)/i2c -I$(EXTINCSRC) $(DRIINCLUDES) \ + -I$(XF86SRC)/shadowfb -I$(XF86SRC)/fbdevhw \ + -I$(XTOP)/include -I$(XF86SRC)/vbe -I$(SERVERSRC)/render \ + $(EXTINCLUDES) +#endif + +#if MakeHasPosixVariableSubstitutions +SubdirLibraryRule($(OBJS)) +#endif + +ModuleObjectRule() + +ObjectModuleTarget(amd,$(OBJS)) +InstallObjectModule(amd,$(MODULEDIR),drivers) + +#if defined(HAVE_LX) && defined(LINUX_2_6) +ObjectModuleTarget(z4l,$(OBJZ)) +InstallObjectModule(z4l,$(MODULEDIR),drivers) +#endif + +#if !defined(XF86DriverSDK) +CppManTarget(amd,) +InstallModuleManPage(amd) +#endif + +DependTarget() + +InstallDriverSDKNonExecFile(Imakefile,$(DRIVERSDKDIR)/drivers/amd) + +InstallDriverSDKObjectModule(amd,$(DRIVERSDKMODULEDIR),drivers) +#if defined(HAVE_LX) +InstallDriverSDKObjectModule(z4l,$(DRIVERSDKMODULEDIR),drivers) +#endif + +InstallDriverSDKNonExecFile(durango.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd.h,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_driver.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_fourcc.h,$(DRIVERSDKDIR)/drivers/amd) + +#if defined(HAVE_GX) +InstallDriverSDKNonExecFile(amd_gx_accel.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_gx_cursor.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_gx_dga.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_gx_driver.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_gx_shadow.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_gx_vga.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_gx_video.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(panel.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(gfx/disp_gu1.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/disp_gu2.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/disp_gu3.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/durango.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_dcdr.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_defs.h,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_disp.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_i2c.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_init.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_mode.h,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_msr.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_priv.h,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_regs.h,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_rndr.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_rtns.h,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_tv.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_type.h,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_vga.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_vid.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/gfx_vip.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/history.h,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/i2c_acc.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/i2c_gpio.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/init_gu1.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/init_gu2.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/init_gu3.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/msr_rdcl.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/release.txt,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/rndr_gu1.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/rndr_gu2.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/saa7114.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/tv_1200.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/tv_fs450.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/tv_fs450.h,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/vga_gu1.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/vid_1200.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/vid_5530.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/vid_cstl.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/vid_rdcl.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(gfx/vip_1200.c,$(DRIVERSDKDIR)/drivers/amd/gfx) +InstallDriverSDKNonExecFile(panel/92xx.h,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/cen9211.c,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/cen9211.h,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/dora9211.c,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/dora9211.h,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/drac9210.c,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/drac9210.h,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/gx2_9211.c,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/gx2_9211.h,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/panel.c,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/panel.h,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/platform.c,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/pnl_bios.c,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/pnl_defs.h,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/pnl_init.c,$(DRIVERSDKDIR)/drivers/amd/panel) +InstallDriverSDKNonExecFile(panel/readme.txt,$(DRIVERSDKDIR)/drivers/amd/panel) +#endif + +#if defined(HAVE_LX) +InstallDriverSDKNonExecFile(amd.h,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_fourcc.h,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(build_num.h,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(cim_dev.h,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_driver.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_lx_accel.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_lx_cursor.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_lx_dga.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_lx_driver.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_lx_shadow.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_lx_vga.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(amd_lx_video.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(cimarron.c,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(Imakefile,$(DRIVERSDKDIR)/drivers/amd) +InstallDriverSDKNonExecFile(cim/cimarron.c,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_defs.h,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_df.c,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_filter.c,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_gp.c,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_init.c,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_modes.c,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_msr.c,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_parm.h,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_regs.h,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_rtns.h,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_version.h,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_vg.c,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_vip.c,$(DRIVERSDKDIR)/drivers/amd/cim) +InstallDriverSDKNonExecFile(cim/cim_vop.c,$(DRIVERSDKDIR)/drivers/amd/cim) + +#if defined(LINUX_2_6) +InstallDriverSDKNonExecFile(z4l.c,$(DRIVERSDKDIR)/drivers/amd) +#endif +#endif + --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_cursor.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_cursor.c 2005-07-13 13:16:48.000000000 -0600 @@ -0,0 +1,300 @@ +/* + * $Workfile: amd_gx_cursor.c $ + * $Revision: #5 $ + * $Author: raymondd $ + * + * File Contents: Xfree cursor implementation routines + * for geode HWcursor init.setting cursor color,image etc + * are done here. + * Project: Geode Xfree Frame buffer device driver. + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86_ansic.h" +#include "xf86Pci.h" +#include "xf86PciInfo.h" +#include "amd.h" + +/* Forward declarations of the functions */ +Bool GXHWCursorInit(ScreenPtr pScrn); +static void GXSetCursorColors(ScrnInfoPtr pScrni, int bg, int fg); +static void GXSetCursorPosition(ScrnInfoPtr pScrni, int x, int y); +void GXLoadCursorImage(ScrnInfoPtr pScrni, unsigned char *src); +void GXHideCursor(ScrnInfoPtr pScrni); +void GXShowCursor(ScrnInfoPtr pScrni); +static Bool GXUseHWCursor(ScreenPtr pScrn, CursorPtr pCurs); +extern void GXSetVideoPosition(int x, int y, int width, int height, + short src_w, short src_h, short drw_w, + short drw_h, int id, int offset, + ScrnInfoPtr pScrn); + +/*---------------------------------------------------------------------------- + * GXHWCursorInit. + * + * Description :This function sets the cursor information by probing the + * hardware. + * + * Parameters. + * pScrn :Screeen pointer structure. + * + * Returns :TRUE on success and FALSE on Failure + * + * Comments :Geode supports the hardware_cursor,no need to enable SW + * cursor. +*---------------------------------------------------------------------------- +*/ +Bool +GXHWCursorInit(ScreenPtr pScrn) +{ + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + GeodePtr pGeode = GEODEPTR(pScrni); + xf86CursorInfoPtr infoPtr; + + infoPtr = xf86CreateCursorInfoRec(); + if (!infoPtr) + return FALSE; + /* the geode structure is intiallized with the cursor infoRec */ + pGeode->CursorInfo = infoPtr; + infoPtr->MaxWidth = 32; + infoPtr->MaxHeight = 32; + /* seeting up the cursor flags */ + infoPtr->Flags = HARDWARE_CURSOR_BIT_ORDER_MSBFIRST | + HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | + HARDWARE_CURSOR_SOURCE_MASK_NOT_INTERLEAVED; + /* cursor info ptr is intiallized with the values obtained from + * * durnago calls + */ + infoPtr->SetCursorColors = GXSetCursorColors; + infoPtr->SetCursorPosition = GXSetCursorPosition; + infoPtr->LoadCursorImage = GXLoadCursorImage; + infoPtr->HideCursor = GXHideCursor; + infoPtr->ShowCursor = GXShowCursor; + infoPtr->UseHWCursor = GXUseHWCursor; + return (xf86InitCursor(pScrn, infoPtr)); +} + +/*---------------------------------------------------------------------------- + * GXSetCursorColors. + * + * Description :This function sets the cursor foreground and background + * colors + * Parameters: + * pScrn: Screeen pointer structure. + * bg: Specifies the color value of cursor background color. + * fg: Specifies the color value of cursor foreground color. + * Returns: none. + * + * Comments: The integer color value passed by this function is + * converted into * RGB value by the gfx_set_color routines. + *---------------------------------------------------------------------------- + */ +static void +GXSetCursorColors(ScrnInfoPtr pScrni, int bg, int fg) +{ + GFX(set_cursor_colors(bg, fg)); +} + +/*---------------------------------------------------------------------------- + * GXSetCursorPosition. + * + * Description :This function sets the cursor co -ordinates and enable the + * cursor. + * + * Parameters: + * pScrn: Screeen pointer structure. + * x: Specifies the x-cordinates of the cursor. + * y: Specifies the y co-ordinate of the cursor. + * Returns: none. + * + *---------------------------------------------------------------------------- + */ +static void +GXSetCursorPosition(ScrnInfoPtr pScrni, int x, int y) +{ + static unsigned long panOffset = 0; + GeodePtr pGeode = GEODEPTR(pScrni); + int newX, newY; + + (*pGeode->Rotation)(x,y,pGeode->HDisplay,pGeode->VDisplay,&newX,&newY); + (*pGeode->RBltXlat)(newX,newY,32,32,&newX,&newY); + if (newX < -31) newX = -31; + if (newY < -31) newY = -31; + + gfx_set_cursor_position(pGeode->CursorStartOffset, newX+31, newY+31, 31,31); + gfx_set_cursor_enable(1); + + if ((pGeode->OverlayON) && (pGeode->Panel)) { + pGeode->PrevDisplayOffset = gfx_get_display_offset(); + if (pGeode->PrevDisplayOffset != panOffset) { + GXSetVideoPosition(pGeode->video_x, pGeode->video_y, + pGeode->video_w, pGeode->video_h, + pGeode->video_srcw, pGeode->video_srch, + pGeode->video_dstw, pGeode->video_dsth, + pGeode->video_id, pGeode->video_offset, + pGeode->video_scrnptr); + panOffset = pGeode->PrevDisplayOffset; + } + } +} + +/*---------------------------------------------------------------------------- + * GXLoadCursorImage + * + * Description :This function loads the 32x32 cursor pattern.The shape + * and color is set by AND and XOR masking of arrays of 32 + * DWORD. + * Parameters: + * pScrn: Screeen pointer structure. + * src : Specifies cursor data. + * Returns : none + * + *---------------------------------------------------------------------------- +*/ +void +GXLoadCursorImage(ScrnInfoPtr pScrni, unsigned char *src) +{ + int i, n, x, y, newX, newY; + unsigned long andMask[32], xorMask[32]; + GeodePtr pGeode = GEODEPTR(pScrni); + unsigned long mskb, rowb; + unsigned char *rowp = &src[0]; + unsigned char *mskp = &src[128]; + + if( src != NULL ) { + mskb = rowb = 0; + for( y=32; --y>=0; ) + andMask[y] = xorMask[y] = 0; + for( y=0; y<32; ++y ) { + for( x=0; x<32; ++x ) { + if( (i=x&7) == 0 ) { + rowb = (*rowp & *mskp); + mskb = ~(*mskp); + ++rowp; ++mskp; + } + (*pGeode->Rotation)(x,y,32,32,&newX,&newY); + i = 7-i; n = 31-newX; + andMask[newY] |= (((mskb>>i)&1)<>i)&1)<=0; ) { + andMask[y] = ~0; + xorMask[y] = 0; + } + } + +#if 0 + andMask[31] = 0; + xorMask[31] = 0; + for( y=31; --y>0; ) { + andMask[y] &= ~0x80000001; + xorMask[y] &= ~0x80000001; + } + andMask[0] = 0; + xorMask[0] = 0; +#endif + + gfx_set_cursor_shape32(pGeode->CursorStartOffset,&andMask[0],&xorMask[0]); +} + +/*---------------------------------------------------------------------------- + * GXHideCursor. + * + * Description :This function will disable the cursor. + * + * Parameters: + * pScrn: Handles to the Screeen pointer structure. + * + * Returns: none. + * + * Comments: gfx_set_cursor enable function is hardcoded to disable + * the cursor. + *---------------------------------------------------------------------------- + */ +void +GXHideCursor(ScrnInfoPtr pScrni) +{ + gfx_set_cursor_enable(0); +} + +/*---------------------------------------------------------------------------- + * GXShowCursor + * + * Description :This function will enable the cursor. + * + * Parameters: + * pScrn :Handles to the Screeen pointer structure. + * + * Returns :none + * + * Comments :gfx_set_cursor enable function is hardcoded to enable the + * cursor + *---------------------------------------------------------------------------- +*/ +void +GXShowCursor(ScrnInfoPtr pScrni) +{ + GFX(set_cursor_enable(1)); +} + +/*---------------------------------------------------------------------------- + * GXUseHwCursor. + * + * Description :This function will sets the hardware cursor flag in + * pscreen structure. + * + * Parameters. + * pScrn :Handles to the Screeen pointer structure. + * + * Returns :none + * + * Comments :none + * + *---------------------------------------------------------------------------- +*/ +static Bool +GXUseHWCursor(ScreenPtr pScrn, CursorPtr pCurs) +{ + ScrnInfoPtr pScrni = XF86SCRNINFO(pScrn); + + if (pScrni->currentMode->Flags & V_DBLSCAN) + return FALSE; + return TRUE; +} + +/* End of File */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/cim_dev.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cim_dev.h 2005-07-13 13:16:49.000000000 -0600 @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + +#ifndef CIMDEV_H_ +#define CIMDEV_H_ + +#define CIM_RESERVE_MEM 0x01 +#define CIM_FREE_MEM 0x02 +#define CIMDEV_MINOR_DEV 156 + +/* Block flags */ +#define CIM_F_FREE 0x01 /* This block is marked as free */ +#define CIM_F_CMDBUF 0x02 /* GP command buffer flag */ +#define CIM_F_PRIVATE 0x04 /* This block is reserved only for its owner */ +#define CIM_F_PUBLIC 0x08 /* This block can be used by the world */ + +typedef struct { + + /* These fields get populated by the client */ + + char owner[10]; + char name[15]; + int flags; + int size; + + /* These fields are populated by the device */ + + unsigned long offset; +} cim_mem_req_t; + +typedef struct { + char owner[10]; + unsigned long offset; +} cim_mem_free_t; + +#endif --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_accel.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_accel.c 2005-08-03 14:53:41.000000000 -0600 @@ -0,0 +1,1588 @@ +/* + * $Workfile: amd_gx_accel.c $ + * $Revision: #4 $ + * $Author: raymondd $ + * + * File Contents: This file is consists of main Xfree + * acceleration supported routines like solid fill used + * here. + * Project: Geode Xfree Frame buffer device driver. + * + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + +/* #undef OPT_ACCEL */ + +/* Xfree86 header files */ +#include "vgaHW.h" +#include "xf86.h" +#include "xf86_ansic.h" +#include "xaalocal.h" +#include "xf86fbman.h" +#include "miline.h" +#include "xf86_libc.h" +#include "xaarop.h" +#include "amd.h" +#include "gfx_defs.h" +#include "gfx_regs.h" + +#undef ulong +typedef unsigned long ulong; +#undef uint +typedef unsigned int uint; +#undef ushort +typedef unsigned short ushort; +#undef uchar +typedef unsigned char uchar; + +#if DEBUGLVL>0 +extern FILE *zdfp; +#if DEBUGTIM>0 +#ifdef NO_RDTSC +#define DBLOG(n,s...) do { if((DEBUGLVL)>=(n)) { long secs,usecs; \ + getsecs(&secs,&usecs); fprintf(zdfp,"%d,%d ",secs,usecs); \ + fprintf(zdfp,s); } } while(0) +#else +#define tsc(n) __asm__ __volatile__ ( \ + " rdtsc" \ + : "=a" (((int*)(&(n)))[0]), "=d" (((int*)(&(n)))[1]) \ + : ) +#define DBLOG(n,s...) do { if((DEBUGLVL)>=(n)) { long long t; \ + tsc(t); fprintf(zdfp,"%lld ",t); \ + fprintf(zdfp,s); } } while(0) +#endif +#else +#define DBLOG(n,s...) do { if((DEBUGLVL)>=(n)) fprintf(zdfp,s); } while(0) +#endif +#else +#define DBLOG(n,s...) do {} while(0) +#endif + +#define CALC_FBOFFSET(x, y) (((ulong)(y) << gu2_yshift) | ((ulong)(x) << gu2_xshift)) +#define FBADDR(x,y) ((unsigned char *)pGeode->FBBase + CALC_FBOFFSET(x, y)) + +#define OS_UDELAY 0 +#if OS_UDELAY > 0 +#define OS_USLEEP(usec) usleep(usec); +#else +#define OS_USLEEP(usec) +#endif + +#ifdef OPT_ACCEL +unsigned int BPP; +unsigned int BLT_MODE, VEC_MODE; +unsigned int ACCEL_STRIDE; + +#define GU2_WAIT_PENDING while(READ_GP32(MGP_BLT_STATUS) & MGP_BS_BLT_PENDING) +#define GU2_WAIT_BUSY while(READ_GP32(MGP_BLT_STATUS) & MGP_BS_BLT_BUSY) +#endif + +#define HOOK(fn) localRecPtr->fn = GX##fn + +/* static storage declarations */ + +typedef struct sGBltBox { + ulong x, y; + ulong w, h; + ulong color; + int bpp, transparent; +} GBltBox; + +#if GX_SCANLINE_SUPPORT +static GBltBox giwr; +#endif +#if GX_CPU2SCREXP_SUPPORT +static GBltBox gc2s; +#endif +#if GX_CLREXP_8X8_PAT_SUPPORT +static ulong *gc8x8p; +#endif + +#if GX_DASH_LINE_SUPPORT +typedef struct sGDashLine { + ulong pat[2]; + int len; + int fg; + int bg; +} GDashLine; + +static GDashLine gdln; +#endif + +static unsigned int gu2_xshift, gu2_yshift; +static XAAInfoRecPtr localRecPtr; + +/* pat 0xF0 */ +/* src 0xCC */ +/* dst 0xAA */ + +/* (src FUNC dst) */ + +static const int SDfn[16] = { + 0x00, 0x88, 0x44, 0xCC, 0x22, 0xAA, 0x66, 0xEE, + 0x11, 0x99, 0x55, 0xDD, 0x33, 0xBB, 0x77, 0xFF +}; + +/* ((src FUNC dst) AND pat-mask) OR (dst AND (NOT pat-mask)) */ + +static const int SDfn_PM[16] = { + 0x0A, 0x8A, 0x4A, 0xCA, 0x2A, 0xAA, 0x6A, 0xEA, + 0x1A, 0x9A, 0x5A, 0xDA, 0x3A, 0xBA, 0x7A, 0xFA +}; + +/* (pat FUNC dst) */ + +static int PDfn[16] = { + 0x00, 0xA0, 0x50, 0xF0, 0x0A, 0xAA, 0x5A, 0xFA, + 0x05, 0xA5, 0x55, 0xF5, 0x0F, 0xAF, 0x5F, 0xFF +}; + +/* ((pat FUNC dst) AND src-mask) OR (dst AND (NOT src-mask)) */ + +static int PDfn_SM[16] = { + 0x22, 0xA2, 0x62, 0xE2, 0x2A, 0xAA, 0x6A, 0xEA, + 0x26, 0xA6, 0x66, 0xE6, 0x2E, 0xAE, 0x6E, 0xEE +}; + +#define move0(d,s,n) \ + __asm__ __volatile__( \ + " rep; movsl\n" \ + : "=&c" (d0), "=&S" (d1), "=&D" (d2) \ + : "0" (n), "1" (s), "2" (d) \ + : "memory") + +#define move1(d,s,n) \ + __asm__ __volatile__( \ + " rep; movsl\n" \ + " movsb\n" \ + : "=&c" (d0), "=&S" (d1), "=&D" (d2) \ + : "0" (n), "1" (s), "2" (d) \ + : "memory") + +#define move2(d,s,n) \ + __asm__ __volatile__( \ + " rep; movsl\n" \ + " movsw\n" \ + : "=&c" (d0), "=&S" (d1), "=&D" (d2) \ + : "0" (n), "1" (s), "2" (d) \ + : "memory") + +#define move3(d,s,n) \ + __asm__ __volatile__( \ + " rep; movsl\n" \ + " movsw\n" \ + " movsb\n" \ + : "=&c" (d0), "=&S" (d1), "=&D" (d2) \ + : "0" (n), "1" (s), "2" (d) \ + : "memory") + +static void +amd_memory_to_screen_blt(unsigned long src, unsigned long dst, + unsigned long sp, unsigned long dp, + long w, long h, int bpp) +{ + int d0, d1, d2; + int n = w*(bpp>>3); + int m = n >> 2; + switch( n&3 ) { + case 0: while( --h>=0 ) { move0(dst,src,m); src+=sp; dst+=dp; } break; + case 1: while( --h>=0 ) { move1(dst,src,m); src+=sp; dst+=dp; } break; + case 2: while( --h>=0 ) { move2(dst,src,m); src+=sp; dst+=dp; } break; + case 3: while( --h>=0 ) { move3(dst,src,m); src+=sp; dst+=dp; } break; + } +} + +/*---------------------------------------------------------------------------- + * GXAccelSync. + * + * Description :This function is called to synchronize with the graphics + * engine and it waits the graphic engine is idle. This is + * required before allowing direct access to the framebuffer. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * + * Returns :none + *---------------------------------------------------------------------------*/ +void +GXAccelSync(ScrnInfoPtr pScrni) +{ + DBLOG(3,"GXAccelSync()\n"); +#ifndef OPT_ACCEL + gfx_wait_until_idle(); +#else + GU2_WAIT_BUSY; +#endif +} + +#if GX_FILL_RECT_SUPPORT +/*---------------------------------------------------------------------------- + * GXSetupForSolidFill. + * + * Description :The SetupFor and Subsequent SolidFill(Rect) provide + * filling rectangular areas of the screen with a + * foreground color. + * + * Parameters. + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * color int foreground fill color + * rop int unmapped raster op + * planemask uint -1 (fill) or pattern data + * + * Returns :none + *--------------------------------------------------------------------------*/ +static void +GXSetupForSolidFill(ScrnInfoPtr pScrni, + int color, int rop, unsigned int planemask) +{ + DBLOG(2,"GXSetupForSolidFill(%#x,%#x,%#x)\n",color,rop,planemask); + rop &= 0x0F; +#ifndef OPT_ACCEL + { + gfx_set_solid_pattern(planemask); + gfx_set_solid_source(color); + gfx_set_raster_operation(planemask == ~0U ? SDfn[rop] : SDfn_PM[rop]); + } +#else + { + unsigned int ROP = BPP | (planemask == ~0U ? SDfn[rop] : SDfn_PM[rop]); + BLT_MODE = ((ROP^(ROP>>2))&0x33) == 0 ? MGP_BM_SRC_MONO : 0; + if( ((ROP^(ROP>>1))&0x55) != 0 ) BLT_MODE |= MGP_BM_DST_REQ; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_PAT_COLOR_0, planemask); + WRITE_GP32(MGP_SRC_COLOR_FG, color); + WRITE_GP32(MGP_RASTER_MODE, ROP); + WRITE_GP32(MGP_STRIDE, ACCEL_STRIDE); + } +#endif +} + +/*---------------------------------------------------------------------------- + * GXSubsequentSolidFillRect. + * + * Description :see GXSetupForSolidFill. + * + * Parameters. + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x int destination x offset + * y int destination y offset + * w int fill area width (pixels) + * h int fill area height (pixels) + * + * Returns :none + * + * Sample application uses: + * - Window backgrounds. + * - pull down highlighting. + * - x11perf: rectangle tests (-rect500). + * - x11perf: fill trapezoid tests (-trap100). + * - x11perf: horizontal line segments (-hseg500). + *----------------------------------------------------------------------------*/ +static void +GXSubsequentSolidFillRect(ScrnInfoPtr pScrni, int x, int y, int w, + int h) +{ + DBLOG(2,"GXSubsequentSolidFillRect() at %d,%d %dx%d\n",x,y,w,h); +#ifndef OPT_ACCEL + { + gfx_pattern_fill(x,y, w,h); + } +#else + { + unsigned int offset = CALC_FBOFFSET(x,y); + unsigned int size = (w<<16) | h; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_DST_OFFSET, offset); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_BLT_MODE, BLT_MODE); + } +#endif +} + +/* GX_FILL_RECT_SUPPORT */ +#endif + +#if GX_CLREXP_8X8_PAT_SUPPORT +/*---------------------------------------------------------------------------- + * GXSetupForColor8x8PatternFill + * + * Description :8x8 color pattern data is 64 pixels of full color data + * stored linearly in offscreen video memory. These patterns + * are useful as a substitute for 8x8 mono patterns when tiling, + * doing opaque stipples, or regular stipples. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * patx int x offset to pattern data + * paty int y offset to pattern data + * rop int unmapped raster operation + * planemask uint -1 (copy) or pattern data + * trans_color int -1 (copy) or transparent color (not enabled) + * trans color only supported on source channel + * or in monochrome pattern channel + * + * Returns :none. + * + *---------------------------------------------------------------------------*/ + +static void +GXSetupForColor8x8PatternFill(ScrnInfoPtr pScrni, int patx, int paty, int rop, + uint planemask, int trans_color) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"GXSetupForColor8x8PatternFill() pat %#x,%#x rop %#x %#x %#x\n" + ,patx,paty,rop,planemask,trans_color); + rop &= 0x0F; + gc8x8p = (unsigned long *)FBADDR(patx,paty); + /* gfx_set_solid_pattern is needed to clear src/pat transparency */ + gfx_set_solid_pattern(0); + gfx_set_raster_operation(planemask == ~0U ? PDfn[rop] : + (gfx_set_solid_source(planemask), PDfn_SM[rop])); + gfx2_set_source_stride(pGeode->AccelPitch); + gfx2_set_destination_stride(pGeode->AccelPitch); + if( trans_color == -1 ) + gfx2_set_source_transparency(0,0); + else + gfx2_set_source_transparency(trans_color,~0); +} + +/*---------------------------------------------------------------------------- + * GXSubsequentColor8x8PatternFillRect + * + * Description :see GXSetupForColor8x8PatternFill. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * patx int pattern phase x offset + * paty int pattern phase y offset + * x int destination x offset + * y int destination y offset + * w int fill area width (pixels) + * h int fill area height (pixels) + * + * Returns :none + * + * Sample application uses: + * - Patterned desktops + * - x11perf: stippled rectangle tests (-srect500). + * - x11perf: opaque stippled rectangle tests (-osrect500). + *--------------------------------------------------------------------------*/ +static void +GXSubsequentColor8x8PatternFillRect(ScrnInfoPtr pScrni, int patx, int paty, + int x, int y, int w, int h) +{ + DBLOG(2,"GXSubsequentColor8x8PatternFillRect() patxy %d,%d at %d,%d %dsx%d\n", + patx,paty,x,y,w,h); + gfx2_set_pattern_origin(patx, paty); + gfx2_color_pattern_fill(CALC_FBOFFSET(x,y), w,h, gc8x8p); +} + +/* GX_CLREXP_8X8_PAT_SUPPORT */ +#endif + +#if GX_MONO_8X8_PAT_SUPPORT +/*---------------------------------------------------------------------------- + * GXSetupForMono8x8PatternFill + * + * Description :8x8 mono pattern data is 64 bits of color expansion data + * with ones indicating the foreground color and zeros + * indicating the background color. These patterns are + * useful when tiling, doing opaque stipples, or regular + * stipples. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * patx int x offset to pattern data + * paty int y offset to pattern data + * fg int foreground color + * bg int -1 (transparent) or background color + * rop int unmapped raster operation + * planemask uint -1 (copy) or pattern data + * + * Returns :none. + * + * Comments :none. + * + *--------------------------------------------------------------------------*/ +static void +GXSetupForMono8x8PatternFill(ScrnInfoPtr pScrni, int patx, int paty, + int fg, int bg, int rop, uint planemask) +{ + DBLOG(2,"GXSetupForMono8x8PatternFill() pat %#x,%#x fg %#x bg %#x %#x %#x\n", + patx,paty,fg,bg,rop,planemask); + rop &= 0x0F; +#ifndef OPT_ACCEL + { + gfx_set_mono_pattern(bg,fg, patx,paty, bg==-1 ? 1 : 0); + gfx_set_raster_operation(planemask == ~0U ? PDfn[rop] : + (gfx_set_solid_source(planemask), PDfn_SM[rop])); + } +#else + { + unsigned int ROP = BPP | + (bg==-1 ? MGP_RM_PAT_MONO | MGP_RM_PAT_TRANS : MGP_RM_PAT_MONO) | + (planemask == ~0U ? PDfn[rop] : PDfn_SM[rop]); + BLT_MODE = ((ROP^(ROP>>2))&0x33) == 0 ? MGP_BM_SRC_MONO : 0; + if( ((ROP^(ROP>>1))&0x55) != 0 ) BLT_MODE |= MGP_BM_DST_REQ; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_SRC_COLOR_FG, planemask); + WRITE_GP32(MGP_PAT_COLOR_0, bg); + WRITE_GP32(MGP_PAT_COLOR_1, fg); + WRITE_GP32(MGP_PAT_DATA_0, patx); + WRITE_GP32(MGP_PAT_DATA_1, paty); + WRITE_GP32(MGP_RASTER_MODE, ROP); + WRITE_GP32(MGP_STRIDE, ACCEL_STRIDE); + } +#endif +} + +/*---------------------------------------------------------------------------- + * GXSubsequentMono8x8PatternFillRect + * + * Description :see GXSetupForMono8x8PatternFill + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * patx int pattern phase x offset + * paty int pattern phase y offset + * x int destination x offset + * y int destination y offset + * w int fill area width (pixels) + * h int fill area height (pixels) + + * Returns :none + * + * Sample application uses: + * - Patterned desktops + * - x11perf: stippled rectangle tests (-srect500). + * - x11perf: opaque stippled rectangle tests (-osrect500). + *--------------------------------------------------------------------------*/ +static void +GXSubsequentMono8x8PatternFillRect(ScrnInfoPtr pScrni, int patx, int paty, + int x, int y, int w, int h) +{ + DBLOG(2,"GXSubsequentMono8x8PatternFillRect() pat %#x,%#x at %d,%d %dx%d\n",patx,paty,x,y,w,h); +#ifndef OPT_ACCEL + { + gfx_pattern_fill(x,y, w,h); + } +#else + { + unsigned int offset = CALC_FBOFFSET(x,y) | ((x&7) << 26) | ((y&7) << 29); + unsigned int size = (w<<16) | h; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_DST_OFFSET, offset); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_BLT_MODE, BLT_MODE); + } +#endif +} + +/* GX_MONO_8X8_PAT_SUPPORT */ +#endif + +#if GX_SCR2SCRCPY_SUPPORT +/*---------------------------------------------------------------------------- + * GXSetupForScreenToScreenCopy + * + * Description :SetupFor and Subsequent ScreenToScreenCopy functions + * provide an interface for copying rectangular areas from + * video memory to video memory. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * xdir int x copy direction (up/dn) + * ydir int y copy direction (up/dn) + * rop int unmapped raster operation + * planemask uint -1 (copy) or pattern data + * trans_color int -1 (copy) or transparent color + * + * Returns :none + *---------------------------------------------------------------------------*/ +static void +GXSetupForScreenToScreenCopy(ScrnInfoPtr pScrni, int xdir, int ydir, int rop, + uint planemask, int trans_color) +{ + DBLOG(2,"GXSetupForScreenToScreenCopy() xd%d yd%d rop %#x %#x %#x\n", + xdir,ydir,rop,planemask,trans_color); + rop &= 0x0F; +#ifndef OPT_ACCEL + { + GeodePtr pGeode = GEODEPTR(pScrni); + gfx_set_solid_pattern(planemask); + /* transparency is a param to set_rop, but set...pattern clears transparency */ + if( trans_color == -1 ) + gfx2_set_source_transparency(0,0); + else + gfx2_set_source_transparency(trans_color,~0); + gfx_set_raster_operation(planemask == ~0U ? SDfn[rop] : SDfn_PM[rop]); + gfx2_set_source_stride(pGeode->AccelPitch); + gfx2_set_destination_stride(pGeode->AccelPitch); + } +#else + { + unsigned int ROP = BPP | (planemask == ~0U ? SDfn[rop] : SDfn_PM[rop]); + if( trans_color != -1 ) ROP |= MGP_RM_SRC_TRANS; + BLT_MODE = ((ROP^(ROP>>1))&0x55) != 0 ? + MGP_BM_SRC_FB | MGP_BM_DST_REQ : + MGP_BM_SRC_FB; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_PAT_COLOR_0, planemask); + WRITE_GP32(MGP_SRC_COLOR_FG, trans_color); + WRITE_GP32(MGP_SRC_COLOR_BG, ~0); + WRITE_GP32(MGP_RASTER_MODE, ROP); + WRITE_GP32(MGP_STRIDE, ACCEL_STRIDE); + } +#endif +} + +/*---------------------------------------------------------------------------- + * GXSubsquentScreenToScreenCopy + * + * Description :see GXSetupForScreenToScreenCopy. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x1 int source x offset + * y1 int source y offset + * x2 int destination x offset + * y2 int destination y offset + * w int copy area width (pixels) + * h int copy area height (pixels) + * + * Returns :none + * + * Sample application uses (non-transparent): + * - Moving windows. + * - x11perf: scroll tests (-scroll500). + * - x11perf: copy from window to window (-copywinwin500). + *---------------------------------------------------------------------------*/ +static void +GXSubsequentScreenToScreenCopy(ScrnInfoPtr pScrni, + int x1, int y1, int x2, int y2, int w, int h) +{ + DBLOG(2,"GXSubsequentScreenToScreenCopy() from %d,%d to %d,%d %dx%d\n",x1,y1,x2,y2,w,h); +#ifndef OPT_ACCEL + { + int flags = 0; + if( x2 > x1 ) flags |= 1; + if( y2 > y1 ) flags |= 2; + gfx2_screen_to_screen_blt(CALC_FBOFFSET(x1,y1), CALC_FBOFFSET(x2,y2), w,h, flags); + } +#else + { + GeodePtr pGeode = GEODEPTR(pScrni); + unsigned int src = CALC_FBOFFSET(x1,y1); + unsigned int dst = CALC_FBOFFSET(x2,y2); + unsigned int size = (w<<16) | h; + unsigned int blt_mode = BLT_MODE; + if( x2 > x1 ) { + int n = (w< y1 ) { + int n = (h-1) * pGeode->AccelPitch; + src += n; dst += n; + blt_mode |= MGP_BM_NEG_YDIR; + } + GU2_WAIT_PENDING; + WRITE_GP32(MGP_SRC_OFFSET, src); + WRITE_GP32(MGP_DST_OFFSET, dst); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP16(MGP_BLT_MODE, blt_mode); + } +#endif +} + +/* GX_SCR2SCRCPY_SUPPORT */ +#endif + +#if GX_SCANLINE_SUPPORT +/*---------------------------------------------------------------------------- + * GXSetupForScanlineImageWrite + * + * Description :SetupFor/Subsequent ScanlineImageWrite and ImageWriteScanline + * transfer full color pixel data from system memory to video + * memory. This is useful for dealing with alignment issues and + * performing raster ops on the data. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * rop int unmapped raster operation + * planemask uint -1 (copy) or pattern data + * bpp int bits per pixel (unused) + * depth int color depth (unused) + * + * Returns :none + * + * x11perf -putimage10 + * x11perf -putimage100 + * x11perf -putimage500 +*---------------------------------------------------------------------------- +*/ +static void +GXSetupForScanlineImageWrite(ScrnInfoPtr pScrni, int rop, uint planemask, + int trans_color, int bpp, int depth) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"GXSetupForScanlineImageWrite() rop %#x %#x %#x %d %d\n", + rop,planemask,trans_color,bpp,depth); + rop &= 0x0F; + /* transparency is a param to set_rop, but set...pattern clears transparency */ + gfx_set_solid_pattern(planemask); + if( trans_color == -1 ) + gfx2_set_source_transparency(0,0); + else + gfx2_set_source_transparency(trans_color,~0); + gfx_set_raster_operation(planemask == ~0U ? SDfn[rop] : SDfn_PM[rop]); + gfx2_set_source_stride(pGeode->AccelPitch); + gfx2_set_destination_stride(pGeode->AccelPitch); +} + +/*---------------------------------------------------------------------------- + * GXSubsequentScanlineImageWriteRect + * + * Description : see GXSetupForScanlineImageWrite. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x int destination x offset + * y int destination y offset + * w int copy area width (pixels) + * h int copy area height (pixels) + * skipleft int x margin (pixels) to skip (not enabled) + * + * Returns :none + *---------------------------------------------------------------------------*/ +static void +GXSubsequentScanlineImageWriteRect(ScrnInfoPtr pScrni, + int x, int y, int w, int h, int skipleft) +{ + DBLOG(2,"GXSubsequentScanlineImageWriteRect() rop %d,%d %dx%d %d\n",x,y,w,h,skipleft); + giwr.x = x; giwr.y = y; + giwr.w = w; giwr.h = h; +#if !GX_USE_OFFSCRN_MEM +#if !GX_ONE_LINE_AT_A_TIME + GXAccelSync(pScrni); +#endif +#endif +} + +/*---------------------------------------------------------------------------- + * GXSubsquentImageWriteScanline + * + * Description : see GXSetupForScanlineImageWrite. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * bufno int scanline number in write group + * + * Returns :none + * + * Sample application uses (non-transparent): + * - Moving windows. + * - x11perf: scroll tests (-scroll500). + * - x11perf: copy from window to window (-copywinwin500). + * + *---------------------------------------------------------------------------*/ +static void +GXSubsequentImageWriteScanline(ScrnInfoPtr pScrni, int bufno) +{ + GeodePtr pGeode = GEODEPTR(pScrni); +#if !GX_USE_OFFSCRN_MEM + unsigned long offset; +#endif + +#if GX_ONE_LINE_AT_A_TIME + DBLOG(3,"GXSubsequentImageWriteScanline() %d\n",bufno); +#if !GX_USE_OFFSCRN_MEM + offset = pGeode->AccelImageWriteBuffers[bufno] - pGeode->FBBase; + gfx2_screen_to_screen_blt(offset, CALC_FBOFFSET(giwr.x,giwr.y), giwr.w,1 ,0); +#else + gfx2_color_bitmap_to_screen_blt(0,0, CALC_FBOFFSET(giwr.x,giwr.y), giwr.w,1, + pGeode->AccelImageWriteBuffers[bufno], pGeode->AccelPitch); +#endif + ++giwr.y; +#else + int blt_height; + DBLOG(3,"GXSubsequentImageWriteScanline() %d\n",bufno); + + if( (blt_height=pGeode->NoOfImgBuffers) > giwr.h ) + blt_height = giwr.h; + if( ++bufno < blt_height ) return; +#if !GX_USE_OFFSCRN_MEM + offset = pGeode->AccelImageWriteBuffers[0] - pGeode->FBBase; + gfx2_screen_to_screen_blt(offset, CALC_FBOFFSET(giwr.x,giwr.y), giwr.w,blt_height ,0); + GXAccelSync(pScrni); +#else + gfx2_color_bitmap_to_screen_blt(0,0, CALC_FBOFFSET(giwr.x,giwr.y), giwr.w,blt_height, + pGeode->AccelImageWriteBuffers[0], pGeode->AccelPitch); +#endif + giwr.h -= blt_height; + giwr.y += blt_height; +#endif +} + +/* GX_SCANLINE_SUPPORT */ +#endif + +#if GX_CPU2SCREXP_SUPPORT +/*---------------------------------------------------------------------------- + * GXSetupForScanlineCPUToScreenColorExpandFill + * + * Description :SetupFor/Subsequent CPUToScreenColorExpandFill and + * ColorExpandScanline routines provide an interface for + * doing expansion blits from source patterns stored in + * system memory. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * fg int foreground color + * bg int -1 (transparent) or background color + * rop int unmapped raster operation + * planemask uint -1 (copy) or pattern data + * + * Returns :none. + *---------------------------------------------------------------------------*/ + +static void +GXSetupForScanlineCPUToScreenColorExpandFill(ScrnInfoPtr pScrni, + int fg, int bg, int rop, + uint planemask) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + ulong srcpitch; + DBLOG(2,"GXSetupForScanlineCPUToScreenColorExpandFill() fg %#x bg %#x rop %#x %#x\n", + fg,bg,rop,planemask); + rop &= 0x0F; + srcpitch = ((pGeode->AccelPitch+31) >> 5) << 2; +#ifndef OPT_ACCEL + { + gfx_set_solid_pattern(planemask); + gfx_set_mono_source(bg, fg, bg==-1 ? 1 : 0); + gfx_set_raster_operation(planemask == ~0U ? SDfn[rop] : SDfn_PM[rop]); + gfx2_set_source_stride(srcpitch); + gfx2_set_destination_stride(pGeode->AccelPitch); + } +#else + { + unsigned int stride = (srcpitch << 16) | pGeode->AccelPitch; + unsigned int ROP = BPP | (planemask == ~0U ? SDfn[rop] : SDfn_PM[rop]); + if( bg == -1 ) ROP |= MGP_RM_SRC_TRANS; + BLT_MODE = ((ROP^(ROP>>1))&0x55) != 0 ? + MGP_BM_SRC_MONO | MGP_BM_SRC_FB | MGP_BM_DST_REQ : + MGP_BM_SRC_MONO | MGP_BM_SRC_FB; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_PAT_COLOR_0, planemask); + WRITE_GP32(MGP_SRC_COLOR_BG, bg); + WRITE_GP32(MGP_SRC_COLOR_FG, fg); + WRITE_GP32(MGP_RASTER_MODE, ROP); + WRITE_GP32(MGP_STRIDE, stride); + } +#endif +} + +/*---------------------------------------------------------------------------- + * GXSubsequentScanlineCPUToScreenColorExpandFill + * + Description :see GXSetupForScanlineCPUToScreenColorExpandFill + * + * Parameters: + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x int destination x offset + * y int destination y offset + * w int fill area width (pixels) + * h int fill area height (pixels) + * + * Returns :none + * + *---------------------------------------------------------------------------*/ +static void +GXSubsequentScanlineCPUToScreenColorExpandFill(ScrnInfoPtr pScrni, + int x, int y, int w, int h, int skipleft) +{ + DBLOG(2,"GXSubsequentScanlineCPUToScreenColorExpandFill() %d,%d %dx%d %d\n", + x,y,w,h,skipleft); + gc2s.x = x; gc2s.y = y; + gc2s.w = w; gc2s.h = h; +#ifdef OPT_ACCEL + { +#if GX_ONE_LINE_AT_A_TIME + unsigned int size = (gc2s.w<<16) | 1; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_WID_HEIGHT, size); +#else + GeodePtr pGeode = GEODEPTR(pScrni); + unsigned int src = pGeode->AccelColorExpandBuffers[0] - pGeode->FBBase; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_SRC_OFFSET, src); +#endif + } +#endif +} + +/*---------------------------------------------------------------------------- + * GXSubsequentColorExpandScanline + * + * Description :see GXSetupForScanlineCPUToScreenColorExpandFill + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * bufno int scanline number in write group + * + * Returns :none +*---------------------------------------------------------------------------- +*/ +static void +GXSubsequentColorExpandScanline(ScrnInfoPtr pScrni, int bufno) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(3,"GXSubsequentColorExpandScanline() %d\n",bufno); +#ifndef OPT_ACCEL + { +#if GX_ONE_LINE_AT_A_TIME + ulong offset = pGeode->AccelColorExpandBuffers[bufno] - pGeode->FBBase; + gfx2_mono_expand_blt(offset, 0,0, CALC_FBOFFSET(gc2s.x,gc2s.y), gc2s.w,1 ,0); + ++gc2s.y; +#else + ulong srcpitch; + int blt_height; + + if( (blt_height=pGeode->NoOfImgBuffers) > gc2s.h ) + blt_height = gc2s.h; + if( ++bufno < blt_height ) return; + + /* convert from bits to dwords */ + srcpitch = ((pGeode->AccelPitch+31) >> 5) << 2; + gfx2_mono_bitmap_to_screen_blt(0,0, CALC_FBOFFSET(gc2s.x,gc2s.y), gc2s.w,blt_height, + pGeode->AccelColorExpandBuffers[0],srcpitch); + gc2s.h -= blt_height; + gc2s.y += blt_height; +#endif + } +#else + { +#if GX_ONE_LINE_AT_A_TIME + unsigned int src = pGeode->AccelColorExpandBuffers[bufno] - pGeode->FBBase; + unsigned int dst = CALC_FBOFFSET(gc2s.x,gc2s.y); + ++gc2s.y; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_SRC_OFFSET, src); + WRITE_GP32(MGP_DST_OFFSET, dst); + WRITE_GP16(MGP_BLT_MODE, BLT_MODE); +#else + unsigned int dst, size; + int blt_height; + GU2_WAIT_BUSY; + if( (blt_height=pGeode->NoOfImgBuffers) > gc2s.h ) + blt_height = gc2s.h; + if( ++bufno < blt_height ) return; + dst = CALC_FBOFFSET(gc2s.x,gc2s.y); + size = (gc2s.w<<16) | blt_height; + gc2s.h -= blt_height; + gc2s.y += blt_height; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_DST_OFFSET, dst); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP16(MGP_BLT_MODE, BLT_MODE); +#endif + } +#endif +} + +/* GX_CPU2SCREXP_SUPPORT */ +#endif + +#if GX_SCR2SCREXP_SUPPORT +/*---------------------------------------------------------------------------- + * GXSetupForScreenToScreenColorExpandFill + * + * Description :SetupFor/Subsequent ScreenToScreenColorExpandFill and + * ColorExpandScanline routines provide an interface for + * doing expansion blits from source patterns stored in + * video memory. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * fg int foreground color + * bg int -1 (transparent) or background color + * rop int unmapped raster operation + * planemask uint -1 (copy) or pattern data + * + * Returns :none. + *---------------------------------------------------------------------------*/ + +static void +GXSetupForScreenToScreenColorExpandFill(ScrnInfoPtr pScrni, int fg, int bg, + int rop, uint planemask) +{ + DBLOG(2,"GXSetupForScreenToScreenColorExpandFill() fg %#x bg %#x rop %#x %#x\n", + fg,bg,rop,planemask); + rop &= 0x0F; +#ifndef OPT_ACCEL + { + GeodePtr pGeode = GEODEPTR(pScrni); + gfx_set_solid_pattern(planemask); + gfx_set_mono_source(bg, fg, bg==-1 ? 1 : 0); + gfx_set_raster_operation(planemask == ~0U ? SDfn[rop] : SDfn_PM[rop]); + gfx2_set_source_stride(pGeode->AccelPitch); + gfx2_set_destination_stride(pGeode->AccelPitch); + } +#else + { + unsigned int ROP = BPP | (planemask == ~0U ? SDfn[rop] : SDfn_PM[rop]); + if( bg == -1 ) ROP |= MGP_RM_SRC_TRANS; + BLT_MODE = ((ROP^(ROP>>1))&0x55) != 0 ? + MGP_BM_SRC_MONO | MGP_BM_SRC_FB | MGP_BM_DST_REQ : + MGP_BM_SRC_MONO | MGP_BM_SRC_FB; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_PAT_COLOR_0, planemask); + WRITE_GP32(MGP_SRC_COLOR_BG, bg); + WRITE_GP32(MGP_SRC_COLOR_FG, fg); + WRITE_GP32(MGP_RASTER_MODE, ROP); + WRITE_GP32(MGP_STRIDE, ACCEL_STRIDE); + } +#endif +} + +/*---------------------------------------------------------------------------- + * GXSubsequentScreenToScreenColorExpandFill + * + * Description :see GXSetupForScreenToScreenColorExpandFill + * + * Parameters: + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x int destination x offset + * y int destination y offset + * w int fill area width (pixels) + * h int fill area height (pixels) + * offset int initial x offset + * + * Returns :none + * + *---------------------------------------------------------------------------*/ +static void +GXSubsequentScreenToScreenColorExpandFill(ScrnInfoPtr pScrni, + int x, int y, int w, int h, + int srcx, int srcy, int offset) +{ + DBLOG(2,"GXSubsequentScreenToScreenColorExpandFill() %d,%d %dx%d %d,%d %d\n", + x,y,w,h,srcx,srcy,offset); +#ifndef OPT_ACCEL + { + gfx2_mono_expand_blt(CALC_FBOFFSET(srcx,srcy), offset,0, CALC_FBOFFSET(x,y), w,h, 0); + } +#else + { + unsigned int src = (CALC_FBOFFSET(srcx,srcy) + (offset>>3)) | ((offset&7)<<26); + unsigned int dst = CALC_FBOFFSET(x,y); + unsigned int size = (w<<16) | h; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_SRC_OFFSET, src); + WRITE_GP32(MGP_DST_OFFSET, dst); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP16(MGP_BLT_MODE, BLT_MODE); + } +#endif +} + +/* GX_SCR2SCREXP_SUPPORT */ +#endif + +#define VM_MAJOR_DEC 0 +#define VM_MINOR_DEC 0 + +static unsigned short vmode[] = { + VM_X_MAJOR | VM_MAJOR_INC | VM_MINOR_INC, /* !XDECREASING !YDECREASING !YMAJOR */ + VM_Y_MAJOR | VM_MAJOR_INC | VM_MINOR_INC, /* !XDECREASING !YDECREASING YMAJOR */ + VM_X_MAJOR | VM_MAJOR_INC | VM_MINOR_DEC, /* !XDECREASING YDECREASING !YMAJOR */ + VM_Y_MAJOR | VM_MAJOR_DEC | VM_MINOR_INC, /* !XDECREASING YDECREASING YMAJOR */ + VM_X_MAJOR | VM_MAJOR_DEC | VM_MINOR_INC, /* XDECREASING !YDECREASING !YMAJOR */ + VM_Y_MAJOR | VM_MAJOR_INC | VM_MINOR_DEC, /* XDECREASING !YDECREASING YMAJOR */ + VM_X_MAJOR | VM_MAJOR_DEC | VM_MINOR_DEC, /* XDECREASING YDECREASING !YMAJOR */ + VM_Y_MAJOR | VM_MAJOR_DEC | VM_MINOR_DEC, /* XDECREASING YDECREASING YMAJOR */ +}; + +#if GX_BRES_LINE_SUPPORT +/*---------------------------------------------------------------------------- + * GXSetupForSolidLine + * + * Description :SetupForSolidLine and Subsequent HorVertLine TwoPointLine + * BresenhamLine provides an interface for drawing thin + * solid lines. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * color int foreground fill color + * rop int unmapped raster op + * planemask uint -1 (fill) or pattern data (not enabled) + * + * Returns :none +*---------------------------------------------------------------------------*/ +static void +GXSetupForSolidLine(ScrnInfoPtr pScrni, + int color, int rop, uint planemask) +{ + DBLOG(2,"GXSetupForSolidLine() %#x %#x %#x\n",color,rop,planemask); + rop &= 0x0F; +#ifndef OPT_ACCEL + { + gfx_set_solid_pattern(color); + gfx_set_raster_operation(planemask == ~0U ? PDfn[rop] : + (gfx_set_solid_source(planemask), PDfn_SM[rop])); + } +#else + { + unsigned int ROP = BPP | (planemask == ~0U ? PDfn[rop] : PDfn_SM[rop]); + BLT_MODE = ((ROP^(ROP>>2))&0x33) == 0 ? MGP_BM_SRC_MONO : 0; + VEC_MODE = ((ROP^(ROP>>1))&0x55) != 0 ? ((BLT_MODE|=MGP_BM_DST_REQ), MGP_VM_DST_REQ) : 0; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_PAT_COLOR_0, color); + WRITE_GP32(MGP_SRC_COLOR_FG, planemask); + WRITE_GP32(MGP_RASTER_MODE, ROP); + WRITE_GP32(MGP_STRIDE, ACCEL_STRIDE); + } +#endif +} + +/*--------------------------------------------------------------------------- + * GXSubsequentSolidBresenhamLine + * + * Description :see GXSetupForSolidLine + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x1 int destination x offset + * y1 int destination y offset + * absmaj int Bresenman absolute major + * absmin int Bresenman absolute minor + * err int Bresenman initial error term + * len int length of the vector (pixels) + * octant int specifies sign and magnitude relationships + * used to determine axis of magor rendering + * and direction of vector progress. + * + * Returns :none + * + * - Window outlines on window move. + * - x11perf: line segments (-line500). + * - x11perf: line segments (-seg500). + *---------------------------------------------------------------------------*/ +static void +GXSubsequentSolidBresenhamLine(ScrnInfoPtr pScrni, int x1, int y1, + int absmaj, int absmin, int err, + int len, int octant) +{ + long axial, diagn; + DBLOG(2,"GXSubsequentSolidBresenhamLine() %d,%d %d %d, %d %d, %d\n", + x1,y1,absmaj,absmin,err,len,octant); + if( len <= 0 ) return; + axial = absmin; + err += axial; + diagn = absmin-absmaj; +#ifndef OPT_ACCEL + { + gfx_bresenham_line(x1,y1, len,err,axial,diagn,vmode[octant]); + } +#else + { + unsigned int offset = CALC_FBOFFSET(x1, y1); + unsigned int vec_err = (axial<<16) | (unsigned short)diagn; + unsigned int vec_len = (len<<16) | (unsigned short)err; + unsigned int vec_mode = VEC_MODE | vmode[octant]; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_DST_OFFSET, offset); + WRITE_GP32(MGP_VEC_ERR, vec_err); + WRITE_GP32(MGP_VEC_LEN, vec_len); + WRITE_GP32(MGP_VECTOR_MODE, vec_mode); + } +#endif +} + +/*--------------------------------------------------------------------------- + * GXSubsequentSolidTwoPointLine + * + * Description :see GXSetupForSolidLine + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x0 int destination x start offset + * y0 int destination y start offset + * x1 int destination x end offset + * y1 int destination y end offset + * flags int OMIT_LAST, dont draw last pixel (not used) + * + * Returns :none + *---------------------------------------------------------------------------*/ +static void +GXSubsequentSolidTwoPointLine(ScrnInfoPtr pScrni, int x0, int y0, + int x1, int y1, int flags) +{ + long dx, dy, dmaj, dmin, octant, bias; + long axial, diagn, err, len; + DBLOG(2,"GXSubsequentSolidTwoPointLine() %d,%d %d,%d, %#x\n", + x0,y0,x1,y1,flags); + + if( (dx=x1-x0) < 0 ) dx = -dx; + if( (dy=y1-y0) < 0 ) dy = -dy; + if( dy >= dx ) { + dmaj = dy; dmin = dx; + octant = YMAJOR; + } + else { + dmaj = dx; dmin = dy; + octant = 0; + } + len = dmaj; + if( (flags&OMIT_LAST) == 0 ) ++len; + if( len <= 0 ) return; + if (x1 < x0) octant |= XDECREASING; + if (y1 < y0) octant |= YDECREASING; + + axial = dmin << 1; + bias = miGetZeroLineBias(pScrni->pScreen); + err = axial - dmaj - ((bias>>octant) & 1); + diagn = (dmin-dmaj) << 1; + +#ifndef OPT_ACCEL + { + gfx_bresenham_line(x0,y0, len,err,axial,diagn, vmode[octant]); + } +#else + { + unsigned int offset = CALC_FBOFFSET(x0, y0); + unsigned int vec_err = (axial<<16) | (unsigned short)diagn; + unsigned int vec_len = (len<<16) | (unsigned short)err; + unsigned int vec_mode = VEC_MODE | vmode[octant]; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_DST_OFFSET, offset); + WRITE_GP32(MGP_VEC_ERR, vec_err); + WRITE_GP32(MGP_VEC_LEN, vec_len); + WRITE_GP32(MGP_VECTOR_MODE, vec_mode); + } +#endif +} + + +/*--------------------------------------------------------------------------- + * GXSubsequentSolidHorVertLine + * + * Description :see GXSetupForSolidLine + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x int destination x offset + * y int destination y offset + * len int length of the vector (pixels) + * dir int DEGREES_270 or DEGREES_0 line direction + * + * Sample application uses: + * - Window outlines on window move. + * - x11perf: line segments (-hseg500). + * - x11perf: line segments (-vseg500). + *--------------------------------------------------------------------------- + */ +static void +GXSubsequentSolidHorVertLine(ScrnInfoPtr pScrni, + int x, int y, int len, int dir) +{ + DBLOG(2,"GXSubsequentHorVertLine() %d,%d %d %d\n",x,y,len,dir); +#ifndef OPT_ACCEL + { + if( dir == DEGREES_0 ) + gfx_pattern_fill(x,y,len,1); + else + gfx_pattern_fill(x,y,1,len); + } +#else + { + unsigned int offset = CALC_FBOFFSET(x,y); + unsigned int size = dir == DEGREES_0 ? (len<<16) | 1 : (1<<16) | len; + GU2_WAIT_PENDING; + WRITE_GP32(MGP_DST_OFFSET, offset); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_BLT_MODE, BLT_MODE); + } +#endif +} + +/* GX_BRES_LINE_SUPPORT */ +#endif + +#if GX_DASH_LINE_SUPPORT +/*---------------------------------------------------------------------------- + * GXSetupForDashedLine + * + * Description :SetupForDashedLine and Subsequent TwoPointLine + * BresenhamLine provides an interface for drawing thin + * dashed lines. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * fg int foreground fill color + * bg int -1 (transp) or background fill color + * rop int unmapped raster op + * planemask uint -1 (fill) or pattern data (not enabled) + * length int pattern length (bits) + * pattern uchar* dash pattern mask + * + * Returns :none +*---------------------------------------------------------------------------*/ +static void +GXSetupForDashedLine(ScrnInfoPtr pScrn, int fg, int bg, int rop, + unsigned int planemask, int length, + unsigned char *pattern) +{ + int i, l, n, m; + CARD32 pat = *pattern; + CARD32 pat8x8[2]; + if( length <= 0 ) return; + i = l = m = 0; + while( i < 2 ) { + m |= pat >> l; + l += length; + if( (n=l-32) >= 0 ) { + pat8x8[i++] = m; + m = pat << (length-n); + l = n; + } + } + gdln.pat[0] = pat8x8[0]; + gdln.pat[1] = pat8x8[1]; + gdln.len = length; + gdln.fg = fg; + gdln.bg = bg; + rop &= 0x0F; + gfx_set_solid_pattern(0); + gfx_set_raster_operation(planemask == ~0U ? PDfn[rop] : + (gfx_set_solid_source(planemask), PDfn_SM[rop])); +} + +/*--------------------------------------------------------------------------- + * GXSubsequentDashedBresenhamLine + * + * Description :This function is used to render a vector using the + * specified bresenham parameters. + * + * Parameters: + * pScrni :Screen handler pointer having screen information. + * x1 :Specifies the starting x position + * y1 :Specifies starting y possition + * absmaj :Specfies the Bresenman absolute major. + * absmin :Specfies the Bresenman absolute minor. + * err :Specifies the bresenham err term. + * len :Specifies the length of the vector interms of pixels. + * octant :not used in this function,may be added for standard + * interface. + * Returns :none + * + * Comments :none + * Sample application uses: + * - Window outlines on window move. + * - x11perf: line segments (-line500). + * - x11perf: line segments (-seg500). +*---------------------------------------------------------------------------- +*/ +static void +GXSubsequentDashedBresenhamLine(ScrnInfoPtr pScrni, + int x1, int y1, int absmaj, int absmin, + int err, int len, int octant, int phase) +{ + int i, n; + int axial, diagn; + int trans = (gdln.bg == -1); + unsigned long pat8x8[2]; + DEBUGMSG(0, (0, 0, "BLine %d, %d, %d, %d, %d, %d, %d\n", + x1, y1, absmaj, absmin, err, len, octant)); + i = phase >= 32 ? (phase-=32, 1) : 0; + n = 32-phase; + pat8x8[0] = ((gdln.pat[i]>>phase)&((1UL<>phase)&((1UL<= 32 ? (phase-=32, 1) : 0; + n = 32-phase; + pat8x8[0] = ((gdln.pat[i]>>phase)&((1UL<>phase)&((1UL<= dx ) { + dmaj = dy; dmin = dx; + octant = YMAJOR; + } + else { + dmaj = dx; dmin = dy; + octant = 0; + } + len = dmaj; + if( (flags&OMIT_LAST) == 0 ) ++len; + if( len <= 0 ) return; + if (x1 < x0) octant |= XDECREASING; + if (y1 < y0) octant |= YDECREASING; + + axial = dmin << 1; + bias = miGetZeroLineBias(pScrni->pScreen); + err = axial-dmaj - ((bias>>octant) & 1); + diagn = (dmin-dmaj) << 1; + + gfx2_set_pattern_origin(x0, y0); + gfx2_bresenham_line(CALC_FBOFFSET(x0,y0), len, err, axial, diagn, vmode[octant]); + +} + +/* GX_DASH_LINE_SUPPORT */ +#endif + +#if GX_WRITE_PIXMAP_SUPPORT +static void +GXWritePixmap(ScrnInfoPtr pScrni, int x, int y, int w, int h, unsigned char *src, int srcwidth, + int rop, unsigned int planemask, int trans, int bpp, int depth) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"GXWritePixmap() %d,%d %dx%d, s%#x sp%d %#x %#x %#x %d %d\n", + x,y, w,h, src, srcwidth, rop, planemask, trans,bpp,depth); + if( bpp == pScrni->bitsPerPixel ) { + rop &= 0x0F; + if( rop == GXcopy && trans == -1 ) { + gfx_wait_until_idle(); + amd_memory_to_screen_blt((unsigned long)src,(unsigned long)FBADDR(x,y), + srcwidth,pGeode->AccelPitch, w,h, bpp); + } + else { + gfx_set_solid_pattern(planemask); + gfx_set_raster_operation(planemask == ~0U ? SDfn[rop] : SDfn_PM[rop]); + if( trans != -1 ) + gfx_color_bitmap_to_screen_xblt(0,0, x,y, w,h, src, srcwidth,trans); + else + gfx_color_bitmap_to_screen_blt(0,0, x,y, w,h, src, srcwidth); + SET_SYNC_FLAG(pGeode->AccelInfoRec); + } + } + else + pGeode->WritePixmap(pScrni,x,y,w,h,src,srcwidth,rop,planemask,trans,bpp,depth); +} +#endif + +/**************************************************************************/ + +/*---------------------------------------------------------------------------- + * GXAccelInit. + * + * Description :This function sets up the supported acceleration routines and + * appropriate flags. + * + * Parameters: + * pScrn :Screeen pointer structure. + * + * Returns :TRUE on success and FALSE on Failure + * + * Comments :This function is called in GXScreenInit in + geode_driver.c to set * the acceleration. +*---------------------------------------------------------------------------- +*/ +Bool +GXAccelInit(ScreenPtr pScrn) +{ + GeodePtr pGeode; + ScrnInfoPtr pScrni; + + pScrni = xf86Screens[pScrn->myNum]; + pGeode = GEODEPTR(pScrni); + + gu2_xshift = pScrni->bitsPerPixel >> 4; + + switch( pGeode->AccelPitch ) { + case 1024: gu2_yshift = 10; break; + case 2048: gu2_yshift = 11; break; + case 4096: gu2_yshift = 12; break; + default: gu2_yshift = 13; break; + } + + /* Getting the pointer for acceleration Inforecord */ + pGeode->AccelInfoRec = localRecPtr = XAACreateInfoRec(); + + /* SET ACCELERATION FLAGS */ + localRecPtr->Flags = PIXMAP_CACHE | OFFSCREEN_PIXMAPS | LINEAR_FRAMEBUFFER; + + /* HOOK SYNCRONIZARION ROUTINE */ + localRecPtr->Sync = GXAccelSync; + +#if GX_FILL_RECT_SUPPORT + /* HOOK FILLED RECTANGLES */ + HOOK(SetupForSolidFill); + HOOK(SubsequentSolidFillRect); + localRecPtr->SolidFillFlags = 0; +#endif + +#if GX_MONO_8X8_PAT_SUPPORT + /* Color expansion */ + HOOK(SetupForMono8x8PatternFill); + HOOK(SubsequentMono8x8PatternFillRect); +/* BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD | NO_TRANSPARENCY | */ + localRecPtr->Mono8x8PatternFillFlags = BIT_ORDER_IN_BYTE_MSBFIRST | + HARDWARE_PATTERN_PROGRAMMED_BITS | HARDWARE_PATTERN_SCREEN_ORIGIN; +#endif + +#if GX_CLREXP_8X8_PAT_SUPPORT + /* Color expansion */ + HOOK(SetupForColor8x8PatternFill); + HOOK(SubsequentColor8x8PatternFillRect); +/* BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD | NO_TRANSPARENCY | */ + localRecPtr->Color8x8PatternFillFlags = + BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD | + HARDWARE_PATTERN_PROGRAMMED_BITS | HARDWARE_PATTERN_PROGRAMMED_ORIGIN; +#endif + +#if GX_SCR2SCRCPY_SUPPORT + /* HOOK SCREEN TO SCREEN COPIES + * Set flag to only allow copy if transparency is enabled. + */ + HOOK(SetupForScreenToScreenCopy); + HOOK(SubsequentScreenToScreenCopy); + localRecPtr->ScreenToScreenCopyFlags = + BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD; +#endif + +#if GX_BRES_LINE_SUPPORT + /* HOOK BRESENHAM SOLID LINES */ + localRecPtr->SolidLineFlags = NO_PLANEMASK; + HOOK(SetupForSolidLine); + HOOK(SubsequentSolidBresenhamLine); + HOOK(SubsequentSolidHorVertLine); + HOOK(SubsequentSolidTwoPointLine); + localRecPtr->SolidBresenhamLineErrorTermBits = 15; +#endif + +#if GX_DASH_LINE_SUPPORT + /* HOOK BRESENHAM DASHED LINES */ + HOOK(SetupForDashedLine); + HOOK(SubsequentDashedBresenhamLine); + HOOK(SubsequentDashedTwoPointLine); + localRecPtr->DashedBresenhamLineErrorTermBits = 15; + localRecPtr->DashPatternMaxLength = 64; + localRecPtr->DashedLineFlags = NO_PLANEMASK | /* TRANSPARENCY_ONLY | */ + LINE_PATTERN_POWER_OF_2_ONLY | LINE_PATTERN_MSBFIRST_MSBJUSTIFIED; +#endif + +#if GX_SCR2SCREXP_SUPPORT + /* Color expansion */ + HOOK(SetupForScreenToScreenColorExpandFill); + HOOK(SubsequentScreenToScreenColorExpandFill); + localRecPtr->ScreenToScreenColorExpandFillFlags = + BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD | NO_TRANSPARENCY; +#endif + + if (pGeode->AccelImageWriteBuffers) { +#if GX_SCANLINE_SUPPORT + localRecPtr->ScanlineImageWriteBuffers = pGeode->AccelImageWriteBuffers; + localRecPtr->NumScanlineImageWriteBuffers = pGeode->NoOfImgBuffers; + HOOK(SetupForScanlineImageWrite); + HOOK(SubsequentScanlineImageWriteRect); + HOOK(SubsequentImageWriteScanline); + localRecPtr->ScanlineImageWriteFlags = NO_PLANEMASK | NO_GXCOPY | + BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD; +#endif + + } else { + localRecPtr->PixmapCacheFlags = DO_NOT_BLIT_STIPPLES; + } + + if (pGeode->AccelColorExpandBuffers) { +#if GX_CPU2SCREXP_SUPPORT + /* Color expansion */ + localRecPtr->ScanlineColorExpandBuffers = pGeode->AccelColorExpandBuffers; + localRecPtr->NumScanlineColorExpandBuffers = pGeode->NoOfColorExpandLines; + HOOK(SetupForScanlineCPUToScreenColorExpandFill); + HOOK(SubsequentScanlineCPUToScreenColorExpandFill); + HOOK(SubsequentColorExpandScanline); + localRecPtr->ScanlineCPUToScreenColorExpandFillFlags = NO_PLANEMASK | + BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD; +#endif + } + +#if GX_WRITE_PIXMAP_SUPPORT + pGeode->WritePixmap = localRecPtr->WritePixmap; + HOOK(WritePixmap); +#endif + +#ifdef OPT_ACCEL + ACCEL_STRIDE = (pGeode->AccelPitch<<16) | pGeode->AccelPitch; + switch (pScrni->bitsPerPixel) { + case 16: BPP = MGP_RM_BPPFMT_565; break; + case 32: BPP = MGP_RM_BPPFMT_8888; break; + default: BPP = MGP_RM_BPPFMT_332; break; + } +#endif + + return (XAAInit(pScrn, localRecPtr)); +} + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/build_num.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/build_num.h 2005-10-13 10:11:10.000000000 -0600 @@ -0,0 +1,66 @@ +#ifndef BUILD_NUM_H +#define BUILD_NUM_H + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + +#ifdef AMD_BUILDNUM_DEFINED +#error "Caution: You have muliple version files in your path. Please correct this." +#endif + +#define AMD_BUILDNUM_DEFINED + +/* Define the following for your driver */ + +#define _NAME "AMD Linux Xorg LX/GX display driver" +#define _MAJOR 3 +#define _MINOR 0 + +/* This defines the current buildlevel and revision of the code */ +#define _BL 01 +#define _BLREV 00 + +#ifdef _BLREV +#define _BUILDLEVEL _x(_BL)_x(_BLREV) +#else +#define _BUILDLEVEL _x(_BL) +#endif + +/* Use this macro to get the version string */ + +#define _VERSION_NUMBER _x(_MAJOR) "." _x(_MINOR) "." _BUILDLEVEL +#define AMD_VERSION _NAME " " _VERSION_NUMBER + +/* Syntatic sugar for use above - you probably don't have to touch this */ + +#define _x(s) _s(s) +#define _s(s) #s + +#endif --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_driver.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_driver.c 2005-08-03 16:36:31.000000000 -0600 @@ -0,0 +1,2410 @@ +/* + * $Workfile: amd_gx_driver.c $ + * $Revision: #8 $ + * $Author: raymondd $ + * + * File Contents: This is the main module configures the interfacing + * with the X server. The individual modules will be + * loaded based upon the options selected from the + * XF86Config. This file also has modules for finding + * supported modes, turning on the modes based on options. + * + * Project: Geode Xfree Frame buffer device driver. + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +/* Includes that are used by all drivers */ +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86_ansic.h" +#include "xf86_libc.h" +#include "xf86Resources.h" + +/* We may want inb() and outb() */ +#include "compiler.h" + +/* We may want to access the PCI config space */ +#include "xf86PciInfo.h" +#include "xf86Pci.h" + +/* Colormap handling stuff */ +#include "xf86cmap.h" + +#define RC_MAX_DEPTH 24 + +#include "amd.h" +#include "gfx_defs.h" +#include "gfx_regs.h" +#include "panel.h" + +/* Frame buffer stuff */ +#if CFB +/* + * If using cfb, cfb.h is required. Select the others for the bpp values + * the driver supports. + */ +#define PSZ 8 /* needed for cfb.h */ +#include "cfb.h" +#undef PSZ +#include "cfb16.h" +#include "cfb24.h" +#include "cfb32.h" +#else +#include "fb.h" +#endif + +#include "shadowfb.h" + +/* Machine independent stuff */ +#include "mipointer.h" +#include "mibank.h" +#include "micmap.h" +/* All drivers implementing backing store need this */ +#include "mibstore.h" +#include "vgaHW.h" +#include "vbe.h" + +/* Check for some extensions */ +#ifdef XFreeXDGA +#define _XF86_DGA_SERVER_ +#include "extensions/xf86dgastr.h" +#endif /* XFreeXDGA */ + +#ifdef DPMSExtension +#include "globals.h" +#include "opaque.h" +#define DPMS_SERVER +#include "extensions/dpms.h" +#endif /* DPMSExtension */ + +#include "amd_gx_vga.c" + +extern SymTabRec GeodeChipsets[]; +extern OptionInfoRec GX_GeodeOptions[]; + +/* Forward definitions */ +static Bool GXPreInit(ScrnInfoPtr, int); +static Bool GXScreenInit(int, ScreenPtr, int, char **); +static Bool GXEnterVT(int, int); +static void GXLeaveVT(int, int); +static void GXFreeScreen(int, int); +void GXAdjustFrame(int, int, int, int); +Bool GXSwitchMode(int, DisplayModePtr, int); +static int GXValidMode(int, DisplayModePtr, Bool, int); +static void GXLoadPalette(ScrnInfoPtr pScrni, + int numColors, int *indizes, + LOCO * colors, VisualPtr pVisual); +static Bool GXMapMem(ScrnInfoPtr); +static Bool GXUnmapMem(ScrnInfoPtr); +static void gx_set_DvLineSize(unsigned int pitch); + +extern Bool GXAccelInit(ScreenPtr pScrn); +extern Bool GXHWCursorInit(ScreenPtr pScrn); +extern void GXHideCursor(ScrnInfoPtr pScrni); +extern void GXShowCursor(ScrnInfoPtr pScrni); +extern void GXPointerMoved(int index, int x, int y); +extern void GXRotationInit(ScrnInfoPtr pScrni); +extern void GXShadowFBInit(ScreenPtr pScrn,GeodePtr pGeode,int bytpp); +extern void GXInitVideo(ScreenPtr pScrn); +extern Bool GXDGAInit(ScreenPtr pScrn); +extern void GXLoadCursorImage(ScrnInfoPtr pScrni, unsigned char *src); + +unsigned char *XpressROMPtr; +unsigned long fb; + +/* Existing Processor Models */ +#define GX1 0x1 +#define GX 0x2 +#define GX_CRT 0x6 +#define GX_TFT 0xA + +/* List of symbols from other modules that this module references.The purpose +* is that to avoid unresolved symbol warnings +*/ +extern const char *amdVgahwSymbols[]; +extern const char *amdVbeSymbols[]; +extern const char *amdInt10Symbols[]; + +#if CFB +extern const char *amdCfbSymbols[]; +#else +extern const char *amdFbSymbols[]; +#endif +extern const char *amdXaaSymbols[]; +extern const char *amdRamdacSymbols[]; +extern const char *amdShadowSymbols[]; + +void GXSetupChipsetFPtr(ScrnInfoPtr pScrn); +GeodePtr GXGetRec(ScrnInfoPtr pScrni); +void get_flatpanel_info(const char *options, int *W, int *H, + int *D, int *C, int *T); +void gx_clear_screen(ScrnInfoPtr pScrni, int width, int height, int bpp); +void gx_enable_dac_power(ScrnInfoPtr pScrni); +void gx_disable_dac_power(ScrnInfoPtr pScrni); + +#if DEBUGLVL>0 +FILE *zdfp = NULL; +#endif + +void +GXSetupChipsetFPtr(ScrnInfoPtr pScrn) +{ +#if DEBUGLVL>0 + if( zdfp == NULL ) { + zdfp = fopen("/tmp/xwin.log","w"); +#if DEBUGTIM==0 + setbuf(zdfp,NULL); +#endif + } +#endif + DEBUGMSG(1,(0, X_INFO, "GXSetupChipsetFPtr!\n")); + pScrn->PreInit = GXPreInit; + pScrn->ScreenInit = GXScreenInit; + pScrn->SwitchMode = GXSwitchMode; + pScrn->AdjustFrame = GXAdjustFrame; + pScrn->EnterVT = GXEnterVT; + pScrn->LeaveVT = GXLeaveVT; + pScrn->FreeScreen = GXFreeScreen; + pScrn->ValidMode = GXValidMode; +} + +/*---------------------------------------------------------------------------- + * GXGetRec. + * + * Description :This function allocate an GeodeRec and hooked into + * pScrni str driverPrivate member of ScreeenInfo + * structure. + * Parameters. + * pScrni :Pointer handle to the screenonfo structure. + * + * Returns :allocated pScrninfo structure. + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +GeodePtr +GXGetRec(ScrnInfoPtr pScrni) +{ + if (!pScrni->driverPrivate) { + GeodePtr pGeode; + + pGeode = pScrni->driverPrivate = xnfcalloc(sizeof(GeodeRec), 1); +#if INT10_SUPPORT + pGeode->vesa = xcalloc(sizeof(VESARec), 1); +#endif + } + return GEODEPTR(pScrni); +} + +/*---------------------------------------------------------------------------- + * GXFreeRec. + * + * Description :This function deallocate an GeodeRec and freed from + * pScrni str driverPrivate member of ScreeenInfo + * structure. + * Parameters. + * pScrni :Pointer handle to the screenonfo structure. + * + * Returns :none + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static void +GXFreeRec(ScrnInfoPtr pScrni) +{ + if (pScrni->driverPrivate == NULL) { + return; + } + xfree(pScrni->driverPrivate); + pScrni->driverPrivate = NULL; +} + +/*---------------------------------------------------------------------------- + * GXSaveScreen. + * + * Description :This is todo the screen blanking + * + * Parameters. + * pScrn :Handle to ScreenPtr structure. + * mode :mode is used by vgaHWSaveScren to check blnak os on. + * + * Returns :TRUE on success and FALSE on failure. + * + * Comments :none +*---------------------------------------------------------------------------- +*/ +static Bool +GXSaveScreen(ScreenPtr pScrn, int mode) +{ + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + + DEBUGMSG(1,(0, X_INFO, "GXSaveScreen!\n")); + + if (!pScrni->vtSema) + return vgaHWSaveScreen(pScrn, mode); + return TRUE; +} + +/*---------------------------------------------------------------------------- + * get_flatpanel_info. + * + * Description :This gets the values of the flatpanel attached. + * + * Parameters: + * options : Pointer to the display options. + * W: Pointer to the width of the panel + * H: Pointer to the height of the panel + * D: Pointer to the depth of the panel. + * C: Pointer to the color of the panel. + * T: Pointer to the type of the panel. + * Returns : none. + * + * Comments :none + *------------------------------------------------------------------------ + */ +void +get_flatpanel_info(const char *options, int *W, int *H, + int *D, int *C, int *T) +{ + char *pnl_opt; + + pnl_opt = strtok((char *)options, ":"); + *W = strtoul(pnl_opt, NULL, 0); + pnl_opt = strtok(NULL, ":"); + *H = strtoul(pnl_opt, NULL, 0); + pnl_opt = strtok(NULL, ":"); + *D = strtoul(pnl_opt, NULL, 0); + pnl_opt = strtok(NULL, ":"); + *C = strtoul(pnl_opt, NULL, 0); + pnl_opt = strtok(NULL, ":"); + *T = strtoul(pnl_opt, NULL, 0); + + *C = (*C) ? PNL_COLOR_PANEL : PNL_MONO_PANEL; + + switch (*T) { + case 0: + *T = PNL_SSTN; + break; + case 1: + *T = PNL_DSTN; + break; + case 2: + default: + *T = PNL_TFT; + break; + } + + if ((*W != 640) && (*W != 800) && (*W != 1024)) + *W = 640; + + if ((*H != 480) && (*H != 600) && (*H != 768)) + *H = 480; +} + +static xf86MonPtr +GXProbeDDC(ScrnInfoPtr pScrni, int index) +{ + vbeInfoPtr pVbe; + xf86MonPtr ddc = NULL; + + if (xf86LoadSubModule(pScrni, "vbe")) { + pVbe = VBEInit(NULL, index); + ddc = vbeDoEDID(pVbe, NULL); + vbeFree(pVbe); + } + return ddc; +} + +static void +GXDecodeDDC(ScrnInfoPtr pScrni,xf86MonPtr ddc) +{ + int i; + DEBUGMSG(1,(0, X_INFO, + "Detected monitor DDC (%4s) id %d serno %d week %d year %d nsects %d\n", + &ddc->vendor.name[0],ddc->vendor.prod_id,ddc->vendor.serial, + ddc->vendor.week,ddc->vendor.year,ddc->no_sections)); + for( i=0; idet_mon[i]; + switch( dp->type ) { + case DT: { + struct detailed_timings *r = &dp->section.d_timings; + DEBUGMSG(1,(0, X_INFO, " mon det timing %0.3f %dx%d\n", + r->clock/1000000.0, r->h_active, r->v_active)); + DEBUGMSG(1,(0, X_INFO, " mon border %d,%d laced %d stereo %d sync %d, misc %d\n", + r->h_border, r->v_border, r->interlaced, r->stereo, r->sync, r->misc)); + } break; + case DS_SERIAL: { + char *serial_no = (char*)&dp->section.serial[0]; + DEBUGMSG(1,(0, X_INFO, " mon serial %13s\n",serial_no)); + } break; + case DS_ASCII_STR: { + char *ascii = (char*)&dp->section.ascii_data[0]; + DEBUGMSG(1,(0, X_INFO, " mon ascii_str %13s\n",ascii)); + } break; + case DS_NAME: { + char *name = (char*)&dp->section.name[0]; + DEBUGMSG(1,(0, X_INFO, " mon name %13s\n",name)); + } break; + case DS_RANGES: { + struct monitor_ranges *r = &dp->section.ranges; + DEBUGMSG(1,(0, X_INFO, " mon ranges v %d-%d h %d-%d clk %d\n", + r->min_v, r->max_v, r->min_h, r->max_h, r->max_clock)); + } break; + case DS_WHITE_P: { + struct whitePoints *wp = &dp->section.wp[0]; + DEBUGMSG(1,(0, X_INFO, " mon whitept %f,%f %f,%f idx %d,%d gamma %f,%f\n", + wp[1].white_x, wp[1].white_y, wp[2].white_x, wp[2].white_y, + wp[1].index, wp[2].index, wp[1].white_gamma, wp[2].white_gamma)); + } break; + case DS_STD_TIMINGS: { + struct std_timings *t = &dp->section.std_t[0]; + DEBUGMSG(1,(0, X_INFO, " mon std_timing no size @rate, id\n")); + for( i=0; i<5; ++i ) + DEBUGMSG(1,(0, X_INFO, " %d %5dx%-5d @%-4d %d\n", + i, t[i].hsize, t[i].vsize, t[i].refresh, t[i].id)); + } break; + } + } +} +/*---------------------------------------------------------------------------- + * GXPreInit. + * + * Description :This function is called only once ate teh server startup + * + * Parameters. + * pScrni :Handle to ScreenPtr structure. + * flags :flags may be used to check the probeed one with config. + * + * Returns :TRUE on success and FALSE on failure. + * + * Comments :none. + *---------------------------------------------------------------------------- + */ +static Bool +GXPreInit(ScrnInfoPtr pScrni, int flags) +{ + ClockRangePtr GeodeClockRange; + MessageType from; + int i = 0; + GeodePtr pGeode; + char *mod = NULL; + xf86MonPtr ddc = NULL; + OptionInfoRec *GeodeOptions = &GX_GeodeOptions[0]; + +#if CFB + char *reqSymbol = NULL; +#endif /* CFB */ +#if INT10_SUPPORT + VESAPtr pVesa; +#endif + unsigned int PitchInc = 0, minPitch = 0, maxPitch = 0; + unsigned int minHeight = 0, maxHeight = 0; + unsigned int SupportFlags; + const char *s; + char **modes; + + /* + * Setup the ClockRanges, which describe what clock ranges are + * available, and what sort of modes they can be used for. + */ + GeodeClockRange = (ClockRangePtr)xnfcalloc(sizeof(ClockRange), 1); + GeodeClockRange->next = NULL; + GeodeClockRange->minClock = 25175; + GeodeClockRange->maxClock = 229500; + GeodeClockRange->clockIndex = -1; /* programmable */ + GeodeClockRange->interlaceAllowed = TRUE; + GeodeClockRange->doubleScanAllowed = FALSE; /* XXX check this */ + + DEBUGMSG(1,(0, X_INFO, "GXPreInit!\n")); + /* Allocate driver private structure */ + if (!(pGeode = GXGetRec(pScrni))) + return FALSE; + + /* This is the general case */ + for (i = 0; i < pScrni->numEntities; i++) { + pGeode->pEnt = xf86GetEntityInfo(pScrni->entityList[i]); + if (pGeode->pEnt->resources) + return FALSE; + pGeode->Chipset = pGeode->pEnt->chipset; + pScrni->chipset = (char *)xf86TokenToString(GeodeChipsets, + pGeode->pEnt->chipset); + } + + ddc = GXProbeDDC(pScrni, pGeode->pEnt->index); + if (flags & PROBE_DETECT) { + ConfiguredMonitor = ddc; + return TRUE; + } + + pGeode->FBVGAActive = 0; /* KFB will Knock of VGA */ +#if INT10_SUPPORT + if (!xf86LoadSubModule(pScrni, "int10")) + return FALSE; + xf86LoaderReqSymLists(amdInt10Symbols, NULL); +#endif + + /* If the vgahw module would be needed it would be loaded here */ + if (!xf86LoadSubModule(pScrni, "vgahw")) { + return FALSE; + } + xf86LoaderReqSymLists(amdVgahwSymbols, NULL); + DEBUGMSG(1,(0, X_INFO, "GXPreInit(1)!\n")); + /* Do the durango hardware detection */ + pGeode->cpu_version = gfx_detect_cpu(); + + /* find the base chipset core. Currently there can be only one + * chip active at any time. + */ +/* pGeode->DetectedChipSet = GX1; */ + if ((pGeode->cpu_version & 0xFF) == GFX_CPU_REDCLOUD) + pGeode->DetectedChipSet = GX; + DEBUGMSG(1,(0, X_INFO, "Detected BaseChip (%d)\n", pGeode->DetectedChipSet)); + { + Q_WORD msrValue; + + /* GX : Can have CRT or TFT only */ + gfx_msr_read(RC_ID_DF, MBD_MSR_CONFIG, &msrValue); + pGeode->DetectedChipSet = + ((msrValue.low & RCDF_CONFIG_FMT_MASK) == + RCDF_CONFIG_FMT_FP) ? GX_TFT : GX_CRT; + DEBUGMSG(1,(0, X_INFO, "Gx2 for %s\n", + ((pGeode->DetectedChipSet == GX_TFT) ? "TFT" : "CRT"))); + } + DEBUGMSG(1,(0, X_INFO, "GXPreInit(1.1)!\n")); + pGeode->vid_version = gfx_detect_video(); + pGeode->FBLinearAddr = gfx_get_frame_buffer_base(); + pGeode->FBAvail = gfx_get_frame_buffer_size(); + + /* update the max clock from the one system suports */ + GeodeClockRange->maxClock = gfx_get_max_supported_pixel_clock(); + + DEBUGMSG(1,(0, X_INFO, "GXPreInit(1.5)!\n")); + /* SET DURANGO REGISTER POINTERS + * * The method of mapping from a physical address to a linear address + * * is operating system independent. Set variables to linear address. + */ + if (pGeode->DetectedChipSet & GX) { + pGeode->cpu_reg_size = 0x4000; + pGeode->gp_reg_size = 0x4000; + pGeode->vid_reg_size = 0x4000; + } else { + pGeode->cpu_reg_size = 0x9000; + pGeode->vid_reg_size = 0x1000; + } + + if (!GXMapMem(pScrni)) + return FALSE; + + /* check if VGA is active */ + /* This routine saves the current VGA state in Durango VGA structure */ + /* check if VGA is active */ + pGeode->FBVGAActive = gu2_get_vga_active(); + + DEBUGMSG(1, (0, X_PROBED, "VGA = %d\n", pGeode->FBVGAActive)); + + /* Fill in the monitor field */ + pScrni->monitor = pScrni->confScreen->monitor; + DEBUGMSG(1,(0, X_INFO, "GXPreInit(2)!\n")); + SupportFlags = Support24bppFb | Support32bppFb; + DEBUGMSG(1,(0, X_INFO, "GXPreInit(2)!\n")); + /* Determine depth, bpp, etc. */ + if (!xf86SetDepthBpp(pScrni, 8, 8, 8, SupportFlags)) { + return FALSE; + } else { + if (!((pScrni->depth == 8) || + (pScrni->depth == 16) || + (pScrni->depth == 24) || (pScrni->depth == 32))) { + /* Depth not supported */ + DEBUGMSG(1, (pScrni->scrnIndex, X_ERROR, + "Given depth (%d bpp) is not supported by this driver\n", + pScrni->depth)); + return FALSE; + } + } + + /*This must happen after pScrni->display has been set + * * because xf86SetWeight references it. + */ + if (pScrni->depth > 8) { + /* The defaults are OK for us */ + rgb BitsPerComponent = { 0, 0, 0 }; + rgb BitMask = { 0, 0, 0 }; + + if (pScrni->depth > 16) { + /* we are operating in 24 bpp, Readcloud */ + BitsPerComponent.red = 8; + BitsPerComponent.green = 8; + BitsPerComponent.blue = 8; + + BitMask.red = 0xFF0000; + BitMask.green = 0x00FF00; + BitMask.blue = 0x0000FF; + } + if (!xf86SetWeight(pScrni, BitsPerComponent, BitMask)) { + return FALSE; + } else { + /* XXX Check if the returned weight is supported */ + } + } + + xf86PrintDepthBpp(pScrni); + + DEBUGMSG(1,(0, X_INFO, "GXPreInit(3)!\n")); + + if (!xf86SetDefaultVisual(pScrni, -1)) + return FALSE; + + DEBUGMSG(1,(0, X_INFO, "GXPreInit(4)!\n")); + + /* The new cmap layer needs this to be initialized */ + if (pScrni->depth > 1) { + Gamma zeros = { 0.0, 0.0, 0.0 }; + + if (!xf86SetGamma(pScrni, zeros)) { + return FALSE; + } + } + DEBUGMSG(1,(0, X_INFO, "GXPreInit(5)!\n")); + + /* We use a programmable clock */ + pScrni->progClock = TRUE; + + /*Collect all of the relevant option flags + * *(fill in pScrni->options) + */ + xf86CollectOptions(pScrni, NULL); + + /*Process the options */ + xf86ProcessOptions(pScrni->scrnIndex, pScrni->options, + GeodeOptions); + +#if INT10_SUPPORT + pVesa = pGeode->vesa; + /* Initialize Vesa record */ + + if ((pVesa->pInt = xf86InitInt10(pGeode->pEnt->index)) == NULL) { + xf86DrvMsg(0, X_ERROR, "Int10 initialization failed.\n"); + return (FALSE); + } +#endif + + /*Set the bits per RGB for 8bpp mode */ + if (pScrni->depth == 8) { + /* Default to 8 */ + pScrni->rgbBits = 8; + } + from = X_DEFAULT; + + /* + * *The preferred method is to use the "hw cursor" option as a tri-state + * *option, with the default set above. + */ + pGeode->HWCursor = TRUE; + if (xf86GetOptValBool(GeodeOptions, GX_OPTION_HW_CURSOR, &pGeode->HWCursor)) { + from = X_CONFIG; + } + /* For compatibility, accept this too (as an override) */ + if (xf86ReturnOptValBool(GeodeOptions, GX_OPTION_SW_CURSOR, FALSE)) { + from = X_CONFIG; + pGeode->HWCursor = FALSE; + } + DEBUGMSG(1, (pScrni->scrnIndex, from, "Using %s cursor\n", + pGeode->HWCursor ? "HW" : "SW")); + + pGeode->Compression = TRUE; + if (xf86ReturnOptValBool(GeodeOptions, GX_OPTION_NOCOMPRESSION, FALSE)) { + pGeode->Compression = FALSE; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "NoCompression\n")); + } + + pGeode->NoAccel = FALSE; + if (xf86ReturnOptValBool(GeodeOptions, GX_OPTION_NOACCEL, FALSE)) { + pGeode->NoAccel = TRUE; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "Acceleration \ + disabled\n")); + } + + if (!xf86GetOptValInteger(GeodeOptions, GX_OPTION_OSM_IMG_BUFS, + &(pGeode->NoOfImgBuffers))) + pGeode->NoOfImgBuffers = DEFAULT_IMG_LINE_BUFS; /* default # of buffers */ + if (pGeode->NoOfImgBuffers <= 0) + pGeode->NoOfImgBuffers = 0; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "NoOfImgBuffers = %d\n", pGeode->NoOfImgBuffers)); + if (!xf86GetOptValInteger(GeodeOptions, GX_OPTION_OSM_CLR_BUFS, + &(pGeode->NoOfColorExpandLines))) + pGeode->NoOfColorExpandLines = DEFAULT_CLR_LINE_BUFS; + if( pGeode->NoOfColorExpandLines <= 0 ) + pGeode->NoOfColorExpandLines = 0; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "NoOfColorExpandLines = %d\n", pGeode->NoOfColorExpandLines)); + + pGeode->Panel = FALSE; + if (xf86ReturnOptValBool(GeodeOptions, GX_OPTION_FLATPANEL, FALSE)) { + DEBUGMSG(0, (pScrni->scrnIndex, X_CONFIG, "FlatPanel Selected\n")); + pGeode->Panel = TRUE; + } + + pGeode->CustomMode = FALSE; + if (xf86ReturnOptValBool(GeodeOptions, GX_OPTION_CUSTOM_MODE, FALSE)) { + pGeode->CustomMode = TRUE; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "Custom mode enabled\n")); + } + + /* Force the Panel on if on a GX TFT part, no crt support */ + if (pGeode->DetectedChipSet == GX_TFT) { + pGeode->Panel = TRUE; + } + + /* If on a CRT and Panel flag set, disable Panel */ + if ((pGeode->DetectedChipSet == GX_CRT) && (pGeode->Panel)) + pGeode->Panel = FALSE; + + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "Quering FP Bios %d\n", pGeode->Panel)); + + /* if FP not supported in BIOS, then turn off user option */ + if (pGeode->Panel) { + /* check if bios supports FP */ +#if defined(PNL_SUP) + pGeode->Panel = Pnl_IsPanelEnabledInBIOS(); + Pnl_GetPanelInfoFromBIOS(&pGeode->FPBX, &pGeode->FPBY, + &pGeode->FPBB, &pGeode->FPBF); + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "FP Bios Params %d %d %d %d\n", + pGeode->FPBX, pGeode->FPBY, pGeode->FPBB, pGeode->FPBF)); + +#endif /* PNL_SUP */ + } + /* if panel not selected and Panel can be supported. + * Power down the panel. + */ +#if defined(PNL_SUP) + if (!pGeode->Panel) { + Pnl_PowerDown(); + } else { + Pnl_PowerUp(); + } +#endif /* PNL_SUP */ + + pGeode->ShadowFB = FALSE; + if (xf86ReturnOptValBool(GeodeOptions, GX_OPTION_SHADOW_FB, FALSE)) { + pGeode->ShadowFB = TRUE; + pGeode->NoAccel = TRUE; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "Using \"Shadow Framebuffer\"\n")); + } + + pGeode->Rotate = 0; + if ((s = xf86GetOptValString(GeodeOptions, GX_OPTION_ROTATE))) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "Rotating - %s\n", s)); + if (!xf86NameCmp(s, "CW")) { + pGeode->Rotate = 1; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "Rotating screen clockwise\n")); + } + else if (!xf86NameCmp(s, "INVERT")) { + pGeode->Rotate = 2; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "Rotating screen inverted\n")); + } + else if (!xf86NameCmp(s, "CCW")) { + pGeode->Rotate = 3; + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "Rotating screen counter clockwise\n")); + } + if( pGeode->Rotate == 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "\"%s\" is not a valid value for Option \"Rotate\"\n", s)); + DEBUGMSG(1, (pScrni->scrnIndex, X_INFO, + "Valid options are \"CW\", \"INVERT\" or \"CCW\"\n")); + } + } + if( pGeode->Rotate != 0 ) { + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, + "Option \"Rotate\" disables acceleration and enables shadow\n")); + pGeode->NoAccel = TRUE; + pGeode->ShadowFB = TRUE; + } + + /* XXX Init further private data here */ + + /* + * * This shouldn't happen because such problems should be caught in + * * GeodeProbe(), but check it just in case. + */ + if (pScrni->chipset == NULL) { + DEBUGMSG(1, (pScrni->scrnIndex, X_ERROR, + "ChipID 0x%04X is not recognised\n", pGeode->Chipset)); + return FALSE; + } + if (pGeode->Chipset < 0) { + DEBUGMSG(1, (pScrni->scrnIndex, X_ERROR, + "Chipset \"%s\" is not recognised\n", + pScrni->chipset)); + return FALSE; + } + DEBUGMSG(1,(0, X_INFO, "GXPreInit(6)!\n")); + + /* + * * Init the screen with some values + */ + DEBUGMSG(1, (pScrni->scrnIndex, from, + "Video I/O registers at 0x%08lX\n", + (unsigned long)VGAHW_GET_IOBASE())); + + if (pScrni->memPhysBase == 0) { + from = X_PROBED; + pScrni->memPhysBase = gfx_get_frame_buffer_base(); + } + pScrni->fbOffset = 0; + + DEBUGMSG(1, (pScrni->scrnIndex, from, + "Linear framebuffer at 0x%08lX\n", + (unsigned long)pScrni->memPhysBase)); + + if (pGeode->pEnt->device->videoRam == 0) { + from = X_PROBED; + pScrni->videoRam = pGeode->FBAvail / 1024; + } else { + pScrni->videoRam = pGeode->pEnt->device->videoRam; + from = X_CONFIG; + } + DEBUGMSG(1, (pScrni->scrnIndex, from, + "VideoRam: %ld kByte\n", + (unsigned long)pScrni->videoRam)); + + DEBUGMSG(1,(0, X_INFO, "GXPreInit(7)!\n")); + + /* + * * xf86ValidateModes will check that the mode HTotal and VTotal values + * * don't exceed the chipset's limit if pScrni->maxHValue adn + * * pScrni->maxVValue are set. Since our GXValidMode() + * * already takes care of this, we don't worry about setting them here. + */ + /* Select valid modes from those available */ + /* + * * min pitch 1024, max 2048 (Pixel count) + * * min height 480, max 1024 (Pixel count) + */ + minPitch = 1024; + maxPitch = 4096; /* Can support upto 1600x1200 32Bpp */ + minHeight = 400; + maxHeight = 1200; /* Can support upto 1600x1200 32Bpp */ + if (pScrni->depth > 16) { + PitchInc = 4096; + } else if (pScrni->depth == 16) { + PitchInc = 2048; + } else { + PitchInc = 1024; + } + PitchInc <<= 3; /* in bits */ + + /* by default use what user sets in the XF86Config file */ + modes = pScrni->display->modes; + + if( ddc != NULL && pScrni->monitor != NULL && pScrni->monitor->DDC == NULL ) { + pScrni->monitor->DDC = ddc; + GXDecodeDDC(pScrni,ddc); + } + + i = xf86ValidateModes(pScrni, + pScrni->monitor->Modes, + modes, GeodeClockRange, + NULL, minPitch, maxPitch, + PitchInc, minHeight, maxHeight, + pScrni->display->virtualX, + pScrni->display->virtualY, + pGeode->FBAvail, + LOOKUP_BEST_REFRESH); + + DEBUGMSG(1, (pScrni->scrnIndex, from, + "xf86ValidateModes: %d %d %d\n", + pScrni->virtualX, + pScrni->virtualY, pScrni->displayWidth)); + if (i == -1) { + GXFreeRec(pScrni); + return FALSE; + } + DEBUGMSG(1,(0, X_INFO, "GXPreInit(8)!\n")); + + /* Prune the modes marked as invalid */ + xf86PruneDriverModes(pScrni); + + DEBUGMSG(1,(0, X_INFO, "GXPreInit(9)!\n")); + if (i == 0 || pScrni->modes == NULL) { + DEBUGMSG(1, (pScrni->scrnIndex, X_ERROR, + "No valid modes found\n")); + GXFreeRec(pScrni); + return FALSE; + } + DEBUGMSG(1,(0, X_INFO, "GXPreInit(10)!\n")); + + xf86SetCrtcForModes(pScrni, 0); + DEBUGMSG(1,(0, X_INFO, "GXPreInit(11)!\n")); + + /* Set the current mode to the first in the list */ + pScrni->currentMode = pScrni->modes; + DEBUGMSG(1,(0, X_INFO, "GXPreInit(12)!\n")); + + /* Print the list of modes being used */ + xf86PrintModes(pScrni); + DEBUGMSG(1,(0, X_INFO, "GXPreInit(13)!\n")); + + /* Set the display resolution */ + xf86SetDpi(pScrni, 0, 0); + DEBUGMSG(1,(0, X_INFO, "GXPreInit(14)!\n")); + + /* Load bpp-specific modules */ + mod = NULL; + +#if CFB + /* Load bpp-specific modules */ + switch (pScrni->bitsPerPixel) { + case 8: + mod = "cfb"; + reqSymbol = "cfbScreenInit"; + break; + case 16: + mod = "cfb16"; + reqSymbol = "cfb16ScreenInit"; + break; + case 24: + mod = "cfb24"; + reqSymbol = "cfb24ScreenInit"; + break; + case 32: + mod = "cfb32"; + reqSymbol = "cfb32ScreenInit"; + break; + default: + return FALSE; + } + if (mod && xf86LoadSubModule(pScrni, mod) == NULL) { + GXFreeRec(pScrni); + return FALSE; + } + + xf86LoaderReqSymbols(reqSymbol, NULL); +#else + if (xf86LoadSubModule(pScrni, "fb") == NULL) { + GXFreeRec(pScrni); + return FALSE; + } + + xf86LoaderReqSymLists(amdFbSymbols, NULL); +#endif + DEBUGMSG(1,(0, X_INFO, "GXPreInit(15)!\n")); + if (pGeode->NoAccel == FALSE) { + if (!xf86LoadSubModule(pScrni, "xaa")) { + GXFreeRec(pScrni); + return FALSE; + } + xf86LoaderReqSymLists(amdXaaSymbols, NULL); + } + DEBUGMSG(1,(0, X_INFO, "GXPreInit(16)!\n")); + if (pGeode->HWCursor == TRUE) { + if (!xf86LoadSubModule(pScrni, "ramdac")) { + GXFreeRec(pScrni); + return FALSE; + } + xf86LoaderReqSymLists(amdRamdacSymbols, NULL); + } + DEBUGMSG(1,(0, X_INFO, "GXPreInit(17)!\n")); + /* Load shadowfb if needed */ + if (pGeode->ShadowFB) { + if (!xf86LoadSubModule(pScrni, "shadowfb")) { + GXFreeRec(pScrni); + return FALSE; + } + xf86LoaderReqSymLists(amdShadowSymbols, NULL); + } + + DEBUGMSG(1,(0, X_INFO, "GXPreInit(18)!\n")); + if (xf86RegisterResources(pGeode->pEnt->index, NULL, ResExclusive)) { + DEBUGMSG(1, (pScrni->scrnIndex, X_ERROR, + "xf86RegisterResources() found resource conflicts\n")); + GXFreeRec(pScrni); + return FALSE; + } + GXUnmapMem(pScrni); + DEBUGMSG(1,(0, X_INFO, "GXPreInit ... done successfully!\n")); + return TRUE; +} + +/*---------------------------------------------------------------------------- + * GXRestore. + * + * Description :This function restores the mode that was saved on server + entry + * Parameters. + * pScrni :Handle to ScreenPtr structure. + * Pmode :poits to screen mode + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static void +GXRestore(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + DEBUGMSG(1,(0, X_INFO, "GXRestore!\n")); + if (pGeode->FBVGAActive) { + vgaHWPtr pvgaHW = VGAHWPTR(pScrni); + + vgaHWProtect(pScrni, TRUE); + vgaHWRestore(pScrni, &pvgaHW->SavedReg, VGA_SR_ALL); + vgaHWProtect(pScrni, FALSE); + } +} + +/*---------------------------------------------------------------------------- + * GXCalculatePitchBytes. + * + * Description :This function restores the mode that was saved on server + * + * Parameters. + * pScrni :Handle to ScreenPtr structure. + * Pmode :Points to screenmode + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static int +GXCalculatePitchBytes(unsigned int width, unsigned int bpp) +{ + int lineDelta = width * (bpp >> 3); + + if (width < 640) { + /* low resolutions have both pixel and line doubling */ + DEBUGMSG(1, (0, X_PROBED, "lower resolution %d %d\n", + width, lineDelta)); + lineDelta <<= 1; + } + /* needed in Rotate mode when in accel is turned off */ + if (1) { /*!pGeode->NoAccel */ + if (lineDelta > 4096) + lineDelta = 8192; + else if (lineDelta > 2048) + lineDelta = 4096; + else if (lineDelta > 1024) + lineDelta = 2048; + else + lineDelta = 1024; + } + + DEBUGMSG(1, (0, X_PROBED, "pitch %d %d\n", width, lineDelta)); + + return lineDelta; +} + +/*---------------------------------------------------------------------------- + * GXGetRefreshRate. + * + * Description :This function restores the mode that saved on server + * + * Parameters. + * Pmode :Pointer to the screen modes + * + * Returns :It returns the selected refresh rate. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static int +GXGetRefreshRate(DisplayModePtr pMode) +{ +#define THRESHOLD 2 + unsigned int i; + static int validRates[] = { 56, 60, 70, 72, 75, 85, 90, 100 }; /* Hz */ + unsigned long dotClock; + int refreshRate; + int selectedRate; + + dotClock = pMode->SynthClock * 1000; + refreshRate = dotClock / pMode->CrtcHTotal / pMode->CrtcVTotal; + + if ((pMode->CrtcHTotal < 640) && (pMode->CrtcVTotal < 480)) + refreshRate >>= 2; /* double pixel and double scan */ + + DEBUGMSG(1, (0, X_PROBED, "dotclock %lu %d\n", dotClock, refreshRate)); + + selectedRate = validRates[0]; + + for (i = 0; i < (sizeof(validRates) / sizeof(validRates[0])); i++) { + if (validRates[i] < (refreshRate + THRESHOLD)) { + selectedRate = validRates[i]; + } + } + return selectedRate; +} + +void +gx_clear_screen(ScrnInfoPtr pScrni, int width, int height, int bpp) +{ + /* no accels, mode is not yet set */ + GeodePtr pGeode = GEODEPTR(pScrni); + unsigned long offset = gfx_get_display_offset(); + unsigned long pitch = gfx_get_display_pitch(); + unsigned long n = width * ((bpp+7)>>3); + DEBUGMSG(1, (0, X_PROBED, "clear screen %lx %d %d %d %ld %ld\n", offset,width,height,bpp,pitch,n)); + while( height > 0 ) { + memset(pGeode->FBBase+offset,0,n); + offset += pitch; + --height; + } +} + +void +gx_clear_fb(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + unsigned char *fb = pGeode->FBBase+pGeode->FBOffset; + memset(fb,0,pGeode->FBSize); + if( pGeode->ShadowPtr != NULL && pGeode->ShadowPtr != fb ) + memset(pGeode->ShadowPtr,0,pGeode->ShadowSize); +} + +void +gx_set_DvLineSize(unsigned int pitch) +{ + unsigned long temp, dv_size = MDC_DV_LINE_SIZE_1024; + + if (pitch > 1024) { + dv_size = MDC_DV_LINE_SIZE_2048; + } + if (pitch > 2048) { + dv_size = MDC_DV_LINE_SIZE_4096; + } + if (pitch > 4096) { + dv_size = MDC_DV_LINE_SIZE_8192; + } + + /* WRITE DIRTY/VALID CONTROL WITH LINE LENGTH */ + + temp = READ_REG32(MDC_DV_CTL); + WRITE_REG32(MDC_DV_CTL, (temp & ~MDC_DV_LINE_SIZE_MASK) | dv_size); +} + +/*---------------------------------------------------------------------------- + * GXSetMode. + * + * Description :This function sets parametrs for screen mode + * + * Parameters. + * pScrni :Pointer to the screenInfo structure. + * Pmode :Pointer to the screen modes + * + * Returns :TRUE on success and FALSE on Failure. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ + +static Bool +GXSetMode(ScrnInfoPtr pScrni, DisplayModePtr pMode) +{ + int flags; + static char *quals[4] = { + " +hsync +vsync", " -hsync +vsync", " +hsync -vsync", " -hsync -vsync" + }; + GeodePtr pGeode = GEODEPTR(pScrni); + gfx_wait_until_idle(); + /* disable video */ + gx_disable_dac_power(pScrni); + + /* unsigned int compOffset, compPitch, compSize; */ + DEBUGMSG(1, (0, X_INFO, "GXSetMode %p %p %p %p %p\n", + gfx_virt_regptr, gfx_virt_gpptr, + gfx_virt_spptr, gfx_virt_vidptr, gfx_virt_fbptr)); + + /* Set the VT semaphore */ + pScrni->vtSema = TRUE; + + /* The timing will be adjusted later */ + flags = 0; + if( (pMode->Flags & V_NHSYNC) != 0 ) flags |= 1; + if( (pMode->Flags & V_NVSYNC) != 0 ) flags |= 2; + DEBUGMSG(1, (0, X_PROBED, + "Setting mode %dx%d %0.3f %d %d %d %d %d %d %d %d%s\n", + pMode->CrtcHDisplay, pMode->CrtcVDisplay, pMode->SynthClock/1000.0, + pMode->CrtcHDisplay, pMode->CrtcHSyncStart, pMode->CrtcHSyncEnd, pMode->CrtcHTotal, + pMode->CrtcVDisplay, pMode->CrtcVSyncStart, pMode->CrtcVSyncEnd, pMode->CrtcVTotal, + quals[flags])); + DEBUGMSG(1,(0, X_INFO, "Set display mode: %dHz Pitch %d\n", + GXGetRefreshRate(pMode), pGeode->Pitch)); + + if (1) { + { /* TV not selected */ + DEBUGMSG(1, (0, X_PROBED, "Setting Display for CRT or TFT\n")); + if( pGeode->CustomMode != 0 ) { + DEBUGMSG(1, (0, X_PROBED, "Setting Custom mode\n")); + GFX(set_display_timings(pScrni->bitsPerPixel, flags, + pMode->CrtcHDisplay, pMode->CrtcHBlankStart, pMode->CrtcHSyncStart, + pMode->CrtcHSyncEnd, pMode->CrtcHBlankEnd, pMode->CrtcHTotal, + pMode->CrtcVDisplay, pMode->CrtcVBlankStart, pMode->CrtcVSyncStart, + pMode->CrtcVSyncEnd, pMode->CrtcVBlankEnd, pMode->CrtcVTotal, + (int)((pMode->SynthClock/1000.0)*0x10000))); + } + else if( pGeode->Panel != 0 ) { + DEBUGMSG(0, (0, X_PROBED, "Setting Display for TFT\n")); + DEBUGMSG(1, (0, X_PROBED, "Restore Panel %d %d %d %d %d\n", + pGeode->FPBX, pGeode->FPBY, + pMode->CrtcHDisplay, + pMode->CrtcVDisplay, pScrni->bitsPerPixel)); + + DEBUGMSG(1, (pScrni->scrnIndex, X_CONFIG, "FP Bios %d\n", + pGeode->Panel)); + GFX(set_fixed_timings(pGeode->FPBX, pGeode->FPBY, + pMode->CrtcHDisplay, + pMode->CrtcVDisplay, + pScrni->bitsPerPixel)); + } else { + /* display is crt */ + DEBUGMSG(1, (0, X_PROBED, "Setting Display for CRT %dx%d-%d@%d\n", + pMode->CrtcHDisplay, + pMode->CrtcVDisplay, + pScrni->bitsPerPixel, + GXGetRefreshRate(pMode))); + GFX(set_display_mode(pMode->CrtcHDisplay, + pMode->CrtcVDisplay, + pScrni->bitsPerPixel, + GXGetRefreshRate(pMode))); + + /* adjust the pitch */ + } + /* enable crt */ + GFX(set_crt_enable(CRT_ENABLE)); + } + GFX(set_display_pitch(pGeode->Pitch)); + GFX(set_display_offset(0L)); + GFX(wait_vertical_blank()); + + DEBUGMSG(1, (0, X_PROBED, "Display mode set\n")); + /* enable compression if option selected */ + if (pGeode->Compression) { + DEBUGMSG(1, (0, X_PROBED, "Compression mode set %d\n", + pGeode->Compression)); + /* set the compression parameters,and it will be turned on later. */ + gx_set_DvLineSize(pGeode->Pitch); + + gfx_set_compression_offset(pGeode->CBOffset); + gfx_set_compression_pitch(pGeode->CBPitch); + gfx_set_compression_size(pGeode->CBSize); + + /* set the compression buffer, all parameters already set */ + gfx_set_compression_enable(1); + } + if (pGeode->HWCursor) { + /* Load blank cursor */ + GXLoadCursorImage(pScrni, NULL); + GFX(set_cursor_position(pGeode->CursorStartOffset, 0, 0, 0, 0)); + GFX(set_cursor_enable(1)); + } + } else { + DEBUGMSG(1,(0, X_INFO, "GXRestore ... ")); + GXRestore(pScrni); + DEBUGMSG(1,(0, X_INFO, "done.\n")); + } + + DEBUGMSG(1,(0, X_INFO, "done.\n")); + /* Reenable the hardware cursor after the mode switch */ + if (pGeode->HWCursor == TRUE) { + DEBUGMSG(1,(0, X_INFO, "GXShowCursor ... ")); + GXShowCursor(pScrni); + DEBUGMSG(1,(0, X_INFO, "done.\n")); + } + if (!pGeode->Panel) + GFX(set_display_offset(pGeode->PrevDisplayOffset)); + /* Restore the contents in the screen info */ + DEBUGMSG(1,(0, X_INFO, "After setting the mode\n")); + switch( pGeode->Rotate ) { + case 1: + case 3: + pGeode->HDisplay = pMode->VDisplay; + pGeode->VDisplay = pMode->HDisplay; + break; + default: + pGeode->HDisplay = pMode->HDisplay; + pGeode->VDisplay = pMode->VDisplay; + break; + } + gx_enable_dac_power(pScrni); + return TRUE; +} + +/*---------------------------------------------------------------------------- + * GXEnterGraphics. + * + * Description :This function will intiallize the displaytiming + structure for nextmode and switch to VGA mode. + * + * Parameters. + * pScrn :Screen information will be stored in this structure. + * pScrni :Pointer to the screenInfo structure. + * + * Returns :TRUE on success and FALSE on Failure. + * + * Comments :gfx_vga_mode_switch() will start and end the + * switching based on the arguments 0 or 1.soft_vga + * is disabled in this function. +*---------------------------------------------------------------------------- +*/ +static Bool +GXEnterGraphics(ScreenPtr pScrn, ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + vgaHWPtr pvgaHW = VGAHWPTR(pScrni); + + gfx_wait_until_idle(); + + /* Save CRT State */ + pGeode->FBgfxdisplaytiming.dwDotClock = gfx_get_clock_frequency(); + pGeode->FBgfxdisplaytiming.wPitch = gfx_get_display_pitch(); + pGeode->FBgfxdisplaytiming.wBpp = gfx_get_display_bpp(); + pGeode->FBgfxdisplaytiming.wHTotal = gfx_get_htotal(); + pGeode->FBgfxdisplaytiming.wHActive = gfx_get_hactive(); + pGeode->FBgfxdisplaytiming.wHSyncStart = gfx_get_hsync_start(); + pGeode->FBgfxdisplaytiming.wHSyncEnd = gfx_get_hsync_end(); + pGeode->FBgfxdisplaytiming.wHBlankStart = gfx_get_hblank_start(); + pGeode->FBgfxdisplaytiming.wHBlankEnd = gfx_get_hblank_end(); + pGeode->FBgfxdisplaytiming.wVTotal = gfx_get_vtotal(); + pGeode->FBgfxdisplaytiming.wVActive = gfx_get_vactive(); + pGeode->FBgfxdisplaytiming.wVSyncStart = gfx_get_vsync_start(); + pGeode->FBgfxdisplaytiming.wVSyncEnd = gfx_get_vsync_end(); + pGeode->FBgfxdisplaytiming.wVBlankStart = gfx_get_vblank_start(); + pGeode->FBgfxdisplaytiming.wVBlankEnd = gfx_get_vblank_end(); + pGeode->FBgfxdisplaytiming.wPolarity = gfx_get_sync_polarities(); + + /* Save Display offset */ + pGeode->FBDisplayOffset = gfx_get_display_offset(); + pGeode->FBBIOSMode = pvgaHW->readCrtc(pvgaHW, 0x040); + DEBUGMSG(1,(0, X_INFO, "FBBIOSMode %d\n", pGeode->FBBIOSMode)); + + /* Save the current Compression state */ + pGeode->FBCompressionEnable = gfx_get_compression_enable(); + pGeode->FBCompressionOffset = gfx_get_compression_offset(); + pGeode->FBCompressionPitch = gfx_get_compression_pitch(); + pGeode->FBCompressionSize = gfx_get_compression_size(); + + /* Save Cursor offset */ + pGeode->FBCursorOffset = gfx_get_cursor_offset(); + +#if defined(PNL_SUP) + /* Save the Panel state */ + Pnl_SavePanelState(); +#endif + + /* only if comming from VGA */ + if (pGeode->FBVGAActive) { + unsigned short sequencer; + vgaHWPtr pvgaHW = VGAHWPTR(pScrni); + + /* Map VGA aperture */ + if (!vgaHWMapMem(pScrni)) + return FALSE; + + /* Unlock VGA registers */ + vgaHWUnlock(pvgaHW); + + /* Save the current state and setup the current mode */ + vgaHWSave(pScrni, &VGAHWPTR(pScrni)->SavedReg, VGA_SR_ALL); + + /* DISABLE VGA SEQUENCER */ + /* This allows the VGA state machine to terminate. We must delay */ + /* such that there are no pending MBUS requests. */ + + gfx_outb(MDC_SEQUENCER_INDEX, MDC_SEQUENCER_CLK_MODE); + sequencer = gfx_inb(MDC_SEQUENCER_DATA); + sequencer |= MDC_CLK_MODE_SCREEN_OFF; + gfx_outb(MDC_SEQUENCER_DATA, sequencer); + + gfx_delay_milliseconds(1); + + /* BLANK THE VGA DISPLAY */ + gfx_outw(MDC_SEQUENCER_INDEX, MDC_SEQUENCER_RESET); + sequencer = gfx_inb(MDC_SEQUENCER_DATA); + sequencer &= ~MDC_RESET_VGA_DISP_ENABLE; + gfx_outb(MDC_SEQUENCER_DATA, sequencer); + + gfx_delay_milliseconds(1); + } + + gx_clear_fb(pScrni); + + if (!GXSetMode(pScrni, pScrni->currentMode)) { + return FALSE; + } + + gx_enable_dac_power(pScrni); + return TRUE; +} + +void +gx_enable_dac_power(ScrnInfoPtr pScrni) +{ + /* enable the DAC POWER */ + gfx_write_vid32(RCDF_VID_MISC, + gfx_read_vid32(RCDF_VID_MISC) & RCDF_GAMMA_BYPASS_BOTH); +} + +void +gx_disable_dac_power(ScrnInfoPtr pScrni) +{ + /* disable the DAC POWER */ + gfx_write_vid32(RCDF_VID_MISC, RCDF_DAC_POWER_DOWN | RCDF_ANALOG_POWER_DOWN | + ( gfx_read_vid32(RCDF_VID_MISC) & RCDF_GAMMA_BYPASS_BOTH) ); +} + +/*---------------------------------------------------------------------------- + * GXLeaveGraphics: + * + * Description :This function will restore the displaymode parameters + * and switches the VGA mode + * + * Parameters. + * pScrn :Screen information will be stored in this structure. + * pScrni :Pointer to the screenInfo structure. + * + * + * Returns :none. + * + * Comments : gfx_vga_mode_switch() will start and end the switching + * based on the arguments 0 or 1.soft_vga is disabled in + * this function. +*---------------------------------------------------------------------------- +*/ +static void +GXLeaveGraphics(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + gfx_wait_until_idle(); + + /* Restore VG registers */ + gfx_set_display_timings(pGeode->FBgfxdisplaytiming.wBpp, + pGeode->FBgfxdisplaytiming.wPolarity, + pGeode->FBgfxdisplaytiming.wHActive, + pGeode->FBgfxdisplaytiming.wHBlankStart, + pGeode->FBgfxdisplaytiming.wHSyncStart, + pGeode->FBgfxdisplaytiming.wHSyncEnd, + pGeode->FBgfxdisplaytiming.wHBlankEnd, + pGeode->FBgfxdisplaytiming.wHTotal, + pGeode->FBgfxdisplaytiming.wVActive, + pGeode->FBgfxdisplaytiming.wVBlankStart, + pGeode->FBgfxdisplaytiming.wVSyncStart, + pGeode->FBgfxdisplaytiming.wVSyncEnd, + pGeode->FBgfxdisplaytiming.wVBlankEnd, + pGeode->FBgfxdisplaytiming.wVTotal, + pGeode->FBgfxdisplaytiming.dwDotClock); + + gfx_set_compression_enable(0); + + /* Restore the previous Compression state */ + if (pGeode->FBCompressionEnable) { + gfx_set_compression_offset(pGeode->FBCompressionOffset); + gfx_set_compression_pitch(pGeode->FBCompressionPitch); + gfx_set_compression_size(pGeode->FBCompressionSize); + gfx_set_compression_enable(1); + } + + gfx_set_display_pitch(pGeode->FBgfxdisplaytiming.wPitch); + + gfx_set_display_offset(pGeode->FBDisplayOffset); + + /* Restore Cursor */ + gfx_set_cursor_position(pGeode->FBCursorOffset, 0, 0, 0, 0); + + DEBUGMSG(1,(0, X_INFO, "FBVGAActive %d\n", pGeode->FBVGAActive)); + + /* For the moment, always do an int 10 */ + + pGeode->vesa->pInt->num = 0x10; + pGeode->vesa->pInt->ax = 0x0 | pGeode->FBBIOSMode; + pGeode->vesa->pInt->bx = 0; + xf86ExecX86int10(pGeode->vesa->pInt); + gfx_delay_milliseconds(3); + GXRestore(pScrni); + + gx_enable_dac_power(pScrni); +} + +/*---------------------------------------------------------------------------- + * GXCloseScreen. + * + * Description :This function will restore the original mode + * and also it unmap video memory + * + * Parameters. + * ScrnIndex :Screen index value of the screen will be closed. + * pScrn :Pointer to the screen structure. + * + * + * Returns :TRUE on success and FALSE on Failure. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static Bool +GXCloseScreen(int scrnIndex, ScreenPtr pScrn) +{ + ScrnInfoPtr pScrni = xf86Screens[scrnIndex]; + GeodePtr pGeode = GEODEPTR(pScrni); + + if (pGeode->ShadowPtr) + xfree(pGeode->ShadowPtr); + + DEBUGMSG(0, (scrnIndex, X_PROBED, "GXCloseScreen %d\n", + pScrni->vtSema)); + if (pScrni->vtSema) + GXLeaveGraphics(pScrni); + + if (pGeode->AccelInfoRec) + XAADestroyInfoRec(pGeode->AccelInfoRec); + + if (pGeode->AccelImageWriteBuffers) { +#if GX_USE_OFFSCRN_MEM + xfree(pGeode->AccelImageWriteBuffers[0]); +#endif + xfree(pGeode->AccelImageWriteBuffers); + pGeode->AccelImageWriteBuffers = NULL; + } + if (pGeode->AccelColorExpandBuffers) { + xfree(pGeode->AccelColorExpandBuffers); + pGeode->AccelColorExpandBuffers = NULL; + } + pScrni->vtSema = FALSE; + + GXUnmapMem(pScrni); + + if (pGeode && (pScrn->CloseScreen = pGeode->CloseScreen)) { + pGeode->CloseScreen = NULL; + return ((*pScrn->CloseScreen) (scrnIndex, pScrn)); + } + return TRUE; +} + +#ifdef DPMSExtension +static void +GXPanelPower(int enable) +{ + unsigned long power = READ_VID32 (RCDF_POWER_MANAGEMENT); + if( enable != 0 ) + power |= RCDF_PM_PANEL_POWER_ON; + else + power &= ~RCDF_PM_PANEL_POWER_ON; + WRITE_VID32 (RCDF_POWER_MANAGEMENT, power); +} + +/*---------------------------------------------------------------------------- + * GXDPMSSet. + * + * Description :This function sets geode into Power Management + * Signalling mode. + * + * Parameters. + * pScrni :Pointer to screen info strucrure. + * mode :Specifies the power management mode. + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static void +GXDPMSSet(ScrnInfoPtr pScrni, int mode, int flags) +{ + GeodePtr pGeode; + + pGeode = GEODEPTR(pScrni); + + DEBUGMSG(1,(0, X_INFO, "GXDPMSSet! %d %d\n",mode,flags)); + + /* Check if we are actively controlling the display */ + if (!pScrni->vtSema) { + ErrorF("GXDPMSSet called when we not controlling the VT!\n"); + return; + } + switch (mode) { + case DPMSModeOn: + /* Screen: On; HSync: On; VSync: On */ + GFX(set_crt_enable(CRT_ENABLE)); +#if defined(PNL_SUP) + if (pGeode->Panel) { + Pnl_PowerUp(); + GXPanelPower(1); + } +#endif + break; + + case DPMSModeStandby: + /* Screen: Off; HSync: Off; VSync: On */ + GFX(set_crt_enable(CRT_STANDBY)); +#if defined(PNL_SUP) + if (pGeode->Panel) { + Pnl_PowerDown(); + GXPanelPower(0); + } +#endif + break; + + case DPMSModeSuspend: + /* Screen: Off; HSync: On; VSync: Off */ + GFX(set_crt_enable(CRT_SUSPEND)); +#if defined(PNL_SUP) + if (pGeode->Panel) { + Pnl_PowerDown(); + GXPanelPower(0); + } +#endif + break; + case DPMSModeOff: + /* Screen: Off; HSync: Off; VSync: Off */ + GFX(set_crt_enable(CRT_DISABLE)); +#if defined(PNL_SUP) + if (pGeode->Panel) { + Pnl_PowerDown(); + GXPanelPower(0); + } +#endif + break; + } +} +#endif + +/*---------------------------------------------------------------------------- + * GXScreenInit. + * + * Description :This function will be called at the each ofserver + * generation. + * + * Parameters. + * scrnIndex :Specfies the screenindex value during generation. + * pScrn :Pointer to screen info strucrure. + * argc :parameters for command line arguments count + * argv :command line arguments if any it is not used. + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static Bool +GXScreenInit(int scrnIndex, ScreenPtr pScrn, int argc, char **argv) +{ + int i, l, bytpp, size, fbsize, fboffset, fbavail; + int pitch, displayWidth, virtualX, virtualY; + int HDisplay, VDisplay, maxHDisplay, maxVDisplay, maxX, maxY; + unsigned char *FBStart; + unsigned char **ap, *bp; + DisplayModePtr p; + GeodePtr pGeode; + VisualPtr visual; + BoxRec AvailBox; + RegionRec OffscreenRegion; + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + Bool Inited = FALSE; + + DEBUGMSG(1,(0, X_INFO, "GXScreenInit!\n")); + /* Get driver private */ + pGeode = GXGetRec(pScrni); + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(0)!\n")); + /* + * * Allocate a vgaHWRec + */ + + if (!vgaHWGetHWRec(pScrni)) + return FALSE; + if (!vgaHWMapMem(pScrni)) + return FALSE; + + vgaHWGetIOBase(VGAHWPTR(pScrni)); + + if (!GXMapMem(pScrni)) + return FALSE; + + pGeode->Pitch = GXCalculatePitchBytes(pScrni->virtualX, + pScrni->bitsPerPixel); + pGeode->AccelPitch = pGeode->Pitch; + bytpp = (pScrni->bitsPerPixel+7)/8; + + /* start of framebuffer for accels */ + fboffset = 0; + /* 0x4000 for gfx_gu2_scratch_buffer */ + fbavail = pGeode->FBAvail - 0x4000; + +#ifdef V4L2_VIDEO_BFR_SZ + fbavail -= V4L2_VIDEO_BFR_SZ; +#endif + + + /* allocate display frame buffer at zero offset */ + fbsize = pScrni->virtualY * pGeode->Pitch; + pGeode->FBSize = fbsize; + + pGeode->CursorSize = 16 * 64; /* 64x64 */ + pGeode->CursorStartOffset = 0; + + DEBUGMSG(1, (scrnIndex, X_PROBED,"%d %d %d\n", + pScrni->virtualX, pScrni->bitsPerPixel, pGeode->Pitch)); + + HDisplay = pScrni->currentMode->HDisplay; + VDisplay = pScrni->currentMode->VDisplay; + pGeode->orig_virtX = pScrni->virtualX; + pGeode->orig_virtY = pScrni->virtualY; + + p = pScrni->modes; + maxHDisplay = p->HDisplay; + maxVDisplay = p->VDisplay; + while( (p=p->next)!=pScrni->modes ) { + if( maxHDisplay < p->HDisplay ) maxHDisplay = p->HDisplay; + if( maxVDisplay < p->VDisplay ) maxVDisplay = p->VDisplay; + } + DEBUGMSG(1, (scrnIndex, X_PROBED,"maxHDisplay %d maxVDisplay %d\n",maxHDisplay,maxVDisplay)); + + switch( pGeode->Rotate ) { + case 1: + case 3: + pGeode->HDisplay = VDisplay; + pGeode->VDisplay = HDisplay; + virtualX = pScrni->virtualY; + virtualY = pScrni->virtualX; + maxX = maxVDisplay; + maxY = maxHDisplay; + break; + default: + pGeode->HDisplay = HDisplay; + pGeode->VDisplay = VDisplay; + virtualX = pScrni->virtualX; + virtualY = pScrni->virtualY; + maxX = maxHDisplay; + maxY = maxVDisplay; + break; + } + + /* shadow may be first in FB, since accels render there */ + + pGeode->ShadowPtr = NULL; + if( pGeode->ShadowFB ) { + if( !pGeode->PointerMoved ) { + pGeode->PointerMoved = pScrni->PointerMoved; + pScrni->PointerMoved = GXPointerMoved; + } + if( pGeode->ShadowPtr == NULL ) { + pGeode->ShadowPitch = BitmapBytePad(pScrni->bitsPerPixel*virtualX); + size = pGeode->ShadowPitch * virtualY; + pGeode->ShadowPtr = xalloc(size); + if( pGeode->ShadowPtr != NULL ) { + pGeode->ShadowSize = size; + if( !pGeode->NoAccel ) { + pGeode->NoAccel = TRUE; + pGeode->HWCursor = FALSE; + xf86DrvMsg(scrnIndex, X_ERROR, "Shadow FB offscreen, All Accels disabled\n"); + } + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Shadow FB, No offscreen Memory, disabled\n"); + pGeode->ShadowFB = FALSE; + pGeode->Rotate = 0; + pGeode->HDisplay = HDisplay; + pGeode->VDisplay = VDisplay; + virtualX = pScrni->virtualX; + virtualY = pScrni->virtualY; + } + } + } + + if( pGeode->ShadowPtr != NULL ) { + displayWidth = pGeode->ShadowPitch / bytpp; + FBStart = pGeode->ShadowPtr; + DEBUGMSG(1, (0, X_PROBED, "Shadow %p \n", FBStart)); + } + else { + displayWidth = pGeode->Pitch / bytpp; + FBStart = pGeode->FBBase; + DEBUGMSG(1, (0, X_PROBED, "FBStart %p \n", FBStart)); + } + + DEBUGMSG(1, (0, X_PROBED, "FB display %X size %X \n",fboffset,fbsize)); + pGeode->FBOffset = fboffset; /* offset of display framebuffer */ + pScrni->fbOffset = fboffset; + fboffset += fbsize; + fbavail -= fbsize; + + if( pGeode->Compression ) { /* Compression enabled */ + pGeode->CBPitch = 512+32; + pGeode->CBSize = 512+32; + size = maxY*pGeode->CBPitch; + DEBUGMSG(1, (0, X_PROBED, "CB %#x size %#x (%d*%d)\n",fboffset,size,maxY,pGeode->CBPitch)); + if( size <= fbavail ) { + pGeode->CBOffset = fboffset; + fboffset += size; + fbavail -= size; + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Compression, No FB Memory, disabled\n"); + pGeode->Compression = FALSE; + } + } + + if( pGeode->HWCursor ) { /* HWCursor enabled */ + size = pGeode->CursorSize; + if( size <= fbavail ) { + pGeode->CursorStartOffset = fboffset; + fboffset += size; + fbavail -= size; + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "HWCursor, No FB Memory, disabled\n"); + pGeode->HWCursor = FALSE; + } + } + + if( !pGeode->NoAccel ) { /* Acceleration enabled */ + if( pGeode->NoOfImgBuffers > 0 ) { + pGeode->AccelImageWriteBuffers = NULL; + pitch = pGeode->AccelPitch; + size = pitch * pGeode->NoOfImgBuffers; +#if !GX_USE_OFFSCRN_MEM + if( size <= fbavail ) { + bp = (unsigned char *)pGeode->FBBase + fboffset; + l = sizeof(pGeode->AccelImageWriteBuffers[0]) * pGeode->NoOfImgBuffers; + ap = (unsigned char **)xalloc(l); + if( ap != NULL ) { + for( i=0; iNoOfImgBuffers; ++i ) { + ap[i] = bp; + DEBUGMSG(1, (scrnIndex, X_PROBED, "img line %d %p\n", i, ap[i])); + bp += pitch; + } + pGeode->AccelImageWriteBuffers = ap; + fboffset += size; + fbavail -= size; + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Image Write, No Memory\n"); + } + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Image Write, No FB Memory\n"); + } +#else + if( (bp=(unsigned char *)xalloc(size)) != NULL ) { + ap = xalloc(sizeof(pGeode->AccelImageWriteBuffers[0]) * pGeode->NoOfImgBuffers); + if( ap != NULL ) { + for( i=0; iNoOfImgBuffers; ++i ) { + ap[i] = bp; + DEBUGMSG(1, (scrnIndex, X_PROBED, "img line %d %x\n", i, ap[i])); + bp += pitch; + } + pGeode->AccelImageWriteBuffers = ap; + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Image Write, No Memory\n"); + } + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Image Write, No offscreen Memory\n"); + } +#endif + if( pGeode->AccelImageWriteBuffers == NULL ) { + xf86DrvMsg(scrnIndex, X_ERROR, "Accel Image Write disabled\n"); + pGeode->NoOfImgBuffers = 0; + } + } + + if (pGeode->NoOfColorExpandLines > 0) { + pGeode->AccelColorExpandBuffers = NULL; + pitch = ((pGeode->AccelPitch+31) >> 5) << 2; + size = pitch * pGeode->NoOfColorExpandLines; + if( size <= fbavail ) { + bp = (unsigned char *)pGeode->FBBase + fboffset; + l = sizeof(pGeode->AccelColorExpandBuffers[0]) * pGeode->NoOfColorExpandLines; + ap = (unsigned char **)xalloc(l); + if( ap != NULL ) { + for( i=0; iNoOfColorExpandLines; ++i ) { + ap[i] = bp; + DEBUGMSG(1, (scrnIndex, X_PROBED, "clr line %d %p\n", i, ap[i])); + bp += pitch; + } + pGeode->AccelColorExpandBuffers = ap; + fboffset += size; + fbavail -= size; + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Color Expansion, No Memory\n"); + } + } + else { + xf86DrvMsg(scrnIndex, X_ERROR, "Color Expansion, No offscreen Memory\n"); + } + if( pGeode->AccelColorExpandBuffers == NULL ) { + xf86DrvMsg(scrnIndex, X_ERROR, "Accel Color Expansion disabled\n"); + pGeode->NoOfColorExpandLines = 0; + } + } + } + else { + pGeode->NoOfImgBuffers = 0; + pGeode->AccelImageWriteBuffers = NULL; + pGeode->NoOfColorExpandLines = 0; + pGeode->AccelColorExpandBuffers = NULL; + } + + /* Initialise graphics mode */ + if (!GXEnterGraphics(pScrn, pScrni)) + return FALSE; + + pScrni->virtualX = virtualX; + pScrni->virtualY = virtualY; + + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(1)!\n")); + + /* Reset visual list */ + miClearVisualTypes(); + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(2)!\n")); + + /* Setup the visual we support */ + if (pScrni->bitsPerPixel > 8) { + DEBUGMSG(1, (scrnIndex, X_PROBED, + "miSetVisualTypes %d %X %X %X\n", + pScrni->depth, + TrueColorMask, + pScrni->rgbBits, pScrni->defaultVisual)); + + if (!miSetVisualTypes(pScrni->depth, + TrueColorMask, + pScrni->rgbBits, + pScrni->defaultVisual)) { + return FALSE; + } + } else { + if (!miSetVisualTypes(pScrni->depth, + miGetDefaultVisualMask(pScrni->depth), + pScrni->rgbBits, + pScrni->defaultVisual)) { + return FALSE; + } + } + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(3)!\n")); + + /* Set for RENDER extensions */ + miSetPixmapDepths(); + + /* Call the framebuffer layer's ScreenInit function, and fill in other + * * pScrn fields. + */ + switch (pScrni->bitsPerPixel) { +#if CFB + case 8: + Inited = cfbScreenInit(pScrn, FBStart, virtualX, virtualY, + pScrni->xDpi, pScrni->yDpi, + displayWidth); + break; + case 16: + Inited = cfb16ScreenInit(pScrn, FBStart, virtualX, virtualY, + pScrni->xDpi, pScrni->yDpi, + displayWidth); + break; + case 24: + case 32: + Inited = cfb32ScreenInit(pScrn, FBStart, virtualX, virtualY, + pScrni->xDpi, pScrni->yDpi, + displayWidth); + break; +#else + case 8: + case 16: + case 24: + case 32: + Inited = fbScreenInit(pScrn, FBStart, virtualX, virtualY, + pScrni->xDpi, pScrni->yDpi, + displayWidth, pScrni->bitsPerPixel); + break; +#endif + default: + xf86DrvMsg(scrnIndex, X_ERROR, + "Internal error: invalid bpp (%d) in ScreenInit\n", + pScrni->bitsPerPixel); + Inited = FALSE; + break; + } + if (!Inited) + return FALSE; + + GXRotationInit(pScrni); + GXAdjustFrame(scrnIndex, pScrni->frameX0, pScrni->frameY0, 0); + + /* SET UP GRAPHICS MEMORY AVAILABLE FOR PIXMAP CACHE */ + AvailBox.x1 = 0; + AvailBox.y1 = (fboffset + pGeode->AccelPitch-1) / pGeode->AccelPitch; + AvailBox.x2 = displayWidth; + AvailBox.y2 = (fboffset + fbavail) / pGeode->AccelPitch; + + DEBUGMSG(1, (scrnIndex, X_PROBED, + "Memory manager initialized to (%d,%d) (%d,%d)\n", + AvailBox.x1, AvailBox.y1, AvailBox.x2, AvailBox.y2)); + + if( AvailBox.y1 < AvailBox.y2 ) { + xf86DrvMsg(scrnIndex, X_INFO, + "Initializing Memory manager to (%d,%d) (%d,%d)\n", + AvailBox.x1, AvailBox.y1, AvailBox.x2, AvailBox.y2); + REGION_INIT(pScrn, &OffscreenRegion, &AvailBox, 2); + if( !xf86InitFBManagerRegion(pScrn, &OffscreenRegion) ) { + xf86DrvMsg(scrnIndex, X_ERROR, + "Memory manager initialization failed, Cache Diabled\n"); + } + REGION_UNINIT(pScrn, &OffscreenRegion); + } + else { + xf86DrvMsg(scrnIndex, X_INFO, + "No Off Screen Memory, Cache Disabled (%d,%d) (%d,%d)\n", + AvailBox.x1, AvailBox.y1, AvailBox.x2, AvailBox.y2); + } + + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(4)!\n")); + xf86SetBlackWhitePixels(pScrn); + + if (!pGeode->ShadowFB) { + GXDGAInit(pScrn); + } + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(5)!\n")); + if (pScrni->bitsPerPixel > 8) { + /* Fixup RGB ordering */ + visual = pScrn->visuals + pScrn->numVisuals; + while (--visual >= pScrn->visuals) { + if ((visual->class | DynamicClass) == DirectColor) { + visual->offsetRed = pScrni->offset.red; + visual->offsetGreen = pScrni->offset.green; + visual->offsetBlue = pScrni->offset.blue; + visual->redMask = pScrni->mask.red; + visual->greenMask = pScrni->mask.green; + visual->blueMask = pScrni->mask.blue; + } + } + } +#if CFB +#else + /* must be after RGB ordering fixed */ + fbPictureInit(pScrn, 0, 0); +#endif + + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(6)!\n")); + if (!pGeode->NoAccel) { + GXAccelInit(pScrn); + } + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(7)!\n")); + miInitializeBackingStore(pScrn); + xf86SetBackingStore(pScrn); + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(8)!\n")); + /* Initialise software cursor */ + miDCInitialize(pScrn, xf86GetPointerScreenFuncs()); + /* Initialize HW cursor layer. + * * Must follow software cursor initialization + */ + if (pGeode->HWCursor) { + if (!GXHWCursorInit(pScrn)) + xf86DrvMsg(pScrni->scrnIndex, X_ERROR, + "Hardware cursor initialization failed\n"); + } + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(9)!\n")); + /* Setup default colourmap */ + if (!miCreateDefColormap(pScrn)) { + return FALSE; + } + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(10)!\n")); + if( pScrni->bitsPerPixel == 8 ) { + /* Initialize colormap layer. + * * Must follow initialization of the default colormap + */ + if (!xf86HandleColormaps(pScrn, 256, 8, + GXLoadPalette, NULL, + CMAP_PALETTED_TRUECOLOR | + CMAP_RELOAD_ON_MODE_SWITCH)) { + return FALSE; + } + } + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(11)!\n")); + + if (pGeode->ShadowFB) { + DEBUGMSG(1,(0, X_INFO, "Shadowed, Rotate=%d, NoAccel=%d\n",pGeode->Rotate,pGeode->NoAccel)); + GXShadowFBInit(pScrn,pGeode,bytpp); + } +#ifdef DPMSExtension + xf86DPMSInit(pScrn, GXDPMSSet, 0); +#endif + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(12)!\n")); + + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(13)!\n")); + GXInitVideo(pScrn); /* needed for video */ + /* Wrap the screen's CloseScreen vector and set its + * SaveScreen vector + */ + pGeode->CloseScreen = pScrn->CloseScreen; + pScrn->CloseScreen = GXCloseScreen; + + pScrn->SaveScreen = GXSaveScreen; + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(14)!\n")); + + /* Report any unused options */ + if (serverGeneration == 1) { + xf86ShowUnusedOptions(pScrni->scrnIndex, pScrni->options); + } + DEBUGMSG(1,(0, X_INFO, "GXScreenInit(15)!\n")); + return TRUE; +} + +/*---------------------------------------------------------------------------- + * GXSwitchMode. + * + * Description :This function will switches the screen mode + * + * Parameters: + * scrnIndex :Specfies the screen index value. + * pMode :pointer to the mode structure. + * flags :may be used for status check?. + * + * Returns :Returns TRUE on success and FALSE on failure. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +Bool +GXSwitchMode(int scrnIndex, DisplayModePtr pMode, int flags) +{ + DEBUGMSG(1,(0, X_INFO, "GXSwitchMode!\n")); + return GXSetMode(xf86Screens[scrnIndex], pMode); +} + +/*---------------------------------------------------------------------------- + * GXAdjustFrame. + * + * Description :This function is used to intiallize the start + * address of the memory. + * Parameters. + * scrnIndex :Specfies the screen index value. + * x :x co-ordinate value interms of pixels. + * y :y co-ordinate value interms of pixels. + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +void +GXAdjustFrame(int scrnIndex, int x, int y, int flags) +{ + ScrnInfoPtr pScrni = xf86Screens[scrnIndex]; + + GeodePtr pGeode = GEODEPTR(pScrni); + int newX, newY; + unsigned long offset; + if( x+pGeode->HDisplay >= pScrni->virtualX ) + x = pScrni->virtualX-pGeode->HDisplay; + if( x < 0 ) x = 0; + if( y+pGeode->VDisplay >= pScrni->virtualY ) + y = pScrni->virtualY-pGeode->VDisplay; + if( y < 0 ) y = 0; + pScrni->frameX0 = x; + pScrni->frameY0 = y; + pScrni->frameX1 = x + pGeode->HDisplay-1; + pScrni->frameY1 = y + pGeode->VDisplay-1; + (*pGeode->Rotation)(x,y,pScrni->virtualX,pScrni->virtualY,&newX,&newY); + (*pGeode->RBltXlat)(newX,newY,pGeode->HDisplay,pGeode->VDisplay,&newX,&newY); + offset = pGeode->FBOffset + newY*pGeode->Pitch + newX*(pScrni->bitsPerPixel>>3); + gfx_set_display_offset(offset); +} + +/*---------------------------------------------------------------------------- + * GXEnterVT. + * + * Description :This is called when VT switching back to the X server + * + * Parameters. + * scrnIndex :Specfies the screen index value. + * flags :Not used inside the function. + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static Bool +GXEnterVT(int scrnIndex, int flags) +{ + DEBUGMSG(1,(0, X_INFO, "GXEnterVT!\n")); + return GXEnterGraphics(NULL, xf86Screens[scrnIndex]); +} + +/*---------------------------------------------------------------------------- + * GXLeaveVT. + * + * Description :This is called when VT switching X server text mode. + * + * Parameters. + * scrnIndex :Specfies the screen index value. + * flags :Not used inside the function. + * + * Returns :none. + * + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static void +GXLeaveVT(int scrnIndex, int flags) +{ + ScrnInfoPtr pScrni = xf86Screens[scrnIndex]; + GeodePtr pGeode = GEODEPTR(pScrni); + + pGeode->PrevDisplayOffset = gfx_get_display_offset(); + DEBUGMSG(1,(0, X_INFO, "GXLeaveVT!\n")); + GXLeaveGraphics(xf86Screens[scrnIndex]); +} + +/*---------------------------------------------------------------------------- + * GXFreeScreen. + * + * Description :This is called to free any persistent data structures. + * + * Parameters. + * scrnIndex :Specfies the screen index value. + * flags :Not used inside the function. + * + * Returns :none. + * + * Comments :This will be called only when screen being deleted.. +*---------------------------------------------------------------------------- +*/ +static void +GXFreeScreen(int scrnIndex, int flags) +{ + DEBUGMSG(1,(0, X_INFO, "GXFreeScreen!\n")); + if (xf86LoaderCheckSymbol("vgaHWFreeHWRec")) + vgaHWFreeHWRec(xf86Screens[scrnIndex]); + GXFreeRec(xf86Screens[scrnIndex]); +} + +/*---------------------------------------------------------------------------- + * GXValidMode. + * + * Description :This function checks if a mode is suitable for selected + * chipset. + * Parameters. + * scrnIndex :Specfies the screen index value. + * pMode :Pointer to the screen mode structure.. + * verbose :not used for implementation. + * flags :not used for implementation + * + * Returns :MODE_OK if the specified mode is supported or + * MODE_NO_INTERLACE. + * Comments :none. +*---------------------------------------------------------------------------- +*/ +static int +GXValidMode(int scrnIndex, DisplayModePtr pMode, Bool Verbose, int flags) +{ + unsigned int total_memory_required; + ScrnInfoPtr pScrni = xf86Screens[scrnIndex]; + int ret = -1; + GeodePtr pGeode = GEODEPTR(pScrni); + + DEBUGMSG(1, (0, X_NONE, "GeodeValidateMode: %dx%d %d %d\n", + pMode->CrtcHDisplay, pMode->CrtcVDisplay, + pScrni->bitsPerPixel, GXGetRefreshRate(pMode))); + if( pGeode->CustomMode == 0 ) { + +#if defined(PNL_SUP) + if( pGeode->Panel != 0 ) { + if( pMode->CrtcHDisplay > pGeode->FPBX || + pMode->CrtcVDisplay > pGeode->FPBY || + gfx_is_panel_mode_supported(pGeode->FPBX,pGeode->FPBY, + pMode->CrtcHDisplay,pMode->CrtcVDisplay, + pScrni->bitsPerPixel) < 0 ) + return MODE_NOMODE; + } +#endif /* PNL_SUP */ + + { + DEBUGMSG(1, (0, X_NONE, "CRT mode\n")); + if (pMode->Flags & V_INTERLACE) + return MODE_NO_INTERLACE; + + ret = gfx_is_display_mode_supported(pMode->CrtcHDisplay, + pMode->CrtcVDisplay, + pScrni->bitsPerPixel, + GXGetRefreshRate(pMode)); + } + if (ret < 0) + return MODE_NOMODE; + } + + total_memory_required = GXCalculatePitchBytes(pMode->CrtcHDisplay, + pScrni->bitsPerPixel) * + pMode->CrtcVDisplay; + + DEBUGMSG(1, (0, X_NONE, "Total Mem %X %lX\n", + total_memory_required, pGeode->FBAvail)); + + if (total_memory_required > pGeode->FBAvail) + return MODE_MEM; + + return MODE_OK; +} + +/*---------------------------------------------------------------------------- + * GXLoadPalette. + * + * Description :This function sets the palette entry used for graphics data + * + * Parameters. + * pScrni:Points the screeninfo structure. + * numColors:Specifies the no of colors it supported. + * indizes :This is used get index value . + * LOCO :to be added. + * pVisual :to be added. + * + * Returns :MODE_OK if the specified mode is supported or + * MODE_NO_INTERLACE. + * Comments :none. +*---------------------------------------------------------------------------- +*/ + +static void +GXLoadPalette(ScrnInfoPtr pScrni, + int numColors, int *indizes, LOCO * colors, VisualPtr pVisual) +{ + int i, index, color; + + for (i = 0; i < numColors; i++) { + index = indizes[i] & 0xFF; + color = (((unsigned long)(colors[index].red & 0xFF)) << 16) | + (((unsigned long)(colors[index].green & 0xFF)) << 8) | + ((unsigned long)(colors[index].blue & 0xFF)); + DEBUGMSG(0, (0, X_NONE, "GXLoadPalette: %d %d %X\n", + numColors, index, color)); + + GFX(set_display_palette_entry(index, color)); + } +} + +static Bool +GXMapMem(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + gfx_virt_regptr = (unsigned char *)xf86MapVidMem(pScrni->scrnIndex, + VIDMEM_MMIO, + (unsigned int) + gfx_get_cpu_register_base + (), pGeode->cpu_reg_size); + + if (pGeode->DetectedChipSet & GX) { + gfx_virt_gpptr = (unsigned char *)xf86MapVidMem(pScrni->scrnIndex, + VIDMEM_MMIO, + (unsigned int) + gfx_get_graphics_register_base + (), + pGeode->gp_reg_size); + } else { + gfx_virt_spptr = gfx_virt_regptr; + } + + gfx_virt_vidptr = (unsigned char *)xf86MapVidMem(pScrni->scrnIndex, + VIDMEM_MMIO, + (unsigned int) + gfx_get_vid_register_base + (), pGeode->vid_reg_size); + + gfx_virt_fbptr = (unsigned char *)xf86MapVidMem(pScrni->scrnIndex, + VIDMEM_FRAMEBUFFER, + pGeode->FBLinearAddr, + pGeode->FBAvail); + + pGeode->FBBase = gfx_virt_fbptr; + + DEBUGMSG(1, (0, X_NONE, "Set mode %p %p %p %p %p\n", + gfx_virt_regptr, + gfx_virt_gpptr, + gfx_virt_spptr, gfx_virt_vidptr, gfx_virt_fbptr)); + + /* CHECK IF REGISTERS WERE MAPPED SUCCESSFULLY */ + if ((!gfx_virt_regptr) || + (!gfx_virt_gpptr) || (!gfx_virt_vidptr) || (!gfx_virt_fbptr)) { + DEBUGMSG(1, (0, X_NONE, "Could not map hardware registers.\n")); + return (FALSE); + } + + /* Map the XpressROM ptr to read what platform are we on */ + XpressROMPtr = (unsigned char *)xf86MapVidMem(pScrni->scrnIndex, + VIDMEM_FRAMEBUFFER, 0xF0000, + 0x10000); + + DEBUGMSG(1, (0, X_NONE, "adapter info %lx %lx %lx %p, %p\n", + pGeode->cpu_version, + pGeode->vid_version, + pGeode->FBAvail, pGeode->FBBase, XpressROMPtr)); + + return TRUE; +} + +/* + * Unmap the framebuffer and MMIO memory. + */ + +static Bool +GXUnmapMem(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + /* unmap all the memory map's */ + xf86UnMapVidMem(pScrni->scrnIndex, + gfx_virt_regptr, pGeode->cpu_reg_size); + if (pGeode->DetectedChipSet & GX) { + xf86UnMapVidMem(pScrni->scrnIndex, + gfx_virt_gpptr, pGeode->gp_reg_size); + } + xf86UnMapVidMem(pScrni->scrnIndex, + gfx_virt_vidptr, pGeode->vid_reg_size); + xf86UnMapVidMem(pScrni->scrnIndex, gfx_virt_fbptr, pGeode->FBAvail); + xf86UnMapVidMem(pScrni->scrnIndex, XpressROMPtr, 0x10000); + return TRUE; +} + +/* End of file */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_fourcc.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_fourcc.h 2005-08-02 15:28:27.000000000 -0600 @@ -0,0 +1,101 @@ +/* + * $Workfile: amd_fourcc.h $ + * $Revision: #2 $ + * $Author: raymondd $ + * + * File Contents: This file consists of main Xfree video macro definitions. + * + * Project: Geode Xfree Frame buffer device driver. + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +#define FOURCC_Y2YU 0x55593259 +#define XVIMAGE_Y2YU \ + { \ + FOURCC_Y2YU, \ + XvYUV, \ + LSBFirst, \ + {'Y','2','Y','U', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 16, \ + XvPacked, \ + 1, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 2, 2, \ + 1, 1, 1, \ + {'Y','V','Y','U', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_YVYU 0x55595659 +#define XVIMAGE_YVYU \ + { \ + FOURCC_YVYU, \ + XvYUV, \ + LSBFirst, \ + {'Y','V','Y','U', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 16, \ + XvPacked, \ + 1, \ + 0, 0, 0, 0, \ + 8, 8, 8, \ + 1, 2, 2, \ + 1, 1, 1, \ + {'Y','V','Y','U', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } + +#define FOURCC_Y800 0x30303859 +#define XVIMAGE_Y800 \ + { \ + FOURCC_Y800, \ + XvYUV, \ + LSBFirst, \ + {'Y','8','0','0', \ + 0x00,0x00,0x00,0x10,0x80,0x00,0x00,0xAA,0x00,0x38,0x9B,0x71}, \ + 8, \ + XvPacked, \ + 1, \ + 0, 0, 0, 0, \ + 8, 0, 0, \ + 1, 0, 0, \ + 1, 0, 0, \ + {'Y','8','0','0', \ + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}, \ + XvTopToBottom \ + } --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_driver.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_driver.c 2005-08-04 08:36:35.000000000 -0600 @@ -0,0 +1,533 @@ +/* + * $Workfile: amd_driver.c $ + * $Revision: #7 $ + * $Author: raymondd $ + * + * File Contents: This is the main module configures the interfacing + * with the X server. The individual modules will be + * loaded based upon the options selected from the + * XF86Config. This file also has modules for finding + * supported modes, turning on the modes based on options. + * + * Project: Amd Xfree Frame buffer device driver. + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + +/* Includes that are used by all drivers */ +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86_ansic.h" +#include "xf86Resources.h" + +/* We may want inb() and outb() */ +#include "compiler.h" + +/* We may want to access the PCI config space */ +#include "xf86PciInfo.h" +#include "xf86Pci.h" + +/* Colormap handling stuff */ +#include "xf86cmap.h" + +#include "amd.h" +#include "build_num.h" + +#define RC_MAX_DEPTH 24 + +/* Frame buffer stuff */ +#if CFB +/* + * If using cfb, cfb.h is required. Select the others for the bpp values + * the driver supports. + */ +#define PSZ 8 /* needed for cfb.h */ +#include "cfb.h" +#undef PSZ +#include "cfb16.h" +#include "cfb24.h" +#include "cfb32.h" +#else +#include "fb.h" +#endif + +#include "shadowfb.h" + +/* Machine independent stuff */ +#include "mipointer.h" +#include "mibank.h" +#include "micmap.h" +/* All drivers implementing backing store need this */ +#include "mibstore.h" +#include "vgaHW.h" +#include "vbe.h" + +/* Check for some extensions */ +#ifdef XFreeXDGA +#define _XF86_DGA_SERVER_ +#include "extensions/xf86dgastr.h" +#endif /* XFreeXDGA */ + +#ifdef DPMSExtension +#include "globals.h" +#include "opaque.h" +#define DPMS_SERVER +#include "extensions/dpms.h" +#endif /* DPMSExtension */ + +/* A few things all drivers should have */ +#define AMD_NAME "AMD" +#define AMD_DRIVER_NAME "amd" +#define _id(n,m)n##m +#define _cat(n,m) _id(n,m) +#define AMD_VERSION_CURRENT ((_cat(0x,_MAJOR) << 24) | (_cat(0x,_MINOR) << 16) | (_cat(0x,_BL) << 8) | _cat(0x,_BLREV) ) + +/* Forward definitions */ +static const OptionInfoRec *AmdAvailableOptions(int chipid, int busid); +static void AmdIdentify(int); +static Bool AmdProbe(DriverPtr, int); +static int CPUDetected; + +/* driver record contains the functions needed by the server after loading + * the driver module. + */ +DriverRec AMD = { + AMD_VERSION_CURRENT, + AMD_DRIVER_NAME, + AmdIdentify, + AmdProbe, + AmdAvailableOptions, + NULL, + 0 +}; + +/* Advanced Micro Devices Chip Models */ +typedef struct _DEVICE_MODEL +{ + int DeviceId; + int Model; +} +DeviceModel; + +DeviceModel ChipModel[] = { +#ifdef HAVE_LX + {PCI_CHIP_GEODELX, LX}, +#endif +#ifdef HAVE_GX + {PCI_CHIP_REDCLOUD, GX2}, +#endif + {-1, 0} +}; + +/* Supported chipsets */ +SymTabRec GeodeChipsets[] = { +#ifdef HAVE_LX + {PCI_CHIP_GEODELX, "GeodeLX"}, +#endif +#ifdef HAVE_GX + {PCI_CHIP_REDCLOUD, "REDCLOUD"}, +#endif + {-1, NULL} +}; + +PciChipsets GeodePCIchipsets[] = { +#ifdef HAVE_LX + {PCI_CHIP_GEODELX, PCI_CHIP_GEODELX, RES_SHARED_VGA}, +#endif +#ifdef HAVE_GX + {PCI_CHIP_REDCLOUD, PCI_CHIP_REDCLOUD, RES_SHARED_VGA}, +#endif + {-1, -1, RES_UNDEFINED}, +}; + +#ifdef HAVE_LX +void LXSetupChipsetFPtr(ScrnInfoPtr pScrni); + +OptionInfoRec LX_GeodeOptions[] = { + {LX_OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE}, + {LX_OPTION_HW_CURSOR, "HWcursor", OPTV_BOOLEAN, {0}, FALSE}, + {LX_OPTION_NOCOMPRESSION, "NoCompression", OPTV_BOOLEAN, {0}, FALSE}, + {LX_OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE}, + {LX_OPTION_TV_ENCODER, "TV_Encoder", OPTV_ANYSTR, {0}, FALSE}, + {LX_OPTION_TV_BUS_FMT, "TV_Bus_Fmt", OPTV_ANYSTR, {0}, FALSE}, + {LX_OPTION_TV_FLAGS, "TV_Flags", OPTV_ANYSTR, {0}, FALSE}, + {LX_OPTION_TV_601_FLAGS, "TV_601_Flags", OPTV_ANYSTR, {0}, FALSE}, + {LX_OPTION_TV_VSYNC_SELECT, "TV_Vsync_Select", OPTV_ANYSTR, {0}, FALSE}, + {LX_OPTION_TV_CONVERSION, "TV_Conversion", OPTV_ANYSTR, {0}, FALSE}, + {LX_OPTION_TV_OVERSCAN, "TV_Overscan", OPTV_ANYSTR, {0}, FALSE}, + {LX_OPTION_SHADOW_FB, "ShadowFB", OPTV_BOOLEAN, {0}, FALSE}, + {LX_OPTION_ROTATE, "Rotate", OPTV_ANYSTR, {0}, FALSE}, + {LX_OPTION_FLATPANEL, "FlatPanel", OPTV_BOOLEAN, {0}, FALSE}, + {LX_OPTION_CRTENABLE, "CrtEnable", OPTV_BOOLEAN, {0}, FALSE}, + {LX_OPTION_COLOR_KEY, "ColorKey", OPTV_INTEGER, {0}, FALSE}, + {LX_OPTION_OSM_IMG_BUFS, "OSMImageBuffers", OPTV_INTEGER, {0}, FALSE}, + {LX_OPTION_OSM_CLR_BUFS, "OSMColorExpBuffers", OPTV_INTEGER, {0}, FALSE}, + {LX_OPTION_CUSTOM_MODE, "CustomMode", OPTV_BOOLEAN, {0}, FALSE}, + {LX_OPTION_FP_DEST_GEOM, "FPDestGeom", OPTV_ANYSTR, {0}, FALSE}, + {LX_OPTION_FP_ACTIVE_GEOM, "FPActiveGeom", OPTV_ANYSTR, {0}, FALSE}, + {-1, NULL, OPTV_NONE, {0}, FALSE} +}; +#endif + +#ifdef HAVE_GX +void GXSetupChipsetFPtr(ScrnInfoPtr pScrni); + +OptionInfoRec GX_GeodeOptions[] = { + {GX_OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE}, + {GX_OPTION_HW_CURSOR, "HWcursor", OPTV_BOOLEAN, {0}, FALSE}, + {GX_OPTION_NOCOMPRESSION, "NoCompression", OPTV_BOOLEAN, {0}, FALSE}, + {GX_OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE}, + {GX_OPTION_TV_SUPPORT, "TV", OPTV_ANYSTR, {0}, FALSE}, + {GX_OPTION_TV_OUTPUT, "TV_Output", OPTV_ANYSTR, {0}, FALSE}, + {GX_OPTION_TV_OVERSCAN, "TVOverscan", OPTV_ANYSTR, {0}, FALSE}, + {GX_OPTION_SHADOW_FB, "ShadowFB", OPTV_BOOLEAN, {0}, FALSE}, + {GX_OPTION_ROTATE, "Rotate", OPTV_ANYSTR, {0}, FALSE}, + {GX_OPTION_FLATPANEL, "FlatPanel", OPTV_BOOLEAN, {0}, FALSE}, + {GX_OPTION_COLOR_KEY, "ColorKey", OPTV_INTEGER, {0}, FALSE}, + {GX_OPTION_OSM_IMG_BUFS, "OSMImageBuffers", OPTV_INTEGER, {0}, FALSE}, + {GX_OPTION_OSM_CLR_BUFS, "OSMColorExpBuffers", OPTV_INTEGER, {0}, FALSE}, + {GX_OPTION_CUSTOM_MODE, "CustomMode", OPTV_BOOLEAN, {0}, FALSE}, + {-1, NULL, OPTV_NONE, {0}, FALSE} +}; +#endif + +OptionInfoRec no_GeodeOptions[] = { + {-1, NULL, OPTV_NONE, {0}, FALSE} +}; + +/* List of symbols from other modules that this module references.The purpose +* is that to avoid unresolved symbol warnings +*/ +const char *amdVgahwSymbols[] = { + "vgaHWGetHWRec", + "vgaHWUnlock", + "vgaHWInit", + "vgaHWSave", + "vgaHWRestore", + "vgaHWProtect", + "vgaHWGetIOBase", + "vgaHWMapMem", + "vgaHWLock", + "vgaHWFreeHWRec", + "vgaHWSaveScreen", + NULL +}; + +const char *amdVbeSymbols[] = { + "VBEInit", + "vbeDoEDID", + "vbeFree", + NULL +}; + +const char *amdInt10Symbols[] = { + "xf86ExecX86int10", + "xf86InitInt10", + "xf86Int10AllocPages", + "xf86Int10Addr", + NULL +}; + +#if CFB +const char *amdCfbSymbols[] = { + "cfbScreenInit", + "cfb16ScreenInit", + "cfb24ScreenInit", + "cfb32ScreenInit", + NULL +}; +#else +const char *amdFbSymbols[] = { + "fbScreenInit", + "fbPictureInit", + NULL +}; +#endif + +const char *amdXaaSymbols[] = { + "XAADestroyInfoRec", + "XAACreateInfoRec", + "XAAInit", + "XAAScreenIndex", + NULL +}; + +const char *amdRamdacSymbols[] = { + "xf86InitCursor", + "xf86CreateCursorInfoRec", + "xf86DestroyCursorInfoRec", + NULL +}; + +const char *amdShadowSymbols[] = { + "ShadowFBInit", + NULL +}; + +#ifdef XFree86LOADER + +/* Module loader interface */ + +static MODULESETUPPROTO(AmdSetup); + +static XF86ModuleVersionInfo AmdVersionRec = { + "amd", + MODULEVENDORSTRING, + MODINFOSTRING1, + MODINFOSTRING2, + XF86_VERSION_CURRENT, + GET_MODULE_MAJOR_VERSION(AMD_VERSION_CURRENT), + GET_MODULE_MINOR_VERSION(AMD_VERSION_CURRENT), + (GET_MODULE_PATCHLEVEL(AMD_VERSION_CURRENT)>>8)*100 + + (GET_MODULE_PATCHLEVEL(AMD_VERSION_CURRENT)&0xff), + ABI_CLASS_VIDEODRV, /* This is a video driver */ + ABI_VIDEODRV_VERSION, + MOD_CLASS_VIDEODRV, + {0, 0, 0, 0} +}; + +/* + * This data is accessed by the loader. The name must be the module name + * followed by "ModuleInit". + */ +XF86ModuleData amdModuleData = { &AmdVersionRec, AmdSetup, NULL }; + +/*------------------------------------------------------------------------- + * AmdSetup. + * + * Description :This function sets up the driver in X list and load the + * module symbols through xf86loader routines.. + * + * Parameters. + * Module :Pointer to the geode module + * options :Driver module options. + * ErrorMajor:Major no + * ErrorMinor:Minor no. + * + * Returns :NULL on success + * + * Comments :Module setup is done by this function + * + *------------------------------------------------------------------------- +*/ +static pointer +AmdSetup(pointer Module, pointer Options, int *ErrorMajor, int *ErrorMinor) +{ + static Bool Initialised = FALSE; + + if (!Initialised) { + Initialised = TRUE; + xf86AddDriver(&AMD, Module, 0); + /* Tell the loader about symbols from other modules that this + * module might refer to. + */ + LoaderRefSymLists(amdVgahwSymbols, amdVbeSymbols, +#if CFB + amdCfbSymbols, +#else + amdFbSymbols, +#endif + amdXaaSymbols, + amdInt10Symbols, amdRamdacSymbols, amdShadowSymbols, + NULL); + return (pointer) TRUE; + } + /*The return value must be non-NULL on success */ + if (ErrorMajor) + *ErrorMajor = LDR_ONCEONLY; + return NULL; +} +#endif /*End of XFree86Loader */ + +/*------------------------------------------------------------------------- + * AmdIdentify. + * + * Description : This function identify an Amdfamily version. + * + * + * Parameters. + * flags : flags may be used in PreInit* + * + * Returns : none + * + * Comments : none + * +*------------------------------------------------------------------------ +*/ +static void +AmdIdentify(int flags) +{ + xf86PrintChipsets(AMD_NAME, AMD_VERSION " for chipsets ", GeodeChipsets); +} + +/*---------------------------------------------------------------------------- + * AmdAvailableOptions. + * + * Description :This function returns the geodeoptions set geodeoption + * + * Parameters. + * chipid :This will identify the chipset. + * busid :This will identify the PCI busid + * + * Returns :ptr to GeodeOptions. + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static const OptionInfoRec * +AmdAvailableOptions(int chipid, int busid) +{ + switch ( chipid ) { +#ifdef HAVE_LX + case PCI_CHIP_GEODELX: + return LX_GeodeOptions; +#endif +#ifdef HAVE_GX + case PCI_CHIP_REDCLOUD: + return GX_GeodeOptions; +#endif + } + return no_GeodeOptions; +} + +/*---------------------------------------------------------------------------- + * AmdProbe. + * + * Description :This is to find that hardware is claimed by another + * driver if not claim the slot & allocate ScreenInfoRec. + * + * Parameters. + * drv :a pointer to the geode driver + * flags :flags may passed to check the config and probe detect + * + * Returns :TRUE on success and FALSE on failure. + * + * Comments :This should ne minimal probe and it should under no + * circumstances change the state of the hardware.Don't do + * any intiallizations other than the required + * ScreenInforec. +*---------------------------------------------------------------------------- +*/ + +static Bool +AmdProbe(DriverPtr drv, int flags) +{ + Bool foundScreen = FALSE; + int numDevSections, numUsed; + GDevPtr *devSections = NULL; + int *usedChips = NULL; + int i; + void (*drvr_setup)(ScrnInfoPtr pScrni); + + DEBUGMSG(1,(0, X_INFO, "AmdProbe: Probing for supported devices!\n")); + /* + * * Find the config file Device sections that match this + * * driver, and return if there are none. + */ + if ((numDevSections = xf86MatchDevice(AMD_NAME, &devSections)) <= 0) { + DEBUGMSG(1,(0, X_INFO, "AmdProbe: failed 1!\n")); + return FALSE; + } + DEBUGMSG(1,(0, X_INFO, "AmdProbe: Before MatchPciInstances!\n")); + /* PCI BUS */ + if (xf86GetPciVideoInfo()) { + numUsed = xf86MatchPciInstances(AMD_NAME, PCI_VENDOR_ID_NS, + GeodeChipsets, GeodePCIchipsets, + devSections, numDevSections, + drv, &usedChips); + + if( numUsed <= 0 ) + numUsed = xf86MatchPciInstances(AMD_NAME, PCI_VENDOR_ID_AMD, + GeodeChipsets, GeodePCIchipsets, + devSections, numDevSections, + drv, &usedChips); + + DEBUGMSG(1,(0, X_INFO, "AmdProbe: MatchPCI (%d)!\n", numUsed)); + + if (numUsed > 0) { + if (flags & PROBE_DETECT) + foundScreen = TRUE; + else { + /* Durango only supports one instance, */ + /* so take the first one */ + for (i = 0; i < numUsed; i++) { + /* Allocate a ScrnInfoRec */ + ScrnInfoPtr pScrni = xf86AllocateScreen(drv, 0); + + EntityInfoPtr pEnt = xf86GetEntityInfo(usedChips[i]); + PciChipsets *p_id; + + for (p_id = GeodePCIchipsets; p_id->numChipset != -1; p_id++) { + if (pEnt->chipset == p_id->numChipset) { + switch( pEnt->chipset ) { +#ifdef HAVE_LX + case PCI_CHIP_GEODELX: + CPUDetected = LX; + drvr_setup = &LXSetupChipsetFPtr; + break; +#endif +#ifdef HAVE_GX + case PCI_CHIP_REDCLOUD: + CPUDetected = GX2; + drvr_setup = &GXSetupChipsetFPtr; + break; +#endif + default: + return FALSE; + } + break; + } + } + xfree(pEnt); + DEBUGMSG(1,(0, X_INFO, "AmdProbe: CPUDetected %d!\n", CPUDetected)); + + pScrni->driverName = AMD_DRIVER_NAME; + pScrni->name = AMD_NAME; + pScrni->Probe = AmdProbe; + drvr_setup(pScrni); + + foundScreen = TRUE; + xf86ConfigActivePciEntity(pScrni, usedChips[i], GeodePCIchipsets, + NULL, NULL, NULL, NULL, NULL); + } + } + } + } + + if (usedChips) + xfree(usedChips); + if (devSections) + xfree(devSections); + DEBUGMSG(1,(0, X_INFO, "AmdProbe: result (%d)!\n", foundScreen)); + return foundScreen; +} --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_video.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_video.c 2005-08-03 16:50:29.000000000 -0600 @@ -0,0 +1,1473 @@ +/* + * $Workfile: amd_gx_video.c $ + * $Revision: #4 $ + * $Author: raymondd $ + * + * File Contents: This file consists of main Xfree video supported routines. + * + * Project: Geode Xfree Frame buffer device driver. + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +/* + * Fixes & Extensions to support Y800 greyscale modes + * Alan Hourihane + */ + +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86Resources.h" +#include "xf86_ansic.h" +#include "compiler.h" +#include "xf86PciInfo.h" +#include "xf86Pci.h" +#include "xf86fbman.h" +#include "regionstr.h" + +#include "amd.h" +#include "Xv.h" +#include "xaa.h" +#include "xaalocal.h" +#include "dixstruct.h" +#include "fourcc.h" +#include "amd_fourcc.h" + +#define OFF_DELAY 200 /* milliseconds */ +#define FREE_DELAY 60000 + +#define OFF_TIMER 0x01 +#define FREE_TIMER 0x02 +#define CLIENT_VIDEO_ON 0x04 + +#define TIMER_MASK (OFF_TIMER | FREE_TIMER) +#define XV_PROFILE 0 +#define REINIT 1 + +#ifndef XvExtension +void +GXInitVideo(ScreenPtr pScrn) +{ +} + +void +GXResetVideo(ScrnInfoPtr pScrni) +{ +} +void +GXSetVideoPosition() +{ +} +#else + +#define DBUF 1 +void GXInitVideo(ScreenPtr pScrn); +void GXResetVideo(ScrnInfoPtr pScrni); +static XF86VideoAdaptorPtr GXSetupImageVideo(ScreenPtr); +static void GXInitOffscreenImages(ScreenPtr); +static void GXStopVideo(ScrnInfoPtr, pointer, Bool); +static int GXSetPortAttribute(ScrnInfoPtr, Atom, INT32, pointer); +static int GXGetPortAttribute(ScrnInfoPtr, Atom, INT32 *, pointer); +static void GXQueryBestSize(ScrnInfoPtr, Bool, + short, short, short, short, unsigned int *, + unsigned int *, pointer); +static int GXPutImage(ScrnInfoPtr, short, short, short, short, short, short, + short, short, int, unsigned char *, short, short, Bool, + RegionPtr, pointer); +static int GXQueryImageAttributes(ScrnInfoPtr, int, unsigned short *, + unsigned short *, int *, int *); + +static void GXBlockHandler(int, pointer, pointer, pointer); +void GXSetVideoPosition(int x, int y, int width, int height, + short src_w, short src_h, short drw_w, + short drw_h, int id, int offset, ScrnInfoPtr pScrni); + +extern void GXAccelSync(ScrnInfoPtr pScrni); + +int DeltaX, DeltaY; + +#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE) + +static Atom xvColorKey, xvColorKeyMode, xvFilter +#if DBUF + , xvDoubleBuffer +#endif + ; + +/*---------------------------------------------------------------------------- + * GXInitVideo + * + * Description :This is the initialization routine.It creates a new video adapter + * and calls GXSetupImageVideo to initialize the adaptor by filling + * XF86VideoAdaptorREc.Then it lists the existing adaptors and adds the + * new one to it. Finally the list of XF86VideoAdaptorPtr pointers are + * passed to the xf86XVScreenInit(). + * + * Parameters. + * ScreenPtr + * pScrn :Screen handler pointer having screen information. + * + * Returns :none + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +void +GXInitVideo(ScreenPtr pScrn) +{ + GeodePtr pGeode; + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + + pGeode = GEODEPTR(pScrni); + + if (!pGeode->NoAccel) { + XF86VideoAdaptorPtr *adaptors, *newAdaptors = NULL; + XF86VideoAdaptorPtr newAdaptor = NULL; + + int num_adaptors; + + newAdaptor = GXSetupImageVideo(pScrn); + GXInitOffscreenImages(pScrn); + + num_adaptors = xf86XVListGenericAdaptors(pScrni, &adaptors); + + if (newAdaptor) { + if (!num_adaptors) { + num_adaptors = 1; + adaptors = &newAdaptor; + } else { + newAdaptors = /* need to free this someplace */ + xalloc((num_adaptors + 1) * sizeof(XF86VideoAdaptorPtr *)); + if (newAdaptors) { + memcpy(newAdaptors, adaptors, num_adaptors * + sizeof(XF86VideoAdaptorPtr)); + newAdaptors[num_adaptors] = newAdaptor; + adaptors = newAdaptors; + num_adaptors++; + } + } + } + + if (num_adaptors) + xf86XVScreenInit(pScrn, adaptors, num_adaptors); + + if (newAdaptors) + xfree(newAdaptors); + } +} + +/* client libraries expect an encoding */ +static XF86VideoEncodingRec DummyEncoding[1] = { + { + 0, + "XV_IMAGE", + 1024, 1024, + {1, 1} + } +}; + +#define NUM_FORMATS 4 + +static XF86VideoFormatRec Formats[NUM_FORMATS] = { + {8, PseudoColor}, {15, TrueColor}, {16, TrueColor}, {24, TrueColor} +}; + +#if DBUF +#define NUM_ATTRIBUTES 4 +#else +#define NUM_ATTRIBUTES 3 +#endif + +static XF86AttributeRec Attributes[NUM_ATTRIBUTES] = { +#if DBUF + {XvSettable | XvGettable, 0, 1, "XV_DOUBLE_BUFFER"}, +#endif + {XvSettable | XvGettable, 0, (1 << 24) - 1, "XV_COLORKEY"}, + {XvSettable | XvGettable, 0, 1, "XV_FILTER"}, + {XvSettable | XvGettable, 0, 1, "XV_COLORKEYMODE"} +}; + +#define NUM_IMAGES 7 + +static XF86ImageRec Images[NUM_IMAGES] = { + XVIMAGE_UYVY, + XVIMAGE_YUY2, + XVIMAGE_Y2YU, + XVIMAGE_YVYU, + XVIMAGE_Y800, + XVIMAGE_I420, + XVIMAGE_YV12 +}; + +typedef struct +{ + FBAreaPtr area; + FBLinearPtr linear; + RegionRec clip; + CARD32 filter; + CARD32 colorKey; + CARD32 colorKeyMode; + CARD32 videoStatus; + Time offTime; + Time freeTime; +#if DBUF + Bool doubleBuffer; + int currentBuffer; +#endif +} +GeodePortPrivRec, *GeodePortPrivPtr; + +#define GET_PORT_PRIVATE(pScrni) \ + (GeodePortPrivPtr)((GEODEPTR(pScrni))->adaptor->pPortPrivates[0].ptr) + +/*---------------------------------------------------------------------------- + * GXSetColorKey + * + * Description :This function reads the color key for the pallete and + * sets the video color key register. + * + * Parameters. + * ScreenInfoPtr + * pScrni :Screen pointer having screen information. + * pPriv :Video port private data + * + * Returns :none + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static INT32 +GXSetColorkey(ScrnInfoPtr pScrni, GeodePortPrivPtr pPriv) +{ + int red, green, blue; + unsigned long key; + + switch (pScrni->depth) { + case 8: + GFX(get_display_palette_entry(pPriv->colorKey & 0xFF, &key)); + red = ((key >> 16) & 0xFF); + green = ((key >> 8) & 0xFF); + blue = (key & 0xFF); + break; + case 16: + red = (pPriv->colorKey & pScrni->mask.red) >> + pScrni->offset.red << (8 - pScrni->weight.red); + green = (pPriv->colorKey & pScrni->mask.green) >> + pScrni->offset.green << (8 - pScrni->weight.green); + blue = (pPriv->colorKey & pScrni->mask.blue) >> + pScrni->offset.blue << (8 - pScrni->weight.blue); + break; + default: + /* for > 16 bpp we send in the mask in xf86SetWeight. This + * function is providing the offset by 1 more. So we take + * this as a special case and subtract 1 for > 16 + */ + red = (pPriv->colorKey & pScrni->mask.red) >> + (pScrni->offset.red - 1) << (8 - pScrni->weight.red); + green = (pPriv->colorKey & pScrni->mask.green) >> + (pScrni->offset.green - 1) << (8 - pScrni->weight.green); + blue = (pPriv->colorKey & pScrni->mask.blue) >> + (pScrni->offset.blue - 1) << (8 - pScrni->weight.blue); + break; + } + + GFX(set_video_color_key((blue | (green << 8) | (red << 16)), 0xFFFFFF, + (pPriv->colorKeyMode == 0))); + REGION_EMPTY(pScrni->pScreen, &pPriv->clip); + return 0; +} + +/*---------------------------------------------------------------------------- + * GXResetVideo + * + * Description : This function resets the video + * + * Parameters. + * ScreenInfoPtr + * pScrni :Screen pointer having screen information. + * + * Returns :None + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ + +void +GXResetVideo(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + if (!pGeode->NoAccel) { + GeodePortPrivPtr pPriv = pGeode->adaptor->pPortPrivates[0].ptr; + + GXAccelSync(pScrni); + GFX(set_video_palette(NULL)); + GXSetColorkey(pScrni, pPriv); + GFX(set_video_filter(pPriv->filter, pPriv->filter)); + } +} + +/*---------------------------------------------------------------------------- + * GXSetupImageVideo + * + * Description : This function allocates space for a Videoadaptor and initializes + * the XF86VideoAdaptorPtr record. + * + * Parameters. + * ScreenPtr + * pScrn :Screen handler pointer having screen information. + * + * Returns :XF86VideoAdaptorPtr :- pointer to the initialized video adaptor record. + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ + +static XF86VideoAdaptorPtr +GXSetupImageVideo(ScreenPtr pScrn) +{ + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + GeodePtr pGeode = GEODEPTR(pScrni); + XF86VideoAdaptorPtr adapt; + GeodePortPrivPtr pPriv; + + if (!(adapt = xcalloc(1, sizeof(XF86VideoAdaptorRec) + + sizeof(GeodePortPrivRec) + sizeof(DevUnion)))) + return NULL; + + adapt->type = XvWindowMask | XvInputMask | XvImageMask; + adapt->flags = VIDEO_OVERLAID_IMAGES | VIDEO_CLIP_TO_VIEWPORT; + adapt->name = "Advanced Micro Devices"; + adapt->nEncodings = 1; + adapt->pEncodings = DummyEncoding; + adapt->nFormats = NUM_FORMATS; + adapt->pFormats = Formats; + adapt->nPorts = 1; + adapt->pPortPrivates = (DevUnion *) (&adapt[1]); + pPriv = (GeodePortPrivPtr) (&adapt->pPortPrivates[1]); + adapt->pPortPrivates[0].ptr = (pointer) (pPriv); + adapt->pAttributes = Attributes; + adapt->nImages = NUM_IMAGES; + adapt->nAttributes = NUM_ATTRIBUTES; + adapt->pImages = Images; + adapt->PutVideo = NULL; + adapt->PutStill = NULL; + adapt->GetVideo = NULL; + adapt->GetStill = NULL; + adapt->StopVideo = GXStopVideo; + adapt->SetPortAttribute = GXSetPortAttribute; + adapt->GetPortAttribute = GXGetPortAttribute; + adapt->QueryBestSize = GXQueryBestSize; + adapt->PutImage = GXPutImage; + adapt->QueryImageAttributes = GXQueryImageAttributes; + + pPriv->filter = 0; + pPriv->colorKey = pGeode->videoKey; + pPriv->colorKeyMode = 0; + pPriv->videoStatus = 0; +#if DBUF + pPriv->doubleBuffer = TRUE; + pPriv->currentBuffer = 0; /* init to first buffer */ +#endif + + /* gotta uninit this someplace */ +#if defined(REGION_NULL) + REGION_NULL(pScrn, &pPriv->clip); +#else + REGION_INIT(pScrn, &pPriv->clip, NullBox, 0); +#endif + + pGeode->adaptor = adapt; + + pGeode->BlockHandler = pScrn->BlockHandler; + pScrn->BlockHandler = GXBlockHandler; + + xvColorKey = MAKE_ATOM("XV_COLORKEY"); + xvColorKeyMode = MAKE_ATOM("XV_COLORKEYMODE"); + xvFilter = MAKE_ATOM("XV_FILTER"); +#if DBUF + xvDoubleBuffer = MAKE_ATOM("XV_DOUBLE_BUFFER"); +#endif + + GXResetVideo(pScrni); + + return adapt; +} + +/*---------------------------------------------------------------------------- + * GXStopVideo + * + * Description :This function is used to stop input and output video + * + * Parameters. + * pScrni :Screen handler pointer having screen information. + * data :Pointer to the video port's private data + * exit :Flag indicating whether the offscreen areas used for video + * to be deallocated or not. + * Returns :none + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static void +GXStopVideo(ScrnInfoPtr pScrni, pointer data, Bool exit) +{ + GeodePortPrivPtr pPriv = (GeodePortPrivPtr) data; + GeodePtr pGeode = GEODEPTR(pScrni); + + REGION_EMPTY(pScrni->pScreen, &pPriv->clip); + + GXAccelSync(pScrni); + if (exit) { + if (pPriv->videoStatus & CLIENT_VIDEO_ON) { + GFX(set_video_enable(0)); + } + if (pPriv->area) { + xf86FreeOffscreenArea(pPriv->area); + pPriv->area = NULL; + } + pPriv->videoStatus = 0; + pGeode->OverlayON = FALSE; + } else { + if (pPriv->videoStatus & CLIENT_VIDEO_ON) { + pPriv->videoStatus |= OFF_TIMER; + pPriv->offTime = currentTime.milliseconds + OFF_DELAY; + } + } +} + +/*---------------------------------------------------------------------------- + * GXSetPortAttribute + * + * Description :This function is used to set the attributes of a port like colorkeymode, + * double buffer support and filter. + * + * Parameters. + * pScrni :Screen handler pointer having screen information. + * data :Pointer to the video port's private data + * attribute :The port attribute to be set + * value :Value of the attribute to be set. + * + * Returns :Sucess if the attribute is supported, else BadMatch + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static int +GXSetPortAttribute(ScrnInfoPtr pScrni, + Atom attribute, INT32 value, pointer data) +{ + GeodePortPrivPtr pPriv = (GeodePortPrivPtr) data; + + GXAccelSync(pScrni); + if (attribute == xvColorKey) { + pPriv->colorKey = value; + GXSetColorkey(pScrni, pPriv); + } +#if DBUF + else if (attribute == xvDoubleBuffer) { + if ((value < 0) || (value > 1)) + return BadValue; + pPriv->doubleBuffer = value; + } +#endif + else if (attribute == xvColorKeyMode) { + pPriv->colorKeyMode = value; + GXSetColorkey(pScrni, pPriv); + } + else if (attribute == xvFilter) { + if ((value < 0) || (value > 1)) + return BadValue; + pPriv->filter = value; + } + else + return BadMatch; + + return Success; +} + +/*---------------------------------------------------------------------------- + * GXGetPortAttribute + * + * Description :This function is used to get the attributes of a port like hue, + * saturation,brightness or contrast. + * + * Parameters. + * pScrni :Screen handler pointer having screen information. + * data :Pointer to the video port's private data + * attribute :The port attribute to be read + * value :Pointer to the value of the attribute to be read. + * + * Returns :Sucess if the attribute is supported, else BadMatch + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static int +GXGetPortAttribute(ScrnInfoPtr pScrni, + Atom attribute, INT32 * value, pointer data) +{ + GeodePortPrivPtr pPriv = (GeodePortPrivPtr) data; + + if (attribute == xvColorKey) { + *value = pPriv->colorKey; + } +#if DBUF + else if (attribute == xvDoubleBuffer) { + *value = (pPriv->doubleBuffer) ? 1 : 0; + } +#endif + else if (attribute == xvColorKeyMode) { + *value = pPriv->colorKeyMode; + } + else if (attribute == xvFilter) { + *value = pPriv->filter; + } else + return BadMatch; + + return Success; +} + +/*---------------------------------------------------------------------------- + * GXQueryBestSize + * + * Description :This function provides a way to query what the destination dimensions + * would end up being if they were to request that an area vid_w by vid_h + * from the video stream be scaled to rectangle of drw_w by drw_h on + * the screen. + * + * Parameters. + * ScreenInfoPtr + * pScrni :Screen handler pointer having screen information. + * data :Pointer to the video port's private data + * vid_w,vid_h :Width and height of the video data. + * drw_w,drw_h :Width and height of the scaled rectangle. + * p_w,p_h :Width and height of the destination rectangle. + * + * Returns :None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ +static void +GXQueryBestSize(ScrnInfoPtr pScrni, + Bool motion, + short vid_w, short vid_h, + short drw_w, short drw_h, + unsigned int *p_w, unsigned int *p_h, pointer data) +{ + *p_w = drw_w; + *p_h = drw_h; + + if (*p_w > 16384) + *p_w = 16384; +} + +static void +GXCopyGreyscale(unsigned char *src, + unsigned char *dst, int srcPitch, int dstPitch, int h, int w) +{ + int i; + unsigned char *src2 = src; + unsigned char *dst2 = dst; + unsigned char *dst3; + unsigned char *src3; + + dstPitch <<= 1; + + while (h--) { + dst3 = dst2; + src3 = src2; + for (i = 0; i < w; i++) { + *dst3++ = *src3++; /* Copy Y data */ + *dst3++ = 0x80; /* Fill UV with 0x80 - greyscale */ + } + src3 = src2; + for (i = 0; i < w; i++) { + *dst3++ = *src3++; /* Copy Y data */ + *dst3++ = 0x80; /* Fill UV with 0x80 - greyscale */ + } + dst2 += dstPitch; + src2 += srcPitch; + } +} + +/*---------------------------------------------------------------------------- + * GXCopyData420 + * + * Description : Copies data from src to destination + * + * Parameters. + * src : pointer to the source data + * dst : pointer to destination data + * srcPitch : pitch of the srcdata + * dstPitch : pitch of the destination data + * h & w : height and width of source data + * + * Returns :None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ + +static void +GXCopyData420(unsigned char *src, unsigned char *dst, + int srcPitch, int dstPitch, int h, int w) +{ + while (h--) { + memcpy(dst, src, w); + src += srcPitch; + dst += dstPitch; + } +} + +/*---------------------------------------------------------------------------- + * GXCopyData422 + * + * Description : Copies data from src to destination + * + * Parameters. + * src : pointer to the source data + * dst : pointer to destination data + * srcPitch : pitch of the srcdata + * dstPitch : pitch of the destination data + * h & w : height and width of source data + * + * Returns :None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ + +static void +GXCopyData422(unsigned char *src, unsigned char *dst, + int srcPitch, int dstPitch, int h, int w) +{ + w <<= 1; + while (h--) { + memcpy(dst, src, w); + src += srcPitch; + dst += dstPitch; + } +} + +static FBAreaPtr +GXAllocateMemory(ScrnInfoPtr pScrni, FBAreaPtr area, int numlines) +{ + ScreenPtr pScrn = screenInfo.screens[pScrni->scrnIndex]; + FBAreaPtr new_area; + + if (area) { + if ((area->box.y2 - area->box.y1) >= numlines) + return area; + + if (xf86ResizeOffscreenArea(area, pScrni->displayWidth, numlines)) + return area; + + xf86FreeOffscreenArea(area); + } + + new_area = xf86AllocateOffscreenArea(pScrn, pScrni->displayWidth, + numlines, 0, NULL, NULL, NULL); + + if (!new_area) { + int max_w, max_h; + + xf86QueryLargestOffscreenArea(pScrn, &max_w, &max_h, 0, + FAVOR_WIDTH_THEN_AREA, PRIORITY_EXTREME); + + if ((max_w < pScrni->displayWidth) || (max_h < numlines)) + return NULL; + + xf86PurgeUnlockedOffscreenAreas(pScrn); + new_area = xf86AllocateOffscreenArea(pScrn, pScrni->displayWidth, + numlines, 0, NULL, NULL, NULL); + } + + return new_area; +} + +static BoxRec dstBox; +static int srcPitch = 0, srcPitch2 = 0, dstPitch = 0, dstPitch2 = 0; +static INT32 Bx1, Bx2, By1, By2; +static int top, left, npixels, nlines; +static int offset, s1offset = 0, s2offset = 0, s3offset = 0; +static unsigned char *dst_start; +static int d2offset = 0, d3offset = 0; +static Bool +RegionsIntersect(BoxPtr pRcl1, BoxPtr pRcl2, BoxPtr pRclResult) +{ + pRclResult->x1 = max(pRcl1->x1, pRcl2->x1); + pRclResult->x2 = min(pRcl1->x2, pRcl2->x2); + + if (pRclResult->x1 <= pRclResult->x2) { + pRclResult->y1 = max(pRcl1->y1, pRcl2->y1); + pRclResult->y2 = min(pRcl1->y2, pRcl2->y2); + + if (pRclResult->y1 <= pRclResult->y2) { + return (TRUE); + } + } + + return (FALSE); +} + +void +GXSetVideoPosition(int x, int y, int width, int height, + short src_w, short src_h, short drw_w, short drw_h, + int id, int offset, ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + long ystart, xend, yend; + unsigned long lines = 0; + unsigned long y_extra, uv_extra = 0; + unsigned long startAddress; + BoxRec ovly, display, result; + + xend = x + drw_w; + yend = y + drw_h; + + /* Take care of panning when panel is present */ + + startAddress = gfx_get_display_offset() - pGeode->FBOffset; + DeltaY = startAddress / pGeode->Pitch; + DeltaX = startAddress & (pGeode->Pitch - 1); + DeltaX /= (pScrni->bitsPerPixel >> 3); + + if (pGeode->Panel) { + ovly.x1 = x; + ovly.x2 = x + pGeode->video_dstw; + ovly.y1 = y; + ovly.y2 = y + pGeode->video_dsth; + + display.x1 = DeltaX; + display.x2 = DeltaX + pGeode->FPBX; + display.y1 = DeltaY; + display.y2 = DeltaY + pGeode->FPBY; + x = xend = 0; + if (RegionsIntersect(&display, &ovly, &result)) { + x = ovly.x1 - DeltaX; + xend = ovly.x2 - DeltaX; + y = ovly.y1 - DeltaY; + yend = ovly.y2 - DeltaY; + } + } + + /* TOP CLIPPING */ + + if (y < 0) { + if (src_h < drw_h) + lines = (-y) * src_h / drw_h; + else + lines = (-y); + ystart = 0; + drw_h += y; + y_extra = lines * dstPitch; + uv_extra = (lines >> 1) * (dstPitch2); + } else { + ystart = y; + lines = 0; + y_extra = 0; + } + + GFX(set_video_window(x, ystart, xend - x, yend - ystart)); + + if ((id == FOURCC_Y800) || (id == FOURCC_I420) || (id == FOURCC_YV12)) { + GFX(set_video_yuv_offsets(offset + y_extra, + offset + d3offset + uv_extra, + offset + d2offset + uv_extra)); + } else { + GFX(set_video_offset(offset + y_extra)); + } +} + +/*---------------------------------------------------------------------------- + * GXDisplayVideo + * + * Description : This function sets up the video registers for playing video + * It sets up the video format,width, height & position of the + * video window ,video offsets( y,u,v) and video pitches(y,u,v) + * Parameters. + * + * Returns :None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ + +static void +GXDisplayVideo(ScrnInfoPtr pScrni, + int id, + int offset, + short width, short height, + int pitch, + int x1, int y1, int x2, int y2, + BoxPtr dstBox, + short src_w, short src_h, short drw_w, short drw_h) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + + GXAccelSync(pScrni); + + GFX(set_video_enable(1)); + + switch (id) { + case FOURCC_UYVY: /* UYVY */ + GFX(set_video_format(VIDEO_FORMAT_UYVY)); + GFX(set_video_size(width, height)); + break; + case FOURCC_Y800: /* Y800 - greyscale - we munge it! */ + case FOURCC_YV12: /* YV12 */ + case FOURCC_I420: /* I420 */ + GFX(set_video_format(VIDEO_FORMAT_Y0Y1Y2Y3)); + GFX(set_video_size(width, height)); + GFX(set_video_yuv_pitch(dstPitch, dstPitch2)); + break; + case FOURCC_YUY2: /* YUY2 */ + GFX(set_video_format(VIDEO_FORMAT_YUYV)); + GFX(set_video_size(width, height)); + break; + case FOURCC_Y2YU: /* Y2YU */ + GFX(set_video_format(VIDEO_FORMAT_Y2YU)); + GFX(set_video_size(width, height)); + break; + case FOURCC_YVYU: /* YVYU */ + GFX(set_video_format(VIDEO_FORMAT_YVYU)); + GFX(set_video_size(width, height)); + break; + } + if (pGeode->Panel) { + pGeode->video_x = dstBox->x1; + pGeode->video_y = dstBox->y1; + pGeode->video_w = width; + pGeode->video_h = height; + pGeode->video_srcw = src_w; + pGeode->video_srch = src_h; + pGeode->video_dstw = drw_w; + pGeode->video_dsth = drw_h; + pGeode->video_offset = offset; + pGeode->video_id = id; + pGeode->video_scrnptr = pScrni; + } + + if ((drw_w >= src_w) && (drw_h >= src_h)) + GFX(set_video_scale(width, height, drw_w, drw_h)); + else if (drw_w < src_w) + GFX(set_video_scale(drw_w, height, drw_w, drw_h)); + else if (drw_h < src_h) + GFX(set_video_scale(width, drw_h, drw_w, drw_h)); + GXSetVideoPosition(dstBox->x1, dstBox->y1, width, height, src_w, + src_h, drw_w, drw_h, id, offset, pScrni); + +} + +#if REINIT +static Bool +RegionsEqual(RegionPtr A, RegionPtr B) +{ + int *dataA, *dataB; + int num; + + num = REGION_NUM_RECTS(A); + if (num != REGION_NUM_RECTS(B)) { + return FALSE; + } + + if ((A->extents.x1 != B->extents.x1) || + (A->extents.x2 != B->extents.x2) || + (A->extents.y1 != B->extents.y1) || (A->extents.y2 != B->extents.y2)) + return FALSE; + + dataA = (int *)REGION_RECTS(A); + dataB = (int *)REGION_RECTS(B); + + while (num--) { + if ((dataA[0] != dataB[0]) || (dataA[1] != dataB[1])) + return FALSE; + dataA += 2; + dataB += 2; + } + + return TRUE; +} +#endif + +/*---------------------------------------------------------------------------- + * GXPutImage : This function writes a single frame of video into a drawable. + * The position and size of the source rectangle is specified by src_x,src_y, + * src_w and src_h. This data is stored in a system memory buffer at buf. + * The position and size of the destination rectangle is specified by drw_x, + * drw_y,drw_w,drw_h.The data is in the format indicated by the image descriptor + * and represents a source of size width by height. If sync is TRUE the driver + * should not return from this function until it is through reading the data from + * buf. Returning when sync is TRUE indicates that it is safe for the data at buf + * to be replaced,freed, or modified. + * + * + * Description : + * Parameters. + * + * Returns :None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ + +static int +GXPutImage(ScrnInfoPtr pScrni, + short src_x, short src_y, + short drw_x, short drw_y, + short src_w, short src_h, + short drw_w, short drw_h, + int id, unsigned char *buf, + short width, short height, + Bool sync, RegionPtr clipBoxes, pointer data) +{ + GeodePortPrivPtr pPriv = (GeodePortPrivPtr) data; + GeodePtr pGeode = GEODEPTR(pScrni); + int new_h; + +#if REINIT + BOOL ReInitVideo = FALSE; + static BOOL DoReinitAgain = 0; +#endif + +#if XV_PROFILE + long oldtime, newtime; + + UpdateCurrentTime(); + oldtime = currentTime.milliseconds; +#endif +#if REINIT +/* update cliplist */ + if (!RegionsEqual(&pPriv->clip, clipBoxes)) { + ReInitVideo = TRUE; + } + if (DoReinitAgain) + ReInitVideo = TRUE; + + if (ReInitVideo) { + DEBUGMSG(1, (0, X_NONE, "Regional Not Equal - Init\n")); +#endif + DoReinitAgain = ~DoReinitAgain; + if (drw_w > 16384) + drw_w = 16384; + + /* Clip */ + Bx1 = src_x; + Bx2 = src_x + src_w; + By1 = src_y; + By2 = src_y + src_h; + + if ((Bx1 >= Bx2) || (By1 >= By2)) + return Success; + + dstBox.x1 = drw_x; + dstBox.x2 = drw_x + drw_w; + dstBox.y1 = drw_y; + dstBox.y2 = drw_y + drw_h; + + dstBox.x1 -= pScrni->frameX0; + dstBox.x2 -= pScrni->frameX0; + dstBox.y1 -= pScrni->frameY0; + dstBox.y2 -= pScrni->frameY0; + + switch (id) { + case FOURCC_YV12: + case FOURCC_I420: + + srcPitch = (width + 3) & ~3; /* of luma */ + dstPitch = (width + 31) & ~31; + + s2offset = srcPitch * height; + d2offset = dstPitch * height; + + srcPitch2 = ((width >> 1) + 3) & ~3; + dstPitch2 = ((width >> 1) + 15) & ~15; + + s3offset = (srcPitch2 * (height >> 1)) + s2offset; + d3offset = (dstPitch2 * (height >> 1)) + d2offset; + + new_h = dstPitch * height; /* Y */ + new_h += (dstPitch2 * height); /* U+V */ + new_h += pGeode->Pitch - 1; + new_h /= pGeode->Pitch; + break; + + case FOURCC_UYVY: + case FOURCC_YUY2: + case FOURCC_Y800: + default: + dstPitch = ((width << 1) + 3) & ~3; + srcPitch = (width << 1); + new_h = ((dstPitch * height) + pGeode->Pitch - 1) / pGeode->Pitch; + break; + } + +#if DBUF + if (pPriv->doubleBuffer) + new_h <<= 1; +#endif + + if (!(pPriv->area = GXAllocateMemory(pScrni, pPriv->area, new_h))) + return BadAlloc; + + /* copy data */ + top = By1; + left = Bx1 & ~1; + npixels = ((Bx2 + 1) & ~1) - left; + + switch (id) { + case FOURCC_YV12: + case FOURCC_I420: + { + int tmp; + + top &= ~1; + offset = (pPriv->area->box.y1 * pGeode->Pitch) + (top * dstPitch); + +#if DBUF + if (pPriv->doubleBuffer && pPriv->currentBuffer) + offset += (new_h >> 1) * pGeode->Pitch; +#endif + + dst_start = pGeode->FBBase + offset + left; + tmp = ((top >> 1) * srcPitch2) + (left >> 1); + s2offset += tmp; + s3offset += tmp; + if (id == FOURCC_I420) { + tmp = s2offset; + s2offset = s3offset; + s3offset = tmp; + } + nlines = ((By2 + 1) & ~1) - top; + } + break; + case FOURCC_UYVY: + case FOURCC_YUY2: + case FOURCC_Y800: + default: + left <<= 1; + buf += (top * srcPitch) + left; + nlines = By2 - top; + offset = (pPriv->area->box.y1 * pGeode->Pitch) + (top * dstPitch); +#if DBUF + if (pPriv->doubleBuffer && pPriv->currentBuffer) + offset += (new_h >> 1) * pGeode->Pitch; +#endif + + dst_start = pGeode->FBBase + offset + left; + break; + } + s1offset = (top * srcPitch) + left; + +#if REINIT + /* update cliplist */ + REGION_COPY(pScrni->pScreen, &pPriv->clip, clipBoxes); + if (pPriv->colorKeyMode == 0) { + /* draw these */ + XAAFillSolidRects(pScrni, pPriv->colorKey, GXcopy, ~0, + REGION_NUM_RECTS(clipBoxes), + REGION_RECTS(clipBoxes)); + } + GXDisplayVideo(pScrni, id, offset, width, height, dstPitch, + Bx1, By1, Bx2, By2, &dstBox, src_w, src_h, drw_w, + drw_h); + } +#endif + + switch (id) { + + case FOURCC_Y800: + GXCopyGreyscale(buf, dst_start, srcPitch, dstPitch, nlines, npixels); + break; + case FOURCC_YV12: + case FOURCC_I420: + GXCopyData420(buf + s1offset, dst_start, srcPitch, dstPitch, nlines, + npixels); + GXCopyData420(buf + s2offset, dst_start + d2offset, srcPitch2, + dstPitch2, nlines >> 1, npixels >> 1); + GXCopyData420(buf + s3offset, dst_start + d3offset, srcPitch2, + dstPitch2, nlines >> 1, npixels >> 1); + break; + case FOURCC_UYVY: + case FOURCC_YUY2: + default: + GXCopyData422(buf, dst_start, srcPitch, dstPitch, nlines, npixels); + break; + } +#if !REINIT + /* update cliplist */ + REGION_COPY(pScrni->pScreen, &pPriv->clip, clipBoxes); + if (pPriv->colorKeyMode == 0) { + /* draw these */ + XAAFillSolidRects(pScrni, pPriv->colorKey, GXcopy, ~0, + REGION_NUM_RECTS(clipBoxes), REGION_RECTS(clipBoxes)); + } + GXDisplayVideo(pScrni, id, offset, width, height, dstPitch, + Bx1, By1, Bx2, By2, &dstBox, src_w, src_h, drw_w, drw_h); +#endif + +#if XV_PROFILE + UpdateCurrentTime(); + newtime = currentTime.milliseconds; + DEBUGMSG(1, (0, X_NONE, "PI %d\n", newtime - oldtime)); +#endif + +#if DBUF + pPriv->currentBuffer ^= 1; +#endif + + pPriv->videoStatus = CLIENT_VIDEO_ON; + pGeode->OverlayON = TRUE; + return Success; +} + +/*---------------------------------------------------------------------------- + * GXQueryImageAttributes + * + * Description :This function is called to let the driver specify how data + * for a particular image of size width by height should be + * stored. + * + * Parameters. + * pScrni :Screen handler pointer having screen information. + * id :Id for the video format + * width :width of the image (can be modified by the driver) + * height :height of the image (can be modified by the driver) + * Returns : Size of the memory required for storing this image + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ +static int +GXQueryImageAttributes(ScrnInfoPtr pScrni, + int id, + unsigned short *w, unsigned short *h, + int *pitches, int *offsets) +{ + int size; + int tmp; + + DEBUGMSG(0, (0, X_NONE, "QueryImageAttributes %X\n", id)); + + if (*w > 1024) + *w = 1024; + if (*h > 1024) + *h = 1024; + + *w = (*w + 1) & ~1; + if (offsets) + offsets[0] = 0; + + switch (id) { + case FOURCC_YV12: + case FOURCC_I420: + *h = (*h + 1) & ~1; + size = (*w + 3) & ~3; + if (pitches) + pitches[0] = size; + size *= *h; + if (offsets) + offsets[1] = size; + tmp = ((*w >> 1) + 3) & ~3; + if (pitches) + pitches[1] = pitches[2] = tmp; + tmp *= (*h >> 1); + size += tmp; + if (offsets) + offsets[2] = size; + size += tmp; + break; + case FOURCC_UYVY: + case FOURCC_YUY2: + case FOURCC_Y800: + default: + size = *w << 1; + if (pitches) + pitches[0] = size; + size *= *h; + break; + } + return size; +} + +static void +GXBlockHandler(int i, pointer blockData, pointer pTimeout, pointer pReadmask) +{ + ScreenPtr pScrn = screenInfo.screens[i]; + ScrnInfoPtr pScrni = xf86Screens[i]; + GeodePtr pGeode = GEODEPTR(pScrni); + GeodePortPrivPtr pPriv = GET_PORT_PRIVATE(pScrni); + + pScrn->BlockHandler = pGeode->BlockHandler; + (*pScrn->BlockHandler) (i, blockData, pTimeout, pReadmask); + pScrn->BlockHandler = GXBlockHandler; + + if (pPriv->videoStatus & TIMER_MASK) { + GXAccelSync(pScrni); + UpdateCurrentTime(); + if (pPriv->videoStatus & OFF_TIMER) { + if (pPriv->offTime < currentTime.milliseconds) { + GFX(set_video_enable(0)); + pPriv->videoStatus = FREE_TIMER; + pPriv->freeTime = currentTime.milliseconds + FREE_DELAY; + } + } else { /* FREE_TIMER */ + if (pPriv->freeTime < currentTime.milliseconds) { + if (pPriv->area) { + xf86FreeOffscreenArea(pPriv->area); + pPriv->area = NULL; + } + pPriv->videoStatus = 0; + } + } + } +} + +/****************** Offscreen stuff ***************/ + +typedef struct +{ + FBAreaPtr area; + FBLinearPtr linear; + Bool isOn; +} +OffscreenPrivRec, *OffscreenPrivPtr; + +/*---------------------------------------------------------------------------- + * GXAllocateSurface + * + * Description :This function allocates an area of w by h in the offscreen + * Parameters. + * pScrni :Screen handler pointer having screen information. + * + * Returns :None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ + +static int +GXAllocateSurface(ScrnInfoPtr pScrni, + int id, + unsigned short w, unsigned short h, XF86SurfacePtr surface) +{ + FBAreaPtr area; + int pitch, fbpitch, numlines; + OffscreenPrivPtr pPriv; + + if ((w > 1024) || (h > 1024)) + return BadAlloc; + + w = (w + 1) & ~1; + pitch = ((w << 1) + 15) & ~15; + fbpitch = pScrni->bitsPerPixel * pScrni->displayWidth >> 3; + numlines = ((pitch * h) + fbpitch - 1) / fbpitch; + + if (!(area = GXAllocateMemory(pScrni, NULL, numlines))) + return BadAlloc; + + surface->width = w; + surface->height = h; + + if (!(surface->pitches = xalloc(sizeof(int)))) + return BadAlloc; + if (!(surface->offsets = xalloc(sizeof(int)))) { + xfree(surface->pitches); + return BadAlloc; + } + if (!(pPriv = xalloc(sizeof(OffscreenPrivRec)))) { + xfree(surface->pitches); + xfree(surface->offsets); + return BadAlloc; + } + + pPriv->area = area; + pPriv->isOn = FALSE; + + surface->pScrn = pScrni; + surface->id = id; + surface->pitches[0] = pitch; + surface->offsets[0] = area->box.y1 * fbpitch; + surface->devPrivate.ptr = (pointer) pPriv; + + return Success; +} + +static int +GXStopSurface(XF86SurfacePtr surface) +{ + OffscreenPrivPtr pPriv = (OffscreenPrivPtr) surface->devPrivate.ptr; + + if (pPriv->isOn) { + pPriv->isOn = FALSE; + } + + return Success; +} + +static int +GXFreeSurface(XF86SurfacePtr surface) +{ + OffscreenPrivPtr pPriv = (OffscreenPrivPtr) surface->devPrivate.ptr; + + if (pPriv->isOn) + GXStopSurface(surface); + xf86FreeOffscreenArea(pPriv->area); + xfree(surface->pitches); + xfree(surface->offsets); + xfree(surface->devPrivate.ptr); + + return Success; +} + +static int +GXGetSurfaceAttribute(ScrnInfoPtr pScrni, Atom attribute, INT32 * value) +{ + return GXGetPortAttribute(pScrni, attribute, value, + (pointer) (GET_PORT_PRIVATE(pScrni))); +} + +static int +GXSetSurfaceAttribute(ScrnInfoPtr pScrni, Atom attribute, INT32 value) +{ + return GXSetPortAttribute(pScrni, attribute, value, + (pointer) (GET_PORT_PRIVATE(pScrni))); +} + +static int +GXDisplaySurface(XF86SurfacePtr surface, + short src_x, short src_y, + short drw_x, short drw_y, + short src_w, short src_h, + short drw_w, short drw_h, RegionPtr clipBoxes) +{ + OffscreenPrivPtr pPriv = (OffscreenPrivPtr) surface->devPrivate.ptr; + ScrnInfoPtr pScrni = surface->pScrn; + GeodePortPrivPtr portPriv = GET_PORT_PRIVATE(pScrni); + INT32 x1, y1, x2, y2; + BoxRec dstBox; + + DEBUGMSG(0, (0, X_NONE, "DisplaySuface\n")); + x1 = src_x; + x2 = src_x + src_w; + y1 = src_y; + y2 = src_y + src_h; + + dstBox.x1 = drw_x; + dstBox.x2 = drw_x + drw_w; + dstBox.y1 = drw_y; + dstBox.y2 = drw_y + drw_h; + + if ((x1 >= x2) || (y1 >= y2)) + return Success; + + dstBox.x1 -= pScrni->frameX0; + dstBox.x2 -= pScrni->frameX0; + dstBox.y1 -= pScrni->frameY0; + dstBox.y2 -= pScrni->frameY0; + + xf86XVFillKeyHelper(pScrni->pScreen, portPriv->colorKey, clipBoxes); + + GXDisplayVideo(pScrni, surface->id, surface->offsets[0], + surface->width, surface->height, surface->pitches[0], + x1, y1, x2, y2, &dstBox, src_w, src_h, drw_w, drw_h); + + pPriv->isOn = TRUE; + if (portPriv->videoStatus & CLIENT_VIDEO_ON) { + REGION_EMPTY(pScrni->pScreen, &portPriv->clip); + UpdateCurrentTime(); + portPriv->videoStatus = FREE_TIMER; + portPriv->freeTime = currentTime.milliseconds + FREE_DELAY; + } + + return Success; +} + +/*---------------------------------------------------------------------------- + * GXInitOffscreenImages + * + * Description :This function sets up the offscreen memory management.It fills + * in the XF86OffscreenImagePtr structure with functions to handle + * offscreen memory operations. + * + * Parameters. + * pScrn :Screen handler pointer having screen information. + * + * Returns : None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ +static void +GXInitOffscreenImages(ScreenPtr pScrn) +{ + XF86OffscreenImagePtr offscreenImages; + + /* need to free this someplace */ + if (!(offscreenImages = xalloc(sizeof(XF86OffscreenImageRec)))) + return; + + offscreenImages[0].image = &Images[0]; + offscreenImages[0].flags = VIDEO_OVERLAID_IMAGES | VIDEO_CLIP_TO_VIEWPORT; + offscreenImages[0].alloc_surface = GXAllocateSurface; + offscreenImages[0].free_surface = GXFreeSurface; + offscreenImages[0].display = GXDisplaySurface; + offscreenImages[0].stop = GXStopSurface; + offscreenImages[0].setAttribute = GXSetSurfaceAttribute; + offscreenImages[0].getAttribute = GXGetSurfaceAttribute; + offscreenImages[0].max_width = 1024; + offscreenImages[0].max_height = 1024; + offscreenImages[0].num_attributes = NUM_ATTRIBUTES; + offscreenImages[0].attributes = Attributes; + + xf86XVRegisterOffscreenImages(pScrn, offscreenImages, 1); +} + +#endif /* !XvExtension */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_shadow.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_shadow.c 2005-08-03 16:35:43.000000000 -0600 @@ -0,0 +1,433 @@ +/* + * $Workfile: amd_lx_shadow.c $ + * $Revision: #3 $ + * $Author: raymondd $ + * + * File Contents: Direct graphics display routines are implemented and + * graphics rendering are all done in memory. + * + * Project: Geode Xfree Frame buffer device driver. + * + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86Resources.h" +#include "xf86_ansic.h" +#include "xf86PciInfo.h" +#include "xf86Pci.h" +#include "amd.h" +#include "shadowfb.h" +#include "servermd.h" + +#define CLIP(sip,bp,u1,v1,u2,v2) \ + u1 = bp->x1; v1 = bp->y1; \ + u2 = bp->x2; v2 = bp->y2; \ + if( u1 < 0 ) u1 = 0; \ + if( v1 < 0 ) v1 = 0; \ + if( u1 > sip->virtualX ) u1 = sip->virtualX; \ + if( v1 > sip->virtualY ) v1 = sip->virtualY; \ + if( u2 < 0 ) u2 = 0; \ + if( v2 < 0 ) v2 = 0; \ + if( u2 > sip->virtualX ) u2 = sip->virtualX; \ + if( v2 > sip->virtualY ) v2 = sip->virtualY; + +void LXAccelSync(ScrnInfoPtr pScrni); + +void +LXRotation0(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = x; + *newY = y; +} + +void +LXRotation1(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = (h-1) - y; + *newY = x; +} + +void +LXRotation2(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = (w-1) - x; + *newY = (h-1) - y; +} + +void +LXRotation3(int x,int y,int w,int h,int *newX,int *newY) +{ + *newY = (w-1) - x; + *newX = y; +} + +void +LXRBltXlat0(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = x; + *newY = y; +} + +void +LXRBltXlat1(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = x - (h-1); + *newY = y; +} + +void +LXRBltXlat2(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = x - (w-1); + *newY = y - (h-1); +} + +void +LXRBltXlat3(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = x; + *newY = y - (w-1); +} + +/*---------------------------------------------------------------------------- + * LXPointerMoved. + * + * Description :This function moves one screen memory from one area to other. + * + * Parameters. + * index :Pointer to screen index. + * x :Specifies the new x co-ordinates of new area. + * y :Specifies the new y co-ordinates of new area. + * Returns :none + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +void +LXPointerMoved(int index, int x, int y) +{ + ScrnInfoPtr pScrni = xf86Screens[index]; + GeodePtr pGeode = GEODEPTR(pScrni); + Bool frameChanged = FALSE; + + if( x < 0 ) + x = 0; + else if( x >= pScrni->virtualX ) + x = pScrni->virtualX-1; + if( y < 0 ) + y = 0; + else if( y >= pScrni->virtualY ) + y = pScrni->virtualY-1; + + if( pScrni->frameX0 > x ) { + pScrni->frameX0 = x; + pScrni->frameX1 = x + pGeode->HDisplay - 1; + frameChanged = TRUE ; + } + + if( pScrni->frameX1 < x ) { + pScrni->frameX1 = x + 1; + pScrni->frameX0 = x - pGeode->HDisplay + 1; + frameChanged = TRUE ; + } + + if( pScrni->frameY0 > y ) { + pScrni->frameY0 = y; + pScrni->frameY1 = y + pGeode->VDisplay - 1; + frameChanged = TRUE; + } + + if( pScrni->frameY1 < y ) { + pScrni->frameY1 = y; + pScrni->frameY0 = y - pGeode->VDisplay + 1; + frameChanged = TRUE; + } + + if(frameChanged && pScrni->AdjustFrame != NULL) + pScrni->AdjustFrame(pScrni->scrnIndex, pScrni->frameX0, pScrni->frameY0, 0); +} + +void +LXRefreshArea_Cpy(ScrnInfoPtr pScrni, int num, BoxPtr pbox) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + int x1, y1, x2, y2, width, height; + unsigned long src, dst; + int Bpp = pScrni->bitsPerPixel >> 3; + gp_declare_blt(0); + gp_set_raster_operation(0xcc); /* copy dst=src */ + gp_write_parameters(); + for( ; --num>=0; ++pbox ) { + CLIP(pScrni,pbox,x1,y1,x2,y2); + if( (width=x2-x1) <=0 || (height=y2-y1) <= 0 ) continue; + src = y1*pGeode->ShadowPitch + x1*Bpp; + dst = pGeode->FBOffset + y1*pGeode->Pitch + x1*Bpp; + gp_declare_blt(0); + gp_set_strides(pGeode->Pitch, pGeode->ShadowPitch); + gp_screen_to_screen_blt(dst,src, width,height, 0); + } +} + +/*---------------------------------------------------------------------------- + * LXRefreshArea8. + * + * Description :This function copies the memory to be displayed from the + * shadow pointer by 8bpp. + * Parameters. + * pScrni :Pointer to ScrnInfo structure. + * num :Specifies the num of squarebox area to be displayed. + * pbox :Points to square of memory to be displayed. + * Returns :none + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ + +static int lx_shdw_fmt[4] = { + CIMGP_SOURCE_FMT_3_3_2, + CIMGP_SOURCE_FMT_0_5_6_5, + CIMGP_SOURCE_FMT_24BPP, + CIMGP_SOURCE_FMT_8_8_8_8 +}; + + +void +LXRefreshArea_Blt(ScrnInfoPtr pScrni, int num, BoxPtr pbox) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + int width, height, x1, y1, x2, y2, newX, newY; + unsigned long src, dst; + int Bpp = pScrni->bitsPerPixel >> 3; + gp_set_source_format(lx_shdw_fmt[Bpp-1]); + gp_declare_blt(0); + gp_set_raster_operation(0xcc); /* copy dst=src */ + gp_write_parameters(); + for( ; --num>=0; ++pbox ) { + CLIP(pScrni,pbox,x1,y1,x2,y2); + if( (width=x2-x1) <=0 || (height=y2-y1) <= 0 ) continue; + (*pGeode->Rotation)(x1,y1,pScrni->virtualX,pScrni->virtualY,&newX,&newY); + (*pGeode->RBltXlat)(newX,newY,width,height,&newX,&newY); + src = y1*pGeode->ShadowPitch + x1*Bpp; + dst = pGeode->FBOffset + newY*pGeode->Pitch + newX*Bpp; + gp_declare_blt(0); + gp_set_strides(pGeode->Pitch, pGeode->ShadowPitch); + gp_rotate_blt(dst,src, width,height, pGeode->Rotate*90); + } +} + +void +LXRefreshArea0_Cpu(ScrnInfoPtr pScrni, int num, BoxPtr pbox) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + int width, height, x1, y1, x2, y2; + unsigned char *src, *dst; + int Bpp = pScrni->bitsPerPixel >> 3; + LXAccelSync(pScrni); + for( ; --num>=0; ++pbox ) { + CLIP(pScrni,pbox,x1,y1,x2,y2); + if( (width=x2-x1) <=0 || (height=y2-y1) <= 0 ) continue; + src = pGeode->ShadowPtr + y1*pGeode->ShadowPitch + x1*Bpp; + dst = pGeode->FBBase+pGeode->FBOffset + y1*pGeode->Pitch + x1*Bpp; + width *= Bpp; + while( --height >= 0 ) { + memcpy(dst,src,width); + dst += pGeode->Pitch; + src += pGeode->ShadowPitch; + } + } +} + +#define RefreshArea1_Cpu(nm,typ) \ +void LXRefreshArea1_Cpu##nm(ScrnInfoPtr pScrni, int num, BoxPtr pbox)\ +{ \ + GeodePtr pGeode = GEODEPTR(pScrni); \ + int l, width, height, x1, y1, x2, y2, newX, newY; \ + unsigned long src, dst, dp; \ + typ *sp; \ + LXAccelSync(pScrni); \ + for( ; --num>=0; ++pbox ) { \ + CLIP(pScrni,pbox,x1,y1,x2,y2); \ + if( (width=x2-x1) <=0 || (height=y2-y1) <= 0 ) continue; \ + src = y1*pGeode->ShadowPitch + x1*sizeof(typ); \ + newX = pScrni->virtualY-1 - y1; \ + newY = x1; \ + dst = pGeode->FBOffset + newY*pGeode->Pitch + newX*sizeof(typ); \ + while( --height >= 0 ) { \ + sp = (typ *)(pGeode->ShadowPtr + src); \ + dp = (unsigned long)(pGeode->FBBase + dst); \ + for( l=width; --l>=0; ) { \ + *(typ *)dp = *sp++; \ + dp += pGeode->Pitch; \ + } \ + dst -= sizeof(typ); \ + src += pGeode->ShadowPitch; \ + } \ + } \ +} + +RefreshArea1_Cpu( 8,unsigned char) +RefreshArea1_Cpu(16,unsigned short) +RefreshArea1_Cpu(32,unsigned int) + +#define RefreshArea2_Cpu(nm,typ) \ +void LXRefreshArea2_Cpu##nm(ScrnInfoPtr pScrni, int num, BoxPtr pbox)\ +{ \ + GeodePtr pGeode = GEODEPTR(pScrni); \ + int l, width, height, x1, y1, x2, y2, newX, newY; \ + unsigned long src, dst, dp; \ + typ *sp; \ + LXAccelSync(pScrni); \ + for( ; --num>=0; ++pbox ) { \ + CLIP(pScrni,pbox,x1,y1,x2,y2); \ + if( (width=x2-x1) <=0 || (height=y2-y1) <= 0 ) continue; \ + src = y1*pGeode->ShadowPitch + x1*sizeof(typ); \ + newX = pScrni->virtualX-1 - x1; \ + newY = pScrni->virtualY-1 - y1; \ + dst = pGeode->FBOffset + newY*pGeode->Pitch + newX*sizeof(typ); \ + while( --height >= 0 ) { \ + sp = (typ *)(pGeode->ShadowPtr + src); \ + dp = (unsigned long)(pGeode->FBBase + dst); \ + for( l=width; --l>=0; ) { \ + *(typ *)dp = *sp++; \ + dp -= sizeof(typ); \ + } \ + src += pGeode->ShadowPitch; \ + dst -= pGeode->Pitch; \ + } \ + } \ +} + +RefreshArea2_Cpu( 8,unsigned char) +RefreshArea2_Cpu(16,unsigned short) +RefreshArea2_Cpu(32,unsigned int) + +#define RefreshArea3_Cpu(nm,typ) \ +void LXRefreshArea3_Cpu##nm(ScrnInfoPtr pScrni, int num, BoxPtr pbox)\ +{ \ + GeodePtr pGeode = GEODEPTR(pScrni); \ + int l, width, height, x1, y1, x2, y2, newX, newY; \ + unsigned long src, dst, dp; \ + typ *sp; \ + LXAccelSync(pScrni); \ + for( ; --num>=0; ++pbox ) { \ + CLIP(pScrni,pbox,x1,y1,x2,y2); \ + if( (width=x2-x1) <=0 || (height=y2-y1) <= 0 ) continue; \ + src = y1*pGeode->ShadowPitch + x1*sizeof(typ); \ + newX = y1; \ + newY = pScrni->virtualX-1 - x1; \ + dst = pGeode->FBOffset + newY*pGeode->Pitch + newX*sizeof(typ); \ + while( --height >= 0 ) { \ + sp = (typ *)(pGeode->ShadowPtr + src); \ + dp = (unsigned long)(pGeode->FBBase + dst); \ + for( l=width; --l>=0; ) { \ + *(typ *)dp = *sp++; \ + dp -= pGeode->Pitch; \ + } \ + dst += sizeof(typ); \ + src += pGeode->ShadowPitch; \ + } \ + } \ +} + +RefreshArea3_Cpu( 8,unsigned char) +RefreshArea3_Cpu(16,unsigned short) +RefreshArea3_Cpu(32,unsigned int) + +void +LXRotationInit(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + switch( pGeode->Rotate ) { + case 1: + pGeode->Rotation = LXRotation1; + pGeode->RBltXlat = LXRBltXlat1; + break; + case 2: + pGeode->Rotation = LXRotation2; + pGeode->RBltXlat = LXRBltXlat2; + break; + case 3: + pGeode->Rotation = LXRotation3; + pGeode->RBltXlat = LXRBltXlat3; + break; + default: + pGeode->Rotation = LXRotation0; + pGeode->RBltXlat = LXRBltXlat0; + break; + } +} + +void +LXShadowFBInit(ScreenPtr pScrn,GeodePtr pGeode,int bytpp) +{ + RefreshAreaFuncPtr refreshArea; + if( pGeode->NoAccel || !pGeode->ShadowInFBMem || 0 ) { + switch( bytpp ) { + case 2: + switch( pGeode->Rotate ) { + case 1: refreshArea = LXRefreshArea1_Cpu16; break; + case 2: refreshArea = LXRefreshArea2_Cpu16; break; + case 3: refreshArea = LXRefreshArea3_Cpu16; break; + default: refreshArea = LXRefreshArea0_Cpu; break; + } + break; + case 4: + switch( pGeode->Rotate ) { + case 1: refreshArea = LXRefreshArea1_Cpu32; break; + case 2: refreshArea = LXRefreshArea2_Cpu32; break; + case 3: refreshArea = LXRefreshArea3_Cpu32; break; + default: refreshArea = LXRefreshArea0_Cpu; break; + } + break; + default: + switch( pGeode->Rotate ) { + case 1: refreshArea = LXRefreshArea1_Cpu8; break; + case 2: refreshArea = LXRefreshArea2_Cpu8; break; + case 3: refreshArea = LXRefreshArea3_Cpu8; break; + default: refreshArea = LXRefreshArea0_Cpu; break; + } + break; + } + } + else { + refreshArea = pGeode->Rotate? LXRefreshArea_Blt : LXRefreshArea_Cpy; + } + ShadowFBInit(pScrn, refreshArea); +} + +/* End of file */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/mak.sh 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/mak.sh 2005-07-13 13:16:49.000000000 -0600 @@ -0,0 +1 @@ +gcc -m32 -O2 -pipe -march=i386 -mcpu=i686 -fno-strength-reduce -fno-strict-aliasing -pipe -ansi -pedantic -Wall -Wpointer-arith -Wundef -fno-merge-constants -I. -I../../../../../../programs/Xserver/hw/xfree86/common -I../../../../../../programs/Xserver/hw/xfree86/os-support -I../../../../../../programs/Xserver/Xext -I../../../../../../programs/Xserver/mfb -I../../../../../../programs/Xserver/mi -I../../../../../../programs/Xserver/cfb -I../../../../../../programs/Xserver/fb -I../../../../../../programs/Xserver/hw/xfree86/xaa -I../../../../../../programs/Xserver/hw/xfree86/vgahw -I../../../../../../programs/Xserver/hw/xfree86/ramdac -I../../../../../../programs/Xserver/hw/xfree86/ddc -I../../../../../../programs/Xserver/hw/xfree86/i2c -I../../../../../../programs/Xserver/hw/xfree86/rac -I../../../../../../programs/Xserver/hw/xfree86/int10 -I../../../../../../programs/Xserver/hw/xfree86/xf24_32bpp -I../../../../../../include/fonts -I../../../../../../programs/Xserver/hw/xfree86/xf8_32bpp -I../../../../../../programs/Xserver/hw/xfree86/xf1bpp -I../../../../../../programs/Xserver/hw/xfree86/xf4bpp -I../../../../../../programs/Xserver/include -I../../../../../../exports/include/X11 -I../../../../../../programs/Xserver/hw/xfree86/ddc -I../../../../../../programs/Xserver/hw/xfree86/i2c -I../../../../../../include/extensions -I../../../../../../programs/Xserver/hw/xfree86/shadowfb -I../../../../../../programs/Xserver/hw/xfree86/fbdevhw -I../../../../../../include -I../../../../../../programs/Xserver/hw/xfree86/vbe -I../../../../../../programs/Xserver/render -I./cim -I../../../../../.. -I../../../../../../exports/include -Dlinux -D__i386__ -D_POSIX_C_SOURCE=199309L -D_POSIX_SOURCE -D_XOPEN_SOURCE -D_BSD_SOURCE -D_SVID_SOURCE -D_GNU_SOURCE -DSHAPE -DXINPUT -DXKB -DLBX -DXAPPGROUP -DXCSECURITY -DTOGCUP -DXF86BIGFONT -DDPMSExtension -DPIXPRIV -DPANORAMIX -DRENDER -DRANDR -DGCCUSESGAS -DAVOID_GLYPHBLT -DPIXPRIV -DSINGLEDEPTH -DXFreeXDGA -DXvExtension -DXFree86LOADER -DXFree86Server -DXF86VIDMODE -DXvMCExtension -DSMART_SCHEDULE -DBUILDDEBUG -DXResExtension -DX_BYTE_ORDER=X_LITTLE_ENDIAN -DNDEBUG -DFUNCPROTO=15 -DNARROWPROTO -DIN_MODULE -DXFree86Module -DLX_2DOT0_SWAPSIF=1 -DREAL_SILICON=1 -c z4l.c --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_regacc.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_regacc.c 2005-07-13 13:16:49.000000000 -0600 @@ -0,0 +1,71 @@ +/* + * $Workfile: amd_regacc.c $ + * $Revision: #2 $ + * $Author: raymondd $ + * + * This is the main file used to add Cimarron graphics support to a software + * project. The main reason to have a single file include the other files + * is that it centralizes the location of the compiler options. This file + * should be tuned for a specific implementation, and then modified as needed + * for new Cimarron releases. The releases.txt file indicates any updates to + * this main file, such as a new definition for a new hardware platform. + * + * In other words, this file should be copied from the Cimarron source files + * once when a software project starts, and then maintained as necessary. + * It should not be recopied with new versions of Cimarron unless the + * developer is willing to tune the file again for the specific project. + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +#include "cim_defs.h" + +extern unsigned char *cim_vid_ptr; + +void cim_write_vid32(unsigned long offset, unsigned long value); +unsigned long cim_read_vid32(unsigned long offset); + + void +cim_write_vid32(unsigned long offset, unsigned long value) +{ + WRITE_VID32(offset, value); +} +unsigned long +cim_read_vid32(unsigned long offset) +{ + unsigned long value; + + value = READ_VID32(offset); + return value; +} + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_accel.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_accel.c 2005-08-03 14:55:35.000000000 -0600 @@ -0,0 +1,1461 @@ +/* + * $Workfile: amd_lx_accel.c $ + * $Revision: #4 $ + * $Author: billm $ + * + * File Contents: This file is consists of main Xfree + * acceleration supported routines like solid fill used + * here. + * Project: Geode Xfree Frame buffer device driver. + * + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +/* Xfree86 header files */ + +#include "vgaHW.h" +#include "xf86.h" +#include "xf86_ansic.h" +#include "xaalocal.h" +#include "xf86fbman.h" +#include "miline.h" +#include "xf86_libc.h" +#include "xaarop.h" +#include "amd.h" + +#undef ulong +typedef unsigned long ulong; +#undef uint +typedef unsigned int uint; +#undef ushort +typedef unsigned short ushort; +#undef uchar +typedef unsigned char uchar; + +#if DEBUGLVL>0 +extern FILE *zdfp; +#if DEBUGTIM>0 +#ifndef USE_RDTSC +#define DBLOG(n,s...) do { if((DEBUGLVL)>=(n)) { long secs,usecs; \ + getsecs(&secs,&usecs); fprintf(zdfp,"%d,%d ",secs,usecs); \ + fprintf(zdfp,s); } } while(0) +#else +#define tsc(n) __asm__ __volatile__ ( \ + " rdtsc" \ + : "=a" (((int*)(&(n)))[0]), "=d" (((int*)(&(n)))[1]) \ + : ) +#define DBLOG(n,s...) do { if((DEBUGLVL)>=(n)) { long long t; \ + tsc(t); fprintf(zdfp,"%lld ",t); \ + fprintf(zdfp,s); } } while(0) +#endif +#else +#define DBLOG(n,s...) do { if((DEBUGLVL)>=(n)) fprintf(zdfp,s); } while(0) +#endif +#else +#define DBLOG(n,s...) do {} while(0) +#endif + +#define CALC_FBOFFSET(x, y) \ + (((ulong)(y) << gu3_yshift) | \ + ((ulong)(x) << gu3_xshift)) + +#define OS_UDELAY 0 +#if OS_UDELAY > 0 +#define OS_USLEEP(usec) usleep(usec); +#else +#define OS_USLEEP(usec) +#endif + +#define HOOK(fn) localRecPtr->fn = LX##fn + +static int lx0 = -1, ly0 = -1; +static int lx1 = -1, ly1 = -1; +static int ROP; + +/* #define ENABLE_PREFETCH CIMGP_ENABLE_PREFETCH */ +#define ENABLE_PREFETCH 0 +#define BLTFLAGS_HAZARD CIMGP_BLTFLAGS_HAZARD + +/* specify dst bounding box, upper left/lower right */ +static int +lx_flags0(int x0,int y0, int x1,int y1) +{ + int n = ((ROP^(ROP>>1))&0x55) == 0 || /* no dst */ + x0 >= lx1 || y0 >= ly1 || /* rght/below */ + x1 <= lx0 || y1 <= ly0 ? /* left/above */ + ENABLE_PREFETCH : BLTFLAGS_HAZARD ; + lx0 = x0; ly0 = y0; lx1 = x1; ly1 = y1; + return n; +} + +/* specify dst bounding box, upper left/WxH */ +static int +lx_flags1(int x0,int y0, int w,int h) +{ + return lx_flags0(x0,y0, x0+w,y0+h); +} + +/* specify dst bounding box, two points */ +static int +lx_flags2(int x0,int y0, int x1,int y1) +{ + int n; + if( x0 >= x1 ) { n = x0; x0 = x1-1; x1 = n+1; } + if( y0 >= y1 ) { n = y0; y0 = y1-1; y1 = n+1; } + return lx_flags0(x0,y0, x1,y1); +} + +/* specify src/dst bounding box, upper left/WxH */ +static int +lx_flags3(int x0,int y0, int x1,int y1, int w,int h) +{ + int x2 = x1+w, y2 = y1+h; + /* dst not hazzard and src not hazzard */ + int n = ( ((ROP^(ROP>>1))&0x55) == 0 || + x1 >= lx1 || y1 >= ly1 || + x2 <= lx0 || y2 <= ly0 ) && + ( ((ROP^(ROP>>2))&0x33) == 0 || + x0 >= lx1 || y0 >= ly1 || + x0+w <= lx0 || y0+h <= ly0 ) ? + ENABLE_PREFETCH : BLTFLAGS_HAZARD; + lx0 = x1; ly0 = y1; lx1 = x2; ly1 = y2; + return n; +} + +static void +lx_endpt(int x,int y,int len, int mag,int min,int err,int oct, int *px, int *py) +{ + int u = len-1; + int v = (u*min-err)/mag; + + switch( oct ) { + default: + case 0: x += u; y += v; break; + case 1: x += v; y += u; break; + case 2: x += u; y -= v; break; + case 3: x += v; y -= u; break; + case 4: x -= u; y += v; break; + case 5: x -= v; y += u; break; + case 6: x -= u; y -= v; break; + case 7: x -= v; y -= u; break; + } + *px = x; *py = y; +} + +/* static storage declarations */ + +typedef struct sGBltBox { + ulong x, y; + ulong w, h; + ulong color; + int bpp, transparent; +} GBltBox; + +static GBltBox giwr; +static GBltBox gc2s; + +typedef struct sGDashLine { + ulong pat; + int len; + int fg; + int bg; +} GDashLine; + +static GDashLine gdln; + +static uint gu3_xshift = 1; +static uint gu3_yshift = 1; +static uint gu3_img_fmt = 0; +#if !LX_USE_OFFSCRN_MEM +static uint ImgBufOffset; +#else +static uchar *ImgLnsBuffers; +#endif +static uchar *ClrLnsBuffers; +static XAAInfoRecPtr localRecPtr; + +static int lx_src_fmt[4] = { + CIMGP_SOURCE_FMT_8BPP_INDEXED, + CIMGP_SOURCE_FMT_0_5_6_5, + CIMGP_SOURCE_FMT_24BPP, + CIMGP_SOURCE_FMT_8_8_8_8 +}; + + +/* pat 0xF0 */ +/* src 0xCC */ +/* dst 0xAA */ + +/* (src FUNC dst) */ + +static const int SDfn[16] = { + 0x00, 0x88, 0x44, 0xCC, 0x22, 0xAA, 0x66, 0xEE, + 0x11, 0x99, 0x55, 0xDD, 0x33, 0xBB, 0x77, 0xFF +}; + +/* ((src FUNC dst) AND pat-mask) OR (dst AND (NOT pat-mask)) */ + +static const int SDfn_PM[16] = { + 0x0A, 0x8A, 0x4A, 0xCA, 0x2A, 0xAA, 0x6A, 0xEA, + 0x1A, 0x9A, 0x5A, 0xDA, 0x3A, 0xBA, 0x7A, 0xFA +}; + +/* (pat FUNC dst) */ + +static int PDfn[16] = { + 0x00, 0xA0, 0x50, 0xF0, 0x0A, 0xAA, 0x5A, 0xFA, + 0x05, 0xA5, 0x55, 0xF5, 0x0F, 0xAF, 0x5F, 0xFF +}; + +/* ((pat FUNC dst) AND src-mask) OR (dst AND (NOT src-mask)) */ + +static int PDfn_SM[16] = { + 0x22, 0xA2, 0x62, 0xE2, 0x2A, 0xAA, 0x6A, 0xEA, + 0x26, 0xA6, 0x66, 0xE6, 0x2E, 0xAE, 0x6E, 0xEE +}; + + + +/*---------------------------------------------------------------------------- + * LXAccelSync. + * + * Description :This function is called to synchronize with the graphics + * engine and it waits the graphic engine is idle. This is + * required before allowing direct access to the framebuffer. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * + * Returns :none + *---------------------------------------------------------------------------*/ +void +LXAccelSync(ScrnInfoPtr pScrni) +{ + DBLOG(3,"LXAccelSync()\n"); + while( gp_test_blt_busy() != 0 ) { OS_USLEEP(OS_UDELAY) } +} + +#if LX_FILL_RECT_SUPPORT +/*---------------------------------------------------------------------------- + * LXSetupForSolidFill. + * + * Description :The SetupFor and Subsequent SolidFill(Rect) provide + * filling rectangular areas of the screen with a + * foreground color. + * + * Parameters. + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * color int foreground fill color + * rop int unmapped raster op + * planemask uint -1 (fill) or pattern data + * + * Returns :none + *--------------------------------------------------------------------------*/ +static void +LXSetupForSolidFill(ScrnInfoPtr pScrni, int color, int rop, uint planemask) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"LXSetupForSolidFill(%#x,%#x,%#x)\n",color,rop,planemask); + rop &= 0x0F; + gp_declare_blt(0); + if( planemask == ~0U ) { /* fill with color */ + gp_set_raster_operation(ROP=SDfn[rop]); + } + else { /* select rop that uses source data for planemask */ + gp_set_raster_operation(ROP=SDfn_PM[rop]); + gp_set_solid_pattern(planemask); + } + gp_set_solid_source(color); + gp_set_strides(pGeode->AccelPitch,pGeode->AccelPitch); + gp_write_parameters(); +} + + /*---------------------------------------------------------------------------- + * LXSubsequentSolidFillRect. + * + * Description :see LXSetupForSolidFill. + * + * Parameters. + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x int destination x offset + * y int destination y offset + * w int fill area width (pixels) + * h int fill area height (pixels) + * + * Returns :none + * + * Sample application uses: + * - Window backgrounds. + * - pull down highlighting. + * - x11perf: rectangle tests (-rect500). + * - x11perf: fill trapezoid tests (-trap100). + * - x11perf: horizontal line segments (-hseg500). + *---------------------------------------------------------------------------*/ +static void +LXSubsequentSolidFillRect(ScrnInfoPtr pScrni, int x, int y, int w, int h) +{ + int flags; + DBLOG(2,"LXSubsequentSolidFillRect() at %d,%d %dx%d\n",x,y,w,h); + flags = lx_flags1(x,y,w,h); + gp_declare_blt(flags); + gp_pattern_fill(CALC_FBOFFSET(x,y), w, h); +} + +/* LX_FILL_RECT_SUPPORT */ +#endif + +#if LX_CLREXP_8X8_PAT_SUPPORT +/*---------------------------------------------------------------------------- + * LXSetupForColor8x8PatternFill + * + * Description :8x8 color pattern data is 64 pixels of full color data + * stored linearly in offscreen video memory. These patterns + * are useful as a substitute for 8x8 mono patterns when tiling, + * doing opaque stipples, or regular stipples. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * patx int x offset to pattern data + * paty int y offset to pattern data + * rop int unmapped raster operation + * planemask uint -1 (copy) or pattern data + * trans_color int -1 (copy) or transparent color (not enabled) + * trans color only supported on source channel + * or in monochrome pattern channel + * + * Returns :none. + * + *---------------------------------------------------------------------------*/ + +static void +LXSetupForColor8x8PatternFill(ScrnInfoPtr pScrni, int patx, int paty, int rop, + uint planemask, int trans_color) +{ + unsigned long *pat_8x8; + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"LXSetupForColor8x8PatternFill() pat %#x,%#x rop %#x %#x %#x\n" + ,patx,paty,rop,planemask,trans_color); + pat_8x8 = (unsigned long *)(pGeode->FBBase+CALC_FBOFFSET(patx,paty)); + /* since the cache may be loaded by blt, we must wait here */ + LXAccelSync(pScrni); + gp_set_color_pattern(pat_8x8,gu3_img_fmt,0,0); + rop &= 0x0F; + gp_declare_blt(0); + if( planemask == ~0U ) { /* fill with pattern */ + gp_set_raster_operation(ROP=PDfn[rop]); + } + else { /* select rop that uses source data for planemask */ + gp_set_raster_operation(ROP=PDfn_SM[rop]); + gp_set_solid_source((ulong)planemask); + } + gp_set_strides(pGeode->AccelPitch,pGeode->AccelPitch); + gp_write_parameters(); +} + +/*---------------------------------------------------------------------------- + * LXSubsequentColor8x8PatternFillRect + * + * Description :see LXSetupForColor8x8PatternFill. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * patx int pattern phase x offset + * paty int pattern phase y offset + * x int destination x offset + * y int destination y offset + * w int fill area width (pixels) + * h int fill area height (pixels) + * + * Returns :none + * + * Sample application uses: + * - Patterned desktops + * - x11perf: stippled rectangle tests (-srect500). + * - x11perf: opaque stippled rectangle tests (-osrect500). + *--------------------------------------------------------------------------*/ +static void +LXSubsequentColor8x8PatternFillRect(ScrnInfoPtr pScrni, int patx, int paty, + int x, int y, int w, int h) +{ + int flags; + DBLOG(2,"LXSubsequentColor8x8PatternFillRect() patxy %d,%d at %d,%d %dsx%d\n", + patx,paty,x,y,w,h); + flags = lx_flags1(x,y,w,h); + gp_declare_blt(flags); + gp_set_pattern_origin(patx,paty); + gp_pattern_fill(CALC_FBOFFSET(x,y), w, h); +} + +/* LX_CLREXP_8X8_PAT_SUPPORT */ +#endif + +#if LX_MONO_8X8_PAT_SUPPORT +/*---------------------------------------------------------------------------- + * LXSetupForMono8x8PatternFill + * + * Description :8x8 mono pattern data is 64 bits of color expansion data + * with ones indicating the foreground color and zeros + * indicating the background color. These patterns are + * useful when tiling, doing opaque stipples, or regular + * stipples. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * patx int x offset to pattern data + * paty int y offset to pattern data + * fg int foreground color + * bg int -1 (transparent) or background color + * rop int unmapped raster operation + * planemask uint -1 (copy) or pattern data + * + * Returns :none. + * + * Comments :none. + * + *--------------------------------------------------------------------------*/ +static void +LXSetupForMono8x8PatternFill(ScrnInfoPtr pScrni, int patx, int paty, + int fg, int bg, int rop, uint planemask) +{ + int trans; + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"LXSetupForMono8x8PatternFill() pat %#x,%#x fg %#x bg %#x %#x %#x\n", + patx,paty,fg,bg,rop,planemask); + rop &= 0x0F; + gp_declare_blt(0); + if( planemask == ~0U ) { /* fill with pattern */ + gp_set_raster_operation(ROP=PDfn[rop]); + } + else { /* select rop that uses source data for planemask */ + gp_set_raster_operation(ROP=PDfn_SM[rop]); + gp_set_solid_source((ulong)planemask); + } + trans = bg==-1 ? 1 : 0; + gp_set_mono_pattern(bg,fg, patx,paty, trans, 0, 0); + gp_set_strides(pGeode->AccelPitch,pGeode->AccelPitch); + gp_write_parameters(); +} + +/*---------------------------------------------------------------------------- + * LXSubsequentMono8x8PatternFillRect + * + * Description :see LXSetupForMono8x8PatternFill + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * patx int pattern phase x offset + * paty int pattern phase y offset + * x int destination x offset + * y int destination y offset + * w int fill area width (pixels) + * h int fill area height (pixels) + + * Returns :none + * + * Sample application uses: + * - Patterned desktops + * - x11perf: stippled rectangle tests (-srect500). + * - x11perf: opaque stippled rectangle tests (-osrect500). + *--------------------------------------------------------------------------*/ +static void +LXSubsequentMono8x8PatternFillRect(ScrnInfoPtr pScrni, int patx, int paty, + int x, int y, int w, int h) +{ + int flags; + DBLOG(2,"LXSubsequentMono8x8PatternFillRect() pat %#x,%#x at %d,%d %dx%d\n",patx,paty,x,y,w,h); + flags = lx_flags1(x,y,w,h); + gp_declare_blt(flags); + gp_set_pattern_origin(patx,paty); + gp_pattern_fill(CALC_FBOFFSET(x,y), w,h); +} + +/* LX_MONO_8X8_PAT_SUPPORT */ +#endif + +#if LX_SCR2SCRCPY_SUPPORT +/*---------------------------------------------------------------------------- + * LXSetupForScreenToScreenCopy + * + * Description :SetupFor and Subsequent ScreenToScreenCopy functions + * provide an interface for copying rectangular areas from + * video memory to video memory. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * xdir int x copy direction (up/dn) + * ydir int y copy direction (up/dn) + * rop int unmapped raster operation + * planemask uint -1 (copy) or pattern data + * trans_color int -1 (copy) or transparent color + * + * Returns :none + *---------------------------------------------------------------------------*/ +static void +LXSetupForScreenToScreenCopy(ScrnInfoPtr pScrni, int xdir, int ydir, int rop, + uint planemask, int trans_color) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"LXSetupForScreenToScreenCopy() xd%d yd%d rop %#x %#x %#x\n", + xdir,ydir,rop,planemask,trans_color); + rop &= 0x0F; + gp_declare_blt(0); + if( planemask == ~0U ) { + gp_set_raster_operation(ROP=SDfn[rop]); + } + else { + gp_set_raster_operation(ROP=SDfn_PM[rop]); + gp_set_solid_pattern((ulong)planemask); + } + gp_set_strides(pGeode->AccelPitch, pGeode->AccelPitch); + gp_write_parameters(); + gc2s.transparent = (trans_color == -1) ? 0 : 1; + gc2s.color = trans_color; +} + +/*---------------------------------------------------------------------------- + * LXSubsquentScreenToScreenCopy + * + * Description :see LXSetupForScreenToScreenCopy. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x1 int source x offset + * y1 int source y offset + * x2 int destination x offset + * y2 int destination y offset + * w int copy area width (pixels) + * h int copy area height (pixels) + * + * Returns :none + * + * Sample application uses (non-transparent): + * - Moving windows. + * - x11perf: scroll tests (-scroll500). + * - x11perf: copy from window to window (-copywinwin500). + *---------------------------------------------------------------------------*/ +static void +LXSubsequentScreenToScreenCopy(ScrnInfoPtr pScrni, + int x1, int y1, int x2, int y2, int w, int h) +{ + int flags; + DBLOG(2,"LXSubsequentScreenToScreenCopy() from %d,%d to %d,%d %dx%d\n",x1,y1,x2,y2,w,h); + flags = lx_flags3(x1,y1,x2,y2,w,h); + gp_declare_blt(flags); + if( gc2s.transparent ) { + gp_set_source_transparency(gc2s.color,~0); + } + flags = 0; + if( x2 > x1 ) flags |= 1; + if( y2 > y1 ) flags |= 2; + gp_screen_to_screen_blt(CALC_FBOFFSET(x2,y2), CALC_FBOFFSET(x1,y1), w,h, flags); +} + +/* LX_SCR2SCRCPY_SUPPORT */ +#endif + +#if LX_SCANLINE_SUPPORT +/*---------------------------------------------------------------------------- + * LXSetupForScanlineImageWrite + * + * Description :SetupFor/Subsequent ScanlineImageWrite and ImageWriteScanline + * transfer full color pixel data from system memory to video + * memory. This is useful for dealing with alignment issues and + * performing raster ops on the data. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * rop int unmapped raster operation + * planemask uint -1 (copy) or pattern data + * bpp int bits per pixel (unused) + * depth int color depth (unused) + * + * Returns :none + * + * x11perf -putimage10 + * x11perf -putimage100 + * x11perf -putimage500 +*---------------------------------------------------------------------------- +*/ +static void +LXSetupForScanlineImageWrite(ScrnInfoPtr pScrni, int rop, uint planemask, + int trans_color, int bpp, int depth) +{ + int Bpp = (bpp+7) >> 3; + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"LXSetupForScanlineImageWrite() rop %#x %#x %#x %d %d\n", + rop,planemask,trans_color,bpp,depth); + rop &= 0x0F; + gp_set_source_format(lx_src_fmt[Bpp-1]); + gp_declare_blt(0); + if( planemask == ~0U ) { + gp_set_raster_operation(ROP=SDfn[rop]); + } + else { + gp_set_raster_operation(ROP=SDfn_PM[rop]); + gp_set_solid_pattern(planemask); + } + gp_set_strides(pGeode->AccelPitch,pGeode->AccelPitch); + gp_write_parameters(); + giwr.transparent = (trans_color == -1) ? 0 : 1; + giwr.color = trans_color; +} + +/*---------------------------------------------------------------------------- + * LXSubsequentScanlineImageWriteRect + * + * Description : see LXSetupForScanlineImageWrite. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x int destination x offset + * y int destination y offset + * w int copy area width (pixels) + * h int copy area height (pixels) + * skipleft int x margin (pixels) to skip (not enabled) + * + * Returns :none + *---------------------------------------------------------------------------*/ +static void +LXSubsequentScanlineImageWriteRect(ScrnInfoPtr pScrni, + int x, int y, int w, int h, int skipleft) +{ + DBLOG(2,"LXSubsequentScanlineImageWriteRect() rop %d,%d %dx%d %d\n",x,y,w,h,skipleft); + giwr.x = x; giwr.y = y; + giwr.w = w; giwr.h = h; + /* since the image buffer must be not busy (it may be busy from + * a previous ScanlineWriteImage), we must add a Sync here */ +#if !LX_USE_OFFSCRN_MEM + LXAccelSync(pScrni); +#endif +} + +/*---------------------------------------------------------------------------- + * LXSubsquentImageWriteScanline + * + * Description : see LXSetupForScanlineImageWrite. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * bufno int scanline number in write group + * + * Returns :none + * + * Sample application uses (non-transparent): + * - Moving windows. + * - x11perf: scroll tests (-scroll500). + * - x11perf: copy from window to window (-copywinwin500). + * + *---------------------------------------------------------------------------*/ +static void +LXSubsequentImageWriteScanline(ScrnInfoPtr pScrni, int bufno) +{ + GeodePtr pGeode; + int blt_height = 0; + DBLOG(3,"LXSubsequentImageWriteScanline() %d\n",bufno); + pGeode = GEODEPTR(pScrni); + + if( (blt_height=pGeode->NoOfImgBuffers) > giwr.h ) + blt_height = giwr.h; + if( ++bufno < blt_height ) return; + + gp_declare_blt(ENABLE_PREFETCH); + if( giwr.transparent ) { + gp_set_source_transparency(giwr.color,~0); + } +#if !LX_USE_OFFSCRN_MEM + gp_screen_to_screen_blt(CALC_FBOFFSET(giwr.x,giwr.y), ImgBufOffset, + giwr.w, blt_height, 0); + LXAccelSync(pScrni); +#else + gp_color_bitmap_to_screen_blt(CALC_FBOFFSET(giwr.x,giwr.y), 0, + giwr.w, blt_height, ImgLnsBuffers, pGeode->AccelPitch); +#endif + giwr.h -= blt_height; + giwr.y += blt_height; +} + +/* LX_SCANLINE_SUPPORT */ +#endif + +#if LX_CPU2SCREXP_SUPPORT +/*---------------------------------------------------------------------------- + * LXSetupForScanlineCPUToScreenColorExpandFill + * + * Description :SetupFor/Subsequent CPUToScreenColorExpandFill and + * ColorExpandScanline routines provide an interface for + * doing expansion blits from source patterns stored in + * system memory. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * fg int foreground color + * bg int -1 (transparent) or background color + * rop int unmapped raster operation + * planemask uint -1 (copy) or pattern data + * + * Returns :none. + *---------------------------------------------------------------------------*/ + +static void +LXSetupForScanlineCPUToScreenColorExpandFill(ScrnInfoPtr pScrni, + int fg, int bg, int rop, + uint planemask) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"LXSetupForScanlineCPUToScreenColorExpandFill() fg %#x bg %#x rop %#x %#x\n", + fg,bg,rop,planemask); + rop &= 0x0F; + gp_declare_blt(0); + if( planemask == ~0U ) { + gp_set_raster_operation(ROP=SDfn[rop]); + } + else { + gp_set_raster_operation(ROP=SDfn_PM[rop]); + gp_set_solid_pattern(planemask); + } + gp_set_mono_source(bg, fg, (bg == -1)); + gp_set_strides(pGeode->AccelPitch, pGeode->AccelPitch); + gp_write_parameters(); + gc2s.bpp = 1; + gc2s.transparent = 0; + gc2s.color = 0; +} + +/*---------------------------------------------------------------------------- + * LXSubsequentScanlineCPUToScreenColorExpandFill + * + * Description :see LXSetupForScanlineCPUToScreenColorExpandFill + * + * Parameters: + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x int destination x offset + * y int destination y offset + * w int fill area width (pixels) + * h int fill area height (pixels) + * + * Returns :none + * + *---------------------------------------------------------------------------*/ +static void +LXSubsequentScanlineCPUToScreenColorExpandFill(ScrnInfoPtr pScrni, + int x, int y, int w, int h, int skipleft) +{ + DBLOG(2,"LXSubsequentScanlineCPUToScreenColorExpandFill() %d,%d %dx%d %d\n", + x,y,w,h,skipleft); + gc2s.x = x; gc2s.y = y; + gc2s.w = w; gc2s.h = h; +} + +/*---------------------------------------------------------------------------- + * LXSubsequentColorExpandScanline + * + * Description :see LXSetupForScanlineCPUToScreenColorExpandFill + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * bufno int scanline number in write group + * + * Returns :none +*---------------------------------------------------------------------------- +*/ +static void +LXSubsequentColorExpandScanline(ScrnInfoPtr pScrni, int bufno) +{ + GeodePtr pGeode; + ulong srcpitch; + int blt_height = 0; + DBLOG(3,"LXSubsequentColorExpandScanline() %d\n",bufno); + pGeode = GEODEPTR(pScrni); + + if( (blt_height=pGeode->NoOfImgBuffers) > gc2s.h ) + blt_height = gc2s.h; + if( ++bufno < blt_height ) return; + + gp_declare_blt(ENABLE_PREFETCH); + /* convert from bits to dwords */ + srcpitch = ((pGeode->AccelPitch+31) >> 5) << 2; + gp_mono_bitmap_to_screen_blt(CALC_FBOFFSET(gc2s.x,gc2s.y), 0, gc2s.w,blt_height, + ClrLnsBuffers,srcpitch); + gc2s.h -= blt_height; + gc2s.y += blt_height; +} + +/* LX_CPU2SCREXP_SUPPORT */ +#endif + +#if LX_SCR2SCREXP_SUPPORT + +/*---------------------------------------------------------------------------- + * LXSetupForScreenToScreenColorExpandFill + * + * Description :SetupFor/Subsequent ScreenToScreenColorExpandFill and + * ColorExpandScanline routines provide an interface for + * doing expansion blits from source patterns stored in + * video memory. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * fg int foreground color + * bg int -1 (transparent) or background color + * rop int unmapped raster operation + * planemask uint -1 (copy) or pattern data + * + * Returns :none. + *---------------------------------------------------------------------------*/ + +static void +LXSetupForScreenToScreenColorExpandFill(ScrnInfoPtr pScrni, int fg, int bg, + int rop, uint planemask) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"LXSetupForScreenToScreenColorExpandFill() fg %#x bg %#x rop %#x %#x\n", + fg,bg,rop,planemask); + rop &= 0x0F; + gp_declare_blt(0); + if( planemask == ~0U ) { + gp_set_raster_operation(ROP=SDfn[rop]); + } + else { + gp_set_raster_operation(ROP=SDfn_PM[rop]); + gp_set_solid_pattern(planemask); + } + gp_set_strides(pGeode->AccelPitch, pGeode->AccelPitch); + gp_set_mono_source(bg, fg, (bg == -1)); + gp_write_parameters(); +} + +/*---------------------------------------------------------------------------- + * LXSubsequentScreenToScreenColorExpandFill + * + * Description :see LXSetupForScreenToScreenColorExpandFill + * + * Parameters: + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x int destination x offset + * y int destination y offset + * w int fill area width (pixels) + * h int fill area height (pixels) + * offset int initial x offset + * + * Returns :none + * + *---------------------------------------------------------------------------*/ +static void +LXSubsequentScreenToScreenColorExpandFill(ScrnInfoPtr pScrni, + int x, int y, int w, int h, + int srcx, int srcy, int offset) +{ + int flags; + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"LXSubsequentScreenToScreenColorExpandFill() %d,%d %dx%d %d,%d %d\n", + x,y,w,h,srcx,srcy,offset); + flags = lx_flags3(srcx,srcy,x,y,w,h); + gp_declare_blt(flags); + gp_set_strides(pGeode->AccelPitch, pGeode->AccelPitch); + gp_mono_expand_blt(CALC_FBOFFSET(x,y), CALC_FBOFFSET(srcx,srcy), offset, w,h, 0); +} + +/* LX_SCR2SCREXP_SUPPORT */ +#endif + +#define VM_X_MAJOR 0 +#define VM_Y_MAJOR 1 +#define VM_MAJOR_INC 2 +#define VM_MAJOR_DEC 0 +#define VM_MINOR_INC 4 +#define VM_MINOR_DEC 0 + +static ushort vmode[] = { + VM_X_MAJOR | VM_MAJOR_INC | VM_MINOR_INC, /* !XDECREASING !YDECREASING !YMAJOR */ + VM_Y_MAJOR | VM_MAJOR_INC | VM_MINOR_INC, /* !XDECREASING !YDECREASING YMAJOR */ + VM_X_MAJOR | VM_MAJOR_INC | VM_MINOR_DEC, /* !XDECREASING YDECREASING !YMAJOR */ + VM_Y_MAJOR | VM_MAJOR_DEC | VM_MINOR_INC, /* !XDECREASING YDECREASING YMAJOR */ + VM_X_MAJOR | VM_MAJOR_DEC | VM_MINOR_INC, /* XDECREASING !YDECREASING !YMAJOR */ + VM_Y_MAJOR | VM_MAJOR_INC | VM_MINOR_DEC, /* XDECREASING !YDECREASING YMAJOR */ + VM_X_MAJOR | VM_MAJOR_DEC | VM_MINOR_DEC, /* XDECREASING YDECREASING !YMAJOR */ + VM_Y_MAJOR | VM_MAJOR_DEC | VM_MINOR_DEC, /* XDECREASING YDECREASING YMAJOR */ +}; + +#define ABS(_val1, _val2) (((_val1) > (_val2)) ? ((_val1)-(_val2)) : ((_val2) - (_val1))) + +#if LX_BRES_LINE_SUPPORT +/*---------------------------------------------------------------------------- + * LXSetupForSolidLine + * + * Description :SetupForSolidLine and Subsequent HorVertLine TwoPointLine + * BresenhamLine provides an interface for drawing thin + * solid lines. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * color int foreground fill color + * rop int unmapped raster op + * planemask uint -1 (fill) or pattern data (not enabled) + * + * Returns :none +*---------------------------------------------------------------------------*/ +static void +LXSetupForSolidLine(ScrnInfoPtr pScrni, + int color, int rop, uint planemask) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"LXSetupForSolidLine() %#x %#x %#x\n",color,rop,planemask); + rop &= 0x0F; + gp_declare_vector(CIMGP_BLTFLAGS_HAZARD); + if( planemask == ~0U ) { + gp_set_raster_operation(ROP=PDfn[rop]); + } + else { + gp_set_raster_operation(ROP=PDfn_SM[rop]); + gp_set_solid_source(planemask); + } + gp_set_solid_pattern((ulong)color); + gp_set_strides(pGeode->AccelPitch, pGeode->AccelPitch); + gp_write_parameters(); +} + +/*--------------------------------------------------------------------------- + * LXSubsequentSolidBresenhamLine + * + * Description :see LXSetupForSolidLine + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x1 int destination x offset + * y1 int destination y offset + * absmaj int Bresenman absolute major + * absmin int Bresenman absolute minor + * err int Bresenman initial error term + * len int length of the vector (pixels) + * octant int specifies sign and magnitude relationships + * used to determine axis of magor rendering + * and direction of vector progress. + * + * Returns :none + * + * - Window outlines on window move. + * - x11perf: line segments (-line500). + * - x11perf: line segments (-seg500). + *---------------------------------------------------------------------------*/ +static void +LXSubsequentSolidBresenhamLine(ScrnInfoPtr pScrni, int x1, int y1, + int absmaj, int absmin, int err, + int len, int octant) +{ + int x2, y2, flags; + long axial, diagn; + DBLOG(2,"LXSubsequentSolidBresenhamLine() %d,%d %d %d, %d %d, %d\n", + x1,y1,absmaj,absmin,err,len,octant); + if( len <= 0 ) return; + lx_endpt(x1,y1,len,absmaj,absmin,err,octant,&x2,&y2); + flags = lx_flags2(x1,y1,x2+1,y2+1); + gp_declare_vector(flags); + axial = absmin; + err += axial; + diagn = absmin-absmaj; + gp_bresenham_line(CALC_FBOFFSET(x1,y1), len, err, axial, diagn, vmode[octant]); +} + +/*--------------------------------------------------------------------------- + * LXSubsequentSolidTwoPointLine + * + * Description :see LXSetupForSolidLine + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x0 int destination x start offset + * y0 int destination y start offset + * x1 int destination x end offset + * y1 int destination y end offset + * flags int OMIT_LAST, dont draw last pixel (not used) + * + * Returns :none + *---------------------------------------------------------------------------*/ +static void +LXSubsequentSolidTwoPointLine(ScrnInfoPtr pScrni, int x0, int y0, + int x1, int y1, int flags) +{ + long dx, dy, dmaj, dmin, octant, bias; + long axial, diagn, err, len; + DBLOG(2,"LXSubsequentSolidTwoPointLine() %d,%d %d,%d, %#x\n", + x0,y0,x1,y1,flags); + + if( (dx=x1-x0) < 0 ) dx = -dx; + if( (dy=y1-y0) < 0 ) dy = -dy; + if( dy >= dx ) { + dmaj = dy; dmin = dx; + octant = YMAJOR; + } + else { + dmaj = dx; dmin = dy; + octant = 0; + } + len = dmaj; + if( (flags&OMIT_LAST) == 0 ) ++len; + if( len <= 0 ) return; + if (x1 < x0) octant |= XDECREASING; + if (y1 < y0) octant |= YDECREASING; + + flags = lx_flags2(x0,y0,x1+1,y1+1); + gp_declare_vector(flags); + axial = dmin << 1; + bias = miGetZeroLineBias(pScrni->pScreen); + err = axial - dmaj - ((bias>>octant) & 1); + diagn = (dmin-dmaj) << 1; + gp_bresenham_line(CALC_FBOFFSET(x0,y0), len, err, axial, diagn, vmode[octant]); +} + +/*--------------------------------------------------------------------------- + * LXSubsequentSolidHorVertLine + * + * Description :see LXSetupForSolidLine + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x int destination x offset + * y int destination y offset + * len int length of the vector (pixels) + * dir int DEGREES_270 or DEGREES_0 line direction + * + * Sample application uses: + * - Window outlines on window move. + * - x11perf: line segments (-hseg500). + * - x11perf: line segments (-vseg500). + *--------------------------------------------------------------------------- + */ +static void +LXSubsequentSolidHorVertLine(ScrnInfoPtr pScrni, + int x, int y, int len, int dir) +{ + int flags, w, h; + DBLOG(2,"LXSubsequentHorVertLine() %d,%d %d %d\n",x,y,len,dir); + gp_declare_blt(0); + if( dir == DEGREES_0 ) { + w = len; h = 1; + } + else { + w = 1; h = len; + } + flags = lx_flags1(x,y,w,h); + gp_declare_blt(flags); + gp_pattern_fill(CALC_FBOFFSET(x,y), + ((dir == DEGREES_0) ? len : 1), + ((dir == DEGREES_0) ? 1 : len)); +} + +/* LX_BRES_LINE_SUPPORT */ +#endif + +#if LX_DASH_LINE_SUPPORT +/*---------------------------------------------------------------------------- + * LXSetupForDashedLine + * + * Description :SetupForDashedLine and Subsequent TwoPointLine + * BresenhamLine provides an interface for drawing thin + * dashed lines. + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * fg int foreground fill color + * bg int -1 (transp) or background fill color + * rop int unmapped raster op + * planemask uint -1 (fill) or pattern data (not enabled) + * length int pattern length (bits) + * pattern uchar* dash pattern mask + * + * Returns :none +*---------------------------------------------------------------------------*/ +static void +LXSetupForDashedLine(ScrnInfoPtr pScrni, + int fg, int bg, int rop, uint planemask, + int length, uchar *pattern) +{ + int n; + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(2,"LXSetupForDashedLine() fg %#x bg %#x rop %#x pm %#x len %d, pat %#x\n", + fg,bg,rop,planemask,length,*(ulong*)pattern); + gdln.fg = fg; + gdln.bg = bg; + gdln.len = length; + n = (length+7)/8; + if( n > sizeof(gdln.pat) ) + n = sizeof(gdln.pat); + memcpy(&gdln.pat,pattern,n); + rop &= 0x0F; + gp_declare_vector(CIMGP_BLTFLAGS_HAZARD); + if( planemask == ~0U ) { + gp_set_raster_operation(ROP=PDfn[rop]); + } + else { + gp_set_raster_operation(ROP=PDfn_SM[rop]); + gp_set_solid_source(planemask); + } + gp_set_strides(pGeode->AccelPitch, pGeode->AccelPitch); + gp_write_parameters(); +} + +/*--------------------------------------------------------------------------- + * LXSubsequentDashedBresenhamLine + * + * Description :see LXSetupForDashedLine + * + * Arg Type Comment + * pScrni ScrnInfoPtr pointer to Screeen info + * x1 int destination x offset + * y1 int destination y offset + * absmaj int Bresenman absolute major + * absmin int Bresenman absolute minor + * err int Bresenman initial error term + * len int length of the vector (pixels) + * octant int specifies sign and magnitude relationships + * used to determine axis of magor rendering + * and direction of vector progress. + * phase int initial pattern offset at x1,y1 + * + * Returns :none + *---------------------------------------------------------------------------*/ +static void +LXSubsequentDashedBresenhamLine(ScrnInfoPtr pScrni, int x1, int y1, + int absmaj, int absmin, int err, + int len, int octant, int phase) +{ + int x2, y2, flags; + long axial, diagn; + ulong pattern; + DBLOG(2,"LXSubsequentDashedBresenhamLine() %d,%d %d %d, %d %d, %d %d\n", + x1,y1,absmaj,absmin,err,len,octant,phase); + if( len <= 0 ) return; + pattern = gdln.pat; + if( phase > 0 ) { + int n = gdln.len-phase; + pattern = ((pattern>>phase)&((1UL<= dx ) { + dmaj = dy; dmin = dx; + octant = YMAJOR; + } + else { + dmaj = dx; dmin = dy; + octant = 0; + } + len = dmaj; + if( (flags&OMIT_LAST) == 0 ) ++len; + if( len <= 0 ) return; + if (x1 < x0) octant |= XDECREASING; + if (y1 < y0) octant |= YDECREASING; + + pattern = gdln.pat; + if( phase > 0 ) { + int n = gdln.len-phase; + pattern = ((pattern>>phase)&((1UL<pScreen); + err = axial-dmaj - ((bias>>octant) & 1); + diagn = (dmin-dmaj) << 1; + gp_bresenham_line(CALC_FBOFFSET(x0,y0), len, err, axial, diagn, vmode[octant]); +} + +/* LX_DASH_LINE_SUPPORT */ +#endif + +#if LX_WRITE_PIXMAP_SUPPORT +void +LXWritePixmap(ScrnInfoPtr pScrni, int x, int y, int w, int h, unsigned char *src, int srcwidth, + int rop, unsigned int planemask, int trans, int bpp, int depth) +{ + int flags, dx, dy; + int Bpp = (bpp+7) >> 3; + unsigned long offset; + GeodePtr pGeode = GEODEPTR(pScrni); + + DBLOG(2,"LXWritePixmap() %d,%d %dx%d, s%#x sp%d %#x %#x %#x %d %d\n", + x,y, w,h, src, srcwidth, rop, planemask, trans,bpp,depth); + + rop &= 0x0F; + gp_set_source_format(lx_src_fmt[Bpp-1]); + /* must assign before lx_flags */ + ROP = planemask == ~0U ? SDfn[rop] : SDfn_PM[rop]; + + if( src >= pGeode->FBBase && src < pGeode->FBBase+pGeode->FBSize ) { + offset = src-pGeode->FBBase; + dx = (offset & ((1<> Bpp; + dy = offset >> gu3_yshift; + flags = lx_flags3(x,y,dx,dy,w,h); + } + else + flags = ENABLE_PREFETCH; + + gp_declare_blt(flags); + gp_set_raster_operation(ROP); + if( planemask != ~0U ) + gp_set_solid_pattern(planemask); + gp_set_strides(pGeode->AccelPitch,pGeode->AccelPitch); + if( trans != -1 ) { + gp_set_source_transparency(trans,~0); + } + + gp_color_bitmap_to_screen_blt(CALC_FBOFFSET(x,y), 0, w,h, src, srcwidth); + SET_SYNC_FLAG(pGeode->AccelInfoRec); +} +#endif + +/*---------------------------------------------------------------------------- + * LXAccelInit. + * + * Description :Create and initialize XAAInfoRec structure. + * The XAAInfoRec structure contains many fields, most of + * which are primitive function pointers and flags. Each + * primitive will have two or more functions and a set of + * associated associated flags. These functions can be + * classified into two principle classes, the "SetupFor" + * and "Subsequent" functions. The "SetupFor" function tells + * the driver that the hardware should be initialized for + * a particular type of graphics operation. After the + * "SetupFor" function, one or more calls to the "Subsequent" + * function will be made to indicate that an instance of the + * particular primitive should be rendered by the hardware. + * + * Arg Type Comment + * pScrn ScreenPtr pointer to active Screen data + * + * Returns :TRUE on success and FALSE on Failure + * + * Comments :This function is called in LXScreenInit in + * amd_lx_driver.c to initialize acceleration. + *---------------------------------------------------------------------------*/ +Bool +LXAccelInit(ScreenPtr pScrn) +{ + GeodePtr pGeode; + ScrnInfoPtr pScrni; +#if DEBUGLVL>0 + if( zdfp == NULL ) { zdfp = fopen("/tmp/xwin.log","w"); setbuf(zdfp,NULL); } +#endif + DBLOG(2,"LXAccelInit()\n"); + + pScrni = xf86Screens[pScrn->myNum]; + pGeode = GEODEPTR(pScrni); + + switch (pScrni->bitsPerPixel) { + case 8: + gu3_img_fmt = CIMGP_SOURCE_FMT_3_3_2; + break; + case 16: + gu3_img_fmt = CIMGP_SOURCE_FMT_0_5_6_5; + break; + case 32: + gu3_img_fmt = CIMGP_SOURCE_FMT_8_8_8_8; + break; + } + + gu3_xshift = pScrni->bitsPerPixel >> 4; + + switch (pGeode->AccelPitch) { + case 1024: + gu3_yshift = 10; + break; + case 2048: + gu3_yshift = 11; + break; + case 4096: + gu3_yshift = 12; + break; + case 8192: + gu3_yshift = 13; + break; + } + + /* Getting the pointer for acceleration Inforecord */ + pGeode->AccelInfoRec = localRecPtr = XAACreateInfoRec(); + + /* SET ACCELERATION FLAGS */ + localRecPtr->Flags = PIXMAP_CACHE | OFFSCREEN_PIXMAPS | LINEAR_FRAMEBUFFER; + + /* HOOK SYNCRONIZARION ROUTINE */ + localRecPtr->Sync = LXAccelSync; + +#if LX_FILL_RECT_SUPPORT + /* HOOK FILLED RECTANGLES */ + HOOK(SetupForSolidFill); + HOOK(SubsequentSolidFillRect); + localRecPtr->SolidFillFlags = 0; +#endif + +#if LX_MONO_8X8_PAT_SUPPORT + /* HOOK 8x8 Mono EXPAND PATTERNS */ + HOOK(SetupForMono8x8PatternFill); + HOOK(SubsequentMono8x8PatternFillRect); + localRecPtr->Mono8x8PatternFillFlags = + BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD | + HARDWARE_PATTERN_PROGRAMMED_BITS | HARDWARE_PATTERN_PROGRAMMED_ORIGIN; +#endif + +#if LX_CLREXP_8X8_PAT_SUPPORT + /* Color expansion */ + HOOK(SetupForColor8x8PatternFill); + HOOK(SubsequentColor8x8PatternFillRect); + localRecPtr->Color8x8PatternFillFlags = + BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD | NO_TRANSPARENCY | + HARDWARE_PATTERN_PROGRAMMED_ORIGIN; +#endif + +#if LX_SCR2SCRCPY_SUPPORT + /* HOOK SCREEN TO SCREEN COPIES + * Set flag to only allow copy if transparency is enabled. + */ + HOOK(SetupForScreenToScreenCopy); + HOOK(SubsequentScreenToScreenCopy); + localRecPtr->ScreenToScreenCopyFlags = + BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD; +#endif + +#if LX_BRES_LINE_SUPPORT + /* HOOK BRESENHAM SOLID LINES */ + localRecPtr->SolidLineFlags = NO_PLANEMASK; + HOOK(SetupForSolidLine); + HOOK(SubsequentSolidBresenhamLine); + HOOK(SubsequentSolidHorVertLine); + HOOK(SubsequentSolidTwoPointLine); + localRecPtr->SolidBresenhamLineErrorTermBits = 15; +#endif + +#if LX_DASH_LINE_SUPPORT + /* HOOK BRESENHAM DASHED LINES */ + localRecPtr->DashedLineFlags = NO_PLANEMASK | TRANSPARENCY_ONLY | + LINE_PATTERN_LSBFIRST_LSBJUSTIFIED | SCANLINE_PAD_DWORD; + HOOK(SetupForDashedLine); + HOOK(SubsequentDashedBresenhamLine); + HOOK(SubsequentDashedTwoPointLine); + localRecPtr->DashedBresenhamLineErrorTermBits = 15; + localRecPtr->DashPatternMaxLength = 32; +#endif + +#if LX_SCR2SCREXP_SUPPORT + /* Color expansion */ + HOOK(SetupForScreenToScreenColorExpandFill); + HOOK(SubsequentScreenToScreenColorExpandFill); + localRecPtr->ScreenToScreenColorExpandFillFlags = + BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD; +#endif + + if (pGeode->AccelImageWriteBuffers) { +#if LX_SCANLINE_SUPPORT + localRecPtr->ScanlineImageWriteBuffers = pGeode->AccelImageWriteBuffers; + localRecPtr->NumScanlineImageWriteBuffers = pGeode->NoOfImgBuffers; + HOOK(SetupForScanlineImageWrite); + HOOK(SubsequentScanlineImageWriteRect); + HOOK(SubsequentImageWriteScanline); + localRecPtr->ScanlineImageWriteFlags = + BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD; +#endif +#if !LX_USE_OFFSCRN_MEM + ImgBufOffset = pGeode->AccelImageWriteBuffers[0] - pGeode->FBBase; +#else + ImgLnsBuffers = (uchar *)pGeode->AccelImageWriteBuffers[0]; +#endif + + } else { + localRecPtr->PixmapCacheFlags = DO_NOT_BLIT_STIPPLES; + } + + if (pGeode->AccelColorExpandBuffers) { +#if LX_CPU2SCREXP_SUPPORT + /* Color expansion */ + localRecPtr->ScanlineColorExpandBuffers = pGeode->AccelColorExpandBuffers; + localRecPtr->NumScanlineColorExpandBuffers = pGeode->NoOfColorExpandLines; + HOOK(SetupForScanlineCPUToScreenColorExpandFill); + HOOK(SubsequentScanlineCPUToScreenColorExpandFill); + HOOK(SubsequentColorExpandScanline); + localRecPtr->ScanlineCPUToScreenColorExpandFillFlags = + BIT_ORDER_IN_BYTE_MSBFIRST | SCANLINE_PAD_DWORD; +#endif + ClrLnsBuffers = (uchar *)pGeode->AccelColorExpandBuffers[0]; + } + +#if LX_WRITE_PIXMAP_SUPPORT + HOOK(WritePixmap); +#endif + + + return (XAAInit(pScrn, localRecPtr)); +} + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd.man 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd.man 2005-08-03 14:57:45.000000000 -0600 @@ -0,0 +1,417 @@ +.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/amd/amd.man,v 1.1 2002/12/10 15:12:23 alanh Exp $ +.\" shorthand for double quote that works everywhere. +.ds q \N'34' +.TH AMD __drivermansuffix__ __vendorversion__ +.SH NAME +amd \- Amd video driver \- lx options +.SH SYNOPSIS +.nf +.B "Section \*qDevice\*q" +.BI " Identifier \*q" devname \*q +.B " Driver \*qamd\*q" +\ \ ... +.B EndSection +.fi +.SH DESCRIPTION +.B amd +is an XFree86 driver for Advanced Micro Devicess GEODE processor family. +It uses the CIMARRON kit provided by Advanced Micro Devices. +The driver is accelerated, and provides support for the following +framebuffer depths: 8, 16 and 24. +.SH SUPPORTED HARDWARE +The +.B amd +driver supports GeodeLX (5536 companion chip). +.SH CONFIGURATION DETAILS +Please refer to XF86Config(__filemansuffix__) for general configuration +details. This section only covers configuration details specific to this +driver. +.PP +The driver will auto-detect the amount of video memory present. +If actual the amount of active video memory should be changed, +this may be specified with a +.B VideoRam +entry in the config file. The driver will attempt to allocate all +public/free reigons from the framebuffer memory, as allocated by the +kernel cimarron module. All private framebuffer reservations should +be made before starting X. Note that X attempts to open /dev/video# +devices during initialization, so that attached drivers may allocate +framebuffer memory before X reserves it. X will try to reserve +framebuffer memory using \*q/dev/cim\*q (char device node 10,156). +.PP +.B \*qDevice\*q +section. +.PP +The following driver +.B Options +are supported: +.TP +.BI "Option \*qHWCursor\*q" +.RS 0 +.BI "Option \*qSWCursor\*q" +.RS +Enable HW or SW cursor. +.br +Default: HW cursor. +.RE +.TP +.BI "Option \*qAccel\*q" +.RS 0 +.BI "Option \*qNoAccel\*q" +.RS +Disable or enable acceleration. +.br +Default: acceleration enabled. +.RE +.TP +.BI "Option \*qCompression\*q" +.RS 0 +.BI "Option \*qNoCompression\*q" +.RS +Disable or enable compression. +.br +Default: compression is enabled. +.RE +.TP +.BI "Option \*qShadowFB\*q" +.RS 0 +.BI "Option \*qNoShadowFB\*q" +.RS +Enable or disable use of the shadow framebuffer layer. +.br +Default: off. +.RE +.TP +.BI "Option \*qRotate\*q \*qCW\*q" +.RS 0 +.BI "Option \*qRotate\*q \*qInvert\*q" +.RS 0 +.BI "Option \*qRotate\*q \*qCCW\*q" +.RS +The display may be "rotated" in 3 ways, ClockWise, Upside-Down and +CounterClocwise using: +This is accomplished using a \*qshadow\*q framebuffer, and using either +a hardware or software operation to transform the image to the +operational display buffer. +.br +Default: no rotation. +.RE +.TP +.BI "Option \*qFPDestGeom\*q "\*qWxH\*q +This allows the configuration to override the bios probe of the +.B FlatPanel +output interface. +Since flat-panels have fixed timing - that is, only one \*qreal\*q mode - +the mode switch operation which normally might select a wide variety +of operational states must scale the mode selection to fit the +fixed panel timing. This option is used to communicate that the mode +selection is for a flat panel. When this option is used, the bios +probe is skipped and the specified geometry is used to derive timings. +.br +Default: bios. +.RE +.TP +.BI "Option \*qFPActiveGeom\*q "\*qWxH\*q +This allows the configuration of the active flatpanel display area. This +area must fit into the destination geometry area. The source (mode WxH) +geometry will be scaled to the active geometry, and centered in the +destination geometry of the +.B FlatPanel +output. +.br +Default: FPDestGeom. +.RE +.TP +.BI "Option \*qFlatPanel\*q" +.RS 0 +.BI "Option \*qNoFlatPanel\*q" +.RS +This allows the configuration to override the initialization probe +to enable or disable the +.B FlatPanel +output interface. +.br +Default: bios. +.RE +.TP +.BI "Option \*qCrtEnable\*q" +.RS 0 +.BI "Option \*qNoCrtEnable\*q" +.RS +This allows the configuration to override the initialization probe +to enable or disable the +.B CRT +output interface. +.br +Default: bios. +.RE +.TP +.BI "Option \*qOSMImageBuffers\*q \*q" integer \*q +This sets the number of scanline buffers to be allocated in offscreen +scanline memory for acceleration. This can take any value 0 will disable +the allocation. Disabled if cannot allocate requested scanline memory. +.br +Default: 20. +.TP +.BI "Option \*qOSMColorExpBuffers\*q \*q" integer \*q +This sets the number of scanline buffers to be allocated in offscreen +color expansiopn memory for acceleration. This can take any value 0 +will disable the allocation. Disabled if cannot allocate requested +scanline memory. +.br +Default: 20. +.PP +.BI "TVOUT Options" +.TP +TVOUT is operated when a tv encoder has been selected by using the +.B TV_Encoder +option describe below, and a tv mode name is selected as the active +display mode. The list of tv mode names are: +.RS + ModeName Geometry Std/Hi Encoders + tv-ntsc 720x480 Std adv7171 saa7127 adv7300 + pnl-ntsc 640x480 Std fs454 + pnl-8x6_ntsc 800x600 Std fs454 + pnl-10x7_ntsc 1024x768 Std fs454 + tv-pal 720x576 Std adv7171 saa7127 adv7300 + pnl-pal 640x480 Std fs454 + pnl-8x6_pal 800x600 Std fs454 + pnl-10x7_pal 1024x768 Std fs454 + tv-480p 720x480 Hi adv7300 + pnl-480p 720x480 Hi fs454 + tv-720p 1280x720 Hi adv7300 + pnl-720p 1280x720 Hi fs454 + tv-1080i 1920x1080 Hi adv7300 fs454 +.br +Default: none - manditory parameter +.RE +.TP +.BI "Option \*qTV_Encoder\*q "\*qencoder\*q +This option is manditory for TVOUT operation. It enables selection +of the subset +.B TVOUT +modes which are permitted for the designated encoder family. The +encoder must be one of: + adv7171 - modes for the adv7171 encoder + saa7127 - modes for the saa7127 encoder + fs454 - modes for the fs454 encoder + adv7300 - modes for the adv7300 encoder +.br +Default: none - manditory parameter +.TP +.BI "Option \*qTV_Bus_Fmt\*q "\*qformat\*q +This option is optional for TVOUT operation. It selects the bus +format of the +.B TVOUT +data. The format must be one of: + disabled - VOP output is disabled + vip1_1 - VIP 1.1 + ccir656 - CCIR 656 output + vip20_8bit - 8-bit VIP 2.0 output + vip20_16bit - 16-bit VIP 2.0 output + 601_yuv_8bit - 601 output, 8-bit YUV 4:2:2 + 601_yuv_16bit - 601 output, 16-bit YUV 4:2:2 + 601_rgb_8_8_8 - 601 output, 24-bit RGB + 601_yuv_4_4_4 - 601 output, YUV 4:4:4 +.br +Default: vip1_1 for Std modes, vip20_16bit for Hi modes +.TP +.BI "Option \*qTV_Conversion\*q "\*qconversion\*q +This option is optional for TVOUT operation. It selects the bus +color conversion sampling method of the +.B TVOUT +data. The conversion must be one of: +.br + cosited - color conversion cosited sampling + interspersed - color conversion interspersed sampling + alternating - color conversion alternating sampling +.br +Default: cosited +.TP +.BI "Option \*qTV_Overscan\*q "\*qX:Y\*q +This option is optional for TVOUT operation. It selects the image +overscale size in pixels. The output image is downscaled and padded +with a blanking region such that the resulting image contains a +left and right margin of X pixels, and a top and bottom margin of Y +pixels. +.br +Default: 0:0 +.TP +.BI "Option \*qTV_Flags\*q "\*qflags\*q +This option is optional for TVOUT operation. It selects standard +features of the +.B TVOUT +data. The flags may be a \*q:\*q seperated list of: +.br + disabled - VOP output is disabled + singlechipcompat - Enables SCx2xx compatibility mode.. + extendedsav - Enables extended SAV/EAV codes. + vbi - Use the task bit to indicate VBI data. + task - Set Task Bit to 1in VIP 2.0 mode. + swap_uv - Swap the U and V data prior to output. + swap_vbi - Swap the VBI bytes prior to output. +.br +Default: no active flags +.TP +.BI "Option \*qTV_601_Flags\*q "\*q601_flags\*q +This option is optional for TVOUT operation. It selects 601 +features of the +.B TVOUT +data. The 601_flags may be a \*q:\*q seperated list of: +.br + inv_de_pol - Invert the polarity of display enable + inv_hs_pol - Invert the polarity of hsync + inv_vs_pol - Invert the polarity of vsync + vsync-4 - The VSync occurs 4 clocks earlier + vsync-2 - The VSync occurs 2 clocks earlier + vsync+0 - The VSync is not shifted at all + vsync+2 - The Vsync occurs 2 clocks later +.br +Default: vsync+0 +.TP +.BI "Option \*qTV_Vsync_Select\*q "\*qsync_select\*q +This option is optional for TVOUT operation. It selects the source +for the +.B VIP +vsync output pin (not the +.B VOP +sync). This normally may be used to generate \*qgenlock\*q timing. +The sync_select may one of: +.br + disabled - VSync out disabled + vg - The VSync signal from the VG (video generator) + vg_inv - The VSync signal from the VG (inverted) + statreg17 - 1 written to VIP status[17] toggles vsync + statreg17_inv - 1 written to VIP status[17] toggles vsync +.br +Default: disabled +.SH NAME +amd \- Amd video driver \- gx options +.SH SYNOPSIS +.nf +.B "Section \*qDevice\*q" +.BI " Identifier \*q" devname \*q +.B " Driver \*qamd\*q" +\ \ ... +.B EndSection +.fi +.SH DESCRIPTION +.B amd +is an XFree86 driver for Advanced Micro Devices GEODE processor family. +It uses the DURANGO kit provided by Advanced Micro Devices. +The driver is accelerated, and provides support for the following +framebuffer depths: 8, 16 and 24. +.SH SUPPORTED HARDWARE +The +.B amd +driver supports GXLV (5530 companion chip), SC1200, SC1400 and +GX (5535 companion chip). +.SH CONFIGURATION DETAILS +Please refer to XF86Config(__filemansuffix__) for general configuration +details. This section only covers configuration details specific to this +driver. +.PP +The driver will auto-detect the amount of video memory present for all +chips. If the amount of memory is detected incorrectly, the actual amount +of video memory should be specified with a +.B VideoRam +entry in the config file +.B \*qDevice\*q +section. +.PP +The following driver +.B Options +are supported: +.TP +.BI "Option \*qSWCursor\*q \*q" boolean \*q +Enable or disable the SW cursor. +Default: off. +.TP +.BI "Option \*qHWCursor\*q \*q" boolean \*q +Enable or disable the HW cursor. +Default: on. +.TP +.BI "Option \*qNoAccel\*q \*q" boolean \*q +Disable or enable acceleration. +Default: acceleration is enabled. +.TP +.BI "Option \*qNoCompression\*q \*q" boolean \*q +Disable or enable compression. +Default: compression is enabled. +.TP +.BI "Option \*qShadowFB\*q \*q" boolean \*q +Enable or disable use of the shadow framebuffer layer. +Default: off. +.TP +.BI "Option \*qRotate\*q \*qCW\*q" +Rotate the display clockwise. This mode is unaccelerated, and uses +the Shadow Frame Buffer layer. +Default: no rotation. +.TP +.BI "Option \*qRotate\*q \*qCCW\*q" +Rotate the display counterclockwise. This mode is unaccelerated, and +uses the Shadow Frame Buffer layer. +Default: no rotation. +.TP +.BI "Option \*qFlatPanel\*q \*q" boolean \*q +This enables the FlatPanel display unit. The FlatPanel depends on the +BIOS to do the Pnale h/w initialization. +In GX based platforms with TFT part Flatpanel is enabled, and on CRT +part is disabled. +Default: off. +.TP +.BI "Option \*qOSMImageBuffers\*q \*q" integer \*q +This sets the number of scanline buffers to be allocated in offscreen +memory for acceleration. This can take any value 0 will disable the +allocation. Disabled if cannot alocate requested scanline memory. +Default: 20. +.TP +.BI "Option \*qColorKey\*q \*q" integer \*q +This sets the default pixel value for the YUV video overlay key. +Default: 0. +.PP +The following +.B Options +are supported only on SC1200 based platforms: +.TP +.BI "Option \*qTV\*q \*qPAL-768x576\*q" +Selects the PAL TV display mode 768x576 and the depth is forced to 16 bpp. +Default: no TV. +.TP +.BI "Option \*qTV\*q \*qPAL-720x576\*q" +Selects the PAL TV display mode 720x576 and the depth is forced to 16 bpp. +Default: no TV. +.TP +.BI "Option \*qTV\*q \*qNTSC-720x480\*q" +Selects the NTSC TV display mode 720x480 and the depth is forced to 16 bpp. +Default: no TV. +.TP +.BI "Option \*qTV\*q \*qNTSC-640x480\*q" +Selects the NTSC TV display mode 640x480 and the depth is forced to 16 bpp. +Default: no TV. +.TP +.BI "Option \*qTV_Output\*q \*qCOMPOSITE\*q" +The selected TV mode output is coded for Composite signal. +Default: no TV. +.TP +.BI "Option \*qTV_Output\*q \*qSVIDEO\*q" +The selected TV mode output is coded for SVIDEO signal. +Default: no TV. +.TP +.BI "Option \*qTV_Output\*q \*qYUV\*q" +The selected TV mode output is coded for YUV signal. +Default: no TV. +.TP +.BI "Option \*qTV_Output\*q \*qSCART\*q" +The selected TV mode output is coded for SCART signal. +Default: no TV. +.TP +.BI "Option \*qTVOverscan\*q \*xx:yy:ww:hh\*q" +This option will let only the viewable display area smaller to be able to +view on TV. The parameters xx: X-offset, yy: Y-offset, ww: Viewable width, +hh: Viewable height. +Default: no TV. +.SH "SEE ALSO" +XFree86(1), XF86Config(__filemansuffix__), xf86config(1), Xserver(1), X(__miscmansuffix__) +.SH AUTHOR +Author: William Morrow --- xc/programs/Xserver/hw/xfree86/drivers/amd/panel.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/panel.c 2005-07-13 13:16:48.000000000 -0600 @@ -0,0 +1,76 @@ +/* + * $Workfile: panel.c $ + * $Revision: #4 $ + * $Author: raymondd $ + * + * File Contents: This file contailns the panel include files and + * external pointer to the hardware. + * + * Project: Geode Xfree Frame buffer device driver. + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +#if defined(linux) /* Linux */ + +#ifdef __KERNEL__ + +#include +#include + +#elif !defined(XFree86Server) + +#include +#include + +#endif /* __KERNEL__ */ +#elif defined(_WIN32) /* windows */ + +#include + +#endif + +#include "panel.h" +#include "gfx_defs.h" +#include "amd.h" + +#define PLATFORM_DYNAMIC 1 /* runtime selection */ +#define PLATFORM_DRACO 0 /* Draco + 9210 */ +#define PLATFORM_CENTAURUS 1 /* Centaurus + 9211 RevA */ +#define PLATFORM_DORADO 1 /* Dorado + 9211 RevC */ +#define PLATFORM_GX2BASED 1 /* Redcloud */ + +unsigned char *XpressROMPtr; + +#include "pnl_init.c" +#include "pnl_bios.c" --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_video.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_lx_video.c 2005-08-03 16:49:59.000000000 -0600 @@ -0,0 +1,1454 @@ +/* + * $Workfile: amd_lx_video.c $ + * $Revision: #3 $ + * $Author: raymondd $ + * + * File Contents: This file consists of main Xfree video supported routines. + * + * Project: Geode Xfree Frame buffer device driver. + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +/* + * Fixes & Extensions to support Y800 greyscale modes + * Alan Hourihane + */ +#ifndef AMD_V4L2_VIDEO +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86Resources.h" +#include "xf86_ansic.h" +#include "compiler.h" +#include "xf86PciInfo.h" +#include "xf86Pci.h" +#include "xf86fbman.h" +#include "regionstr.h" + +#include "amd.h" +#include "Xv.h" +#include "xaa.h" +#include "xaalocal.h" +#include "dixstruct.h" +#include "fourcc.h" +#include "amd_fourcc.h" + +#if DEBUGLVL>0 +#define DBLOG(n,s...) do { if((DEBUGLVL)>=(n)) fprintf(zdfp,s); } while(0) +#include "xf86_ansic.h" +extern FILE *zdfp; +#else +#define DBLOG(n,s...) do {} while(0) +#endif + +#define OFF_DELAY 200 /* milliseconds */ +#define FREE_DELAY 60000 + +#define OFF_TIMER 0x01 +#define FREE_TIMER 0x02 +#define CLIENT_VIDEO_ON 0x04 + +#define TIMER_MASK (OFF_TIMER | FREE_TIMER) +#define XV_PROFILE 0 +#define REINIT 1 + +#ifndef XvExtension +void +LXInitVideo(ScreenPtr pScrn) +{ +} + +void +LXResetVideo(ScrnInfoPtr pScrni) +{ +} + +void LXSetVideoPosition(int x, int y, int width, int height, + short src_w, short src_h, short drw_w, + short drw_h, int id, int offset, ScrnInfoPtr pScrni) +{ +} +#else + +#define DBUF 1 +void LXInitVideo(ScreenPtr pScrn); +void LXResetVideo(ScrnInfoPtr pScrni); +static XF86VideoAdaptorPtr LXSetupImageVideo(ScreenPtr); +static void LXInitOffscreenImages(ScreenPtr); +static void LXStopVideo(ScrnInfoPtr, pointer, Bool); +static int LXSetPortAttribute(ScrnInfoPtr, Atom, INT32, pointer); +static int LXGetPortAttribute(ScrnInfoPtr, Atom, INT32 *, pointer); +static void LXQueryBestSize(ScrnInfoPtr, Bool, + short, short, short, short, unsigned int *, + unsigned int *, pointer); +static int LXPutImage(ScrnInfoPtr, short, short, short, short, short, short, + short, short, int, unsigned char *, short, short, Bool, + RegionPtr, pointer); +static int LXQueryImageAttributes(ScrnInfoPtr, int, unsigned short *, + unsigned short *, int *, int *); + +static void LXBlockHandler(int, pointer, pointer, pointer); +void LXSetVideoPosition(int x, int y, int width, int height, + short src_w, short src_h, short drw_w, + short drw_h, int id, int offset, ScrnInfoPtr pScrni); + +extern void LXAccelSync(ScrnInfoPtr pScrni); + +#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE) + +static Atom xvColorKey, xvColorKeyMode, xvFilter +#if DBUF + , xvDoubleBuffer +#endif + ; + +/*---------------------------------------------------------------------------- + * LXInitVideo + * + * Description :This is the initialization routine.It creates a new video adapter + * and calls LXSetupImageVideo to initialize the adaptor by filling + * XF86VideoAdaptorREc.Then it lists the existing adaptors and adds the + * new one to it. Finally the list of XF86VideoAdaptorPtr pointers are + * passed to the xf86XVScreenInit(). + * + * Parameters. + * ScreenPtr + * pScrn :Screen handler pointer having screen information. + * + * Returns :none + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +void +LXInitVideo(ScreenPtr pScrn) +{ + GeodePtr pGeode; + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + DBLOG(1,"LXInitVideo()\n"); + + pGeode = GEODEPTR(pScrni); + + if (!pGeode->NoAccel) { + XF86VideoAdaptorPtr *adaptors, *newAdaptors = NULL; + XF86VideoAdaptorPtr newAdaptor = NULL; + + int num_adaptors; + + newAdaptor = LXSetupImageVideo(pScrn); + LXInitOffscreenImages(pScrn); + + num_adaptors = xf86XVListGenericAdaptors(pScrni, &adaptors); + + if (newAdaptor) { + if (!num_adaptors) { + num_adaptors = 1; + adaptors = &newAdaptor; + } else { + newAdaptors = /* need to free this someplace */ + xalloc((num_adaptors + 1) * sizeof(XF86VideoAdaptorPtr *)); + if (newAdaptors) { + memcpy(newAdaptors, adaptors, num_adaptors * + sizeof(XF86VideoAdaptorPtr)); + newAdaptors[num_adaptors] = newAdaptor; + adaptors = newAdaptors; + num_adaptors++; + } + } + } + + if (num_adaptors) + xf86XVScreenInit(pScrn, adaptors, num_adaptors); + + if (newAdaptors) + xfree(newAdaptors); + } +} + +/* client libraries expect an encoding */ +static XF86VideoEncodingRec DummyEncoding[1] = { + { + 0, + "XV_IMAGE", + 1024, 1024, + {1, 1} + } +}; + +#define NUM_FORMATS 4 + +static XF86VideoFormatRec Formats[NUM_FORMATS] = { + {8, PseudoColor}, {15, TrueColor}, {16, TrueColor}, {24, TrueColor} +}; + +#if DBUF +#define NUM_ATTRIBUTES 4 +#else +#define NUM_ATTRIBUTES 3 +#endif + +static XF86AttributeRec Attributes[NUM_ATTRIBUTES] = { +#if DBUF + {XvSettable | XvGettable, 0, 1, "XV_DOUBLE_BUFFER"}, +#endif + {XvSettable | XvGettable, 0, (1 << 24) - 1, "XV_COLORKEY"}, + {XvSettable | XvGettable, 0, 1, "XV_FILTER"}, + {XvSettable | XvGettable, 0, 1, "XV_COLORKEYMODE"} +}; + +static XF86ImageRec Images[] = { + XVIMAGE_UYVY, + XVIMAGE_YUY2, + XVIMAGE_Y2YU, + XVIMAGE_YVYU, + XVIMAGE_Y800, + XVIMAGE_I420, + XVIMAGE_YV12 +}; + +#define NUM_IMAGES (sizeof(Images)/sizeof(Images[0])); + +typedef struct +{ + FBAreaPtr area; + FBLinearPtr linear; + RegionRec clip; + CARD32 filter; + CARD32 colorKey; + CARD32 colorKeyMode; + CARD32 videoStatus; + Time offTime; + Time freeTime; +#if DBUF + Bool doubleBuffer; + int currentBuffer; +#endif +} +GeodePortPrivRec, *GeodePortPrivPtr; + +#define GET_PORT_PRIVATE(pScrni) \ + (GeodePortPrivPtr)((GEODEPTR(pScrni))->adaptor->pPortPrivates[0].ptr) + +/*---------------------------------------------------------------------------- + * LXSetColorKey + * + * Description :This function reads the color key for the pallete and + * sets the video color key register. + * + * Parameters. + * ScreenInfoPtr + * pScrni :Screen pointer having screen information. + * pPriv :Video port private data + * + * Returns :none + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static INT32 +LXSetColorkey(ScrnInfoPtr pScrni, GeodePortPrivPtr pPriv) +{ + int red, green, blue; + unsigned long key; + + switch (pScrni->depth) { + case 8: + vg_get_display_palette_entry(pPriv->colorKey & 0xFF, &key); + red = ((key >> 16) & 0xFF); + green = ((key >> 8) & 0xFF); + blue = (key & 0xFF); + break; + case 16: + red = (pPriv->colorKey & pScrni->mask.red) >> + pScrni->offset.red << (8 - pScrni->weight.red); + green = (pPriv->colorKey & pScrni->mask.green) >> + pScrni->offset.green << (8 - pScrni->weight.green); + blue = (pPriv->colorKey & pScrni->mask.blue) >> + pScrni->offset.blue << (8 - pScrni->weight.blue); + break; + default: + /* for > 16 bpp we send in the mask in xf86SetWeight. This + * function is providing the offset by 1 more. So we take + * this as a special case and subtract 1 for > 16 + */ + red = (pPriv->colorKey & pScrni->mask.red) >> + (pScrni->offset.red - 1) << (8 - pScrni->weight.red); + green = (pPriv->colorKey & pScrni->mask.green) >> + (pScrni->offset.green - 1) << (8 - pScrni->weight.green); + blue = (pPriv->colorKey & pScrni->mask.blue) >> + (pScrni->offset.blue - 1) << (8 - pScrni->weight.blue); + break; + } + + DBLOG(1,"LXSetColorkey() %08x %d\n",blue|(green<<8)|(red<<16),pPriv->colorKeyMode); + if( pPriv->colorKeyMode != 0 ) + df_set_video_color_key((blue | (green << 8) | (red << 16)), 0xFFFFFF, 1); + else + df_set_video_color_key(0,0,1); + REGION_EMPTY(pScrni->pScreen, &pPriv->clip); + return 0; +} + +/*---------------------------------------------------------------------------- + * LXResetVideo + * + * Description : This function resets the video + * + * Parameters. + * ScreenInfoPtr + * pScrni :Screen pointer having screen information. + * + * Returns :None + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ + +void +LXResetVideo(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(1,"LXResetVideo()\n"); + + if (!pGeode->NoAccel) { + GeodePortPrivPtr pPriv = pGeode->adaptor->pPortPrivates[0].ptr; + + LXAccelSync(pScrni); + df_set_video_palette(NULL); + LXSetColorkey(pScrni, pPriv); + } +} + +/*---------------------------------------------------------------------------- + * LXSetupImageVideo + * + * Description : This function allocates space for a Videoadaptor and initializes + * the XF86VideoAdaptorPtr record. + * + * Parameters. + * ScreenPtr + * pScrn :Screen handler pointer having screen information. + * + * Returns :XF86VideoAdaptorPtr :- pointer to the initialized video adaptor record. + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ + +static XF86VideoAdaptorPtr +LXSetupImageVideo(ScreenPtr pScrn) +{ + ScrnInfoPtr pScrni = xf86Screens[pScrn->myNum]; + GeodePtr pGeode = GEODEPTR(pScrni); + XF86VideoAdaptorPtr adapt; + GeodePortPrivPtr pPriv; + DBLOG(1,"LXSetupImageVideo()\n"); + + if (!(adapt = xcalloc(1, sizeof(XF86VideoAdaptorRec) + + sizeof(GeodePortPrivRec) + sizeof(DevUnion)))) + return NULL; + + adapt->type = XvWindowMask | XvInputMask | XvImageMask; + adapt->flags = VIDEO_OVERLAID_IMAGES | VIDEO_CLIP_TO_VIEWPORT; + adapt->name = "Advanced Micro Devices"; + adapt->nEncodings = 1; + adapt->pEncodings = DummyEncoding; + adapt->nFormats = NUM_FORMATS; + adapt->pFormats = Formats; + adapt->nPorts = 1; + adapt->pPortPrivates = (DevUnion *) (&adapt[1]); + pPriv = (GeodePortPrivPtr) (&adapt->pPortPrivates[1]); + adapt->pPortPrivates[0].ptr = (pointer) (pPriv); + adapt->pAttributes = Attributes; + adapt->nImages = NUM_IMAGES; + adapt->nAttributes = NUM_ATTRIBUTES; + adapt->pImages = Images; + adapt->PutVideo = NULL; + adapt->PutStill = NULL; + adapt->GetVideo = NULL; + adapt->GetStill = NULL; + adapt->StopVideo = LXStopVideo; + adapt->SetPortAttribute = LXSetPortAttribute; + adapt->GetPortAttribute = LXGetPortAttribute; + adapt->QueryBestSize = LXQueryBestSize; + adapt->PutImage = LXPutImage; + adapt->QueryImageAttributes = LXQueryImageAttributes; + + pPriv->filter = 0; + pPriv->colorKey = pGeode->videoKey; + pPriv->colorKeyMode = 0; + pPriv->videoStatus = 0; +#if DBUF + pPriv->doubleBuffer = TRUE; + pPriv->currentBuffer = 0; /* init to first buffer */ +#endif + + /* gotta uninit this someplace */ +#if defined(REGION_NULL) + REGION_NULL(pScrn, &pPriv->clip); +#else + REGION_INIT(pScrn, &pPriv->clip, NullBox, 0); +#endif + + pGeode->adaptor = adapt; + + pGeode->BlockHandler = pScrn->BlockHandler; + pScrn->BlockHandler = LXBlockHandler; + + xvColorKey = MAKE_ATOM("XV_COLORKEY"); + xvColorKeyMode = MAKE_ATOM("XV_COLORKEYMODE"); + xvFilter = MAKE_ATOM("XV_FILTER"); +#if DBUF + xvDoubleBuffer = MAKE_ATOM("XV_DOUBLE_BUFFER"); +#endif + + LXResetVideo(pScrni); + + return adapt; +} + +/*---------------------------------------------------------------------------- + * LXStopVideo + * + * Description :This function is used to stop input and output video + * + * Parameters. + * pScrni :Screen handler pointer having screen information. + * data :Pointer to the video port's private data + * exit :Flag indicating whether the offscreen areas used for video + * to be deallocated or not. + * Returns :none + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static void +LXStopVideo(ScrnInfoPtr pScrni, pointer data, Bool exit) +{ + GeodePortPrivPtr pPriv = (GeodePortPrivPtr) data; + GeodePtr pGeode = GEODEPTR(pScrni); + DBLOG(1,"LXStopVideo()\n"); + + REGION_EMPTY(pScrni->pScreen, &pPriv->clip); + + LXAccelSync(pScrni); + if (exit) { + if (pPriv->videoStatus & CLIENT_VIDEO_ON) { + df_set_video_enable(0,0); + } + if (pPriv->area) { + xf86FreeOffscreenArea(pPriv->area); + pPriv->area = NULL; + } + pPriv->videoStatus = 0; + pGeode->OverlayON = FALSE; + } else { + if (pPriv->videoStatus & CLIENT_VIDEO_ON) { + pPriv->videoStatus |= OFF_TIMER; + pPriv->offTime = currentTime.milliseconds + OFF_DELAY; + } + } +} + +/*---------------------------------------------------------------------------- + * LXSetPortAttribute + * + * Description :This function is used to set the attributes of a port like colorkeymode, + * double buffer support and filter. + * + * Parameters. + * pScrni :Screen handler pointer having screen information. + * data :Pointer to the video port's private data + * attribute :The port attribute to be set + * value :Value of the attribute to be set. + * + * Returns :Sucess if the attribute is supported, else BadMatch + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static int +LXSetPortAttribute(ScrnInfoPtr pScrni, + Atom attribute, INT32 value, pointer data) +{ + GeodePortPrivPtr pPriv = (GeodePortPrivPtr) data; + DBLOG(1,"LXSetPortAttribute(%d,%#x)\n",attribute,value); + + LXAccelSync(pScrni); + if (attribute == xvColorKey) { + pPriv->colorKey = value; + LXSetColorkey(pScrni, pPriv); + } +#if DBUF + else if (attribute == xvDoubleBuffer) { + if ((value < 0) || (value > 1)) + return BadValue; + pPriv->doubleBuffer = value; + } +#endif + else if (attribute == xvColorKeyMode) { + pPriv->colorKeyMode = value; + LXSetColorkey(pScrni, pPriv); + } + else if (attribute == xvFilter) { + if ((value < 0) || (value > 1)) + return BadValue; + pPriv->filter = value; + } + else + return BadMatch; + + return Success; +} + +/*---------------------------------------------------------------------------- + * LXGetPortAttribute + * + * Description :This function is used to get the attributes of a port like hue, + * saturation,brightness or contrast. + * + * Parameters. + * pScrni :Screen handler pointer having screen information. + * data :Pointer to the video port's private data + * attribute :The port attribute to be read + * value :Pointer to the value of the attribute to be read. + * + * Returns :Sucess if the attribute is supported, else BadMatch + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +static int +LXGetPortAttribute(ScrnInfoPtr pScrni, + Atom attribute, INT32 * value, pointer data) +{ + GeodePortPrivPtr pPriv = (GeodePortPrivPtr) data; + DBLOG(1,"LXGetPortAttribute(%d)\n",attribute); + + if (attribute == xvColorKey) { + *value = pPriv->colorKey; + } +#if DBUF + else if (attribute == xvDoubleBuffer) { + *value = (pPriv->doubleBuffer) ? 1 : 0; + } +#endif + else if (attribute == xvColorKeyMode) { + *value = pPriv->colorKeyMode; + } + else if (attribute == xvFilter) { + *value = pPriv->filter; + } else + return BadMatch; + + return Success; +} + +/*---------------------------------------------------------------------------- + * LXQueryBestSize + * + * Description :This function provides a way to query what the destination dimensions + * would end up being if they were to request that an area vid_w by vid_h + * from the video stream be scaled to rectangle of drw_w by drw_h on + * the screen. + * + * Parameters. + * ScreenInfoPtr + * pScrni :Screen handler pointer having screen information. + * data :Pointer to the video port's private data + * vid_w,vid_h :Width and height of the video data. + * drw_w,drw_h :Width and height of the scaled rectangle. + * p_w,p_h :Width and height of the destination rectangle. + * + * Returns :None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ +static void +LXQueryBestSize(ScrnInfoPtr pScrni, + Bool motion, + short vid_w, short vid_h, + short drw_w, short drw_h, + unsigned int *p_w, unsigned int *p_h, pointer data) +{ + *p_w = drw_w; + *p_h = drw_h; + + if (*p_w > 16384) + *p_w = 16384; + DBLOG(1,"LXQueryBestSize(%d, src %dx%d scl %dx%d dst %dx%d)\n",motion,vid_w,vid_h,drw_w,drw_h,*p_w,*p_h); +} + +static void +LXCopyGreyscale(unsigned char *src, unsigned char *dst, int srcp, int dstp, int h, int w) +{ + int i; + unsigned char *src2 = src; + unsigned char *dst2 = dst; + unsigned char *dst3; + unsigned char *src3; + + dstp <<= 1; + + while (h--) { + dst3 = dst2; + src3 = src2; + for (i = 0; i < w; i++) { + *dst3++ = *src3++; /* Copy Y data */ + *dst3++ = 0x80; /* Fill UV with 0x80 - greyscale */ + } + src3 = src2; + for (i = 0; i < w; i++) { + *dst3++ = *src3++; /* Copy Y data */ + *dst3++ = 0x80; /* Fill UV with 0x80 - greyscale */ + } + dst2 += dstp; + src2 += srcp; + } +} + +/*---------------------------------------------------------------------------- + * LXCopyData420 + * + * Description : Copies data from src to destination + * + * Parameters. + * src : pointer to the source data + * dst : pointer to destination data + * srcp : pitch of the srcdata + * dstp : pitch of the destination data + * h & w : height and width of source data + * + * Returns :None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ + +static void +LXCopyData420(unsigned char *src, unsigned char *dst, int srcp, int dstp, int h, int w) +{ + while (h--) { + memcpy(dst, src, w); + src += srcp; dst += dstp; + } +} + +/*---------------------------------------------------------------------------- + * LXCopyData422 + * + * Description : Copies data from src to destination + * + * Parameters. + * src : pointer to the source data + * dst : pointer to destination data + * srcp : pitch of the srcdata + * dstp : pitch of the destination data + * h & w : height and width of source data + * + * Returns :None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ + +static void +LXCopyData422(unsigned char *src, unsigned char *dst, + int srcp, int dstp, int h, int w) +{ + w <<= 1; + while (h--) { + memcpy(dst, src, w); + src += srcp; dst += dstp; + } +} + +static FBAreaPtr +LXAllocateMemory(ScrnInfoPtr pScrni, FBAreaPtr area, int numlines) +{ + ScreenPtr pScrn = screenInfo.screens[pScrni->scrnIndex]; + FBAreaPtr new_area; + + if (area) { + if ((area->box.y2 - area->box.y1) >= numlines) + return area; + + if (xf86ResizeOffscreenArea(area, pScrni->displayWidth, numlines)) + return area; + + xf86FreeOffscreenArea(area); + } + + new_area = xf86AllocateOffscreenArea(pScrn, pScrni->displayWidth, + numlines, 0, NULL, NULL, NULL); + + if (!new_area) { + int max_w, max_h; + + xf86QueryLargestOffscreenArea(pScrn, &max_w, &max_h, 0, + FAVOR_WIDTH_THEN_AREA, PRIORITY_EXTREME); + + if ((max_w < pScrni->displayWidth) || (max_h < numlines)) + return NULL; + + xf86PurgeUnlockedOffscreenAreas(pScrn); + new_area = xf86AllocateOffscreenArea(pScrn, pScrni->displayWidth, + numlines, 0, NULL, NULL, NULL); + } + + return new_area; +} + +static BoxRec dstBox; +static int srcPitch = 0, srcPitch2 = 0, dstPitch = 0, dstPitch2 = 0; +static INT32 Bx1, Bx2, By1, By2; +static int top, left, npixels, nlines; +static int offset, s1offset = 0, s2offset = 0, s3offset = 0; +static unsigned char *dst_start; +static int d2offset = 0, d3offset = 0; + +static DF_VIDEO_SOURCE_PARAMS vSrcParams; + +void +LXSetVideoPosition(int x, int y, int width, int height, + short src_w, short src_h, short drw_w, short drw_h, + int id, int offset, ScrnInfoPtr pScrni) +{ + long ystart, xend, yend; + unsigned long lines = 0; + unsigned long y_extra, uv_extra = 0; + DF_VIDEO_POSITION vidPos; + + DBLOG(1,"LXSetVideoPosition(%d,%d %dx%d, src %dx%d, dst %dx%d, id %d, ofs %d)\n", + x,y,width,height,src_w,src_h,drw_w,drw_h,id,offset); + + xend = x + drw_w; + yend = y + drw_h; + + /* TOP CLIPPING */ + + if (y < 0) { + if (src_h < drw_h) + lines = (-y) * src_h / drw_h; + else + lines = (-y); + ystart = 0; + drw_h += y; + y_extra = lines * dstPitch; + uv_extra = (lines >> 1) * (dstPitch2); + } else { + ystart = y; + lines = 0; + y_extra = 0; + } + + memset(&vidPos,0,sizeof(vidPos)); + vidPos.x= x; + vidPos.y = ystart; + vidPos.width = xend - x; + vidPos.height = yend - ystart; + + DBLOG(1,"video_pos %d,%d %dx%d\n",vidPos.x,vidPos.y,vidPos.width,vidPos.height); + df_set_video_position(&vidPos); + + vSrcParams.y_offset = offset + y_extra; + if ((id == FOURCC_Y800) || (id == FOURCC_I420) || (id == FOURCC_YV12)) { + vSrcParams.u_offset = offset + d3offset + uv_extra; + vSrcParams.v_offset = offset + d2offset + uv_extra; + } + else { + vSrcParams.u_offset = vSrcParams.v_offset = 0; + } + vSrcParams.flags = DF_SOURCEFLAG_IMPLICITSCALING; + + DBLOG(1,"video_format %#x yofs %#x uofs %#x vofs %#x yp %d uvp %d wh %dx%d flg %#x\n", + vSrcParams.video_format, vSrcParams.y_offset, vSrcParams.u_offset, + vSrcParams.v_offset, vSrcParams.y_pitch, vSrcParams.uv_pitch, + vSrcParams.width, vSrcParams.height, vSrcParams.flags); + + df_configure_video_source(&vSrcParams, &vSrcParams); +} + +/*---------------------------------------------------------------------------- + * LXDisplayVideo + * + * Description : This function sets up the video registers for playing video + * It sets up the video format,width, height & position of the + * video window ,video offsets( y,u,v) and video pitches(y,u,v) + * Parameters. + * + * Returns :None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ + +static void +LXDisplayVideo(ScrnInfoPtr pScrni, + int id, + int offset, + short width, short height, + int pitch, + int x1, int y1, int x2, int y2, + BoxPtr dstBox, + short src_w, short src_h, short drw_w, short drw_h) +{ + DBLOG(1,"LXDisplayVideo(id %d, ofs %d, %dx%d, p %d, %d,%d, %d,%d, src %dx%d dst %dx%d)\n", + id,offset,width,height,pitch,x1,y1,x2,y2,src_w,src_h,drw_w,drw_h); + + LXAccelSync(pScrni); + + switch (id) { + case FOURCC_UYVY: vSrcParams.video_format = DF_VIDFMT_UYVY; break; + case FOURCC_Y800: + case FOURCC_YV12: + case FOURCC_I420: vSrcParams.video_format = DF_VIDFMT_Y0Y1Y2Y3; break; + case FOURCC_YUY2: vSrcParams.video_format = DF_VIDFMT_YUYV; break; + case FOURCC_Y2YU: vSrcParams.video_format = DF_VIDFMT_Y2YU; break; + case FOURCC_YVYU: vSrcParams.video_format = DF_VIDFMT_YVYU; break; + } + + vSrcParams.width = width; + vSrcParams.height = height; + vSrcParams.y_pitch = dstPitch; + vSrcParams.uv_pitch = dstPitch2; + + df_set_video_filter_coefficients(NULL,1); + if ((drw_w >= src_w) && (drw_h >= src_h)) + df_set_video_scale(width, height, drw_w, drw_h, + DF_SCALEFLAG_CHANGEX | DF_SCALEFLAG_CHANGEY); + else if (drw_w < src_w) + df_set_video_scale(drw_w, height, drw_w, drw_h, + DF_SCALEFLAG_CHANGEX | DF_SCALEFLAG_CHANGEY); + else if (drw_h < src_h) + df_set_video_scale(width, drw_h, drw_w, drw_h, + DF_SCALEFLAG_CHANGEX | DF_SCALEFLAG_CHANGEY); + + LXSetVideoPosition(dstBox->x1, dstBox->y1, width, height, src_w, + src_h, drw_w, drw_h, id, offset, pScrni); + + df_set_video_enable(1,0); +} + +#if REINIT +static Bool +RegionsEqual(RegionPtr A, RegionPtr B) +{ + int *dataA, *dataB; + int num; + + num = REGION_NUM_RECTS(A); + if (num != REGION_NUM_RECTS(B)) { + return FALSE; + } + + if ((A->extents.x1 != B->extents.x1) || + (A->extents.x2 != B->extents.x2) || + (A->extents.y1 != B->extents.y1) || (A->extents.y2 != B->extents.y2)) + return FALSE; + + dataA = (int *)REGION_RECTS(A); + dataB = (int *)REGION_RECTS(B); + + while (num--) { + if ((dataA[0] != dataB[0]) || (dataA[1] != dataB[1])) + return FALSE; + dataA += 2; + dataB += 2; + } + + return TRUE; +} +#endif + +/*---------------------------------------------------------------------------- + * LXPutImage : This function writes a single frame of video into a drawable. + * The position and size of the source rectangle is specified by src_x,src_y, + * src_w and src_h. This data is stored in a system memory buffer at buf. + * The position and size of the destination rectangle is specified by drw_x, + * drw_y,drw_w,drw_h.The data is in the format indicated by the image descriptor + * and represents a source of size width by height. If sync is TRUE the driver + * should not return from this function until it is through reading the data from + * buf. Returning when sync is TRUE indicates that it is safe for the data at buf + * to be replaced,freed, or modified. + * + * + * Description : + * Parameters. + * + * Returns :None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ + +static int +LXPutImage(ScrnInfoPtr pScrni, + short src_x, short src_y, + short drw_x, short drw_y, + short src_w, short src_h, + short drw_w, short drw_h, + int id, unsigned char *buf, + short width, short height, + Bool sync, RegionPtr clipBoxes, pointer data) +{ + GeodePortPrivPtr pPriv = (GeodePortPrivPtr) data; + GeodePtr pGeode = GEODEPTR(pScrni); + int new_h; + +#if REINIT + BOOL ReInitVideo = FALSE; + static BOOL DoReinitAgain = 0; +#endif + +#if XV_PROFILE + long oldtime, newtime; + + UpdateCurrentTime(); + oldtime = currentTime.milliseconds; +#endif + DBLOG(1,"LXPutImage(src %d,%d %dx%d dst %d,%d %dx%d, id %d %dx%d sync %d)\n", + src_x,src_y,src_w,src_h,drw_x,drw_y,drw_w,drw_h,id,width,height,sync); + +#if REINIT +/* update cliplist */ + if (!RegionsEqual(&pPriv->clip, clipBoxes)) { + ReInitVideo = TRUE; + } + if (DoReinitAgain) + ReInitVideo = TRUE; + + if (ReInitVideo) { + DBLOG(1, "Regional Not Equal - Init\n"); +#endif + DoReinitAgain = ~DoReinitAgain; + if (drw_w > 16384) + drw_w = 16384; + + /* Clip */ + Bx1 = src_x; + Bx2 = src_x + src_w; + By1 = src_y; + By2 = src_y + src_h; + + if ((Bx1 >= Bx2) || (By1 >= By2)) + return Success; + + dstBox.x1 = drw_x; + dstBox.x2 = drw_x + drw_w; + dstBox.y1 = drw_y; + dstBox.y2 = drw_y + drw_h; + + dstBox.x1 -= pScrni->frameX0; + dstBox.x2 -= pScrni->frameX0; + dstBox.y1 -= pScrni->frameY0; + dstBox.y2 -= pScrni->frameY0; + + switch (id) { + case FOURCC_YV12: + case FOURCC_I420: + + srcPitch = (width + 3) & ~3; /* of luma */ + dstPitch = (width + 31) & ~31; + + s2offset = srcPitch * height; + d2offset = dstPitch * height; + + srcPitch2 = ((width >> 1) + 3) & ~3; + dstPitch2 = ((width >> 1) + 15) & ~15; + + s3offset = (srcPitch2 * (height >> 1)) + s2offset; + d3offset = (dstPitch2 * (height >> 1)) + d2offset; + + new_h = dstPitch * height; /* Y */ + new_h += (dstPitch2 * height); /* U+V */ + new_h += pGeode->Pitch - 1; + new_h /= pGeode->Pitch; + break; + + case FOURCC_UYVY: + case FOURCC_YUY2: + case FOURCC_Y800: + default: + dstPitch = ((width << 1) + 3) & ~3; + srcPitch = (width << 1); + new_h = ((dstPitch * height) + pGeode->Pitch - 1) / pGeode->Pitch; + break; + } + +#if DBUF + if (pPriv->doubleBuffer) + new_h <<= 1; +#endif + + if (!(pPriv->area = LXAllocateMemory(pScrni, pPriv->area, new_h))) + return BadAlloc; + + /* copy data */ + top = By1; + left = Bx1 & ~1; + npixels = ((Bx2 + 1) & ~1) - left; + + switch (id) { + case FOURCC_YV12: + case FOURCC_I420: + { + int tmp; + + top &= ~1; + offset = (pPriv->area->box.y1 * pGeode->Pitch) + (top * dstPitch); + +#if DBUF + if (pPriv->doubleBuffer && pPriv->currentBuffer) + offset += (new_h >> 1) * pGeode->Pitch; +#endif + + dst_start = pGeode->FBBase + offset + left; + tmp = ((top >> 1) * srcPitch2) + (left >> 1); + s2offset += tmp; + s3offset += tmp; + if (id == FOURCC_I420) { + tmp = s2offset; + s2offset = s3offset; + s3offset = tmp; + } + nlines = ((By2 + 1) & ~1) - top; + } + break; + case FOURCC_UYVY: + case FOURCC_YUY2: + case FOURCC_Y800: + default: + left <<= 1; + buf += (top * srcPitch) + left; + nlines = By2 - top; + offset = (pPriv->area->box.y1 * pGeode->Pitch) + (top * dstPitch); +#if DBUF + if (pPriv->doubleBuffer && pPriv->currentBuffer) + offset += (new_h >> 1) * pGeode->Pitch; +#endif + + dst_start = pGeode->FBBase + offset + left; + break; + } + s1offset = (top * srcPitch) + left; + +#if REINIT + /* update cliplist */ + REGION_COPY(pScrni->pScreen, &pPriv->clip, clipBoxes); + if (pPriv->colorKeyMode == 0) { + /* draw these */ + XAAFillSolidRects(pScrni, pPriv->colorKey, GXcopy, ~0, + REGION_NUM_RECTS(clipBoxes), + REGION_RECTS(clipBoxes)); + } + LXDisplayVideo(pScrni, id, offset, width, height, dstPitch, + Bx1, By1, Bx2, By2, &dstBox, src_w, src_h, drw_w, + drw_h); + } +#endif + + switch (id) { + + case FOURCC_Y800: + LXCopyGreyscale(buf, dst_start, srcPitch, dstPitch, nlines, npixels); + break; + case FOURCC_YV12: + case FOURCC_I420: + LXCopyData420(buf + s1offset, dst_start, srcPitch, dstPitch, nlines, + npixels); + LXCopyData420(buf + s2offset, dst_start + d2offset, srcPitch2, + dstPitch2, nlines >> 1, npixels >> 1); + LXCopyData420(buf + s3offset, dst_start + d3offset, srcPitch2, + dstPitch2, nlines >> 1, npixels >> 1); + break; + case FOURCC_UYVY: + case FOURCC_YUY2: + default: + LXCopyData422(buf, dst_start, srcPitch, dstPitch, nlines, npixels); + break; + } +#if !REINIT + /* update cliplist */ + REGION_COPY(pScrni->pScreen, &pPriv->clip, clipBoxes); + if (pPriv->colorKeyMode == 0) { + /* draw these */ + XAAFillSolidRects(pScrni, pPriv->colorKey, GXcopy, ~0, + REGION_NUM_RECTS(clipBoxes), REGION_RECTS(clipBoxes)); + } + LXDisplayVideo(pScrni, id, offset, width, height, dstPitch, + Bx1, By1, Bx2, By2, &dstBox, src_w, src_h, drw_w, drw_h); +#endif + +#if XV_PROFILE + UpdateCurrentTime(); + newtime = currentTime.milliseconds; + DBLOG(1, "PI %d\n", newtime - oldtime); +#endif + +#if DBUF + pPriv->currentBuffer ^= 1; +#endif + + pPriv->videoStatus = CLIENT_VIDEO_ON; + pGeode->OverlayON = TRUE; + return Success; +} + +/*---------------------------------------------------------------------------- + * LXQueryImageAttributes + * + * Description :This function is called to let the driver specify how data + * for a particular image of size width by height should be + * stored. + * + * Parameters. + * pScrni :Screen handler pointer having screen information. + * id :Id for the video format + * width :width of the image (can be modified by the driver) + * height :height of the image (can be modified by the driver) + * Returns : Size of the memory required for storing this image + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ +static int +LXQueryImageAttributes(ScrnInfoPtr pScrni, + int id, + unsigned short *w, unsigned short *h, + int *pitches, int *offsets) +{ + int size; + int tmp; + + if (*w > 1024) + *w = 1024; + if (*h > 1024) + *h = 1024; + + *w = (*w + 1) & ~1; + if (offsets) + offsets[0] = 0; + + switch (id) { + case FOURCC_YV12: + case FOURCC_I420: + *h = (*h + 1) & ~1; + size = (*w + 3) & ~3; + if (pitches) + pitches[0] = size; + size *= *h; + if (offsets) + offsets[1] = size; + tmp = ((*w >> 1) + 3) & ~3; + if (pitches) + pitches[1] = pitches[2] = tmp; + tmp *= (*h >> 1); + size += tmp; + if (offsets) + offsets[2] = size; + size += tmp; + break; + case FOURCC_UYVY: + case FOURCC_YUY2: + case FOURCC_Y800: + default: + size = *w << 1; + if (pitches) + pitches[0] = size; + size *= *h; + break; + } + DBLOG(1,"LXQueryImageAttributes(%d)= %d, %dx%d %d/%d/%d %d/%d/%d\n", + id,size,*w,*h,pitches[0],pitches[1],pitches[2],offsets[0],offsets[1],offsets[2]); + return size; +} + +static void +LXBlockHandler(int i, pointer blockData, pointer pTimeout, pointer pReadmask) +{ + ScreenPtr pScrn = screenInfo.screens[i]; + ScrnInfoPtr pScrni = xf86Screens[i]; + GeodePtr pGeode = GEODEPTR(pScrni); + GeodePortPrivPtr pPriv = GET_PORT_PRIVATE(pScrni); + + pScrn->BlockHandler = pGeode->BlockHandler; + (*pScrn->BlockHandler) (i, blockData, pTimeout, pReadmask); + pScrn->BlockHandler = LXBlockHandler; + + if (pPriv->videoStatus & TIMER_MASK) { + DBLOG(1,"LXBlockHandler(%d)\n",i); + LXAccelSync(pScrni); + UpdateCurrentTime(); + if (pPriv->videoStatus & OFF_TIMER) { + if (pPriv->offTime < currentTime.milliseconds) { + df_set_video_enable(0,0); + pPriv->videoStatus = FREE_TIMER; + pPriv->freeTime = currentTime.milliseconds + FREE_DELAY; + } + } else { /* FREE_TIMER */ + if (pPriv->freeTime < currentTime.milliseconds) { + if (pPriv->area) { + xf86FreeOffscreenArea(pPriv->area); + pPriv->area = NULL; + } + pPriv->videoStatus = 0; + } + } + } +} + +/****************** Offscreen stuff ***************/ + +typedef struct +{ + FBAreaPtr area; + FBLinearPtr linear; + Bool isOn; +} +OffscreenPrivRec, *OffscreenPrivPtr; + +/*---------------------------------------------------------------------------- + * LXAllocateSurface + * + * Description :This function allocates an area of w by h in the offscreen + * Parameters. + * pScrni :Screen handler pointer having screen information. + * + * Returns :None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ + +static int +LXAllocateSurface(ScrnInfoPtr pScrni, + int id, + unsigned short w, unsigned short h, XF86SurfacePtr surface) +{ + FBAreaPtr area; + int pitch, fbpitch, numlines; + OffscreenPrivPtr pPriv; + DBLOG(1,"LXAllocateSurface(id %d, %dx%d)\n",id,w,h); + + if ((w > 1024) || (h > 1024)) + return BadAlloc; + + w = (w + 1) & ~1; + pitch = ((w << 1) + 15) & ~15; + fbpitch = pScrni->bitsPerPixel * pScrni->displayWidth >> 3; + numlines = ((pitch * h) + fbpitch - 1) / fbpitch; + + if (!(area = LXAllocateMemory(pScrni, NULL, numlines))) + return BadAlloc; + + surface->width = w; + surface->height = h; + + if (!(surface->pitches = xalloc(sizeof(int)))) + return BadAlloc; + if (!(surface->offsets = xalloc(sizeof(int)))) { + xfree(surface->pitches); + return BadAlloc; + } + if (!(pPriv = xalloc(sizeof(OffscreenPrivRec)))) { + xfree(surface->pitches); + xfree(surface->offsets); + return BadAlloc; + } + + pPriv->area = area; + pPriv->isOn = FALSE; + + surface->pScrn = pScrni; + surface->id = id; + surface->pitches[0] = pitch; + surface->offsets[0] = area->box.y1 * fbpitch; + surface->devPrivate.ptr = (pointer) pPriv; + + return Success; +} + +static int +LXStopSurface(XF86SurfacePtr surface) +{ + OffscreenPrivPtr pPriv = (OffscreenPrivPtr) surface->devPrivate.ptr; + DBLOG(1,"LXStopSurface()\n"); + + if (pPriv->isOn) { + pPriv->isOn = FALSE; + } + + return Success; +} + +static int +LXFreeSurface(XF86SurfacePtr surface) +{ + OffscreenPrivPtr pPriv = (OffscreenPrivPtr) surface->devPrivate.ptr; + DBLOG(1,"LXFreeSurface()\n"); + + if (pPriv->isOn) + LXStopSurface(surface); + xf86FreeOffscreenArea(pPriv->area); + xfree(surface->pitches); + xfree(surface->offsets); + xfree(surface->devPrivate.ptr); + + return Success; +} + +static int +LXGetSurfaceAttribute(ScrnInfoPtr pScrni, Atom attribute, INT32 * value) +{ + return LXGetPortAttribute(pScrni, attribute, value, + (pointer) (GET_PORT_PRIVATE(pScrni))); +} + +static int +LXSetSurfaceAttribute(ScrnInfoPtr pScrni, Atom attribute, INT32 value) +{ + return LXSetPortAttribute(pScrni, attribute, value, + (pointer) (GET_PORT_PRIVATE(pScrni))); +} + +static int +LXDisplaySurface(XF86SurfacePtr surface, + short src_x, short src_y, + short drw_x, short drw_y, + short src_w, short src_h, + short drw_w, short drw_h, RegionPtr clipBoxes) +{ + OffscreenPrivPtr pPriv = (OffscreenPrivPtr) surface->devPrivate.ptr; + ScrnInfoPtr pScrni = surface->pScrn; + GeodePortPrivPtr portPriv = GET_PORT_PRIVATE(pScrni); + INT32 x1, y1, x2, y2; + BoxRec dstBox; + DBLOG(1,"LXDisplaySurface(src %d,%d %dx%d, dst %d,%d %dx%d)\n", + src_x,src_y,src_w,src_h,drw_x,drw_y,drw_w,drw_h); + + DEBUGMSG(0, (0, X_NONE, "DisplaySuface\n")); + x1 = src_x; + x2 = src_x + src_w; + y1 = src_y; + y2 = src_y + src_h; + + dstBox.x1 = drw_x; + dstBox.x2 = drw_x + drw_w; + dstBox.y1 = drw_y; + dstBox.y2 = drw_y + drw_h; + + if ((x1 >= x2) || (y1 >= y2)) + return Success; + + dstBox.x1 -= pScrni->frameX0; + dstBox.x2 -= pScrni->frameX0; + dstBox.y1 -= pScrni->frameY0; + dstBox.y2 -= pScrni->frameY0; + + xf86XVFillKeyHelper(pScrni->pScreen, portPriv->colorKey, clipBoxes); + + LXDisplayVideo(pScrni, surface->id, surface->offsets[0], + surface->width, surface->height, surface->pitches[0], + x1, y1, x2, y2, &dstBox, src_w, src_h, drw_w, drw_h); + + pPriv->isOn = TRUE; + if (portPriv->videoStatus & CLIENT_VIDEO_ON) { + REGION_EMPTY(pScrni->pScreen, &portPriv->clip); + UpdateCurrentTime(); + portPriv->videoStatus = FREE_TIMER; + portPriv->freeTime = currentTime.milliseconds + FREE_DELAY; + } + + return Success; +} + +/*---------------------------------------------------------------------------- + * LXInitOffscreenImages + * + * Description :This function sets up the offscreen memory management.It fills + * in the XF86OffscreenImagePtr structure with functions to handle + * offscreen memory operations. + * + * Parameters. + * pScrn :Screen handler pointer having screen information. + * + * Returns : None + * + * Comments :None + * +*---------------------------------------------------------------------------- +*/ +static void +LXInitOffscreenImages(ScreenPtr pScrn) +{ + XF86OffscreenImagePtr offscreenImages; + DBLOG(1,"LXInitOffscreenImages()\n"); + + /* need to free this someplace */ + if (!(offscreenImages = xalloc(sizeof(XF86OffscreenImageRec)))) + return; + + offscreenImages[0].image = &Images[0]; + offscreenImages[0].flags = VIDEO_OVERLAID_IMAGES | VIDEO_CLIP_TO_VIEWPORT; + offscreenImages[0].alloc_surface = LXAllocateSurface; + offscreenImages[0].free_surface = LXFreeSurface; + offscreenImages[0].display = LXDisplaySurface; + offscreenImages[0].stop = LXStopSurface; + offscreenImages[0].setAttribute = LXSetSurfaceAttribute; + offscreenImages[0].getAttribute = LXGetSurfaceAttribute; + offscreenImages[0].max_width = 1024; + offscreenImages[0].max_height = 1024; + offscreenImages[0].num_attributes = NUM_ATTRIBUTES; + offscreenImages[0].attributes = Attributes; + + xf86XVRegisterOffscreenImages(pScrn, offscreenImages, 1); +} + +#endif /* !XvExtension */ +#endif /* !AMD_V4L2_VIDEO */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/cimarron.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/cimarron.c 2005-07-13 13:16:49.000000000 -0600 @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * Base include file for the Cimarron library. This file should be modified + * and included in any Cimarron-based project. + * */ + +/*----------------------------------------------------------------------*/ +/* MODULE SETTINGS */ +/* The following #defines affect which modules are included in the */ +/* project. */ +/*----------------------------------------------------------------------*/ + +#define CIMARRON_INCLUDE_GP 1 +#define CIMARRON_INCLUDE_VG 1 +#define CIMARRON_INCLUDE_VIP 1 +#define CIMARRON_INCLUDE_VOP 1 +#define CIMARRON_INCLUDE_VIDEO 1 +#define CIMARRON_INCLUDE_INIT 1 + +#define CIMARRON_INCLUDE_VG_READ_ROUTINES 1 +#define CIMARRON_INCLUDE_DF_READ_ROUTINES 1 +#define CIMARRON_INCLUDE_VIP_READ_ROUTINES 1 +#define CIMARRON_INCLUDE_VOP_READ_ROUTINES 1 + +/*----------------------------------------------------------------------*/ +/* HARDWARE ACCESS SETTINGS */ +/* The following #defines affect how the Cimarron macros access the */ +/* hardware. The hardware access macros are broken up into groups. */ +/* Each group includes an enabling #define as well as several #define */ +/* options that modify the macro configuration that is included. */ +/* If the enabling define is deleted or all options are set to 0, the */ +/* corresponding macros must be implemented by the user. The */ +/* combinations are explained as follows: */ +/* must be manually defined by the user. This allows a user to use the */ +/* cim_defs.h file for only those macros that suit the needs of his/her */ +/* project. For example, a user may need custom implementations of the */ +/* I/O and MSR macros, but may still want to use the default macros to */ +/* read and write hardware registers. The combinations are explained as */ +/* follows: */ +/* */ +/* Register Group: */ +/* Disabling define: */ +/* CIMARRON_EXCLUDE_REGISTER_ACCESS_MACROS */ +/* Define this setting to exclude the register access macros. */ +/* This setting is the inverse of the other group settings in */ +/* that these macros are included by default. This allows the */ +/* cim_defs.h file to be included outside of cimarron.c for */ +/* basic operations. */ +/* */ +/* Memory Group: */ +/* Enabling define: */ +/* CIMARRON_INCLUDE_STRING_MACROS */ +/* Options: */ +/* CIMARRON_OPTIMIZE_ASSEMBLY */ +/* Set to 1 to allow the use of inline assembly when writing */ +/* large chunks of data to memory. Essentially, this allows */ +/* a rep movsd in place of a slower C for-loop. */ +/* CIMARRON_OPTIMIZE_FORLOOP */ +/* Define for C only data writes. */ +/* */ +/* MSR Group: */ +/* Enabling define: */ +/* CIMARRON_INCLUDE_MSR_MACROS */ +/* Options: */ +/* CIMARRON_MSR_DIRECT_ASM */ +/* Set to 1 to allow the use of the rdmsr and wrmsr opcodes in */ +/* inline assembly. */ +/* CIMARRON_MSR_VSA_IO */ +/* Set to 1 to access MSRs using a VSAII virtual register. */ +/* CIMARRON_MSR_KERNEL_ROUTINE */ +/* Set to 1 to access MSRs using a wrapper routine in the */ +/* Linux kernel. */ +/* */ +/* IO Group: */ +/* Enabling define: */ +/* CIMARRON_INCLUDE_IO_MACROS */ +/* Options: */ +/* CIMARRON_IO_DIRECT_ACCESS */ +/* Set to 1 to perform IO accesses using inline assembly. */ +/* CIMARRON_IO_ABSTRACTED_ASM */ +/* Set to 1 to perform IO using abstracted IO in Linux. */ +/* */ +/* Custom Group: */ +/* Disabling define: */ +/* CIMARRON_EXCLUDE_CUSTOM_MACROS */ +/* By default, the custom macros (the macros used by */ +/* gp_custom_convert_blt) are mapped to the normal command */ +/* string macros. Setting this to 1 allows the user to */ +/* create a custom implementation. */ +/*----------------------------------------------------------------------*/ + +/* UNCOMMENT THE FOLLOWING LINE TO EXCLUDE BASIC REGISTER ACCESS MACROS */ + +/* #define CIMARRON_EXCLUDE_REGISTER_ACCESS_MACROS */ + +#define CIMARRON_INCLUDE_STRING_MACROS +#define CIMARRON_OPTIMIZE_ASSEMBLY 0 +#define CIMARRON_OPTIMIZE_FORLOOP 0 +#define CIMARRON_OPTIMIZE_ABSTRACTED_ASM 1 + +#define CIMARRON_INCLUDE_MSR_MACROS +#define CIMARRON_MSR_DIRECT_ASM 0 +#define CIMARRON_MSR_VSA_IO 0 +#define CIMARRON_MSR_ABSTRACTED_ASM 1 +#define CIMARRON_MSR_KERNEL_ROUTINE 0 + +#define CIMARRON_INCLUDE_IO_MACROS +#define CIMARRON_IO_DIRECT_ACCESS 0 +#define CIMARRON_IO_ABSTRACTED_ASM 1 + +/* UNCOMMENT THE FOLLOWING LINE TO IMPLEMENT CUSTOM MACROS FOR GP_CUSTOM_CONVERT_BLT */ + +/* #define CIMARRON_EXCLUDE_CUSTOM_MACROS */ + +/*----------------------------------------------------------------------*/ +/* MODULE VARIABLES */ +/* The following #defines affect how global variables in each Cimarron */ +/* module are defined. These variables can be made static (to prevent */ +/* naming conflicts) or they can be defined without the static keyword */ +/* (to allow extern references). */ +/*----------------------------------------------------------------------*/ + +#if 1 +#define CIMARRON_STATIC static +#else +#define CIMARRON_STATIC +#endif + +/*----------------------------------------------------------------------*/ +/* CIMARRON GLOBAL VARIABLES */ +/* These globals are used by the hardware access macros. They must be */ +/* initialized by the application to point to the memory-mapped */ +/* registers of their respective blocks. */ +/*----------------------------------------------------------------------*/ + +unsigned char *cim_gp_ptr = (unsigned char *)0; +unsigned char *cim_fb_ptr = (unsigned char *)0; +unsigned char *cim_cmd_base_ptr = (unsigned char *)0; +unsigned char *cim_cmd_ptr = (unsigned char *)0; +unsigned char *cim_vid_ptr = (unsigned char *)0; +unsigned char *cim_vip_ptr = (unsigned char *)0; +unsigned char *cim_vg_ptr = (unsigned char *)0; + +/*----------------------------------------------------------------------*/ +/* INCLUDE RELEVANT CIMARRON HEADERS */ +/*----------------------------------------------------------------------*/ + +/* HARDWARE REGISTER DEFINITIONS */ + +#include "cim_regs.h" + +/* ROUTINE DEFINITIONS */ +/* All routines have a prototype, even those that are not included */ +/* via #ifdefs. This prevents the user from having to include the */ +/* correct #defines anywhere he/she wants to call a Cimarron routine. */ + +#include "cim_rtns.h" + +/* HARDWARE ACCESS MACROS */ + +#include "cim_defs.h" + +/*----------------------------------------------------------------------*/ +/* CIMARRON MODULES */ +/* Modules and sub-modules are included based on user settings. Note */ +/* that excluding one or more modules may result in functionality */ +/* holes. */ +/*----------------------------------------------------------------------*/ + +/* GRAPHICS PROCESSOR */ + +#if CIMARRON_INCLUDE_GP +#include "cim_gp.c" +#endif + +/* VIDEO GENERATOR */ + +#if CIMARRON_INCLUDE_VG +#include "cim_modes.c" +#include "cim_vg.c" +#endif + +/* DISPLAY FILTER */ + +#if CIMARRON_INCLUDE_VIDEO +#include "cim_filter.c" +#include "cim_df.c" +#endif + +/* INITIALIZATION AND DETECTION */ + +#if CIMARRON_INCLUDE_INIT +#include "cim_init.c" +#endif + +/* VIP SUPPORT */ + +#if CIMARRON_INCLUDE_VIP +#include "cim_vip.c" +#endif + +/* VOP SUPPORT */ + +#if CIMARRON_INCLUDE_VOP +#include "cim_vop.c" +#endif + +/* MSR ACCESS */ +/* This module is used to access machine-specific registers. */ +/* It cannot be excluded from a project. */ + +#include "cim_msr.c" + --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_shadow.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_shadow.c 2005-08-03 16:37:41.000000000 -0600 @@ -0,0 +1,394 @@ +/* + * $Workfile: amd_gx3_shadow.c $ + * $Revision: #3 $ + * $Author: raymondd $ + * + * File Contents: Direct graphics display routines are implemented and + * graphics rendering are all done in memory. + * + * Project: Geode Xfree Frame buffer device driver. + * + * + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + + +#include "xf86.h" +#include "xf86_OSproc.h" +#include "xf86Resources.h" +#include "xf86_ansic.h" +#include "xf86PciInfo.h" +#include "xf86Pci.h" +#include "amd.h" +#include "shadowfb.h" +#include "servermd.h" + +#define CLIP(sip,bp,u1,v1,u2,v2) \ + u1 = bp->x1; v1 = bp->y1; \ + u2 = bp->x2; v2 = bp->y2; \ + if( u1 < 0 ) u1 = 0; \ + if( v1 < 0 ) v1 = 0; \ + if( u1 > sip->virtualX ) u1 = sip->virtualX; \ + if( v1 > sip->virtualY ) v1 = sip->virtualY; \ + if( u2 < 0 ) u2 = 0; \ + if( v2 < 0 ) v2 = 0; \ + if( u2 > sip->virtualX ) u2 = sip->virtualX; \ + if( v2 > sip->virtualY ) v2 = sip->virtualY; + +void GXAccelSync(ScrnInfoPtr pScrni); + +void +GXRotation0(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = x; + *newY = y; +} + +void +GXRotation1(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = (h-1) - y; + *newY = x; +} + +void +GXRotation2(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = (w-1) - x; + *newY = (h-1) - y; +} + +void +GXRotation3(int x,int y,int w,int h,int *newX,int *newY) +{ + *newY = (w-1) - x; + *newX = y; +} + +void +GXRBltXlat0(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = x; + *newY = y; +} + +void +GXRBltXlat1(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = x - (h-1); + *newY = y; +} + +void +GXRBltXlat2(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = x - (w-1); + *newY = y - (h-1); +} + +void +GXRBltXlat3(int x,int y,int w,int h,int *newX,int *newY) +{ + *newX = x; + *newY = y - (w-1); +} + +/*---------------------------------------------------------------------------- + * GXPointerMoved. + * + * Description :This function moves one screen memory from one area to other. + * + * Parameters. + * index :Pointer to screen index. + * x :Specifies the new x co-ordinates of new area. + * y :Specifies the new y co-ordinates of new area. + * Returns :none + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ +void +GXPointerMoved(int index, int x, int y) +{ + ScrnInfoPtr pScrni = xf86Screens[index]; + GeodePtr pGeode = GEODEPTR(pScrni); + Bool frameChanged = FALSE; + + if( x < 0 ) + x = 0; + else if( x >= pScrni->virtualX ) + x = pScrni->virtualX-1; + if( y < 0 ) + y = 0; + else if( y >= pScrni->virtualY ) + y = pScrni->virtualY-1; + + if( pScrni->frameX0 > x ) { + pScrni->frameX0 = x; + pScrni->frameX1 = x + pGeode->HDisplay - 1; + frameChanged = TRUE ; + } + + if( pScrni->frameX1 < x ) { + pScrni->frameX1 = x + 1; + pScrni->frameX0 = x - pGeode->HDisplay + 1; + frameChanged = TRUE ; + } + + if( pScrni->frameY0 > y ) { + pScrni->frameY0 = y; + pScrni->frameY1 = y + pGeode->VDisplay - 1; + frameChanged = TRUE; + } + + if( pScrni->frameY1 < y ) { + pScrni->frameY1 = y; + pScrni->frameY0 = y - pGeode->VDisplay + 1; + frameChanged = TRUE; + } + + if(frameChanged && pScrni->AdjustFrame != NULL) + pScrni->AdjustFrame(pScrni->scrnIndex, pScrni->frameX0, pScrni->frameY0, 0); +} + +void +GXRefreshArea_Cpy(ScrnInfoPtr pScrni, int num, BoxPtr pbox) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + int x1, y1, x2, y2, width, height; + unsigned long src, dst; + int Bpp = pScrni->bitsPerPixel >> 3; + gfx_set_raster_operation(0xcc); /* copy dst=src */ + for( ; --num>=0; ++pbox ) { + CLIP(pScrni,pbox,x1,y1,x2,y2); + if( (width=x2-x1) <=0 || (height=y2-y1) <= 0 ) continue; + src = y1*pGeode->ShadowPitch + x1*Bpp; + dst = pGeode->FBOffset + y1*pGeode->Pitch + x1*Bpp; + gfx2_set_destination_stride(pGeode->Pitch); + gfx2_color_bitmap_to_screen_blt(0,0, dst, width,height, + pGeode->ShadowPtr+src, pGeode->ShadowPitch); + } +} + +/*---------------------------------------------------------------------------- + * GXRefreshArea8. + * + * Description :This function copies the memory to be displayed from the + * shadow pointer by 8bpp. + * Parameters. + * pScrni :Pointer to ScrnInfo structure. + * num :Specifies the num of squarebox area to be displayed. + * pbox :Points to square of memory to be displayed. + * Returns :none + * + * Comments :none + * +*---------------------------------------------------------------------------- +*/ + +void +GXRefreshArea0_Cpu(ScrnInfoPtr pScrni, int num, BoxPtr pbox) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + int width, height, x1, y1, x2, y2; + unsigned char *src, *dst; + int Bpp = pScrni->bitsPerPixel >> 3; + GXAccelSync(pScrni); + for( ; --num>=0; ++pbox ) { + CLIP(pScrni,pbox,x1,y1,x2,y2); + if( (width=x2-x1) <=0 || (height=y2-y1) <= 0 ) continue; + src = pGeode->ShadowPtr + y1*pGeode->ShadowPitch + x1*Bpp; + dst = pGeode->FBBase+pGeode->FBOffset + y1*pGeode->Pitch + x1*Bpp; + width *= Bpp; + while( --height >= 0 ) { + memcpy(dst,src,width); + dst += pGeode->Pitch; + src += pGeode->ShadowPitch; + } + } +} + +#define RefreshArea1_Cpu(nm,typ) \ +void GXRefreshArea1_Cpu##nm(ScrnInfoPtr pScrni, int num, BoxPtr pbox)\ +{ \ + GeodePtr pGeode = GEODEPTR(pScrni); \ + int l, width, height, x1, y1, x2, y2, newX, newY; \ + unsigned long src, dst, dp; \ + typ *sp; \ + GXAccelSync(pScrni); \ + for( ; --num>=0; ++pbox ) { \ + CLIP(pScrni,pbox,x1,y1,x2,y2); \ + if( (width=x2-x1) <=0 || (height=y2-y1) <= 0 ) continue; \ + src = y1*pGeode->ShadowPitch + x1*sizeof(typ); \ + newX = pScrni->virtualY-1 - y1; \ + newY = x1; \ + dst = pGeode->FBOffset + newY*pGeode->Pitch + newX*sizeof(typ); \ + while( --height >= 0 ) { \ + sp = (typ *)(pGeode->ShadowPtr + src); \ + dp = (unsigned long)(pGeode->FBBase + dst); \ + for( l=width; --l>=0; ) { \ + *(typ *)dp = *sp++; \ + dp += pGeode->Pitch; \ + } \ + dst -= sizeof(typ); \ + src += pGeode->ShadowPitch; \ + } \ + } \ +} + +RefreshArea1_Cpu( 8,unsigned char) +RefreshArea1_Cpu(16,unsigned short) +RefreshArea1_Cpu(32,unsigned int) + +#define RefreshArea2_Cpu(nm,typ) \ +void GXRefreshArea2_Cpu##nm(ScrnInfoPtr pScrni, int num, BoxPtr pbox)\ +{ \ + GeodePtr pGeode = GEODEPTR(pScrni); \ + int l, width, height, x1, y1, x2, y2, newX, newY; \ + unsigned long src, dst, dp; \ + typ *sp; \ + GXAccelSync(pScrni); \ + for( ; --num>=0; ++pbox ) { \ + CLIP(pScrni,pbox,x1,y1,x2,y2); \ + if( (width=x2-x1) <=0 || (height=y2-y1) <= 0 ) continue; \ + src = y1*pGeode->ShadowPitch + x1*sizeof(typ); \ + newX = pScrni->virtualX-1 - x1; \ + newY = pScrni->virtualY-1 - y1; \ + dst = pGeode->FBOffset + newY*pGeode->Pitch + newX*sizeof(typ); \ + while( --height >= 0 ) { \ + sp = (typ *)(pGeode->ShadowPtr + src); \ + dp = (unsigned long)(pGeode->FBBase + dst); \ + for( l=width; --l>=0; ) { \ + *(typ *)dp = *sp++; \ + dp -= sizeof(typ); \ + } \ + src += pGeode->ShadowPitch; \ + dst -= pGeode->Pitch; \ + } \ + } \ +} + +RefreshArea2_Cpu( 8,unsigned char) +RefreshArea2_Cpu(16,unsigned short) +RefreshArea2_Cpu(32,unsigned int) + +#define RefreshArea3_Cpu(nm,typ) \ +void GXRefreshArea3_Cpu##nm(ScrnInfoPtr pScrni, int num, BoxPtr pbox)\ +{ \ + GeodePtr pGeode = GEODEPTR(pScrni); \ + int l, width, height, x1, y1, x2, y2, newX, newY; \ + unsigned long src, dst, dp; \ + typ *sp; \ + GXAccelSync(pScrni); \ + for( ; --num>=0; ++pbox ) { \ + CLIP(pScrni,pbox,x1,y1,x2,y2); \ + if( (width=x2-x1) <=0 || (height=y2-y1) <= 0 ) continue; \ + src = y1*pGeode->ShadowPitch + x1*sizeof(typ); \ + newX = y1; \ + newY = pScrni->virtualX-1 - x1; \ + dst = pGeode->FBOffset + newY*pGeode->Pitch + newX*sizeof(typ); \ + while( --height >= 0 ) { \ + sp = (typ *)(pGeode->ShadowPtr + src); \ + dp = (unsigned long)(pGeode->FBBase + dst); \ + for( l=width; --l>=0; ) { \ + *(typ *)dp = *sp++; \ + dp -= pGeode->Pitch; \ + } \ + dst += sizeof(typ); \ + src += pGeode->ShadowPitch; \ + } \ + } \ +} + +RefreshArea3_Cpu( 8,unsigned char) +RefreshArea3_Cpu(16,unsigned short) +RefreshArea3_Cpu(32,unsigned int) + +void +GXRotationInit(ScrnInfoPtr pScrni) +{ + GeodePtr pGeode = GEODEPTR(pScrni); + switch( pGeode->Rotate ) { + case 1: + pGeode->Rotation = GXRotation1; + pGeode->RBltXlat = GXRBltXlat1; + break; + case 2: + pGeode->Rotation = GXRotation2; + pGeode->RBltXlat = GXRBltXlat2; + break; + case 3: + pGeode->Rotation = GXRotation3; + pGeode->RBltXlat = GXRBltXlat3; + break; + default: + pGeode->Rotation = GXRotation0; + pGeode->RBltXlat = GXRBltXlat0; + break; + } +} + +void +GXShadowFBInit(ScreenPtr pScrn,GeodePtr pGeode,int bytpp) +{ + RefreshAreaFuncPtr refreshArea; + switch( bytpp ) { + case 2: + switch( pGeode->Rotate ) { + case 1: refreshArea = GXRefreshArea1_Cpu16; break; + case 2: refreshArea = GXRefreshArea2_Cpu16; break; + case 3: refreshArea = GXRefreshArea3_Cpu16; break; + default: refreshArea = GXRefreshArea0_Cpu; break; + } + break; + case 4: + switch( pGeode->Rotate ) { + case 1: refreshArea = GXRefreshArea1_Cpu32; break; + case 2: refreshArea = GXRefreshArea2_Cpu32; break; + case 3: refreshArea = GXRefreshArea3_Cpu32; break; + default: refreshArea = GXRefreshArea0_Cpu; break; + } + break; + default: + switch( pGeode->Rotate ) { + case 1: refreshArea = GXRefreshArea1_Cpu8; break; + case 2: refreshArea = GXRefreshArea2_Cpu8; break; + case 3: refreshArea = GXRefreshArea3_Cpu8; break; + default: refreshArea = GXRefreshArea0_Cpu; break; + } + break; + } + ShadowFBInit(pScrn, refreshArea); +} + +/* End of file */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_regacc.c 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/amd_gx_regacc.c 2005-08-03 13:20:51.000000000 -0600 @@ -0,0 +1,340 @@ +/* + * $Workfile: amd_regacc.c $ + * $Revision: #2 $ + * $Author: raymondd $ + * + * This is the main file used to add Durango graphics support to a software + * project. The main reason to have a single file include the other files + * is that it centralizes the location of the compiler options. This file + * should be tuned for a specific implementation, and then modified as needed + * for new Durango releases. The releases.txt file indicates any updates to + * this main file, such as a new definition for a new hardware platform. + * + * In other words, this file should be copied from the Durango source files + * once when a software project starts, and then maintained as necessary. + * It should not be recopied with new versions of Durango unless the + * developer is willing to tune the file again for the specific project. + */ + +/* + * Copyright (c) 2003-2005 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Neither the name of the Advanced Micro Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * */ +/* + * */ +/* + * */ + +#include "gfx_rtns.h" +#include "gfx_defs.h" +#include "gfx_regs.h" + +#define GU2_WAIT_PENDING while(READ_GP32(MGP_BLT_STATUS) & MGP_BS_BLT_PENDING) +#define GU2_WAIT_HALF_EMPTY while(!(READ_GP32(MGP_BLT_STATUS) & MGP_BS_HALF_EMPTY)) + +extern unsigned long gu2_pitch; +extern unsigned long gu2_xshift; +extern unsigned short GFXpatternFlags; +extern unsigned long gu2_rop32; +extern unsigned short gu2_blt_mode; + + + +void gfx_write_reg8(unsigned long offset, unsigned char value); +void gfx_write_reg16(unsigned long offset, unsigned short value); +void gfx_write_reg32(unsigned long offset, unsigned long value); +unsigned short gfx_read_reg16(unsigned long offset); +unsigned long gfx_read_reg32(unsigned long offset); +void gfx_write_vid32(unsigned long offset, unsigned long value); +unsigned long gfx_read_vid32(unsigned long offset); +unsigned long gfx_read_vip32(unsigned long offset); +void gfx_write_vip32(unsigned long offset, unsigned long value); +void gfx_mono_bitmap_to_screen_blt_swp(unsigned short srcx, + unsigned short srcy, + unsigned short dstx, + unsigned short dsty, + unsigned short width, + unsigned short height, + unsigned char *data, short pitch); +unsigned int GetVideoMemSize(void); + +/* ROUTINES added accessing hardware reg */ +void +gfx_write_reg8(unsigned long offset, unsigned char value) +{ + WRITE_REG8(offset, value); +} + +void +gfx_write_reg16(unsigned long offset, unsigned short value) +{ + WRITE_REG16(offset, value); +} + +void +gfx_write_reg32(unsigned long offset, unsigned long value) +{ + WRITE_REG32(offset, value); +} +unsigned short +gfx_read_reg16(unsigned long offset) +{ + unsigned short value; + + value = READ_REG16(offset); + return value; +} +unsigned long +gfx_read_reg32(unsigned long offset) +{ + unsigned long value; + + value = READ_REG32(offset); + return value; +} + +void +gfx_write_vid32(unsigned long offset, unsigned long value) +{ + WRITE_VID32(offset, value); +} +unsigned long +gfx_read_vid32(unsigned long offset) +{ + unsigned long value; + + value = READ_VID32(offset); + return value; +} + +/*Addition for the VIP code */ +unsigned long +gfx_read_vip32(unsigned long offset) +{ + unsigned long value; + + value = READ_VIP32(offset); + return value; +} + +void +gfx_write_vip32(unsigned long offset, unsigned long value) +{ + WRITE_VIP32(offset, value); +} + +#define SWAP_BITS_IN_BYTES(v) \ + (((0x01010101 & (v)) << 7) | ((0x02020202 & (v)) << 5) | \ + ((0x04040404 & (v)) << 3) | ((0x08080808 & (v)) << 1) | \ + ((0x10101010 & (v)) >> 1) | ((0x20202020 & (v)) >> 3) | \ + ((0x40404040 & (v)) >> 5) | ((0x80808080 & (v)) >> 7)) + +#define WRITE_GPREG_STRING32_SWP(regoffset, dwords, counter, array, array_offset, temp) \ +{ \ + temp = (unsigned long)array + (array_offset); \ + for (counter = 0; counter < dwords; counter++) \ + WRITE_GP32 (regoffset, SWAP_BITS_IN_BYTES(*((unsigned long *)temp + counter))); \ +} + +void +gfx_mono_bitmap_to_screen_blt_swp(unsigned short srcx, unsigned short srcy, + unsigned short dstx, unsigned short dsty, + unsigned short width, unsigned short height, + unsigned char *data, short pitch) +{ + unsigned long dstoffset, size, bytes; + unsigned long offset, temp_offset, temp1 = 0, temp2 = 0; + unsigned long i, j = 0, fifo_lines, dwords_extra, bytes_extra; + unsigned long shift = 0; + + size = (((unsigned long)width) << 16) | height; + + /* CALCULATE STARTING OFFSETS */ + + offset = (unsigned long)srcy *pitch + ((unsigned long)srcx >> 3); + + dstoffset = (unsigned long)dsty *gu2_pitch + + (((unsigned long)dstx) << gu2_xshift); + + /* CHECK IF PATTERN ORIGINS NEED TO BE SET */ + + if (GFXpatternFlags) { + /* COMBINE X AND Y PATTERN ORIGINS WITH OFFSET */ + + dstoffset |= ((unsigned long)(dstx & 7)) << 26; + dstoffset |= ((unsigned long)(dsty & 7)) << 29; + } + + bytes = ((srcx & 7) + width + 7) >> 3; + fifo_lines = bytes >> 5; + dwords_extra = (bytes & 0x0000001Cl) >> 2; + bytes_extra = bytes & 0x00000003l; + + /* POLL UNTIL ABLE TO WRITE TO THE REGISTERS */ + /* Put off poll for as long as possible (do most calculations first). */ + /* The source offset is always 0 since we allow misaligned dword reads. */ + /* Need to wait for busy instead of pending, since hardware clears */ + /* the host data FIFO at the beginning of a BLT. */ + + GU2_WAIT_PENDING; + WRITE_GP32(MGP_RASTER_MODE, gu2_rop32); + WRITE_GP32(MGP_SRC_OFFSET, ((unsigned long)srcx & 7) << 26); + WRITE_GP32(MGP_DST_OFFSET, dstoffset); + WRITE_GP32(MGP_WID_HEIGHT, size); + WRITE_GP32(MGP_STRIDE, gu2_pitch); + WRITE_GP16(MGP_BLT_MODE, gu2_blt_mode | MGP_BM_SRC_HOST | MGP_BM_SRC_MONO); + + /* WAIT FOR BLT TO BE LATCHED */ + + GU2_WAIT_PENDING; + + /* WRITE ALL OF THE DATA TO THE HOST SOURCE REGISTER */ + + while (height--) { + temp_offset = offset; + + /* WRITE ALL FULL FIFO LINES */ + + for (i = 0; i < fifo_lines; i++) { + GU2_WAIT_HALF_EMPTY; + WRITE_GPREG_STRING32_SWP(MGP_HST_SOURCE, 8, j, data, temp_offset, + temp1); + temp_offset += 32; + } + + /* WRITE ALL FULL DWORDS */ + + GU2_WAIT_HALF_EMPTY; + if (dwords_extra) { + WRITE_GPREG_STRING32_SWP(MGP_HST_SOURCE, dwords_extra, i, data, + temp_offset, temp1); + temp_offset += (dwords_extra << 2); + } + + /* WRITE REMAINING BYTES */ + + shift = 0; + if (bytes_extra) + WRITE_GPREG_STRING8(MGP_HST_SOURCE, bytes_extra, shift, i, data, + temp_offset, temp1, temp2); + + offset += pitch; + } +} +unsigned int +GetVideoMemSize(void) +{ + unsigned int graphicsMemBaseAddr; + unsigned int totalMem = 0; + int i; + unsigned int graphicsMemMask, graphicsMemShift; + + /* Read graphics base address. */ + + graphicsMemBaseAddr = gfx_read_reg32(0x8414); + + if (1) { + unsigned int mcBankCfg = gfx_read_reg32(0x8408); + unsigned int dimmShift = 4; + + graphicsMemMask = 0x7FF; + graphicsMemShift = 19; + + /* Calculate total memory size for GXm. */ + + for (i = 0; i < 2; i++) { + if (((mcBankCfg >> dimmShift) & 0x7) != 0x7) { + switch ((mcBankCfg >> (dimmShift + 4)) & 0x7) { + case 0: + totalMem += 0x400000; + break; + case 1: + totalMem += 0x800000; + break; + case 2: + totalMem += 0x1000000; + break; + case 3: + totalMem += 0x2000000; + break; + case 4: + totalMem += 0x4000000; + break; + case 5: + totalMem += 0x8000000; + break; + case 6: + totalMem += 0x10000000; + break; + case 7: + totalMem += 0x20000000; + break; + default: + break; + } + } + dimmShift += 16; + } + } else { + unsigned int mcMemCntrl1 = gfx_read_reg32(0x8400); + unsigned int bankSizeShift = 12; + + graphicsMemMask = 0x3FF; + graphicsMemShift = 17; + + /* Calculate total memory size for GX. */ + + for (i = 0; i < 4; i++) { + switch ((mcMemCntrl1 >> bankSizeShift) & 0x7) { + case 1: + totalMem += 0x200000; + break; + case 2: + totalMem += 0x400000; + break; + case 3: + totalMem += 0x800000; + break; + case 4: + totalMem += 0x1000000; + break; + case 5: + totalMem += 0x2000000; + break; + default: + break; + } + bankSizeShift += 3; + } + } + + /* Calculate graphics memory base address */ + + graphicsMemBaseAddr &= graphicsMemMask; + graphicsMemBaseAddr <<= graphicsMemShift; + + return (totalMem - graphicsMemBaseAddr); +} + +/* END OF FILE */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/linux_v26/linux/videodev2.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/linux_v26/linux/videodev2.h 2005-07-13 13:16:49.000000000 -0600 @@ -0,0 +1,946 @@ +#ifndef __LINUX_VIDEODEV2_H +#define __LINUX_VIDEODEV2_H +/* + * Video for Linux Two + * + * Header file for v4l or V4L2 drivers and applications, for + * Linux kernels 2.2.x or 2.4.x. + * + * See http://bytesex.org/v4l/ for API specs and other + * v4l2 documentation. + * + * Author: Bill Dirks + * Justin Schoeman + * et al. + */ +#ifdef __KERNEL__ +#include /* need struct timeval */ +#endif + +/* + * M I S C E L L A N E O U S + */ + +/* Four-character-code (FOURCC) */ +#define v4l2_fourcc(a,b,c,d)\ + (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) + +/* + * E N U M S + */ +enum v4l2_field { + V4L2_FIELD_ANY = 0, /* driver can choose from none, + top, bottom, interlaced + depending on whatever it thinks + is approximate ... */ + V4L2_FIELD_NONE = 1, /* this device has no fields ... */ + V4L2_FIELD_TOP = 2, /* top field only */ + V4L2_FIELD_BOTTOM = 3, /* bottom field only */ + V4L2_FIELD_INTERLACED = 4, /* both fields interlaced */ + V4L2_FIELD_SEQ_TB = 5, /* both fields sequential into one + buffer, top-bottom order */ + V4L2_FIELD_SEQ_BT = 6, /* same as above + bottom-top order */ + V4L2_FIELD_ALTERNATE = 7, /* both fields alternating into + separate buffers */ +}; +#define V4L2_FIELD_HAS_TOP(field) \ + ((field) == V4L2_FIELD_TOP ||\ + (field) == V4L2_FIELD_INTERLACED ||\ + (field) == V4L2_FIELD_SEQ_TB ||\ + (field) == V4L2_FIELD_SEQ_BT) +#define V4L2_FIELD_HAS_BOTTOM(field) \ + ((field) == V4L2_FIELD_BOTTOM ||\ + (field) == V4L2_FIELD_INTERLACED ||\ + (field) == V4L2_FIELD_SEQ_TB ||\ + (field) == V4L2_FIELD_SEQ_BT) +#define V4L2_FIELD_HAS_BOTH(field) \ + ((field) == V4L2_FIELD_INTERLACED ||\ + (field) == V4L2_FIELD_SEQ_TB ||\ + (field) == V4L2_FIELD_SEQ_BT) + +enum v4l2_buf_type { + V4L2_BUF_TYPE_VIDEO_CAPTURE = 1, + V4L2_BUF_TYPE_VIDEO_OUTPUT = 2, + V4L2_BUF_TYPE_VIDEO_OVERLAY = 3, + V4L2_BUF_TYPE_VBI_CAPTURE = 4, + V4L2_BUF_TYPE_VBI_OUTPUT = 5, + V4L2_BUF_TYPE_PRIVATE = 0x80, +}; + +enum v4l2_ctrl_type { + V4L2_CTRL_TYPE_INTEGER = 1, + V4L2_CTRL_TYPE_BOOLEAN = 2, + V4L2_CTRL_TYPE_MENU = 3, + V4L2_CTRL_TYPE_BUTTON = 4, +}; + +enum v4l2_tuner_type { + V4L2_TUNER_RADIO = 1, + V4L2_TUNER_ANALOG_TV = 2, +}; + +enum v4l2_memory { + V4L2_MEMORY_MMAP = 1, + V4L2_MEMORY_USERPTR = 2, + V4L2_MEMORY_OVERLAY = 3, +}; + +/* see also http://vektor.theorem.ca/graphics/ycbcr/ */ +enum v4l2_colorspace { + /* ITU-R 601 -- broadcast NTSC/PAL */ + V4L2_COLORSPACE_SMPTE170M = 1, + + /* 1125-Line (US) HDTV */ + V4L2_COLORSPACE_SMPTE240M = 2, + + /* HD and modern captures. */ + V4L2_COLORSPACE_REC709 = 3, + + /* broken BT878 extents (601, luma range 16-253 instead of 16-235) */ + V4L2_COLORSPACE_BT878 = 4, + + /* These should be useful. Assume 601 extents. */ + V4L2_COLORSPACE_470_SYSTEM_M = 5, + V4L2_COLORSPACE_470_SYSTEM_BG = 6, + + /* I know there will be cameras that send this. So, this is + * unspecified chromaticities and full 0-255 on each of the + * Y'CbCr components + */ + V4L2_COLORSPACE_JPEG = 7, + + /* For RGB colourspaces, this is probably a good start. */ + V4L2_COLORSPACE_SRGB = 8, +}; + +enum v4l2_priority { + V4L2_PRIORITY_UNSET = 0, /* not initialized */ + V4L2_PRIORITY_BACKGROUND = 1, + V4L2_PRIORITY_INTERACTIVE = 2, + V4L2_PRIORITY_RECORD = 3, + V4L2_PRIORITY_DEFAULT = V4L2_PRIORITY_INTERACTIVE, +}; + +struct v4l2_rect { + __s32 left; + __s32 top; + __s32 width; + __s32 height; +}; + +struct v4l2_fract { + __u32 numerator; + __u32 denominator; +}; + +/* + * D R I V E R C A P A B I L I T I E S + */ +struct v4l2_capability +{ + __u8 driver[16]; /* i.e. "bttv" */ + __u8 card[32]; /* i.e. "Hauppauge WinTV" */ + __u8 bus_info[32]; /* "PCI:" + pci_name(pci_dev) */ + __u32 version; /* should use KERNEL_VERSION() */ + __u32 capabilities; /* Device capabilities */ + __u32 reserved[4]; +}; + +/* Values for 'capabilities' field */ +#define V4L2_CAP_VIDEO_CAPTURE 0x00000001 /* Is a video capture device */ +#define V4L2_CAP_VIDEO_OUTPUT 0x00000002 /* Is a video output device */ +#define V4L2_CAP_VIDEO_OVERLAY 0x00000004 /* Can do video overlay */ +#define V4L2_CAP_VBI_CAPTURE 0x00000010 /* Is a VBI capture device */ +#define V4L2_CAP_VBI_OUTPUT 0x00000020 /* Is a VBI output device */ +#define V4L2_CAP_RDS_CAPTURE 0x00000100 /* RDS data capture */ + +#define V4L2_CAP_TUNER 0x00010000 /* has a tuner */ +#define V4L2_CAP_AUDIO 0x00020000 /* has audio support */ +#define V4L2_CAP_RADIO 0x00040000 /* is a radio device */ + +#define V4L2_CAP_READWRITE 0x01000000 /* read/write systemcalls */ +#define V4L2_CAP_ASYNCIO 0x02000000 /* async I/O */ +#define V4L2_CAP_STREAMING 0x04000000 /* streaming I/O ioctls */ + +/* + * V I D E O I M A G E F O R M A T + */ + +struct v4l2_pix_format +{ + __u32 width; + __u32 height; + __u32 pixelformat; + enum v4l2_field field; + __u32 bytesperline; /* for padding, zero if unused */ + __u32 sizeimage; + enum v4l2_colorspace colorspace; + __u32 priv; /* private data, depends on pixelformat */ +}; + +/* Pixel format FOURCC depth Description */ +#define V4L2_PIX_FMT_RGB332 v4l2_fourcc('R','G','B','1') /* 8 RGB-3-3-2 */ +#define V4L2_PIX_FMT_RGB555 v4l2_fourcc('R','G','B','O') /* 16 RGB-5-5-5 */ +#define V4L2_PIX_FMT_RGB565 v4l2_fourcc('R','G','B','P') /* 16 RGB-5-6-5 */ +#define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R','G','B','Q') /* 16 RGB-5-5-5 BE */ +#define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R','G','B','R') /* 16 RGB-5-6-5 BE */ +#define V4L2_PIX_FMT_BGR24 v4l2_fourcc('B','G','R','3') /* 24 BGR-8-8-8 */ +#define V4L2_PIX_FMT_RGB24 v4l2_fourcc('R','G','B','3') /* 24 RGB-8-8-8 */ +#define V4L2_PIX_FMT_BGR32 v4l2_fourcc('B','G','R','4') /* 32 BGR-8-8-8-8 */ +#define V4L2_PIX_FMT_RGB32 v4l2_fourcc('R','G','B','4') /* 32 RGB-8-8-8-8 */ +#define V4L2_PIX_FMT_GREY v4l2_fourcc('G','R','E','Y') /* 8 Greyscale */ +#define V4L2_PIX_FMT_YVU410 v4l2_fourcc('Y','V','U','9') /* 9 YVU 4:1:0 */ +#define V4L2_PIX_FMT_YVU420 v4l2_fourcc('Y','V','1','2') /* 12 YVU 4:2:0 */ +#define V4L2_PIX_FMT_YUYV v4l2_fourcc('Y','U','Y','V') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_UYVY v4l2_fourcc('U','Y','V','Y') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_YUV422P v4l2_fourcc('4','2','2','P') /* 16 YVU422 planar */ +#define V4L2_PIX_FMT_YUV411P v4l2_fourcc('4','1','1','P') /* 16 YVU411 planar */ +#define V4L2_PIX_FMT_Y41P v4l2_fourcc('Y','4','1','P') /* 12 YUV 4:1:1 */ + +/* two planes -- one Y, one Cr + Cb interleaved */ +#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N','V','1','2') /* 12 Y/CbCr 4:2:0 */ +#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N','V','2','1') /* 12 Y/CrCb 4:2:0 */ + +/* The following formats are not defined in the V4L2 specification */ +#define V4L2_PIX_FMT_YUV410 v4l2_fourcc('Y','U','V','9') /* 9 YUV 4:1:0 */ +#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y','U','1','2') /* 12 YUV 4:2:0 */ +#define V4L2_PIX_FMT_YYUV v4l2_fourcc('Y','Y','U','V') /* 16 YUV 4:2:2 */ +#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H','I','2','4') /* 8 8-bit color */ + +/* see http://www.siliconimaging.com/RGB%20Bayer.htm */ +#define V4L2_PIX_FMT_SBGGR8 v4l2_fourcc('B','A','8','1') /* 8 BGBG.. GRGR.. */ + +/* compressed formats */ +#define V4L2_PIX_FMT_MJPEG v4l2_fourcc('M','J','P','G') /* Motion-JPEG */ +#define V4L2_PIX_FMT_JPEG v4l2_fourcc('J','P','E','G') /* JFIF JPEG */ +#define V4L2_PIX_FMT_DV v4l2_fourcc('d','v','s','d') /* 1394 */ +#define V4L2_PIX_FMT_MPEG v4l2_fourcc('M','P','E','G') /* MPEG */ + +/* Vendor-specific formats */ +#define V4L2_PIX_FMT_WNVA v4l2_fourcc('W','N','V','A') /* Winnov hw compress */ + +/* + * F O R M A T E N U M E R A T I O N + */ +struct v4l2_fmtdesc +{ + __u32 index; /* Format number */ + enum v4l2_buf_type type; /* buffer type */ + __u32 flags; + __u8 description[32]; /* Description string */ + __u32 pixelformat; /* Format fourcc */ + __u32 reserved[4]; +}; + +#define V4L2_FMT_FLAG_COMPRESSED 0x0001 + + +/* + * T I M E C O D E + */ +struct v4l2_timecode +{ + __u32 type; + __u32 flags; + __u8 frames; + __u8 seconds; + __u8 minutes; + __u8 hours; + __u8 userbits[4]; +}; + +/* Type */ +#define V4L2_TC_TYPE_24FPS 1 +#define V4L2_TC_TYPE_25FPS 2 +#define V4L2_TC_TYPE_30FPS 3 +#define V4L2_TC_TYPE_50FPS 4 +#define V4L2_TC_TYPE_60FPS 5 + +/* Flags */ +#define V4L2_TC_FLAG_DROPFRAME 0x0001 /* "drop-frame" mode */ +#define V4L2_TC_FLAG_COLORFRAME 0x0002 +#define V4L2_TC_USERBITS_field 0x000C +#define V4L2_TC_USERBITS_USERDEFINED 0x0000 +#define V4L2_TC_USERBITS_8BITCHARS 0x0008 +/* The above is based on SMPTE timecodes */ + + +/* + * C O M P R E S S I O N P A R A M E T E R S + */ +#if 0 +/* ### generic compression settings don't work, there is too much + * ### codec-specific stuff. Maybe reuse that for MPEG codec settings + * ### later ... */ +struct v4l2_compression +{ + __u32 quality; + __u32 keyframerate; + __u32 pframerate; + __u32 reserved[5]; + +/* what we'll need for MPEG, extracted from some postings on + the v4l list (Gert Vervoort, PlasmaJohn). + +system stream: + - type: elementary stream(ES), packatised elementary stream(s) (PES) + program stream(PS), transport stream(TS) + - system bitrate + - PS packet size (DVD: 2048 bytes, VCD: 2324 bytes) + - TS video PID + - TS audio PID + - TS PCR PID + - TS system information tables (PAT, PMT, CAT, NIT and SIT) + - (MPEG-1 systems stream vs. MPEG-2 program stream (TS not supported + by MPEG-1 systems) + +audio: + - type: MPEG (+Layer I,II,III), AC-3, LPCM + - bitrate + - sampling frequency (DVD: 48 Khz, VCD: 44.1 KHz, 32 kHz) + - Trick Modes? (ff, rew) + - Copyright + - Inverse Telecine + +video: + - picturesize (SIF, 1/2 D1, 2/3 D1, D1) and PAL/NTSC norm can be set + through excisting V4L2 controls + - noise reduction, parameters encoder specific? + - MPEG video version: MPEG-1, MPEG-2 + - GOP (Group Of Pictures) definition: + - N: number of frames per GOP + - M: distance between reference (I,P) frames + - open/closed GOP + - quantiser matrix: inter Q matrix (64 bytes) and intra Q matrix (64 bytes) + - quantiser scale: linear or logarithmic + - scanning: alternate or zigzag + - bitrate mode: CBR (constant bitrate) or VBR (variable bitrate). + - target video bitrate for CBR + - target video bitrate for VBR + - maximum video bitrate for VBR - min. quantiser value for VBR + - max. quantiser value for VBR + - adaptive quantisation value + - return the number of bytes per GOP or bitrate for bitrate monitoring + +*/ +}; +#endif + +struct v4l2_jpegcompression +{ + int quality; + + int APPn; /* Number of APP segment to be written, + * must be 0..15 */ + int APP_len; /* Length of data in JPEG APPn segment */ + char APP_data[60]; /* Data in the JPEG APPn segment. */ + + int COM_len; /* Length of data in JPEG COM segment */ + char COM_data[60]; /* Data in JPEG COM segment */ + + __u32 jpeg_markers; /* Which markers should go into the JPEG + * output. Unless you exactly know what + * you do, leave them untouched. + * Inluding less markers will make the + * resulting code smaller, but there will + * be fewer aplications which can read it. + * The presence of the APP and COM marker + * is influenced by APP_len and COM_len + * ONLY, not by this property! */ + +#define V4L2_JPEG_MARKER_DHT (1<<3) /* Define Huffman Tables */ +#define V4L2_JPEG_MARKER_DQT (1<<4) /* Define Quantization Tables */ +#define V4L2_JPEG_MARKER_DRI (1<<5) /* Define Restart Interval */ +#define V4L2_JPEG_MARKER_COM (1<<6) /* Comment segment */ +#define V4L2_JPEG_MARKER_APP (1<<7) /* App segment, driver will + * allways use APP0 */ +}; + + +/* + * M E M O R Y - M A P P I N G B U F F E R S + */ +struct v4l2_requestbuffers +{ + __u32 count; + enum v4l2_buf_type type; + enum v4l2_memory memory; + __u32 reserved[2]; +}; + +struct v4l2_buffer +{ + __u32 index; + enum v4l2_buf_type type; + __u32 bytesused; + __u32 flags; + enum v4l2_field field; + struct timeval timestamp; + struct v4l2_timecode timecode; + __u32 sequence; + + /* memory location */ + enum v4l2_memory memory; + union { + __u32 offset; + unsigned long userptr; + } m; + __u32 length; + __u32 input; + __u32 reserved; +}; + +/* Flags for 'flags' field */ +#define V4L2_BUF_FLAG_MAPPED 0x0001 /* Buffer is mapped (flag) */ +#define V4L2_BUF_FLAG_QUEUED 0x0002 /* Buffer is queued for processing */ +#define V4L2_BUF_FLAG_DONE 0x0004 /* Buffer is ready */ +#define V4L2_BUF_FLAG_KEYFRAME 0x0008 /* Image is a keyframe (I-frame) */ +#define V4L2_BUF_FLAG_PFRAME 0x0010 /* Image is a P-frame */ +#define V4L2_BUF_FLAG_BFRAME 0x0020 /* Image is a B-frame */ +#define V4L2_BUF_FLAG_TIMECODE 0x0100 /* timecode field is valid */ +#define V4L2_BUF_FLAG_INPUT 0x0200 /* input field is valid */ + +/* + * O V E R L A Y P R E V I E W + */ +struct v4l2_framebuffer +{ + __u32 capability; + __u32 flags; +/* FIXME: in theory we should pass something like PCI device + memory + * region + offset instead of some physical address */ + void* base; + struct v4l2_pix_format fmt; +}; +/* Flags for the 'capability' field. Read only */ +#define V4L2_FBUF_CAP_EXTERNOVERLAY 0x0001 +#define V4L2_FBUF_CAP_CHROMAKEY 0x0002 +#define V4L2_FBUF_CAP_LIST_CLIPPING 0x0004 +#define V4L2_FBUF_CAP_BITMAP_CLIPPING 0x0008 +/* Flags for the 'flags' field. */ +#define V4L2_FBUF_FLAG_PRIMARY 0x0001 +#define V4L2_FBUF_FLAG_OVERLAY 0x0002 +#define V4L2_FBUF_FLAG_CHROMAKEY 0x0004 + +struct v4l2_clip +{ + struct v4l2_rect c; + struct v4l2_clip *next; +}; + +struct v4l2_window +{ + struct v4l2_rect w; + enum v4l2_field field; + __u32 chromakey; + struct v4l2_clip *clips; + __u32 clipcount; + void *bitmap; +}; + + +/* + * C A P T U R E P A R A M E T E R S + */ +struct v4l2_captureparm +{ + __u32 capability; /* Supported modes */ + __u32 capturemode; /* Current mode */ + struct v4l2_fract timeperframe; /* Time per frame in .1us units */ + __u32 extendedmode; /* Driver-specific extensions */ + __u32 readbuffers; /* # of buffers for read */ + __u32 reserved[4]; +}; +/* Flags for 'capability' and 'capturemode' fields */ +#define V4L2_MODE_HIGHQUALITY 0x0001 /* High quality imaging mode */ +#define V4L2_CAP_TIMEPERFRAME 0x1000 /* timeperframe field is supported */ + +struct v4l2_outputparm +{ + __u32 capability; /* Supported modes */ + __u32 outputmode; /* Current mode */ + struct v4l2_fract timeperframe; /* Time per frame in seconds */ + __u32 extendedmode; /* Driver-specific extensions */ + __u32 writebuffers; /* # of buffers for write */ + __u32 reserved[4]; +}; + +/* + * I N P U T I M A G E C R O P P I N G + */ + +struct v4l2_cropcap { + enum v4l2_buf_type type; + struct v4l2_rect bounds; + struct v4l2_rect defrect; + struct v4l2_fract pixelaspect; +}; + +struct v4l2_crop { + enum v4l2_buf_type type; + struct v4l2_rect c; +}; + +/* + * A N A L O G V I D E O S T A N D A R D + */ + +typedef __u64 v4l2_std_id; + +/* one bit for each */ +#define V4L2_STD_PAL_B ((v4l2_std_id)0x00000001) +#define V4L2_STD_PAL_B1 ((v4l2_std_id)0x00000002) +#define V4L2_STD_PAL_G ((v4l2_std_id)0x00000004) +#define V4L2_STD_PAL_H ((v4l2_std_id)0x00000008) +#define V4L2_STD_PAL_I ((v4l2_std_id)0x00000010) +#define V4L2_STD_PAL_D ((v4l2_std_id)0x00000020) +#define V4L2_STD_PAL_D1 ((v4l2_std_id)0x00000040) +#define V4L2_STD_PAL_K ((v4l2_std_id)0x00000080) + +#define V4L2_STD_PAL_M ((v4l2_std_id)0x00000100) +#define V4L2_STD_PAL_N ((v4l2_std_id)0x00000200) +#define V4L2_STD_PAL_Nc ((v4l2_std_id)0x00000400) +#define V4L2_STD_PAL_60 ((v4l2_std_id)0x00000800) + +#define V4L2_STD_NTSC_M ((v4l2_std_id)0x00001000) +#define V4L2_STD_NTSC_M_JP ((v4l2_std_id)0x00002000) + +#define V4L2_STD_SECAM_B ((v4l2_std_id)0x00010000) +#define V4L2_STD_SECAM_D ((v4l2_std_id)0x00020000) +#define V4L2_STD_SECAM_G ((v4l2_std_id)0x00040000) +#define V4L2_STD_SECAM_H ((v4l2_std_id)0x00080000) +#define V4L2_STD_SECAM_K ((v4l2_std_id)0x00100000) +#define V4L2_STD_SECAM_K1 ((v4l2_std_id)0x00200000) +#define V4L2_STD_SECAM_L ((v4l2_std_id)0x00400000) + +/* ATSC/HDTV */ +#define V4L2_STD_ATSC_8_VSB ((v4l2_std_id)0x01000000) +#define V4L2_STD_ATSC_16_VSB ((v4l2_std_id)0x02000000) + +/* some common needed stuff */ +#define V4L2_STD_PAL_BG (V4L2_STD_PAL_B |\ + V4L2_STD_PAL_B1 |\ + V4L2_STD_PAL_G) +#define V4L2_STD_PAL_DK (V4L2_STD_PAL_D |\ + V4L2_STD_PAL_D1 |\ + V4L2_STD_PAL_K) +#define V4L2_STD_PAL (V4L2_STD_PAL_BG |\ + V4L2_STD_PAL_DK |\ + V4L2_STD_PAL_H |\ + V4L2_STD_PAL_I) +#define V4L2_STD_NTSC (V4L2_STD_NTSC_M |\ + V4L2_STD_NTSC_M_JP) +#define V4L2_STD_SECAM_DK (V4L2_STD_SECAM_D |\ + V4L2_STD_SECAM_K |\ + V4L2_STD_SECAM_K1) +#define V4L2_STD_SECAM (V4L2_STD_SECAM_B |\ + V4L2_STD_SECAM_G |\ + V4L2_STD_SECAM_H |\ + V4L2_STD_SECAM_DK |\ + V4L2_STD_SECAM_L) + +#define V4L2_STD_525_60 (V4L2_STD_PAL_M |\ + V4L2_STD_PAL_60 |\ + V4L2_STD_NTSC) +#define V4L2_STD_625_50 (V4L2_STD_PAL |\ + V4L2_STD_PAL_N |\ + V4L2_STD_PAL_Nc |\ + V4L2_STD_SECAM) +#define V4L2_STD_ATSC (V4L2_STD_ATSC_8_VSB |\ + V4L2_STD_ATSC_16_VSB) + +#define V4L2_STD_UNKNOWN 0 +#define V4L2_STD_ALL (V4L2_STD_525_60 |\ + V4L2_STD_625_50) + +struct v4l2_standard +{ + __u32 index; + v4l2_std_id id; + __u8 name[24]; + struct v4l2_fract frameperiod; /* Frames, not fields */ + __u32 framelines; + __u32 reserved[4]; +}; + + +/* + * V I D E O I N P U T S + */ +struct v4l2_input +{ + __u32 index; /* Which input */ + __u8 name[32]; /* Label */ + __u32 type; /* Type of input */ + __u32 audioset; /* Associated audios (bitfield) */ + __u32 tuner; /* Associated tuner */ + v4l2_std_id std; + __u32 status; + __u32 reserved[4]; +}; +/* Values for the 'type' field */ +#define V4L2_INPUT_TYPE_TUNER 1 +#define V4L2_INPUT_TYPE_CAMERA 2 + +/* field 'status' - general */ +#define V4L2_IN_ST_NO_POWER 0x00000001 /* Attached device is off */ +#define V4L2_IN_ST_NO_SIGNAL 0x00000002 +#define V4L2_IN_ST_NO_COLOR 0x00000004 + +/* field 'status' - analog */ +#define V4L2_IN_ST_NO_H_LOCK 0x00000100 /* No horizontal sync lock */ +#define V4L2_IN_ST_COLOR_KILL 0x00000200 /* Color killer is active */ + +/* field 'status' - digital */ +#define V4L2_IN_ST_NO_SYNC 0x00010000 /* No synchronization lock */ +#define V4L2_IN_ST_NO_EQU 0x00020000 /* No equalizer lock */ +#define V4L2_IN_ST_NO_CARRIER 0x00040000 /* Carrier recovery failed */ + +/* field 'status' - VCR and set-top box */ +#define V4L2_IN_ST_MACROVISION 0x01000000 /* Macrovision detected */ +#define V4L2_IN_ST_NO_ACCESS 0x02000000 /* Conditional access denied */ +#define V4L2_IN_ST_VTR 0x04000000 /* VTR time constant */ + +/* + * V I D E O O U T P U T S + */ +struct v4l2_output +{ + __u32 index; /* Which output */ + __u8 name[32]; /* Label */ + __u32 type; /* Type of output */ + __u32 audioset; /* Associated audios (bitfield) */ + __u32 modulator; /* Associated modulator */ + v4l2_std_id std; + __u32 reserved[4]; +}; +/* Values for the 'type' field */ +#define V4L2_OUTPUT_TYPE_MODULATOR 1 +#define V4L2_OUTPUT_TYPE_ANALOG 2 +#define V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY 3 + +/* + * C O N T R O L S + */ +struct v4l2_control +{ + __u32 id; + __s32 value; +}; + +/* Used in the VIDIOC_QUERYCTRL ioctl for querying controls */ +struct v4l2_queryctrl +{ + __u32 id; + enum v4l2_ctrl_type type; + __u8 name[32]; /* Whatever */ + __s32 minimum; /* Note signedness */ + __s32 maximum; + __s32 step; + __s32 default_value; + __u32 flags; + __u32 reserved[2]; +}; + +/* Used in the VIDIOC_QUERYMENU ioctl for querying menu items */ +struct v4l2_querymenu +{ + __u32 id; + __u32 index; + __u8 name[32]; /* Whatever */ + __u32 reserved; +}; + +/* Control flags */ +#define V4L2_CTRL_FLAG_DISABLED 0x0001 +#define V4L2_CTRL_FLAG_GRABBED 0x0002 + +/* Control IDs defined by V4L2 */ +#define V4L2_CID_BASE 0x00980900 +/* IDs reserved for driver specific controls */ +#define V4L2_CID_PRIVATE_BASE 0x08000000 + +#define V4L2_CID_BRIGHTNESS (V4L2_CID_BASE+0) +#define V4L2_CID_CONTRAST (V4L2_CID_BASE+1) +#define V4L2_CID_SATURATION (V4L2_CID_BASE+2) +#define V4L2_CID_HUE (V4L2_CID_BASE+3) +#define V4L2_CID_AUDIO_VOLUME (V4L2_CID_BASE+5) +#define V4L2_CID_AUDIO_BALANCE (V4L2_CID_BASE+6) +#define V4L2_CID_AUDIO_BASS (V4L2_CID_BASE+7) +#define V4L2_CID_AUDIO_TREBLE (V4L2_CID_BASE+8) +#define V4L2_CID_AUDIO_MUTE (V4L2_CID_BASE+9) +#define V4L2_CID_AUDIO_LOUDNESS (V4L2_CID_BASE+10) +#define V4L2_CID_BLACK_LEVEL (V4L2_CID_BASE+11) +#define V4L2_CID_AUTO_WHITE_BALANCE (V4L2_CID_BASE+12) +#define V4L2_CID_DO_WHITE_BALANCE (V4L2_CID_BASE+13) +#define V4L2_CID_RED_BALANCE (V4L2_CID_BASE+14) +#define V4L2_CID_BLUE_BALANCE (V4L2_CID_BASE+15) +#define V4L2_CID_GAMMA (V4L2_CID_BASE+16) +#define V4L2_CID_WHITENESS (V4L2_CID_GAMMA) /* ? Not sure */ +#define V4L2_CID_EXPOSURE (V4L2_CID_BASE+17) +#define V4L2_CID_AUTOGAIN (V4L2_CID_BASE+18) +#define V4L2_CID_GAIN (V4L2_CID_BASE+19) +#define V4L2_CID_HFLIP (V4L2_CID_BASE+20) +#define V4L2_CID_VFLIP (V4L2_CID_BASE+21) +#define V4L2_CID_HCENTER (V4L2_CID_BASE+22) +#define V4L2_CID_VCENTER (V4L2_CID_BASE+23) +#define V4L2_CID_LASTP1 (V4L2_CID_BASE+24) /* last CID + 1 */ + +/* + * T U N I N G + */ +struct v4l2_tuner +{ + __u32 index; + __u8 name[32]; + enum v4l2_tuner_type type; + __u32 capability; + __u32 rangelow; + __u32 rangehigh; + __u32 rxsubchans; + __u32 audmode; + __s32 signal; + __s32 afc; + __u32 reserved[4]; +}; + +struct v4l2_modulator +{ + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 rangelow; + __u32 rangehigh; + __u32 txsubchans; + __u32 reserved[4]; +}; + +/* Flags for the 'capability' field */ +#define V4L2_TUNER_CAP_LOW 0x0001 +#define V4L2_TUNER_CAP_NORM 0x0002 +#define V4L2_TUNER_CAP_STEREO 0x0010 +#define V4L2_TUNER_CAP_LANG2 0x0020 +#define V4L2_TUNER_CAP_SAP 0x0020 +#define V4L2_TUNER_CAP_LANG1 0x0040 + +/* Flags for the 'rxsubchans' field */ +#define V4L2_TUNER_SUB_MONO 0x0001 +#define V4L2_TUNER_SUB_STEREO 0x0002 +#define V4L2_TUNER_SUB_LANG2 0x0004 +#define V4L2_TUNER_SUB_SAP 0x0004 +#define V4L2_TUNER_SUB_LANG1 0x0008 + +/* Values for the 'audmode' field */ +#define V4L2_TUNER_MODE_MONO 0x0000 +#define V4L2_TUNER_MODE_STEREO 0x0001 +#define V4L2_TUNER_MODE_LANG2 0x0002 +#define V4L2_TUNER_MODE_SAP 0x0002 +#define V4L2_TUNER_MODE_LANG1 0x0003 + +struct v4l2_frequency +{ + __u32 tuner; + enum v4l2_tuner_type type; + __u32 frequency; + __u32 reserved[8]; +}; + +/* + * A U D I O + */ +struct v4l2_audio +{ + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 mode; + __u32 reserved[2]; +}; +/* Flags for the 'capability' field */ +#define V4L2_AUDCAP_STEREO 0x00001 +#define V4L2_AUDCAP_AVL 0x00002 + +/* Flags for the 'mode' field */ +#define V4L2_AUDMODE_AVL 0x00001 + +struct v4l2_audioout +{ + __u32 index; + __u8 name[32]; + __u32 capability; + __u32 mode; + __u32 reserved[2]; +}; + +/* + * D A T A S E R V I C E S ( V B I ) + * + * Data services API by Michael Schimek + */ + +struct v4l2_vbi_format +{ + __u32 sampling_rate; /* in 1 Hz */ + __u32 offset; + __u32 samples_per_line; + __u32 sample_format; /* V4L2_PIX_FMT_* */ + __s32 start[2]; + __u32 count[2]; + __u32 flags; /* V4L2_VBI_* */ + __u32 reserved[2]; /* must be zero */ +}; + +/* VBI flags */ +#define V4L2_VBI_UNSYNC (1<< 0) +#define V4L2_VBI_INTERLACED (1<< 1) + + +/* + * A G G R E G A T E S T R U C T U R E S + */ + +/* Stream data format + */ +struct v4l2_format +{ + enum v4l2_buf_type type; + union + { + struct v4l2_pix_format pix; /* V4L2_BUF_TYPE_VIDEO_CAPTURE */ + struct v4l2_window win; /* V4L2_BUF_TYPE_VIDEO_OVERLAY */ + struct v4l2_vbi_format vbi; /* V4L2_BUF_TYPE_VBI_CAPTURE */ + __u8 raw_data[200]; /* user-defined */ + } fmt; +}; + + +/* Stream type-dependent parameters + */ +struct v4l2_streamparm +{ + enum v4l2_buf_type type; + union + { + struct v4l2_captureparm capture; + struct v4l2_outputparm output; + __u8 raw_data[200]; /* user-defined */ + } parm; +}; + + + +/* + * I O C T L C O D E S F O R V I D E O D E V I C E S + * + */ +#define VIDIOC_QUERYCAP _IOR ('V', 0, struct v4l2_capability) +#define VIDIOC_RESERVED _IO ('V', 1) +#define VIDIOC_ENUM_FMT _IOWR ('V', 2, struct v4l2_fmtdesc) +#define VIDIOC_G_FMT _IOWR ('V', 4, struct v4l2_format) +#define VIDIOC_S_FMT _IOWR ('V', 5, struct v4l2_format) +#if 0 +#define VIDIOC_G_COMP _IOR ('V', 6, struct v4l2_compression) +#define VIDIOC_S_COMP _IOW ('V', 7, struct v4l2_compression) +#endif +#define VIDIOC_REQBUFS _IOWR ('V', 8, struct v4l2_requestbuffers) +#define VIDIOC_QUERYBUF _IOWR ('V', 9, struct v4l2_buffer) +#define VIDIOC_G_FBUF _IOR ('V', 10, struct v4l2_framebuffer) +#define VIDIOC_S_FBUF _IOW ('V', 11, struct v4l2_framebuffer) +#define VIDIOC_OVERLAY _IOW ('V', 14, int) +#define VIDIOC_QBUF _IOWR ('V', 15, struct v4l2_buffer) +#define VIDIOC_DQBUF _IOWR ('V', 17, struct v4l2_buffer) +#define VIDIOC_STREAMON _IOW ('V', 18, int) +#define VIDIOC_STREAMOFF _IOW ('V', 19, int) +#define VIDIOC_G_PARM _IOWR ('V', 21, struct v4l2_streamparm) +#define VIDIOC_S_PARM _IOWR ('V', 22, struct v4l2_streamparm) +#define VIDIOC_G_STD _IOR ('V', 23, v4l2_std_id) +#define VIDIOC_S_STD _IOW ('V', 24, v4l2_std_id) +#define VIDIOC_ENUMSTD _IOWR ('V', 25, struct v4l2_standard) +#define VIDIOC_ENUMINPUT _IOWR ('V', 26, struct v4l2_input) +#define VIDIOC_G_CTRL _IOWR ('V', 27, struct v4l2_control) +#define VIDIOC_S_CTRL _IOWR ('V', 28, struct v4l2_control) +#define VIDIOC_G_TUNER _IOWR ('V', 29, struct v4l2_tuner) +#define VIDIOC_S_TUNER _IOW ('V', 30, struct v4l2_tuner) +#define VIDIOC_G_AUDIO _IOR ('V', 33, struct v4l2_audio) +#define VIDIOC_S_AUDIO _IOW ('V', 34, struct v4l2_audio) +#define VIDIOC_QUERYCTRL _IOWR ('V', 36, struct v4l2_queryctrl) +#define VIDIOC_QUERYMENU _IOWR ('V', 37, struct v4l2_querymenu) +#define VIDIOC_G_INPUT _IOR ('V', 38, int) +#define VIDIOC_S_INPUT _IOWR ('V', 39, int) +#define VIDIOC_G_OUTPUT _IOR ('V', 46, int) +#define VIDIOC_S_OUTPUT _IOWR ('V', 47, int) +#define VIDIOC_ENUMOUTPUT _IOWR ('V', 48, struct v4l2_output) +#define VIDIOC_G_AUDOUT _IOR ('V', 49, struct v4l2_audioout) +#define VIDIOC_S_AUDOUT _IOW ('V', 50, struct v4l2_audioout) +#define VIDIOC_G_MODULATOR _IOWR ('V', 54, struct v4l2_modulator) +#define VIDIOC_S_MODULATOR _IOW ('V', 55, struct v4l2_modulator) +#define VIDIOC_G_FREQUENCY _IOWR ('V', 56, struct v4l2_frequency) +#define VIDIOC_S_FREQUENCY _IOW ('V', 57, struct v4l2_frequency) +#define VIDIOC_CROPCAP _IOWR ('V', 58, struct v4l2_cropcap) +#define VIDIOC_G_CROP _IOWR ('V', 59, struct v4l2_crop) +#define VIDIOC_S_CROP _IOW ('V', 60, struct v4l2_crop) +#define VIDIOC_G_JPEGCOMP _IOR ('V', 61, struct v4l2_jpegcompression) +#define VIDIOC_S_JPEGCOMP _IOW ('V', 62, struct v4l2_jpegcompression) +#define VIDIOC_QUERYSTD _IOR ('V', 63, v4l2_std_id) +#define VIDIOC_TRY_FMT _IOWR ('V', 64, struct v4l2_format) +#define VIDIOC_ENUMAUDIO _IOWR ('V', 65, struct v4l2_audio) +#define VIDIOC_ENUMAUDOUT _IOWR ('V', 66, struct v4l2_audioout) +#define VIDIOC_G_PRIORITY _IOR ('V', 67, enum v4l2_priority) +#define VIDIOC_S_PRIORITY _IOW ('V', 68, enum v4l2_priority) + +/* for compatibility, will go away some day */ +#define VIDIOC_OVERLAY_OLD _IOWR ('V', 14, int) +#define VIDIOC_S_PARM_OLD _IOW ('V', 22, struct v4l2_streamparm) +#define VIDIOC_S_CTRL_OLD _IOW ('V', 28, struct v4l2_control) +#define VIDIOC_G_AUDIO_OLD _IOWR ('V', 33, struct v4l2_audio) +#define VIDIOC_G_AUDOUT_OLD _IOWR ('V', 49, struct v4l2_audioout) +#define VIDIOC_CROPCAP_OLD _IOR ('V', 58, struct v4l2_cropcap) + +#define BASE_VIDIOC_PRIVATE 192 /* 192-255 are private */ + + +#ifdef __KERNEL__ +/* + * + * V 4 L 2 D R I V E R H E L P E R A P I + * + * Some commonly needed functions for drivers (v4l2-common.o module) + */ +#include + +/* Video standard functions */ +extern unsigned int v4l2_video_std_fps(struct v4l2_standard *vs); +extern int v4l2_video_std_construct(struct v4l2_standard *vs, + int id, char *name); + +/* prority handling */ +struct v4l2_prio_state { + atomic_t prios[4]; +}; +int v4l2_prio_init(struct v4l2_prio_state *global); +int v4l2_prio_change(struct v4l2_prio_state *global, enum v4l2_priority *local, + enum v4l2_priority new); +int v4l2_prio_open(struct v4l2_prio_state *global, enum v4l2_priority *local); +int v4l2_prio_close(struct v4l2_prio_state *global, enum v4l2_priority *local); +enum v4l2_priority v4l2_prio_max(struct v4l2_prio_state *global); +int v4l2_prio_check(struct v4l2_prio_state *global, enum v4l2_priority *local); + +/* names for fancy debug output */ +extern char *v4l2_field_names[]; +extern char *v4l2_type_names[]; +extern char *v4l2_ioctl_names[]; + +/* Compatibility layer interface -- v4l1-compat module */ +typedef int (*v4l2_kioctl)(struct inode *inode, struct file *file, + unsigned int cmd, void *arg); +int v4l_compat_translate_ioctl(struct inode *inode, struct file *file, + int cmd, void *arg, v4l2_kioctl driver_ioctl); + +#endif /* __KERNEL__ */ +#endif /* __LINUX_VIDEODEV2_H */ + +/* + * Local variables: + * c-basic-offset: 8 + * End: + */ --- xc/programs/Xserver/hw/xfree86/drivers/amd/linux_v26/linux/videodev.h 1969-12-31 17:00:00.000000000 -0700 +++ xc.new/programs/Xserver/hw/xfree86/drivers/amd/linux_v26/linux/videodev.h 2005-07-13 13:16:49.000000000 -0600 @@ -0,0 +1,440 @@ +#ifndef __LINUX_VIDEODEV_H +#define __LINUX_VIDEODEV_H + +#include +#include + +#define HAVE_V4L2 1 +#include + +#ifdef __KERNEL__ + +#include +#include +#include + +struct video_device +{ + /* device info */ + struct device *dev; + char name[32]; + int type; /* v4l1 */ + int type2; /* v4l2 */ + int hardware; + int minor; + + /* device ops + callbacks */ + struct file_operations *fops; + void (*release)(struct video_device *vfd); + + +#if 1 /* to be removed in 2.7.x */ + /* obsolete -- fops->owner is used instead */ + struct module *owner; + /* dev->driver_data will be used instead some day. + * Use the video_{get|set}_drvdata() helper functions, + * so the switch over will be transparent for you. + * Or use {pci|usb}_{get|set}_drvdata() directly. */ + void *priv; +#endif + + /* for videodev.c intenal usage -- please don't touch */ + int users; /* video_exclusive_{open|close} ... */ + struct semaphore lock; /* ... helper function uses these */ + char devfs_name[64]; /* devfs */ + struct class_device class_dev; /* sysfs */ +}; + +#define VIDEO_MAJOR 81 + +#define VFL_TYPE_GRABBER 0 +#define VFL_TYPE_VBI 1 +#define VFL_TYPE_RADIO 2 +#define VFL_TYPE_VTX 3 + +extern int video_register_device(struct video_device *, int type, int nr); +extern void video_unregister_device(struct video_device *); +extern struct video_device* video_devdata(struct file*); + +#define to_video_device(cd) container_of(cd, struct video_device, class_dev) +static inline void +video_device_create_file(struct video_device *vfd, + struct class_device_attribute *attr) +{ + class_device_create_file(&vfd->class_dev, attr); +} +static inline void +video_device_remove_file(struct video_device *vfd, + struct class_device_attribute *attr) +{ + class_device_remove_file(&vfd->class_dev, attr); +} + +/* helper functions to alloc / release struct video_device, the + later can be used for video_device->release() */ +struct video_device *video_device_alloc(void); +void video_device_release(struct video_device *vfd); + +/* helper functions to access driver private data. */ +static inline void *video_get_drvdata(struct video_device *dev) +{ + return dev->priv; +} + +static inline void video_set_drvdata(struct video_device *dev, void *data) +{ + dev->priv = data; +} + +extern int video_exclusive_open(struct inode *inode, struct file *file); +extern int video_exclusive_release(struct inode *inode, struct file *file); +extern int video_usercopy(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg, + int (*func)(struct inode *inode, struct file *file, + unsigned int cmd, void *arg)); +#endif /* __KERNEL__ */ + +#define VID_TYPE_CAPTURE 1 /* Can capture */ +#define VID_TYPE_TUNER 2 /* Can tune */ +#define VID_TYPE_TELETEXT 4 /* Does teletext */ +#define VID_TYPE_OVERLAY 8 /* Overlay onto frame buffer */ +#define VID_TYPE_CHROMAKEY 16 /* Overlay by chromakey */ +#define VID_TYPE_CLIPPING 32 /* Can clip */ +#define VID_TYPE_FRAMERAM 64 /* Uses the frame buffer memory */ +#define VID_TYPE_SCALES 128 /* Scalable */ +#define VID_TYPE_MONOCHROME 256 /* Monochrome only */ +#define VID_TYPE_SUBCAPTURE 512 /* Can capture subareas of the image */ +#define VID_TYPE_MPEG_DECODER 1024 /* Can decode MPEG streams */ +#define VID_TYPE_MPEG_ENCODER 2048 /* Can encode MPEG streams */ +#define VID_TYPE_MJPEG_DECODER 4096 /* Can decode MJPEG streams */ +#define VID_TYPE_MJPEG_ENCODER 8192 /* Can encode MJPEG streams */ + +struct video_capability +{ + char name[32]; + int type; + int channels; /* Num channels */ + int audios; /* Num audio devices */ + int maxwidth; /* Supported width */ + int maxheight; /* And height */ + int minwidth; /* Supported width */ + int minheight; /* And height */ +}; + + +struct video_channel +{ + int channel; + char name[32]; + int tuners; + __u32 flags; +#define VIDEO_VC_TUNER 1 /* Channel has a tuner */ +#define VIDEO_VC_AUDIO 2 /* Channel has audio */ + __u16 type; +#define VIDEO_TYPE_TV 1 +#define VIDEO_TYPE_CAMERA 2 + __u16 norm; /* Norm set by channel */ +}; + +struct video_tuner +{ + int tuner; + char name[32]; + unsigned long rangelow, rangehigh; /* Tuner range */ + __u32 flags; +#define VIDEO_TUNER_PAL 1 +#define VIDEO_TUNER_NTSC 2 +#define VIDEO_TUNER_SECAM 4 +#define VIDEO_TUNER_LOW 8 /* Uses KHz not MHz */ +#define VIDEO_TUNER_NORM 16 /* Tuner can set norm */ +#define VIDEO_TUNER_STEREO_ON 128 /* Tuner is seeing stereo */ +#define VIDEO_TUNER_RDS_ON 256 /* Tuner is seeing an RDS datastream */ +#define VIDEO_TUNER_MBS_ON 512 /* Tuner is seeing an MBS datastream */ + __u16 mode; /* PAL/NTSC/SECAM/OTHER */ +#define VIDEO_MODE_PAL 0 +#define VIDEO_MODE_NTSC 1 +#define VIDEO_MODE_SECAM 2 +#define VIDEO_MODE_AUTO 3 + __u16 signal; /* Signal strength 16bit scale */ +}; + +struct video_picture +{ + __u16 brightness; + __u16 hue; + __u16 colour; + __u16 contrast; + __u16 whiteness; /* Black and white only */ + __u16 depth; /* Capture depth */ + __u16 palette; /* Palette in use */ +#define VIDEO_PALETTE_GREY 1 /* Linear greyscale */ +#define VIDEO_PALETTE_HI240 2 /* High 240 cube (BT848) */ +#define VIDEO_PALETTE_RGB565 3 /* 565 16 bit RGB */ +#define VIDEO_PALETTE_RGB24 4 /* 24bit RGB */ +#define VIDEO_PALETTE_RGB32 5 /* 32bit RGB */ +#define VIDEO_PALETTE_RGB555 6 /* 555 15bit RGB */ +#define VIDEO_PALETTE_YUV422 7 /* YUV422 capture */ +#define VIDEO_PALETTE_YUYV 8 +#define VIDEO_PALETTE_UYVY 9 /* The great thing about standards is ... */ +#define VIDEO_PALETTE_YUV420 10 +#define VIDEO_PALETTE_YUV411 11 /* YUV411 capture */ +#define VIDEO_PALETTE_RAW 12 /* RAW capture (BT848) */ +#define VIDEO_PALETTE_YUV422P 13 /* YUV 4:2:2 Planar */ +#define VIDEO_PALETTE_YUV411P 14 /* YUV 4:1:1 Planar */ +#define VIDEO_PALETTE_YUV420P 15 /* YUV 4:2:0 Planar */ +#define VIDEO_PALETTE_YUV410P 16 /* YUV 4:1:0 Planar */ +#define VIDEO_PALETTE_PLANAR 13 /* start of planar entries */ +#define VIDEO_PALETTE_COMPONENT 7 /* start of component entries */ +}; + +struct video_audio +{ + int audio; /* Audio channel */ + __u16 volume; /* If settable */ + __u16 bass, treble; + __u32 flags; +#define VIDEO_AUDIO_MUTE 1 +#define VIDEO_AUDIO_MUTABLE 2 +#define VIDEO_AUDIO_VOLUME 4 +#define VIDEO_AUDIO_BASS 8 +#define VIDEO_AUDIO_TREBLE 16 +#define VIDEO_AUDIO_BALANCE 32 + char name[16]; +#define VIDEO_SOUND_MONO 1 +#define VIDEO_SOUND_STEREO 2 +#define VIDEO_SOUND_LANG1 4 +#define VIDEO_SOUND_LANG2 8 + __u16 mode; + __u16 balance; /* Stereo balance */ + __u16 step; /* Step actual volume uses */ +}; + +struct video_clip +{ + __s32 x,y; + __s32 width, height; + struct video_clip *next; /* For user use/driver use only */ +}; + +struct video_window +{ + __u32 x,y; /* Position of window */ + __u32 width,height; /* Its size */ + __u32 chromakey; + __u32 flags; + struct video_clip *clips; /* Set only */ + int clipcount; +#define VIDEO_WINDOW_INTERLACE 1 +#define VIDEO_WINDOW_CHROMAKEY 16 /* Overlay by chromakey */ +#define VIDEO_CLIP_BITMAP -1 +/* bitmap is 1024x625, a '1' bit represents a clipped pixel */ +#define VIDEO_CLIPMAP_SIZE (128 * 625) +}; + +struct video_capture +{ + __u32 x,y; /* Offsets into image */ + __u32 width, height; /* Area to capture */ + __u16 decimation; /* Decimation divider */ + __u16 flags; /* Flags for capture */ +#define VIDEO_CAPTURE_ODD 0 /* Temporal */ +#define VIDEO_CAPTURE_EVEN 1 +}; + +struct video_buffer +{ + void *base; + int height,width; + int depth; + int bytesperline; +}; + +struct video_mmap +{ + unsigned int frame; /* Frame (0 - n) for double buffer */ + int height,width; + unsigned int format; /* should be VIDEO_PALETTE_* */ +}; + +struct video_key +{ + __u8 key[8]; + __u32 flags; +}; + + +#define VIDEO_MAX_FRAME 32 + +struct video_mbuf +{ + int size; /* Total memory to map */ + int frames; /* Frames */ + int offsets[VIDEO_MAX_FRAME]; +}; + + +#define VIDEO_NO_UNIT (-1) + + +struct video_unit +{ + int video; /* Video minor */ + int vbi; /* VBI minor */ + int radio; /* Radio minor */ + int audio; /* Audio minor */ + int teletext; /* Teletext minor */ +}; + +struct vbi_format { + __u32 sampling_rate; /* in Hz */ + __u32 samples_per_line; + __u32 sample_format; /* VIDEO_PALETTE_RAW only (1 byte) */ + __s32 start[2]; /* starting line for each frame */ + __u32 count[2]; /* count of lines for each frame */ + __u32 flags; +#define VBI_UNSYNC 1 /* can distingues between top/bottom field */ +#define VBI_INTERLACED 2 /* lines are interlaced */ +}; + +/* video_info is biased towards hardware mpeg encode/decode */ +/* but it could apply generically to any hardware compressor/decompressor */ +struct video_info +{ + __u32 frame_count; /* frames output since decode/encode began */ + __u32 h_size; /* current unscaled horizontal size */ + __u32 v_size; /* current unscaled veritcal size */ + __u32 smpte_timecode; /* current SMPTE timecode (for current GOP) */ + __u32 picture_type; /* current picture type */ + __u32 temporal_reference; /* current temporal reference */ + __u8 user_data[256]; /* user data last found in compressed stream */ + /* user_data[0] contains user data flags, user_data[1] has count */ +}; + +/* generic structure for setting playback modes */ +struct video_play_mode +{ + int mode; + int p1; + int p2; +}; + +/* for loading microcode / fpga programming */ +struct video_code +{ + char loadwhat[16]; /* name or tag of file being passed */ + int datasize; + __u8 *data; +}; + +#define VIDIOCGCAP _IOR('v',1,struct video_capability) /* Get capabilities */ +#define VIDIOCGCHAN _IOWR('v',2,struct video_channel) /* Get channel info (sources) */ +#define VIDIOCSCHAN _IOW('v',3,struct video_channel) /* Set channel */ +#define VIDIOCGTUNER _IOWR('v',4,struct video_tuner) /* Get tuner abilities */ +#define VIDIOCSTUNER _IOW('v',5,struct video_tuner) /* Tune the tuner for the current channel */ +#define VIDIOCGPICT _IOR('v',6,struct video_picture) /* Get picture properties */ +#define VIDIOCSPICT _IOW('v',7,struct video_picture) /* Set picture properties */ +#define VIDIOCCAPTURE _IOW('v',8,int) /* Start, end capture */ +#define VIDIOCGWIN _IOR('v',9, struct video_window) /* Get the video overlay window */ +#define VIDIOCSWIN _IOW('v',10, struct video_window) /* Set the video overlay window - passes clip list for hardware smarts , chromakey etc */ +#define VIDIOCGFBUF _IOR('v',11, struct video_buffer) /* Get frame buffer */ +#define VIDIOCSFBUF _IOW('v',12, struct video_buffer) /* Set frame buffer - root only */ +#define VIDIOCKEY _IOR('v',13, struct video_key) /* Video key event - to dev 255 is to all - cuts capture on all DMA windows with this key (0xFFFFFFFF == all) */ +#define VIDIOCGFREQ _IOR('v',14, unsigned long) /* Set tuner */ +#define VIDIOCSFREQ _IOW('v',15, unsigned long) /* Set tuner */ +#define VIDIOCGAUDIO _IOR('v',16, struct video_audio) /* Get audio info */ +#define VIDIOCSAUDIO _IOW('v',17, struct video_audio) /* Audio source, mute etc */ +#define VIDIOCSYNC _IOW('v',18, int) /* Sync with mmap grabbing */ +#define VIDIOCMCAPTURE _IOW('v',19, struct video_mmap) /* Grab frames */ +#define VIDIOCGMBUF _IOR('v',20, struct video_mbuf) /* Memory map buffer info */ +#define VIDIOCGUNIT _IOR('v',21, struct video_unit) /* Get attached units */ +#define VIDIOCGCAPTURE _IOR('v',22, struct video_capture) /* Get subcapture */ +#define VIDIOCSCAPTURE _IOW('v',23, struct video_capture) /* Set subcapture */ +#define VIDIOCSPLAYMODE _IOW('v',24, struct video_play_mode) /* Set output video mode/feature */ +#define VIDIOCSWRITEMODE _IOW('v',25, int) /* Set write mode */ +#define VIDIOCGPLAYINFO _IOR('v',26, struct video_info) /* Get current playback info from hardware */ +#define VIDIOCSMICROCODE _IOW('v',27, struct video_code) /* Load microcode into hardware */ +#define VIDIOCGVBIFMT _IOR('v',28, struct vbi_format) /* Get VBI information */ +#define VIDIOCSVBIFMT _IOW('v',29, struct vbi_format) /* Set VBI information */ + + +#define BASE_VIDIOCPRIVATE 192 /* 192-255 are private */ + +/* VIDIOCSWRITEMODE */ +#define VID_WRITE_MPEG_AUD 0 +#define VID_WRITE_MPEG_VID 1 +#define VID_WRITE_OSD 2 +#define VID_WRITE_TTX 3 +#define VID_WRITE_CC 4 +#define VID_WRITE_MJPEG 5 + +/* VIDIOCSPLAYMODE */ +#define VID_PLAY_VID_OUT_MODE 0 + /* p1: = VIDEO_MODE_PAL, VIDEO_MODE_NTSC, etc ... */ +#define VID_PLAY_GENLOCK 1 + /* p1: 0 = OFF, 1 = ON */ + /* p2: GENLOCK FINE DELAY value */ +#define VID_PLAY_NORMAL 2 +#define VID_PLAY_PAUSE 3 +#define VID_PLAY_SINGLE_FRAME 4 +#define VID_PLAY_FAST_FORWARD 5 +#define VID_PLAY_SLOW_MOTION 6 +#define VID_PLAY_IMMEDIATE_NORMAL 7 +#define VID_PLAY_SWITCH_CHANNELS 8 +#define VID_PLAY_FREEZE_FRAME 9 +#define VID_PLAY_STILL_MODE 10 +#define VID_PLAY_MASTER_MODE 11 + /* p1: see below */ +#define VID_PLAY_MASTER_NONE 1 +#define VID_PLAY_MASTER_VIDEO 2 +#define VID_PLAY_MASTER_AUDIO 3 +#define VID_PLAY_ACTIVE_SCANLINES 12 + /* p1 = first active; p2 = last active */ +#define VID_PLAY_RESET 13 +#define VID_PLAY_END_MARK 14 + + + +#define VID_HARDWARE_BT848 1 +#define VID_HARDWARE_QCAM_BW 2 +#define VID_HARDWARE_PMS 3 +#define VID_HARDWARE_QCAM_C 4 +#define VID_HARDWARE_PSEUDO 5 +#define VID_HARDWARE_SAA5249 6 +#define VID_HARDWARE_AZTECH 7 +#define VID_HARDWARE_SF16MI 8 +#define VID_HARDWARE_RTRACK 9 +#define VID_HARDWARE_ZOLTRIX 10 +#define VID_HARDWARE_SAA7146 11 +#define VID_HARDWARE_VIDEUM 12 /* Reserved for Winnov videum */ +#define VID_HARDWARE_RTRACK2 13 +#define VID_HARDWARE_PERMEDIA2 14 /* Reserved for Permedia2 */ +#define VID_HARDWARE_RIVA128 15 /* Reserved for RIVA 128 */ +#define VID_HARDWARE_PLANB 16 /* PowerMac motherboard video-in */ +#define VID_HARDWARE_BROADWAY 17 /* Broadway project */ +#define VID_HARDWARE_GEMTEK 18 +#define VID_HARDWARE_TYPHOON 19 +#define VID_HARDWARE_VINO 20 /* SGI Indy Vino */ +#define VID_HARDWARE_CADET 21 /* Cadet radio */ +#define VID_HARDWARE_TRUST 22 /* Trust FM Radio */ +#define VID_HARDWARE_TERRATEC 23 /* TerraTec ActiveRadio */ +#define VID_HARDWARE_CPIA 24 +#define VID_HARDWARE_ZR36120 25 /* Zoran ZR36120/ZR36125 */ +#define VID_HARDWARE_ZR36067 26 /* Zoran ZR36067/36060 */ +#define VID_HARDWARE_OV511 27 +#define VID_HARDWARE_ZR356700 28 /* Zoran 36700 series */ +#define VID_HARDWARE_W9966 29 +#define VID_HARDWARE_SE401 30 /* SE401 USB webcams */ +#define VID_HARDWARE_PWC 31 /* Philips webcams */ +#define VID_HARDWARE_MEYE 32 /* Sony Vaio MotionEye cameras */ +#define VID_HARDWARE_CPIA2 33 +#define VID_HARDWARE_VICAM 34 +#define VID_HARDWARE_SF16FMR2 35 +#define VID_HARDWARE_W9968CF 36 +#define VID_HARDWARE_SAA7114H 37 +#endif /* __LINUX_VIDEODEV_H */ + +/* + * Local variables: + * c-basic-offset: 8 + * End: + */